From 3be7149bbbfbd4e7a871c3f636673c1dcae895a1 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Mon, 23 Dec 2024 13:02:20 -0800 Subject: [PATCH 01/14] config: Add mt8365.toml Add mt8365.toml to support sof-mt8365.ri binary build. Signed-off-by: Andrew Perepech --- tools/rimage/config/mt8365.toml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 tools/rimage/config/mt8365.toml diff --git a/tools/rimage/config/mt8365.toml b/tools/rimage/config/mt8365.toml new file mode 100644 index 000000000000..1cec40f48ca5 --- /dev/null +++ b/tools/rimage/config/mt8365.toml @@ -0,0 +1,15 @@ +version = [1, 0] # use simple file write + +[adsp] +name = "mt8365" + +[[adsp.mem_zone]] +type = "IRAM" +base = "0x40020000" +size = "0x00040000" +host_offset = "0x0" +[[adsp.mem_zone]] +type = "SRAM" +base = "0x60000000" +size = "0x00600000" +host_offset = "0x0" From 251082fc4adc1e06d98acedb9554c7cfe3271347 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 16:53:23 -0800 Subject: [PATCH 02/14] platform: mtk: add xtensa headers for mt8365 Add xtensa headers for mtk mt8365 platform. Signed-off-by: Andrew Perepech --- .../include/arch/xtensa/config/core-isa.h | 649 ++++++++++++++++++ .../include/arch/xtensa/config/core-matmap.h | 103 +++ .../mt8365/include/arch/xtensa/config/defs.h | 38 + .../include/arch/xtensa/config/specreg.h | 103 +++ .../include/arch/xtensa/config/system.h | 267 +++++++ .../include/arch/xtensa/config/tie-asm.h | 336 +++++++++ .../mt8365/include/arch/xtensa/config/tie.h | 189 +++++ 7 files changed, 1685 insertions(+) create mode 100644 src/platform/mt8365/include/arch/xtensa/config/core-isa.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/core-matmap.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/defs.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/specreg.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/system.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/tie-asm.h create mode 100644 src/platform/mt8365/include/arch/xtensa/config/tie.h diff --git a/src/platform/mt8365/include/arch/xtensa/config/core-isa.h b/src/platform/mt8365/include/arch/xtensa/config/core-isa.h new file mode 100644 index 000000000000..b8efd6318c50 --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/core-isa.h @@ -0,0 +1,649 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 11 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI4 1 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_PDX 0 /* PDX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_PDX8 0 /* PDX8 */ +#define XCHAL_HAVE_PDX16 0 /* PDX16 */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1200009 /* sw version of this header */ + +#define XCHAL_CORE_ID "hifi4_Aquila_E2_PROD" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00075F5E /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC0F3FBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x22475F5E /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.0.9" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 9 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 270009 /* major*100+minor */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_0 1 +#define XCHAL_HW_REL_LX7_0_9 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 9 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 270009 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 9 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 270009 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 6 +#define XCHAL_DCACHE_SETWIDTH 6 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 4 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 65536 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0x40010000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40010000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 65536 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM1 1 +#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x1E000000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x1E000000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 262144 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x1E040000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x1E040000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 262144 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IDMA 0 +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 25 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 18 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00B900FF +#define XCHAL_INTLEVEL2_MASK 0x0142FF00 +#define XCHAL_INTLEVEL3_MASK 0x00040000 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00B900FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x01FBFFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x01FFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 2 +#define XCHAL_INT18_LEVEL 3 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 1 +#define XCHAL_INT22_LEVEL 2 +#define XCHAL_INT23_LEVEL 1 +#define XCHAL_INT24_LEVEL 2 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFE000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00600000 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x0000C0C0 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x01803F3F +#define XCHAL_INTTYPE_MASK_TIMER 0x00070000 +#define XCHAL_INTTYPE_MASK_NMI 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00080000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00100000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 16 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 17 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 18 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_WRITE_ERROR_INTERRUPT 19 +#define XCHAL_PROFILING_INTERRUPT 20 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL3_NUM 18 +/* (There are many interrupts each at level(s) 1, 2.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 23 /* (intlevel 1) */ +#define XCHAL_EXTINT17_NUM 24 /* (intlevel 2) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT14_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT15_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT23_EXTNUM 16 /* (intlevel 1) */ +#define XCHAL_INT24_EXTNUM 17 /* (intlevel 2) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40020400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40020400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x40020000 +#define XCHAL_RESET_VECTOR0_PADDR 0x40020000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000640 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000640 +#define XCHAL_RESET_VECTOR_VADDR 0x40000640 +#define XCHAL_RESET_VECTOR_PADDR 0x40000640 +#define XCHAL_USER_VECOFS 0x000001FC +#define XCHAL_USER_VECTOR_VADDR 0x400205FC +#define XCHAL_USER_VECTOR_PADDR 0x400205FC +#define XCHAL_KERNEL_VECOFS 0x000001DC +#define XCHAL_KERNEL_VECTOR_VADDR 0x400205DC +#define XCHAL_KERNEL_VECTOR_PADDR 0x400205DC +#define XCHAL_DOUBLEEXC_VECOFS 0x0000021C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x4002061C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x4002061C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40020400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40020400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x4002057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x4002057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x4002059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x4002059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x400205BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x400205BC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 12 +#define XCHAL_MPU_ALIGN 4096 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h new file mode 100644 index 000000000000..1235cf0f758b --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/core-matmap.h @@ -0,0 +1,103 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ + +/* Mappings for legacy constants where appropriate */ + +#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx ) + +#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_ILLEGAL (XTHAL_AR_NONE | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\ + XTHAL_MEM_BUFFERABLE) +#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 + +#define XCHAL_CA_R (XTHAL_AR_R) +#define XCHAL_CA_RX (XTHAL_AR_RX) +#define XCHAL_CA_RW (XTHAL_AR_RW) +#define XCHAL_CA_RWX (XTHAL_AR_RWX) + + +/* + * Contents of MPU background map. + * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here + * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro. + * + * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) + * + * s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand + * vaddr_start = first byte of region (always 0 for first entry) + * vaddr_end = last byte of region (always 0xFFFFFFFF for last entry) + * rights = access rights + * memtype = memory type + * x = reserved for future use (0 until then) + */ +#define XCHAL_MPU_BACKGROUND_MAP(s) \ + XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \ + XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \ + /* end */ + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/src/platform/mt8365/include/arch/xtensa/config/defs.h b/src/platform/mt8365/include/arch/xtensa/config/defs.h new file mode 100644 index 000000000000..2a05ec08e4bb --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/defs.h @@ -0,0 +1,38 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=13943; Build=0x75f5e; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/mt8365/include/arch/xtensa/config/specreg.h b/src/platform/mt8365/include/arch/xtensa/config/specreg.h new file mode 100644 index 000000000000..9345cc424d5a --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/specreg.h @@ -0,0 +1,103 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=13943; Build=0x75f5e; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define MPUENB 90 +#define ERACCESS 95 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEADRDIS 98 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/src/platform/mt8365/include/arch/xtensa/config/system.h b/src/platform/mt8365/include/arch/xtensa/config/system.h new file mode 100644 index 000000000000..2368853e0097 --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/system.h @@ -0,0 +1,267 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=13943; Build=0x75f5e; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + +/*#include */ + + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 +/* Alternatives: */ +/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ +/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ + +#define XSHAL_CLIB XTHAL_CLIB_XCLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 +/* Alternatives: */ +/*#define XSHAL_NEWLIB 0*/ /* set if newlib C library selected */ +/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ +/*#define XSHAL_XCLIB 1*/ /* set if Xtensa C library selected */ + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 1 + +/* SW workarounds enabled for HW errata: */ + +/* SW options for functional safety: */ +#define XSHAL_FUNC_SAFETY_ENABLED 0 + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x50000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x50000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ +/*#define XSHAL_ROM_[VP]ADDR ...not configured...*/ +/*#define XSHAL_ROM_SIZE ...not configured...*/ +/*#define XSHAL_ROM_AVAIL_V{ADDR,SIZE} ...not configured...*/ + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x40020000 +#define XSHAL_RAM_PADDR 0x40020000 +#define XSHAL_RAM_VSIZE 0x80000000 +#define XSHAL_RAM_PSIZE 0x80000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x4002061C +#define XSHAL_RAM_AVAIL_VSIZE 0x7FFFF9E4 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 + +/* Alternate system RAM (different device than system RAM): */ +/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ +/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0x20000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0x20000000 +#define XSHAL_SIMIO_PADDR 0x20000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0xcce5000 + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x24444424 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x21111121 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x21111121 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xF44444F4 /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xF11111F1 /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xF11111F1 /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xF22222F2 /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x24444424 /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x21111121 /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x21111121 /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xF4444224 /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xF1111221 /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xF1111221 /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xF2222222 /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000014 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 +#define XSHAL_STATIC_VECTOR_SELECT 1 +#define XSHAL_RESET_VECTOR_VADDR 0x40000640 +#define XSHAL_RESET_VECTOR_PADDR 0x40000640 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x000002E0 +#define XSHAL_RESET_VECTOR_ISROM 0 +#define XSHAL_USER_VECTOR_SIZE 0x0000001C +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x0000001C +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM + + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h new file mode 100644 index 000000000000..2d9c889ecc5b --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/tie-asm.h @@ -0,0 +1,336 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional global registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 // threadptr option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.BR \at1 // boolean option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1012, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.accreg_0 \at1 // ureg 3 + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.accreg_1 \at1 // ureg 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1012, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store + .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 + ae_movae \at1, aep0 + s8i \at1, \ptr, .Lxchal_ofs_+40 + ae_movae \at1, aep1 + s8i \at1, \ptr, .Lxchal_ofs_+41 + ae_movae \at1, aep2 + s8i \at1, \ptr, .Lxchal_ofs_+42 + ae_movae \at1, aep3 + s8i \at1, \ptr, .Lxchal_ofs_+43 + ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 + ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 + ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 + addi \ptr, \ptr, -192 + ae_movvfcrfsr aed0 // ureg FCR_FSR + ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 + rur.AE_OVF_SAR \at1 // ureg 240 + s32i \at1, \ptr, .Lxchal_ofs_+8 + rur.AE_BITHEAD \at1 // ureg 241 + s32i \at1, \ptr, .Lxchal_ofs_+12 + rur.AE_TS_FTS_BU_BP \at1 // ureg 242 + s32i \at1, \ptr, .Lxchal_ofs_+16 + rur.AE_CW_SD_NO \at1 // ureg 243 + s32i \at1, \ptr, .Lxchal_ofs_+20 + rur.AE_CBEGIN0 \at1 // ureg 246 + s32i \at1, \ptr, .Lxchal_ofs_+24 + rur.AE_CEND0 \at1 // ureg 247 + s32i \at1, \ptr, .Lxchal_ofs_+28 + rur.AE_CBEGIN1 \at1 // ureg 248 + s32i \at1, \ptr, .Lxchal_ofs_+32 + rur.AE_CEND1 \at1 // ureg 249 + s32i \at1, \ptr, .Lxchal_ofs_+36 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .endif + .endm // xchal_cp1_store + + /* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load + .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg FCR_FSR + ae_movfcrfsrv aed0 + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.AE_OVF_SAR \at1 // ureg 240 + l32i \at1, \ptr, .Lxchal_ofs_+12 + wur.AE_BITHEAD \at1 // ureg 241 + l32i \at1, \ptr, .Lxchal_ofs_+16 + wur.AE_TS_FTS_BU_BP \at1 // ureg 242 + l32i \at1, \ptr, .Lxchal_ofs_+20 + wur.AE_CW_SD_NO \at1 // ureg 243 + l32i \at1, \ptr, .Lxchal_ofs_+24 + wur.AE_CBEGIN0 \at1 // ureg 246 + l32i \at1, \ptr, .Lxchal_ofs_+28 + wur.AE_CEND0 \at1 // ureg 247 + l32i \at1, \ptr, .Lxchal_ofs_+32 + wur.AE_CBEGIN1 \at1 // ureg 248 + l32i \at1, \ptr, .Lxchal_ofs_+36 + wur.AE_CEND1 \at1 // ureg 249 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 + addi \ptr, \ptr, 40 + l8ui \at1, \ptr, .Lxchal_ofs_+0 + ae_movea aep0, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+1 + ae_movea aep1, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+2 + ae_movea aep2, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+3 + ae_movea aep3, \at1 + addi \ptr, \ptr, 8 + ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 + ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 + ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 + ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .endif + .endm // xchal_cp1_load + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/src/platform/mt8365/include/arch/xtensa/config/tie.h b/src/platform/mt8365/include/arch/xtensa/config/tie.h new file mode 100644 index 000000000000..196c1fd575b8 --- /dev/null +++ b/src/platform/mt8365/include/arch/xtensa/config/tie.h @@ -0,0 +1,189 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Customer ID=13943; Build=0x75f5e; Copyright (c) 1999-2018 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "AudioEngineLX" +#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 16 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 224 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 4 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, accreg_0, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, accreg_1, 4, 4, 4,0x0304, ur,4 , 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 33 +#define XCHAL_CP1_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, fcr_fsr, 8, 8, 8,0x1019, ur,-1 , 7,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 4, 4, 4,0x03F0, ur,240, 15,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cbegin1, 4, 4, 4,0x03F8, ur,248, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cend1, 4, 4, 4,0x03F9, ur,249, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1000, aed,0 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1001, aed,1 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1002, aed,2 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1003, aed,3 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1004, aed,4 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1005, aed,5 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1006, aed,6 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1007, aed,7 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1008, aed,8 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1009, aed,9 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep0, 1, 1, 1,0x1014, aep,0 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep1, 1, 1, 1,0x1015, aep,1 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep2, 1, 1, 1,0x1016, aep,2 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep3, 1, 1, 1,0x1017, aep,3 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1010, u,0 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1011, u,1 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1012, u,2 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1013, u,3 , 64,0,0,0) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */ +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,11 + +#endif /*_XTENSA_CORE_TIE_H*/ + From 7b6c715ce6614c090cdd87047ad8cffa48517fa9 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 17:16:22 -0800 Subject: [PATCH 03/14] platform: mtk: add mt8365 memory layout and register definitions Add memory layout and register addresses for mt8365. [Cache] I-Cache: 32KB, 4-way Associativity D-Cache: 32KB, 4-way Associativity [Memory] DRAM: DSP can access DRAM shared with CPU Signed-off-by: Andrew Perepech --- .../include/platform/drivers/mt_reg_base.h | 138 ++++++++++ .../mt8365/include/platform/lib/memory.h | 243 ++++++++++++++++++ 2 files changed, 381 insertions(+) create mode 100644 src/platform/mt8365/include/platform/drivers/mt_reg_base.h create mode 100644 src/platform/mt8365/include/platform/lib/memory.h diff --git a/src/platform/mt8365/include/platform/drivers/mt_reg_base.h b/src/platform/mt8365/include/platform/drivers/mt_reg_base.h new file mode 100644 index 000000000000..289ab7d256d6 --- /dev/null +++ b/src/platform/mt8365/include/platform/drivers/mt_reg_base.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifndef MT_REG_BASE_H +#define MT_REG_BASE_H + +#define DSP_REG_BASE (0x1D062000) /* DSPCFG base */ +#define DSP_TIMER_BASE (0x1D060000) +#define DSP_UART0_BASE (0x1D061000) +#define DSP_WDT_BASE (0x1D062400) +#define DSP_IRQ_BASE (0x1D063000) +#define DSP_D_TCM (CFG_HIFI4_DTCM_ADDRESS) +#define DSP_I_TCM (CFG_HIFI4_ITCM_ADDRESS) +#define DSP_DRAM_BASE (CFG_HIFI4_DRAM_ADDRESS) + +#define DSP_AUDIO_SRAM_BASE (0x11221000) +#define DSP_AUDIO_SRAM_SIZE (0xA000) +#define DSP_REG_REMAP_BASE (0x1D060000) +#define DSP_REG_REMAP_SIZE (0x8000) +#define DSP_SYS_REG_BASE (0x10000000) +#define DSP_SYS_REG_SIZE (0x1221000) +#define DSP_VER_REG_BASE (0x08000000) +#define DSP_VER_REG_SIZE (0x1000) + + +#define DSP_JTAGMUX (DSP_REG_BASE + 0x0000) +#define DSP_ALTRESETVEC (DSP_REG_BASE + 0x0004) +#define DSP_PDEBUGDATA (DSP_REG_BASE + 0x0008) +#define DSP_PDEBUGBUS0 (DSP_REG_BASE + 0x000c) +#define DSP_PDEBUGBUS1 (DSP_REG_BASE + 0x0010) +#define DSP_PDEBUGINST (DSP_REG_BASE + 0x0014) +#define DSP_PDEBUGLS0STAT (DSP_REG_BASE + 0x0018) +#define DSP_PDEBUGLS1STAT (DSP_REG_BASE + 0x001c) +#define DSP_PDEBUGPC (DSP_REG_BASE + 0x0020) +#define DSP_RESET_SW (DSP_REG_BASE + 0x0024) +#define DSP_PFAULTBUS (DSP_REG_BASE + 0x0028) +#define DSP_PFAULTINFO (DSP_REG_BASE + 0x002c) +#define DSP_GPR00 (DSP_REG_BASE + 0x0030) +#define DSP_GPR01 (DSP_REG_BASE + 0x0034) +#define DSP_GPR02 (DSP_REG_BASE + 0x0038) +#define DSP_GPR03 (DSP_REG_BASE + 0x003c) +#define DSP_GPR04 (DSP_REG_BASE + 0x0040) +#define DSP_GPR05 (DSP_REG_BASE + 0x0044) +#define DSP_GPR06 (DSP_REG_BASE + 0x0048) +#define DSP_GPR07 (DSP_REG_BASE + 0x004c) +#define DSP_GPR08 (DSP_REG_BASE + 0x0050) +#define DSP_GPR09 (DSP_REG_BASE + 0x0054) +#define DSP_GPR0A (DSP_REG_BASE + 0x0058) +#define DSP_GPR0B (DSP_REG_BASE + 0x005c) +#define DSP_GPR0C (DSP_REG_BASE + 0x0060) +#define DSP_GPR0D (DSP_REG_BASE + 0x0064) +#define DSP_GPR0E (DSP_REG_BASE + 0x0068) +#define DSP_GPR0F (DSP_REG_BASE + 0x006c) +#define DSP_GPR10 (DSP_REG_BASE + 0x0070) +#define DSP_GPR11 (DSP_REG_BASE + 0x0074) +#define DSP_GPR12 (DSP_REG_BASE + 0x0078) +#define DSP_GPR13 (DSP_REG_BASE + 0x007c) +#define DSP_GPR14 (DSP_REG_BASE + 0x0080) +#define DSP_GPR15 (DSP_REG_BASE + 0x0084) +#define DSP_GPR16 (DSP_REG_BASE + 0x0088) +#define DSP_GPR17 (DSP_REG_BASE + 0x008c) +#define DSP_GPR18 (DSP_REG_BASE + 0x0090) +#define DSP_GPR19 (DSP_REG_BASE + 0x0094) +#define DSP_GPR1A (DSP_REG_BASE + 0x0098) +#define DSP_GPR1B (DSP_REG_BASE + 0x009c) +#define DSP_GPR1C (DSP_REG_BASE + 0x00a0) +#define DSP_GPR1D (DSP_REG_BASE + 0x00a4) +#define DSP_GPR1E (DSP_REG_BASE + 0x00a8) +#define DSP_GPR1F (DSP_REG_BASE + 0x00ac) +#define DSP_TCM_OFFSET (DSP_REG_BASE + 0x00b0) /* not used */ +#define DSP_DDR_OFFSET (DSP_REG_BASE + 0x00b4) /* not used */ +#define DSP_INTFDSP (DSP_REG_BASE + 0x00d0) +#define DSP_INTFDSP_CLR (DSP_REG_BASE + 0x00d4) +#define DSP_SRAM_PD_SW1 (DSP_REG_BASE + 0x00d8) +#define DSP_SRAM_PD_SW2 (DSP_REG_BASE + 0x00dc) +#define DSP_OCD (DSP_REG_BASE + 0x00e0) +#define DSP_RG_DSP_IRQ_POL (DSP_REG_BASE + 0x00f0) /* not used */ +#define DSP_DSP_IRQ_EN (DSP_REG_BASE + 0x00f4) /* not used */ +#define DSP_DSP_IRQ_LEVEL (DSP_REG_BASE + 0x00f8) /* not used */ +#define DSP_DSP_IRQ_STATUS (DSP_REG_BASE + 0x00fc) /* not used */ +#define DSP_RG_INT2CIRQ (DSP_REG_BASE + 0x0114) +#define DSP_RG_INT_POL_CTL0 (DSP_REG_BASE + 0x0120) +#define DSP_RG_INT_EN_CTL0 (DSP_REG_BASE + 0x0130) +#define DSP_RG_INT_LV_CTL0 (DSP_REG_BASE + 0x0140) +#define DSP_RG_INT_STATUS0 (DSP_REG_BASE + 0x0150) +#define DSP_PDEBUGSTATUS0 (DSP_REG_BASE + 0x0200) +#define DSP_PDEBUGSTATUS1 (DSP_REG_BASE + 0x0204) +#define DSP_PDEBUGSTATUS2 (DSP_REG_BASE + 0x0208) +#define DSP_PDEBUGSTATUS3 (DSP_REG_BASE + 0x020c) +#define DSP_PDEBUGSTATUS4 (DSP_REG_BASE + 0x0210) +#define DSP_PDEBUGSTATUS5 (DSP_REG_BASE + 0x0214) +#define DSP_PDEBUGSTATUS6 (DSP_REG_BASE + 0x0218) +#define DSP_PDEBUGSTATUS7 (DSP_REG_BASE + 0x021c) +#define DSP_DSP2PSRAM_PRIORITY (DSP_REG_BASE + 0x0220) /* not used */ +#define DSP_AUDIO_DSP2SPM_INT (DSP_REG_BASE + 0x0224) +#define DSP_AUDIO_DSP2SPM_INT_ACK (DSP_REG_BASE + 0x0228) +#define DSP_AUDIO_DSP_DEBUG_SEL (DSP_REG_BASE + 0x022C) +#define DSP_AUDIO_DSP_EMI_BASE_ADDR (DSP_REG_BASE + 0x02E0) /* not used */ +#define DSP_AUDIO_DSP_SHARED_IRAM (DSP_REG_BASE + 0x02E4) +#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (DSP_REG_BASE + 0x02F0) +#define DSP_RG_SEMAPHORE00 (DSP_REG_BASE + 0x0300) +#define DSP_RG_SEMAPHORE01 (DSP_REG_BASE + 0x0304) +#define DSP_RG_SEMAPHORE02 (DSP_REG_BASE + 0x0308) +#define DSP_RG_SEMAPHORE03 (DSP_REG_BASE + 0x030C) +#define DSP_RG_SEMAPHORE04 (DSP_REG_BASE + 0x0310) +#define DSP_RG_SEMAPHORE05 (DSP_REG_BASE + 0x0314) +#define DSP_RG_SEMAPHORE06 (DSP_REG_BASE + 0x0318) +#define DSP_RG_SEMAPHORE07 (DSP_REG_BASE + 0x031C) +#define DSP_RESERVED_0 (DSP_REG_BASE + 0x03F0) +#define DSP_RESERVED_1 (DSP_REG_BASE + 0x03F4) /* use for tickless status */ + +/* Redefinition for using Special registers */ +#define TICKLESS_STATUS_REG (DSP_RESERVED_1) + +/* WDT CONFIGS */ +#define ADSP_WDT_MODE (DSP_REG_BASE + 0x400 + 0x00) +#define ADSP_WDT_LENGTH (DSP_REG_BASE + 0x400 + 0x04) +#define ADSP_WDT_RESTART (DSP_REG_BASE + 0x400 + 0x08) +#define ADSP_WDT_STA (DSP_REG_BASE + 0x400 + 0x0C) +#define ADSP_WDT_SWRST (DSP_REG_BASE + 0x400 + 0x14) + +#define ADSP_WDT_SWRST_KEY 0x1209 +#define ADSP_WDT_RESTART_RELOAD 0x1971 +#define ADSP_WDT_LENGTH_KEY 0x8 + +#define WDT_LENGTH_TIMEOUT(n) ((n) << 5) + +/* DSP IPI IRQ */ +#define CPU2DSP_IRQ BIT(0) +#define DSP2CPU_IRQ BIT(1) +#define DSP2SPM_IRQ_B BIT(2) + +#endif /* MT_REG_BASE_H */ + diff --git a/src/platform/mt8365/include/platform/lib/memory.h b/src/platform/mt8365/include/platform/lib/memory.h new file mode 100644 index 000000000000..3f0532d4d417 --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/memory.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include +#include + +#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/ +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN sizeof(void *) + +/* + * +-----------------------------------+-----------------------------+ + * | | AUDIO_DSP_SHARED_DRAM | + * +------------+----------------------+---------+---------+---------+ + * | DSP | Sys | Size | 00b | 01b *** | 11b | + * +------------+------------+---------+---------+---------+---------+ + * | 0x40000000 | 0x1e100000 | 0x8000 | iram0_0 | iram0_0 | iram0_0 | + * | 0x40008000 | 0x1e108000 | 0x8000 | iram0_1 | iram0_1 | --- | + * | 0x40010000 | 0x1e110000 | 0x8000 | iram1 | --- | --- | + * +------------+------------+---------+---------+---------+---------+ + * | 0x1e000000 | 0x1e000000 | 0x40000 | dram0 | dram0 | dram0 | + * | 0x1e040000 | 0x1e040000 | 0x20000 | dram1 | dram1 | dram1 | + * | 0x1e060000 | 0x1e060000 | 0x8000 | --- | iram1 | iram1 | + * | 0x1e068000 | 0x1e068000 | 0x8000 | --- | --- | iram0_1 | + * +------------+------------+---------+---------+---------+---------+ + */ + +/* BOOT_WITH_DRAM ONLY */ +/* physical DSP addresses */ +#define DRAM_BASE 0x60000000 +#define DRAM_AUDIO_SHARED_SIZE 0x280000 +#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/ + +#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/ +#define VECTOR_SIZE 0x628 + +#define SRAM0_BASE DRAM_BASE +#define SRAM0_SIZE (DRAM_SIZE >> 1) +#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE) +#define SRAM1_SIZE \ + (DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE - \ + LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE) + +#define DMA_SIZE 0x100000 + +#define UUID_ENTRY_ELF_SIZE 0x6000 +#define LOG_ENTRY_ELF_SIZE 0x200000 +#define EXT_MANIFEST_ELF_SIZE 0x100000 + +#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE) +#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) + +/* + * The Memory Layout on MT8365 are organised like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | XCHAL_RESET_VECTOR0 | DSP Vectors | VECTOR_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM0_BASE | fw_ready | SRAM0_SIZE | + * | | RO Data | | + * | | module_init | | + * | | Text | | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | SRAM1_BASE | MAILBOX | SOF_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +/* Mailbox configuration */ +#define SRAM_OUTBOX_BASE SRAM1_BASE +#define SRAM_OUTBOX_SIZE 0x1000 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) + +/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/ +#define SOF_MAILBOX_SIZE \ + (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +/* Heap section sizes for module pool */ +#define HEAP_RT_COUNT8 0 +#define HEAP_RT_COUNT16 48 +#define HEAP_RT_COUNT32 48 +#define HEAP_RT_COUNT64 32 +#define HEAP_RT_COUNT128 32 +#define HEAP_RT_COUNT256 32 +#define HEAP_RT_COUNT512 32 +#define HEAP_RT_COUNT1024 4 +#define HEAP_RT_COUNT2048 2 +#define HEAP_RT_COUNT4096 2 + +/* Heap section sizes for system runtime heap */ +#define HEAP_SYS_RT_COUNT64 128 +#define HEAP_SYS_RT_COUNT512 16 +#define HEAP_SYS_RT_COUNT1024 8 + +/* Heap configuration */ + +#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE) +#define HEAP_SYSTEM_SIZE 0x6000 + +#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE + +#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) +/*24KB*/ +#define HEAP_SYS_RUNTIME_SIZE \ + (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024) + +#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) +/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/ +#define HEAP_RUNTIME_SIZE \ + (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ + HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ + HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096) + +#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) +#define HEAP_BUFFER_SIZE \ + (SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \ + HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE) + +#define HEAP_BUFFER_BLOCK_SIZE 0x100 +#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) + +#define PLATFORM_HEAP_SYSTEM 1 /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_BUFFER 1 + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x8000 +#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/ +#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE) +#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE) + +/* Vector and literal sizes - not in core-isa.h */ +#define SOF_MEM_VECT_LIT_SIZE 0x4 +#define SOF_MEM_VECT_TEXT_SIZE 0x1c +#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) + +#define SOF_MEM_RESET_TEXT_SIZE 0x2e0 +#define SOF_MEM_RESET_LIT_SIZE 0x120 +#define SOF_MEM_VECBASE_LIT_SIZE 0x178 + +#define SOF_MEM_RO_SIZE 0x8 + +#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE + +/** \brief EDF task's default stack size in bytes. */ +#ifdef CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING +#define PLATFORM_TASK_DEFAULT_STACK_SIZE (12 * 1024) +#else +#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072 +#endif + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +struct sof; + +/** + * \brief Data shared between different cores. + * Does nothing, since mt8195 doesn't support SMP. + */ +#define SHARED_DATA + +void platform_init_memmap(struct sof *sof); + +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define cache_to_uncache_init(address) address +#define is_uncached(address) 0 + +/** + * \brief Function for keeping shared data synchronized. + * It's used after usage of data shared by different cores. + * Such data is either statically marked with SHARED_DATA + * or dynamically allocated with SOF_MEM_FLAG_SHARED flag. + * Does nothing, since mt8195 doesn't support SMP. + */ + +static inline void *platform_rfree_prepare(void *ptr) +{ + return ptr; +} + +#endif + +#define host_to_local(addr) (addr) +#define local_to_host(addr) (addr) + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ From dd4183f3c5f81e0303b8da3b79a75b2f156e07d4 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 17:38:30 -0800 Subject: [PATCH 04/14] drivers: mtk: Add drivers for mt8365 Add interrupt, timer, and ipc drivers for mt8365 mt8365 DSP has 25 interrupts. Signed-off-by: Andrew Perepech --- src/drivers/mediatek/CMakeLists.txt | 3 + src/drivers/mediatek/mt8365/CMakeLists.txt | 4 + src/drivers/mediatek/mt8365/interrupt.c | 225 ++++++++++++++++++ src/drivers/mediatek/mt8365/ipc.c | 175 ++++++++++++++ src/drivers/mediatek/mt8365/timer.c | 166 +++++++++++++ .../include/platform/drivers/interrupt.h | 77 ++++++ .../mt8365/include/platform/drivers/timer.h | 68 ++++++ 7 files changed, 718 insertions(+) create mode 100644 src/drivers/mediatek/mt8365/CMakeLists.txt create mode 100644 src/drivers/mediatek/mt8365/interrupt.c create mode 100644 src/drivers/mediatek/mt8365/ipc.c create mode 100644 src/drivers/mediatek/mt8365/timer.c create mode 100644 src/platform/mt8365/include/platform/drivers/interrupt.h create mode 100644 src/platform/mt8365/include/platform/drivers/timer.h diff --git a/src/drivers/mediatek/CMakeLists.txt b/src/drivers/mediatek/CMakeLists.txt index 0dfbebbccf19..4362b62ec7cb 100644 --- a/src/drivers/mediatek/CMakeLists.txt +++ b/src/drivers/mediatek/CMakeLists.txt @@ -10,3 +10,6 @@ endif() if(CONFIG_MT8196) add_subdirectory(mt8196) endif() +if(CONFIG_MT8365) + add_subdirectory(mt8365) +endif() diff --git a/src/drivers/mediatek/mt8365/CMakeLists.txt b/src/drivers/mediatek/mt8365/CMakeLists.txt new file mode 100644 index 000000000000..0c8e351f06b5 --- /dev/null +++ b/src/drivers/mediatek/mt8365/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof ipc.c timer.c interrupt.c) + diff --git a/src/drivers/mediatek/mt8365/interrupt.c b/src/drivers/mediatek/mt8365/interrupt.c new file mode 100644 index 000000000000..1e341ab87a28 --- /dev/null +++ b/src/drivers/mediatek/mt8365/interrupt.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PENDING_IRQ_INDEX_MAX 10 + +SOF_DEFINE_REG_UUID(interrupt); + +DECLARE_TR_CTX(int_tr, SOF_UUID(interrupt_uuid), LOG_LEVEL_INFO); + +static void mtk_irq_init(void) +{ + /* disable all ADSP IRQ */ + io_reg_write(RG_DSP_IRQ_EN, 0x0); +} + +static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + if (!desc) { + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_BIT_OFFSET), 0); + } else { + switch (desc->irq) { + case IRQ_EXT_GROUP1_BASE: + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET), 0); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", irq); + return; + } + } +} + +static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + if (!desc) { + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_BIT_OFFSET), + BIT(irq + IRQ_EXT_BIT_OFFSET)); + } else { + switch (desc->irq) { + case IRQ_EXT_GROUP1_BASE: + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET), + BIT(irq + IRQ_EXT_GROUP1_BIT_OFFSET)); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", irq); + return; + } + } +} + +static uint32_t mtk_irq_group_pending_status(uint32_t irq) +{ + uint32_t irq_status = 0; + + if (irq == IRQ_EXT_GROUP1_BASE) { + irq_status = io_reg_read(RG_DSP_IRQ_STATUS); + irq_status &= IRQ_EXT_MASK; + } + + return irq_status; +} + +static uint32_t mtk_get_pending_index(uint32_t current, uint32_t *next) +{ + uint32_t index; + + if (current == 0) + return PENDING_IRQ_INDEX_MAX; + + /* ffs returns one plus the index of the least significant 1-bit of input int */ + index = ffs(current) - 1; + + /* remove the handling index from current pending status */ + *next = current & ~(1ull << index); + + return index; +} + +static inline void mtk_handle_group_pending_irq(struct irq_cascade_desc *cascade, + uint32_t line_index, uint32_t status) +{ + int core = cpu_get_id(); + struct list_item *clist; + struct irq_desc *child = NULL; + uint32_t idx; + uint32_t next_status; + bool handled; + k_spinlock_key_t key; + + idx = mtk_get_pending_index(status, &next_status); + while (idx < PENDING_IRQ_INDEX_MAX) { + handled = false; + + key = k_spin_lock(&cascade->lock); + list_for_item(clist, &cascade->child[idx - IRQ_EXT_GROUP1_BIT_OFFSET].list) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child->handler && (child->cpu_mask & 1 << core)) { + child->handler(child->handler_arg); + handled = true; + } + } + k_spin_unlock(&cascade->lock, key); + + if (!handled) { + tr_err(&int_tr, "Not handle irq %u in group %u", + idx, line_index); + } + + idx = mtk_get_pending_index(next_status, &next_status); + } +} + +static inline void mtk_irq_group_handler(void *data, uint32_t line_index) +{ + struct irq_desc *parent = data; + struct irq_cascade_desc *cascade = + container_of(parent, struct irq_cascade_desc, desc); + uint32_t status; + + status = mtk_irq_group_pending_status(line_index); + if (status) + mtk_handle_group_pending_irq(cascade, line_index, status); + else + tr_err(&int_tr, "No pending irq in group %d", line_index); +} + +#define DEFINE_IRQ_HANDLER(n) \ + static void irqhandler_##n(void *arg) \ + { \ + mtk_irq_group_handler(arg, n); \ + } + +DEFINE_IRQ_HANDLER(1) + +static const char mtk_ext_irq[] = "mtk_ext_irq"; + +static const struct irq_cascade_ops irq_ops = { + .mask = mtk_irq_mask, + .unmask = mtk_irq_unmask, +}; + +static const struct irq_cascade_tmpl dsp_irq[] = { + { + .name = mtk_ext_irq, + .irq = IRQ_EXT_GROUP1_BASE, + .handler = irqhandler_1, + .ops = &irq_ops, + .global_mask = false, + }, +}; + +int mtk_irq_group_id(uint32_t in_irq) +{ + if (in_irq >= PLATFORM_IRQ_HW_NUM) + in_irq -= PLATFORM_IRQ_HW_NUM; + + return interrupt_get_irq(in_irq, dsp_irq[0].name); +} + +void platform_interrupt_init(void) +{ + int i; + + mtk_irq_init(); + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) + interrupt_cascade_register(dsp_irq + i); +} + +void platform_interrupt_set(uint32_t irq) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_set(irq); +} + +void platform_interrupt_clear(uint32_t irq, uint32_t mask) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_clear(irq); +} + +uint32_t platform_interrupt_get_enabled(void) +{ + return 0; +} + +void interrupt_mask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->mask) + cascade->ops->mask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_mask(NULL, irq, 0); +} + +void interrupt_unmask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->unmask) + cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_unmask(NULL, irq, 0); +} diff --git a/src/drivers/mediatek/mt8365/ipc.c b/src/drivers/mediatek/mt8365/ipc.c new file mode 100644 index 000000000000..c97dd348a997 --- /dev/null +++ b/src/drivers/mediatek/mt8365/ipc.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +SOF_DEFINE_REG_UUID(ipc_task); + +static struct ipc *local_ipc; + +struct ipc_data { + struct ipc_data_host_buffer dh_buffer; +}; + +static void irq_handler(void *args) +{ + uint32_t status; + + /* Interrupt arrived, check src */ + status = mailbox_sw_reg_read(SRAM_REG_OP_CPU2DSP); + + tr_dbg(&ipc_tr, "ipc: irq isr 0x%x", status); + + /* reply message(done) from host */ + if (status == ADSP_IPI_OP_RSP) { + /* clear interrupt */ + io_reg_update_bits(DSP_RG_INT2CIRQ, CPU2DSP_IRQ, 0); + local_ipc->is_notification_pending = false; + } + + /* new message from host */ + if (status == ADSP_IPI_OP_REQ) { + /* clear interrupt */ + io_reg_update_bits(DSP_RG_INT2CIRQ, CPU2DSP_IRQ, 0); + ipc_schedule_process(local_ipc); + } +} + +/* DSP -> HOST RSP */ +void trigger_irq_to_host_rsp(void) +{ + mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, ADSP_IPI_OP_RSP); + /* trigger host irq */ + io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2SPM_IRQ_B, 0); + io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2CPU_IRQ, DSP2CPU_IRQ); +} + +/* DSP -> HOST REQ */ +void trigger_irq_to_host_req(void) +{ + mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, ADSP_IPI_OP_REQ); + /* trigger host irq */ + io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2SPM_IRQ_B, 0); + io_reg_update_bits(DSP_RG_INT2CIRQ, DSP2CPU_IRQ, DSP2CPU_IRQ); +} + +enum task_state ipc_platform_do_cmd(struct ipc *ipc) +{ + struct ipc_cmd_hdr *hdr; + + hdr = mailbox_validate(); + ipc_cmd(hdr); + + return SOF_TASK_STATE_COMPLETED; +} + +void ipc_platform_complete_cmd(struct ipc *ipc) +{ + trigger_irq_to_host_rsp(); + while (ipc->pm_prepare_D3) { + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_SUSPEND_CPU_HZ); + asm volatile("waiti 15"); + } +} + +int ipc_platform_send_msg(const struct ipc_msg *msg) +{ + struct ipc *ipc = ipc_get(); + + if (ipc->is_notification_pending) + return -EBUSY; + + /* now send the message */ + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + + tr_dbg(&ipc_tr, "ipc: msg tx -> 0x%x", msg->header); + + ipc->is_notification_pending = true; + + /* now interrupt host to tell it we have sent a message */ + trigger_irq_to_host_req(); + return 0; +} + +void ipc_platform_send_msg_direct(const struct ipc_msg *msg) +{ + /* TODO: add support */ +} + +#if CONFIG_HOST_PTABLE +struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc) +{ + struct ipc_data *iipc = ipc_get_drvdata(ipc); + + return &iipc->dh_buffer; +} +#endif + +int platform_ipc_init(struct ipc *ipc) +{ + uint32_t ipi_irq; + +#if CONFIG_HOST_PTABLE + struct ipc_data *iipc; + + iipc = rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, sizeof(*iipc)); + if (!iipc) { + tr_err(&ipc_tr, "Unable to allocate IPC private data"); + return -ENOMEM; + } + ipc_set_drvdata(ipc, iipc); +#else + ipc_set_drvdata(ipc, NULL); +#endif + + local_ipc = ipc; + + /* schedule */ + schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), &ipc_task_ops, ipc, 0, 0); + +#if CONFIG_HOST_PTABLE + /* allocate page table buffer */ + iipc->dh_buffer.page_table = + rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, PLATFORM_PAGE_TABLE_SIZE); + + iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED); + if (!iipc->dh_buffer.dmac) { + tr_err(&ipc_tr, "Unable to find DMA for host page table"); + sof_panic(SOF_IPC_PANIC_IPC); + } +#endif + + ipi_irq = mtk_irq_group_id(LX_MCU_IRQ_B); + interrupt_register(ipi_irq, irq_handler, ipc); + interrupt_enable(ipi_irq, ipc); + + return 0; +} diff --git a/src/drivers/mediatek/mt8365/timer.c b/src/drivers/mediatek/mt8365/timer.c new file mode 100644 index 000000000000..222fd85b7275 --- /dev/null +++ b/src/drivers/mediatek/mt8365/timer.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void platform_timer_start(struct timer *timer) +{ + if (timer->id >= NR_TMRS) + return; + + /*timer use 13M clksrc*/ + /*clear irq, if pending and enable timer*/ + io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT); +} + +void platform_timer_stop(struct timer *timer) +{ + if (timer->id >= NR_TMRS) + return; + + io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT); + io_reg_write(TIMER_CON(timer->id), 0); + +} + +/* IRQs off in arch_timer_get_system() */ +uint64_t platform_timer_get_atomic(struct timer *timer) +{ + return platform_timer_get(timer); +} + +int64_t platform_timer_set(struct timer *timer, uint64_t ticks) +{ + uint64_t time; + uint32_t flags; + uint32_t ticks_set; + + if (timer->id >= NR_TMRS) + return -EINVAL; + + flags = arch_interrupt_global_disable(); + + time = platform_timer_get(timer); + ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time + ticks; + timer->hitimeout = ticks >> 32; + timer->lowtimeout = ticks_set; + + io_reg_write(TIMER_CNT_VAL(timer->id), ticks_set); + io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_ENABLE | TIMER_ENABLE_BIT); + + arch_interrupt_global_enable(flags); + + return ticks; +} + +void platform_timer_clear(struct timer *timer) +{ + if (timer->id >= NR_TMRS) + return; + + io_reg_write(TIMER_CON(timer->id), TIMER_IRQ_CLEAR | TIMER_ENABLE_BIT); +} + +uint64_t platform_timer_get(struct timer *timer) +{ + uint64_t time; + uint32_t low, high; + + if (timer->id >= NR_TMRS) + return -EINVAL; + + /* must read 'low' first, and 'high' next */ + low = io_reg_read(CNTCV_L); + high = io_reg_read(CNTCV_H); + time = ((uint64_t)high << 32) | low; + + return time; +} + +/* get timestamp for host stream DMA position */ +void platform_host_timestamp(struct comp_dev *host, + struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get host position */ + err = comp_position(host, posn); + if (err == 0) + posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64; +} + +/* get timestamp for DAI stream DMA position */ +void platform_dai_timestamp(struct comp_dev *dai, + struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get DAI position */ + err = comp_position(dai, posn); + if (err == 0) + posn->flags |= SOF_TIME_DAI_VALID; + + posn->wallclock = timer_get_system(timer_get()) - posn->wallclock; + posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64; +} + +/* get current wallclock for componnent */ +void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock) +{ + *wallclock = platform_timer_get(timer_get()); +} + +static void platform_timer_handler(void *arg) +{ + struct timer *timer = arg; + + timer->handler(timer->data); +} + +static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg) +{ + timer->handler = handler; + timer->data = arg; + timer->hitime = 0; + timer->hitimeout = 0; + + return interrupt_register(timer->irq, platform_timer_handler, timer); +} + +int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg) +{ + switch (timer->id) { + case OSTIMER0: + return platform_timer_register(timer, handler, arg); + default: + return -EINVAL; + } +} + +void timer_unregister(struct timer *timer, void *arg) +{ + interrupt_unregister(timer->irq, arg); +} + +void timer_enable(struct timer *timer, void *arg, int core) +{ + interrupt_unmask(timer->irq, cpu_get_id()); + interrupt_enable(timer->irq, arg); +} + +void timer_disable(struct timer *timer, void *arg, int core) +{ + interrupt_disable(timer->irq, arg); + interrupt_mask(timer->irq, cpu_get_id()); +} diff --git a/src/platform/mt8365/include/platform/drivers/interrupt.h b/src/platform/mt8365/include/platform/drivers/interrupt.h new file mode 100644 index 000000000000..c40b68ab1f42 --- /dev/null +++ b/src/platform/mt8365/include/platform/drivers/interrupt.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_DRIVERS_INTERRUPT_H__ + +#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ +#define __PLATFORM_DRIVERS_INTERRUPT_H__ + +#include +#include + +#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS +#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM +#define PLATFORM_IRQ_CHILDREN (LX_MCU_IRQ_B - LX_CQDMA_IRQ0_B + 1) + +#define IRQ_EXT_MASK 0x3F0 + +/* interrupt table */ +#define MTK_DSP_EXT_IRQ0 0 +#define L1_INT_IRQ_B 1 // (INT_LEVEL(1) | IRQ_INVALID) +#define L1_DSP_TIMER_IRQ0_B 2 // (INT_LEVEL(2) | INTERRUPT_ID(0)) +#define L1_DSP_TIMER_IRQ1_B 3 // (INT_LEVEL(3) | INTERRUPT_ID(1)) +#define L1_DSP_TIMER_IRQ2_B 4 // (INT_LEVEL(4) | INTERRUPT_ID(2)) +#define L1_DSP_TIMER_IRQ3_B 5 // (INT_LEVEL(5) | INTERRUPT_ID(3)) +#define MTK_DSP_EXT_IRQ6 6 +#define MTK_DSP_EXT_IRQ7 7 +#define MTK_DSP_EXT_IRQ8 8 +#define MTK_DSP_EXT_IRQ9 9 +#define MTK_DSP_EXT_IRQ10 10 +#define MTK_DSP_EXT_IRQ11 11 +#define MTK_DSP_EXT_IRQ12 12 +#define MTK_DSP_EXT_IRQ13 13 +#define MTK_DSP_EXT_IRQ14 14 +#define MTK_DSP_EXT_IRQ15 15 +/* HiFi internal interrupts */ +#define MTK_DSP_IRQ_TIMER0 16 +#define MTK_DSP_IRQ_TIMER1 17 +#define MTK_DSP_IRQ_TIMER2 18 +#define MTK_DSP_IRQ_WRITE_ERROR 19 +#define MTK_DSP_IRQ_PROFILING 20 +#define MTK_DSP_IRQ_SOFTWARE0 21 +#define MTK_DSP_IRQ_SOFTWARE1 22 +/* HiFi external interrupts */ +#define MTK_DSP_EXT_INT23 23 +#define MTK_DSP_EXT_INT24 24 + +/* group 1 cascaded IRQ trigger L1_INT_IRQ_B */ +#define IRQ_EXT_GROUP1_BASE L1_INT_IRQ_B +#define LX_CQDMA_IRQ0_B 25 // (INT_LEVEL(1) | INTERRUPT_ID(4)) +#define LX_CQDMA_IRQ1_B 26 // (INT_LEVEL(1) | INTERRUPT_ID(5)) +#define LX_CQDMA_IRQ2_B 27 // (INT_LEVEL(1) | INTERRUPT_ID(6)) +#define LX_UART_IRQ_B 28 // (INT_LEVEL(1) | INTERRUPT_ID(7)) +#define LX_AFE_IRQ_B 29 // (INT_LEVEL(1) | INTERRUPT_ID(8)) +#define LX_MCU_IRQ_B 30 // (INT_LEVEL(1) | INTERRUPT_ID(9)) + +int mtk_irq_group_id(uint32_t irq); + +/* L1_DSP_TIMER_IRQ0_B corresponds to bit# 0 of RG_DSP_IRQ_EN */ +#define IRQ_EXT_BIT_OFFSET (-2) + +/* base_irq = 25; (LX_CQDMA_IRQ0_B - base_irq) corresponds to bit# 4 of RG_DSP_IRQ_EN */ +#define IRQ_EXT_GROUP1_BIT_OFFSET (4) + +#define RG_DSP_IRQ_EN DSP_RG_INT_EN_CTL0 +#define RG_DSP_IRQ_STATUS DSP_RG_INT_STATUS0 + +#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" + +#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/mt8365/include/platform/drivers/timer.h b/src/platform/mt8365/include/platform/drivers/timer.h new file mode 100644 index 000000000000..8d389d5da4e0 --- /dev/null +++ b/src/platform/mt8365/include/platform/drivers/timer.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifndef __PLATFORM_DRIVERS_TIMER_H__ +#define __PLATFORM_DRIVERS_TIMER_H__ + +#include +#include + + +/*-------timer:ostimer0-------*/ +enum ostimer { + OSTIMER0 = 0, + OSTIMER1, + OSTIMER2, + OSTIMER3, + NR_TMRS +}; + +#define TIMER_CON(n) (DSP_TIMER_BASE + 0x40 + 0x8 * (n)) +#define TIMER_CNT_VAL(n) (DSP_TIMER_BASE + 0x44 + 0x8 * (n)) + +#define TIMER_ENABLE_BIT (0x1 << 0) +#define TIMER_IRQ_ENABLE (0x1 << 1) +#define TIMER_IRQ_STA (0x1 << 4) +#define TIMER_IRQ_CLEAR (0x1 << 4) + +/** + * system timer register map + */ +#define CNTCR (DSP_TIMER_BASE + 0x00) +#define CNTSR (DSP_TIMER_BASE + 0x04) +#define CNTCV_L (DSP_TIMER_BASE + 0x08) +#define CNTCV_H (DSP_TIMER_BASE + 0x0c) +#define CNTWACR (DSP_TIMER_BASE + 0x10) +#define CNTRACR (DSP_TIMER_BASE + 0x14) +#define CNTACR_LOCK (DSP_TIMER_BASE + 0x18) +#define CNTFID0 (DSP_TIMER_BASE + 0x20) +#define CNTFID1 (DSP_TIMER_BASE + 0x24) +#define CNTFID2 (DSP_TIMER_BASE + 0x28) +#define CNTFIDE (DSP_TIMER_BASE + 0x2c) + +#define CNT_EN_BIT BIT(0) +#define CLKSRC_BIT (BIT(8) | BIT(9)) +#define CLKSRC_13M_BIT BIT(8) +#define COMP_BIT (BIT(10) | BIT(11) | BIT(12)) +#define COMP_20_25_EN_BIT (BIT(11) | BIT(12)) + +#define CNT_EN (0x1 << 0) +#define CNTTVAL_EN (0x1 << 0) +#define CNTIRQ_EN (0x1 << 1) +#define CNTIRQ_STACLR (0x1 << 4) +#define CNTMODE_REPEAT (0x1 << 8) + + +#define DELAY_TIMER_1US_TICK (13U) // (13MHz) +#define DELAY_TIMER_1MS_TICK (13000U) // (13MHz) +#define TIME_TO_TICK_US(us) ((us)*DELAY_TIMER_1US_TICK) +#define TIME_TO_TICK_MS(ms) ((ms)*DELAY_TIMER_1MS_TICK) + +#define SYSTICK_TIMER_IRQ L1_DSP_TIMER_IRQ0_B + + +#endif /* __PLATFORM_DRIVERS_TIMER_H__ */ From 4e38e84558bdb67fad66faa58bc98c56c150449f Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 18:57:01 -0800 Subject: [PATCH 05/14] platform: mtk: Add support for mt8365 platform mt8365 platform integrates a single-core HIFI4 DSP. The highest DSP operation frequency is 600MHz which requires 0.75v working voltage. otherwise, it should switch to 13M which can operate at the lowest working voltage 0.55v. Signed-off-by: Andrew Perepech --- .../mt8365/include/platform/drivers/idc.h | 33 ++ .../mt8365/include/platform/lib/clk.h | 90 ++++ .../mt8365/include/platform/lib/cpu.h | 22 + .../mt8365/include/platform/lib/dai.h | 19 + .../mt8365/include/platform/lib/dma.h | 30 ++ .../mt8365/include/platform/lib/mailbox.h | 84 +++ .../mt8365/include/platform/lib/pm_runtime.h | 66 +++ .../mt8365/include/platform/platform.h | 89 ++++ .../mt8365/include/platform/trace/trace.h | 26 + src/platform/mt8365/lib/clk.c | 188 +++++++ src/platform/mt8365/lib/dma.c | 45 ++ src/platform/mt8365/lib/memory.c | 101 ++++ src/platform/mt8365/mt8365.x.in | 492 ++++++++++++++++++ src/platform/mt8365/platform.c | 219 ++++++++ uuid-registry.txt | 1 + 15 files changed, 1505 insertions(+) create mode 100644 src/platform/mt8365/include/platform/drivers/idc.h create mode 100644 src/platform/mt8365/include/platform/lib/clk.h create mode 100644 src/platform/mt8365/include/platform/lib/cpu.h create mode 100644 src/platform/mt8365/include/platform/lib/dai.h create mode 100644 src/platform/mt8365/include/platform/lib/dma.h create mode 100644 src/platform/mt8365/include/platform/lib/mailbox.h create mode 100644 src/platform/mt8365/include/platform/lib/pm_runtime.h create mode 100644 src/platform/mt8365/include/platform/platform.h create mode 100644 src/platform/mt8365/include/platform/trace/trace.h create mode 100644 src/platform/mt8365/lib/clk.c create mode 100644 src/platform/mt8365/lib/dma.c create mode 100644 src/platform/mt8365/lib/memory.c create mode 100644 src/platform/mt8365/mt8365.x.in create mode 100644 src/platform/mt8365/platform.c diff --git a/src/platform/mt8365/include/platform/drivers/idc.h b/src/platform/mt8365/include/platform/drivers/idc.h new file mode 100644 index 000000000000..b638b9ec987e --- /dev/null +++ b/src/platform/mt8365/include/platform/drivers/idc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__) + +#ifndef __PLATFORM_DRIVERS_IDC_H__ +#define __PLATFORM_DRIVERS_IDC_H__ + +#include + +struct idc_msg; + +static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode) +{ + return 0; +} + +static inline int idc_init(void) +{ + return 0; +} + +#endif /* __PLATFORM_DRIVERS_IDC_H__ */ + +#else + +#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h" + +#endif diff --git a/src/platform/mt8365/include/platform/lib/clk.h b/src/platform/mt8365/include/platform/lib/clk.h new file mode 100644 index 000000000000..beaa2f762bbe --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/clk.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +struct sof; + +#define CPU_DEFAULT_IDX 4 + +#define CLK_CPU(x) (x) +#define CLK_DEFAULT_CPU_HZ 600000000 +#define CLK_MAX_CPU_HZ 600000000 +#define CLK_SUSPEND_CPU_HZ 26000000 +#define NUM_CLOCKS 1 +#define NUM_CPU_FREQ 5 + +void platform_clock_init(struct sof *sof); + +#define REG_APMIXDSYS_BASE 0x1000C000 +#define REG_TOPCKGEN_BASE 0x10000000 + +#define DSPPLL_CON0 (REG_APMIXDSYS_BASE + 0x390) +#define DSPPLL_CON1 (REG_APMIXDSYS_BASE + 0x394) +#define DSPPLL_CON2 (REG_APMIXDSYS_BASE + 0x398) +#define DSPPLL_CON3 (REG_APMIXDSYS_BASE + 0x39C) + +#define ULPLL_CON0 (REG_APMIXDSYS_BASE + 0x3B0) +#define ULPLL_CON1 (REG_APMIXDSYS_BASE + 0x3B4) + +#define PLL_BASE_EN BIT(0) +#define PLL_PWR_ON BIT(0) +#define PLL_ISO_EN BIT(1) + +#define DSPPLL_312MHZ 0 +#define DSPPLL_400MHZ 1 +#define DSPPLL_600MHZ 2 + +#define CLK_MODE (REG_TOPCKGEN_BASE + 0x0) +#define CLK_CFG_UPDATE1 (REG_TOPCKGEN_BASE + 0x8) +#define CLK_CFG_8 (REG_TOPCKGEN_BASE + 0xC0) +#define CLK_CFG_8_SET (REG_TOPCKGEN_BASE + 0xC4) +#define CLK_CFG_8_CLR (REG_TOPCKGEN_BASE + 0xC8) + +#define CLK_SCP_CFG_1 (REG_TOPCKGEN_BASE + 0x204) + +#define CLK_DSP_SEL_26M 0 +#define CLK_DSP_SEL_26M_D_2 1 +#define CLK_DSP_SEL_DSPPLL 2 +#define CLK_DSP_SEL_DSPPLL_D_2 3 +#define CLK_DSP_SEL_DSPPLL_D_4 4 +#define CLK_DSP_SEL_DSPPLL_D_8 5 + +#define CLK_TOPCKGEN_SEL_PLLGP_26M 1 +#define CLK_TOPCKGEN_SEL_ULPLL_26M 2 +#define CLK_TOPCKGEN_SEL_GPIO_26M 4 + +enum mux_id_t { + MUX_CLK_DSP_SEL = 0, + MUX_CLK_TOPCKGEN_26M_SEL, + HIFI4DSP_MUX_NUM, +}; + +enum mux_26m_t { + DCXO_26 = 0, + ULPLL_26M, +}; + +enum DSP_HW_DSP_CLK { + DSP_CLK_13M = 0, + DSP_CLK_26M, + DSP_CLK_PLL_312M, + DSP_CLK_PLL_400M, + DSP_CLK_PLL_600M, +}; +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/mt8365/include/platform/lib/cpu.h b/src/platform/mt8365/include/platform/lib/cpu.h new file mode 100644 index 000000000000..1c72bd51b176 --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/cpu.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +/** \brief Id of primary DSP core */ +#define PLATFORM_PRIMARY_CORE_ID 0 + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/mt8365/include/platform/lib/dai.h b/src/platform/mt8365/include/platform/lib/dai.h new file mode 100644 index 000000000000..98fe70955f2f --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/dai.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/mt8365/include/platform/lib/dma.h b/src/platform/mt8365/include/platform/lib/dma.h new file mode 100644 index 000000000000..479591ab5daa --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/dma.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +#define PLATFORM_NUM_DMACS 2 + +/* max number of supported DMA channels */ +#define PLATFORM_MAX_DMA_CHAN 32 + +#define DMA_ID_AFE_MEMIF 0 +#define DMA_ID_HOST 1 + +#define dma_chan_irq(dma, chan) dma_irq(dma) +#define dma_chan_irq_name(dma, chan) dma_irq_name(dma) + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/mt8365/include/platform/lib/mailbox.h b/src/platform/mt8365/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..27f48a72238c --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/mailbox.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include +#include +#include + +/* + * The Window Region on MT8365 SRAM is organised like this :- + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_TRACE_BASE | Trace Buffer | SRAM_TRACE_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_DEBUG_BASE | Debug data | SRAM_DEBUG_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_INBOX_BASE | Inbox | SRAM_INBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_OUTBOX_BASE | Outbox | SRAM_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + */ + +#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE +#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE +#define MAILBOX_DSPBOX_OFFSET SRAM_OUTBOX_OFFSET + +#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE +#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE +#define MAILBOX_HOSTBOX_OFFSET SRAM_INBOX_OFFSET + +#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE +#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE +#define MAILBOX_DEBUG_OFFSET SRAM_DEBUG_OFFSET + +#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE +#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE +#define MAILBOX_TRACE_OFFSET SRAM_TRACE_OFFSET + +#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE +#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE +#define MAILBOX_EXCEPTION_OFFSET SRAM_EXCEPT_OFFSET + +#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET + +static inline void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset); + *ptr = src; +} + +static inline uint32_t mailbox_sw_reg_read(size_t offset) +{ + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset); + + return *ptr; +} + + #define ADSP_IPI_OP_REQ 0x1 + #define ADSP_IPI_OP_RSP 0x2 +void trigger_irq_to_host_req(void); +void trigger_irq_to_host_rsp(void); + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/mt8365/include/platform/lib/pm_runtime.h b/src/platform/mt8365/include/platform/lib/pm_runtime.h new file mode 100644 index 000000000000..e93410938f30 --- /dev/null +++ b/src/platform/mt8365/include/platform/lib/pm_runtime.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_LIB_PM_RUNTIME_H__ + +#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ +#define __PLATFORM_LIB_PM_RUNTIME_H__ + +#include + +struct pm_runtime_data; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) +{ +} + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index) +{ +} + +static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index) +{ +} + +static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index) +{ + return false; +} + +#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" + +#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/mt8365/include/platform/platform.h b/src/platform/mt8365/include/platform/platform.h new file mode 100644 index 000000000000..c447312c16a5 --- /dev/null +++ b/src/platform/mt8365/include/platform/platform.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +#include +#include +#include + +struct ll_schedule_domain; +struct timer; + +#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0) +#define LPSRAM_SIZE 16384 + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 +#define PLATFORM_PAGE_TABLE_SIZE 256 + +/* pipeline IRQ */ +#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SOFTWARE0 +#define PLATFORM_SCHEDULE_IRQ_NAME NULL + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE + +/* trace bytes flushed during panic */ +#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) + +/* the interval of DMA trace copying */ +#define DMA_TRACE_PERIOD 500000 + +/* + * the interval of reschedule DMA trace copying in special case like half + * fullness of local DMA trace buffer + */ +#define DMA_TRACE_RESCHEDULE_TIME 100 + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +#define SRAM_REG_FW_STATUS 0x4 +#define SRAM_REG_OP_CPU2DSP 0x8 +#define SRAM_REG_OP_DSP2CPU 0xC + +/* Platform defined panic code */ +static inline void platform_panic(uint32_t p) +{ + /* Store the error code in the debug box so the + * application processor can pick it up. Takes up 4 bytes + * from the debug box. + */ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p); + + /* Notify application processor */ + trigger_irq_to_host_req(); +} + +/** + * \brief Platform specific CPU entering idle. + * May be power-optimized using platform specific capabilities. + * @param level Interrupt level. + */ +void platform_wait_for_interrupt(int level); + +extern intptr_t _module_init_start; +extern intptr_t _module_init_end; +#endif + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/mt8365/include/platform/trace/trace.h b/src/platform/mt8365/include/platform/trace/trace.h new file mode 100644 index 000000000000..63122335e650 --- /dev/null +++ b/src/platform/mt8365/include/platform/trace/trace.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +#define platform_trace_point(__x) + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/mt8365/lib/clk.c b/src/platform/mt8365/lib/clk.c new file mode 100644 index 000000000000..80f95ea30708 --- /dev/null +++ b/src/platform/mt8365/lib/clk.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +SOF_DEFINE_REG_UUID(clkdrv_mt8365); + +DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8365_uuid), LOG_LEVEL_INFO); + +static int dsppll_enable; /* default no adsp clock*/ +static int adsp_clock; + +const struct freq_table platform_cpu_freq[] = { + { 13000000, 13000}, + { 26000000, 13000}, + { 312000000, 13000}, + { 400000000, 13000}, + { 600000000, 13000}, +}; + +const uint32_t cpu_freq_enc[] = { + 13000000, + 26000000, + 0x83180000, + 0x820F6276, + 0x821713B1, +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, + invalid_number_of_cpu_frequencies); + +static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; + +static inline void clk_setl(uint32_t addr, uint32_t val) +{ + io_reg_write(addr, io_reg_read(addr) | (val)); +} + +static inline void clk_clrl(uint32_t addr, uint32_t val) +{ + io_reg_write(addr, io_reg_read(addr) & ~(val)); +} + +static inline int dsp_clk_value_convert(int value) +{ + int ret; + + switch (value) { + case DSP_CLK_13M: + ret = CLK_DSP_SEL_26M_D_2; + break; + case DSP_CLK_26M: + ret = CLK_DSP_SEL_26M; + break; + case DSP_CLK_PLL_312M: + case DSP_CLK_PLL_400M: + case DSP_CLK_PLL_600M: + ret = CLK_DSP_SEL_DSPPLL; + break; + default: + ret = CLK_DSP_SEL_26M; + break; + } + + return ret; +} + +static void clk_dsppll_enable(void) +{ + tr_dbg(&clkdrv_tr, "clk_dsppll_enable\n"); + + clk_setl(DSPPLL_CON3, PLL_PWR_ON); + wait_delay_us(1); + clk_clrl(DSPPLL_CON3, PLL_ISO_EN); + wait_delay_us(1); + clk_setl(DSPPLL_CON0, PLL_BASE_EN); + wait_delay_us(20); + dsppll_enable = 1; + +} + +static void clk_dsppll_disable(void) +{ + tr_dbg(&clkdrv_tr, "clk_dsppll_disable\n"); + + clk_clrl(DSPPLL_CON0, PLL_BASE_EN); + wait_delay_us(1); + clk_setl(DSPPLL_CON3, PLL_ISO_EN); + wait_delay_us(1); + clk_clrl(DSPPLL_CON3, PLL_PWR_ON); + dsppll_enable = 0; +} + +static int dsppll_get_enable(void) +{ + tr_dbg(&clkdrv_tr, "dsppll_enable=%d.\n", dsppll_enable); + + return dsppll_enable; +} + +static int set_mux_sel(enum mux_id_t mux_id, uint32_t value) +{ + switch (mux_id) { + case MUX_CLK_DSP_SEL: + io_reg_update_bits(CLK_CFG_8_CLR, (0x7 << 24), (0x7 << 24)); + io_reg_update_bits(CLK_CFG_8_SET, (0x7 << 24), (value << 24)); + io_reg_write(CLK_CFG_UPDATE1, 0x8); + + tr_dbg(&clkdrv_tr, "adspclk_mux=%x, CLK_CFG_8=0x%08x\n", + value, io_reg_read(CLK_CFG_8)); + break; + default: + tr_dbg(&clkdrv_tr, "error: unknown mux_id (%d)\n", mux_id); + break; + } + + return 0; +} + +static int clock_platform_set_dsp_freq(int clock, int freq_idx) +{ + uint32_t enc = cpu_freq_enc[freq_idx]; + int clk_mux; + int adsp_clk_req = platform_cpu_freq[freq_idx].freq; + + if (adsp_clock == adsp_clk_req) + return 0; + + tr_info(&clkdrv_tr, "clock_platform_set_cpu_freq %d\n", adsp_clk_req); + + /* convert res manager value to driver map */ + clk_mux = dsp_clk_value_convert(freq_idx); + + if (enc > 26000000) { + /* adsp pll */ + if (!dsppll_get_enable()) { + clk_dsppll_enable(); + set_mux_sel(MUX_CLK_DSP_SEL, clk_mux); + } + /* set adsp pll clock */ + io_reg_update_bits(DSPPLL_CON1, 0xffffffff, enc); + } else { + /* clk26m */ + if (dsppll_get_enable()) { + set_mux_sel(MUX_CLK_DSP_SEL, clk_mux); + clk_dsppll_disable(); + } + } + + adsp_clock = adsp_clk_req; + + return 0; +} + +void platform_clock_init(struct sof *sof) +{ + int i; + + sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info)); + + for (i = 0; i < CONFIG_CORE_COUNT; i++) { + sof->clocks[i] = (struct clock_info){ + .freqs_num = NUM_CPU_FREQ, + .freqs = platform_cpu_freq, + .default_freq_idx = CPU_DEFAULT_IDX, + .current_freq_idx = CPU_DEFAULT_IDX, + .notification_id = NOTIFIER_ID_CPU_FREQ, + .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), + .set_freq = clock_platform_set_dsp_freq, + }; + } + + adsp_clock = 0; + dsppll_enable = 0; + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ); +} diff --git a/src/platform/mt8365/lib/dma.c b/src/platform/mt8365/lib/dma.c new file mode 100644 index 000000000000..8eb2bf5938b4 --- /dev/null +++ b/src/platform/mt8365/lib/dma.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include + +extern const struct dma_ops dummy_dma_ops; + +static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { +{ + .plat_data = { + .id = DMA_ID_HOST, + .dir = DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM, + .devs = DMA_DEV_HOST, + .channels = 16, + }, + .ops = &dummy_dma_ops, +}, +}; + +static const struct dma_info lib_dma = { + .dma_array = cache_to_uncache_init((struct dma *)dma), + .num_dmas = ARRAY_SIZE(dma) +}; + +int dmac_init(struct sof *sof) +{ + int i; + + /* early lock initialization for ref counting */ + for (i = 0; i < ARRAY_SIZE(dma); i++) + k_spinlock_init(&dma[i].lock); + + sof->dma_info = &lib_dma; + + return 0; +} diff --git a/src/platform/mt8365/lib/memory.c b/src/platform/mt8365/lib/memory.c new file mode 100644 index 000000000000..13c7a9b2bdd4 --- /dev/null +++ b/src/platform/mt8365/lib/memory.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include + +/* Heap blocks for system runtime */ +static SHARED_DATA struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64]; +static SHARED_DATA struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512]; +static SHARED_DATA struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024]; + +/* Heap memory for system runtime */ +static SHARED_DATA struct block_map sys_rt_heap_map[] = { + BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64), + BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512), + BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024), +}; + +/* Heap blocks for modules */ +static SHARED_DATA struct block_hdr mod_block16[HEAP_RT_COUNT16]; +static SHARED_DATA struct block_hdr mod_block32[HEAP_RT_COUNT32]; +static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64]; +static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128]; +static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256]; +static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512]; +static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024]; +static SHARED_DATA struct block_hdr mod_block2048[HEAP_RT_COUNT2048]; +static SHARED_DATA struct block_hdr mod_block4096[HEAP_RT_COUNT4096]; + +/* Heap memory map for modules */ +static SHARED_DATA struct block_map rt_heap_map[] = { + BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16), + BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32), + BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64), + BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128), + BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256), + BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512), + BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024), + BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048), + BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096), +}; + +/* Heap blocks for buffers */ +static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT]; + +/* Heap memory map for buffers */ +static SHARED_DATA struct block_map buf_heap_map[] = { + BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block), +}; + +static SHARED_DATA struct mm memmap = { + .system[0] = { + .heap = HEAP_SYSTEM_BASE, + .size = HEAP_SYSTEM_SIZE, + .info = {.free = HEAP_SYSTEM_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .system_runtime[0] = { + .blocks = ARRAY_SIZE(sys_rt_heap_map), + .map = sys_rt_heap_map, + .heap = HEAP_SYS_RUNTIME_BASE, + .size = HEAP_SYS_RUNTIME_SIZE, + .info = {.free = HEAP_SYS_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .runtime[0] = { + .blocks = ARRAY_SIZE(rt_heap_map), + .map = rt_heap_map, + .heap = HEAP_RUNTIME_BASE, + .size = HEAP_RUNTIME_SIZE, + .info = {.free = HEAP_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .buffer[0] = { + .blocks = ARRAY_SIZE(buf_heap_map), + .map = buf_heap_map, + .heap = HEAP_BUFFER_BASE, + .size = HEAP_BUFFER_SIZE, + .info = {.free = HEAP_BUFFER_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE + + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,}, +}; + +void platform_init_memmap(struct sof *sof) +{ + /* memmap has been initialized statically as a part of .data */ + sof->memory_map = platform_shared_get(&memmap, sizeof(memmap)); +} diff --git a/src/platform/mt8365/mt8365.x.in b/src/platform/mt8365/mt8365.x.in new file mode 100644 index 000000000000..fdf588d33e4f --- /dev/null +++ b/src/platform/mt8365/mt8365.x.in @@ -0,0 +1,492 @@ +/* + * Linker Script for mt8365 MediaTek + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + +#include +#include + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR, + len = SOF_MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, + len = SOF_MEM_RESET_LIT_SIZE + vector_base_text : + org = XCHAL_VECBASE_RESET_PADDR, + len = SOF_MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int2_text : + org = XCHAL_INTLEVEL2_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int3_text : + org = XCHAL_INTLEVEL3_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int4_text : + org = XCHAL_INTLEVEL4_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_kernel_text : + org = XCHAL_KERNEL_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_user_lit : + org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_user_text : + org = XCHAL_USER_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_double_lit : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_double_text : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + sof_sram : + org = SRAM0_BASE, + len = SRAM0_SIZE + system_heap : + org = HEAP_SYSTEM_BASE, + len = HEAP_SYSTEM_SIZE + system_runtime_heap : + org = HEAP_SYS_RUNTIME_BASE, + len = HEAP_SYS_RUNTIME_SIZE + runtime_heap : + org = HEAP_RUNTIME_BASE, + len = HEAP_RUNTIME_SIZE + buffer_heap : + org = HEAP_BUFFER_BASE, + len = HEAP_BUFFER_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + static_uuid_entries_seg (!ari) : + org = UUID_ENTRY_ELF_BASE, + len = UUID_ENTRY_ELF_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_base_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + sof_sram_phdr PT_LOAD; + system_heap_phdr PT_LOAD; + system_runtime_heap_phdr PT_LOAD; + runtime_heap_phdr PT_LOAD; + buffer_heap_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + static_uuid_entries_phdr PT_NOTE; + static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; +} + +/* Default entry point: */ +ENTRY(_ResetVector) +_rom_store_table = 0; + +/* ABI0 does not use Window base */ +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x00000100; +_memmap_cacheattr_wt_base = 0x00000300; +_memmap_cacheattr_bp_base = 0x00000400; +_memmap_cacheattr_unused_mask = 0xFFFFF0FF; +_memmap_cacheattr_wb_trapnull = 0x44444140; +_memmap_cacheattr_wba_trapnull = 0x44444140; +_memmap_cacheattr_wbna_trapnull = 0x44444240; +_memmap_cacheattr_wt_trapnull = 0x44444340; +_memmap_cacheattr_bp_trapnull = 0x44444440; +_memmap_cacheattr_wb_strict = 0x00000100; +_memmap_cacheattr_wt_strict = 0x00000300; +_memmap_cacheattr_bp_strict = 0x00000400; +_memmap_cacheattr_wb_allvalid = 0x44444144; +_memmap_cacheattr_wt_allvalid = 0x44444344; +_memmap_cacheattr_bp_allvalid = 0x44444444; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) + +SECTIONS +{ + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .fw_ready : ALIGN(4) + { + KEEP (*(.fw_ready)) + KEEP (*(.fw_ready_metadata)) + } >sof_sram :sof_sram_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + .module_init : ALIGN(4) + { + _module_init_start = ABSOLUTE(.); + *(*.initcall) + _module_init_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >sof_sram :sof_sram_phdr + + .reset.rodata : ALIGN(4) + { + _reset_rodata_start = ABSOLUTE(.); + *(.reset.rodata) + _reset_rodata_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _trace_ctx_start = ABSOLUTE(.); + *(.trace_ctx) + _trace_ctx_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sof_sram :sof_sram_phdr + + /* stack */ + _end = SOF_STACK_END; + PROVIDE(end = SOF_STACK_END); + _stack_sentry = SOF_STACK_END; + __stack = SOF_STACK_BASE; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + + .system_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _system_heap_start = ABSOLUTE(.); + . = . + HEAP_SYSTEM_SIZE; + _system_heap_end = ABSOLUTE(.); + } >system_heap :system_heap_phdr + + .system_runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _system_runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_SYS_RUNTIME_SIZE; + _system_runtime_heap_end = ABSOLUTE(.); + } >system_runtime_heap :system_runtime_heap_phdr + + .runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_RUNTIME_SIZE; + _runtime_heap_end = ABSOLUTE(.); + } >runtime_heap :runtime_heap_phdr + + .buffer_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _buffer_heap_start = ABSOLUTE(.); + . = . + HEAP_BUFFER_SIZE; + _buffer_heap_end = ABSOLUTE(.); + } >buffer_heap :buffer_heap_phdr + + .sof_stack (NOLOAD) : ALIGN(8) + { + . = ALIGN (4096); + _sof_stack_start = ABSOLUTE(.); + . = . + SOF_STACK_TOTAL_SIZE; + _sof_stack_end = ABSOLUTE(.); + } >sof_stack :sof_stack_phdr + + .static_uuid_entries (COPY) : ALIGN(1024) + { + *(*.static_uuids) + } > static_uuid_entries_seg :static_uuid_entries_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr +} diff --git a/src/platform/mt8365/platform.c b/src/platform/mt8365/platform.c new file mode 100644 index 000000000000..989bdc2312d5 --- /dev/null +++ b/src/platform/mt8365/platform.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sof; + +static const struct sof_ipc_fw_ready ready + __section(".fw_ready") = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + .src_hash = SOF_SRC_HASH, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +#define NUM_MTK_WINDOWS 6 + +const struct ext_man_windows xsram_window + __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { + .hdr = { + .type = EXT_MAN_ELEM_WINDOW, + .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), + }, + .window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window), + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_MTK_WINDOWS, + .window = { + { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, + { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + { + .type = SOF_IPC_REGION_EXCEPTION, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_EXCEPTION_SIZE, + .offset = MAILBOX_EXCEPTION_OFFSET, + }, + }, + } +}; + +static SHARED_DATA struct timer timer_shared = { + .id = OSTIMER0, + .irq = SYSTICK_TIMER_IRQ, +}; + +/* Override the default MPU setup. This table matches the memory map + * of the 'sample_controller' core and will need to be modified for + * other cores. + * NOTE: This table sets up all of external memory as shared uncached. + * For best results, edit the LSP memory map to create a separate + * section in shared memory, place all sections that need to be uncached + * into that section, and only map that section uncached. See README + * for more details. + */ +const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = { + XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // infra + XTHAL_MPU_ENTRY(0x40020000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // vectors + XTHAL_MPU_ENTRY(0x40060000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused + XTHAL_MPU_ENTRY(0x60000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // DSP FW + XTHAL_MPU_ENTRY(0x60800000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // shared + XTHAL_MPU_ENTRY(0x61000000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused +}; + +const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") = + ARRAY_SIZE(__xt_mpu_init_table); + +int platform_boot_complete(uint32_t boot_message) +{ + mailbox_dspbox_write(0, &ready, sizeof(ready)); + + /* now interrupt host to tell it we are done booting */ + trigger_irq_to_host_req(); + + return 0; +} + +int platform_init(struct sof *sof) +{ + int ret; + + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, 0); + mailbox_sw_reg_write(SRAM_REG_OP_CPU2DSP, 0); + mailbox_sw_reg_write(SRAM_REG_OP_DSP2CPU, 0); + + sof->platform_timer = platform_shared_get(&timer_shared, sizeof(timer_shared)); + sof->cpu_timers = sof->platform_timer; + + platform_interrupt_init(); + platform_clock_init(sof); + + scheduler_init_edf(); + + /* init low latency domains and schedulers */ + sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); + scheduler_init_ll(sof->platform_timer_domain); + + platform_timer_start(sof->platform_timer); + sa_init(sof, CONFIG_SYSTICK_PERIOD); + + /* init DMA */ + ret = dmac_init(sof); + if (ret < 0) + return -ENODEV; + + /* Init platform domain */ + sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1, + PLATFORM_DEFAULT_CLOCK, false); + scheduler_init_ll(sof->platform_dma_domain); + + /* initialize the host IPC mechanims */ + ipc_init(sof); + + /* TO-DO: dai init */ + +#if CONFIG_TRACE + /* Initialize DMA for Trace*/ + trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE); + dma_trace_init_complete(sof->dmat); +#endif + + /* show heap status */ + heap_trace_all(1); + + return 0; +} + +int platform_context_save(struct sof *sof) +{ + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ); + return 0; +} + +void platform_wait_for_interrupt(int level) +{ + arch_wait_for_interrupt(level); +} + diff --git a/uuid-registry.txt b/uuid-registry.txt index 4d77005ee1a7..3b60a926c03b 100644 --- a/uuid-registry.txt +++ b/uuid-registry.txt @@ -47,6 +47,7 @@ ec290e95-4a20-47eb-bbffd9c888431831 chmap 19d4e680-4479-48cc-af869f63d8b0098b clkdrv_mt8188 23b12fd5-c2a9-41a8-a2b3231ab7dcdc70 clkdrv_mt8195 e87bf747-e574-4362-bf2cc015d2859dd9 clkdrv_mt8196 +de358908-c146-4411-98b430ebd002957f clkdrv_mt8365 8890ea76-0df9-44ae-87e6994f4c15e9fa clock 7c42ce8b-0108-43d0-913756d660478c5f component 9ba00c83-ca12-4a83-943c1fa2e82f9dda copier From a3211689b3a2e6b9869ebb3885f4262faa866b22 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Mon, 23 Dec 2024 13:33:36 -0800 Subject: [PATCH 06/14] platform: mtk: Add afe-platform support for mt8365 Add mt8365 AFE common header and register header files. Add AFE platform for mt8365 audio. Signed-off-by: Andrew Perepech --- src/platform/mt8365/afe-platform.c | 336 +++++ .../include/platform/mt8365-afe-common.h | 55 + .../mt8365/include/platform/mt8365-afe-regs.h | 1207 +++++++++++++++++ 3 files changed, 1598 insertions(+) create mode 100644 src/platform/mt8365/afe-platform.c create mode 100644 src/platform/mt8365/include/platform/mt8365-afe-common.h create mode 100644 src/platform/mt8365/include/platform/mt8365-afe-regs.h diff --git a/src/platform/mt8365/afe-platform.c b/src/platform/mt8365/afe-platform.c new file mode 100644 index 000000000000..1255972479ce --- /dev/null +++ b/src/platform/mt8365/afe-platform.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include + +/* + * AFE: Audio Front-End + * + * frontend (memif): + * memory interface + * AWB, VULx, TDM_IN (uplink for capture) + * DLx, TDM_OUT (downlink for playback) + * backend: + * TDM In + * TMD out + * DMIC + * GASRC + * etc. + * interconn: + * inter-connection, + * connect frontends and backends as DSP path + */ + +static const struct mtk_base_memif_data memif_data[MT8365_MEMIF_NUM] = { + [MT8365_MEMIF_DL1] = { + .name = "DL1", + .id = MT8365_MEMIF_DL1, + .reg_ofs_base = AFE_DL1_BASE, + .reg_ofs_cur = AFE_DL1_CUR, + .reg_ofs_end = AFE_DL1_END, + .fs_reg = AFE_DAC_CON1, + .fs_shift = 0, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON1, + .mono_shift = 21, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 1, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 16, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = -1, + .msb_shift = 0, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_DL2] = { + .name = "DL2", + .id = MT8365_MEMIF_DL2, + .reg_ofs_base = AFE_DL2_BASE, + .reg_ofs_cur = AFE_DL2_CUR, + .reg_ofs_end = AFE_DL2_END, + .fs_reg = AFE_DAC_CON1, + .fs_shift = 4, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON1, + .mono_shift = 22, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 2, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 18, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = -1, + .msb_shift = 0, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_TDM_OUT] = { + .name = "TDM_OUT", + .id = MT8365_MEMIF_DL2, + .reg_ofs_base = AFE_HDMI_OUT_BASE, + .reg_ofs_cur = AFE_HDMI_OUT_CUR, + .reg_ofs_end = AFE_HDMI_OUT_END, + .fs_reg = -1, + .fs_shift = 0, + .fs_maskbit = 0, + .mono_reg = -1, + .mono_shift = 0, + .enable_reg = AFE_HDMI_OUT_CON0, + .enable_shift = 0, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 28, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = -1, + .msb_shift = 0, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_AWB] = { + .name = "AWB", + .id = MT8365_MEMIF_AWB, + .reg_ofs_base = AFE_AWB_BASE, + .reg_ofs_cur = AFE_AWB_CUR, + .reg_ofs_end = AFE_AWB_END, + .fs_reg = AFE_DAC_CON1, + .fs_shift = 12, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON1, + .mono_shift = 24, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 6, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 20, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_MEMIF_MSB, + .msb_shift = 17, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_VUL] = { + .name = "VUL", + .id = MT8365_MEMIF_VUL, + .reg_ofs_base = AFE_VUL_BASE, + .reg_ofs_cur = AFE_VUL_CUR, + .reg_ofs_end = AFE_VUL_END, + .fs_reg = AFE_DAC_CON1, + .fs_shift = 16, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON1, + .mono_shift = 27, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 3, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 22, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_MEMIF_MSB, + .msb_shift = 20, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_VUL2] = { + .name = "VUL2", + .id = MT8365_MEMIF_VUL2, + .reg_ofs_base = AFE_VUL_D2_BASE, + .reg_ofs_cur = AFE_VUL_D2_CUR, + .reg_ofs_end = AFE_VUL_D2_END, + .fs_reg = AFE_DAC_CON0, + .fs_shift = 20, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON0, + .mono_shift = 10, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 9, + .hd_reg = AFE_MEMIF_PBUF_SIZE, + .hd_shift = 14, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_MEMIF_MSB, + .msb_shift = 21, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_VUL3] = { + .name = "VUL3", + .id = MT8365_MEMIF_VUL3, + .reg_ofs_base = AFE_VUL3_BASE, + .reg_ofs_cur = AFE_VUL3_CUR, + .reg_ofs_end = AFE_VUL3_END, + .fs_reg = AFE_DAC_CON1, + .fs_shift = 8, + .fs_maskbit = 0xf, + .mono_reg = AFE_DAC_CON0, + .mono_shift = 13, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 12, + .hd_reg = AFE_MEMIF_PBUF2_SIZE, + .hd_shift = 10, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_MEMIF_MSB, + .msb_shift = 27, + .msb2_reg = -1, + .msb2_shift = 0, + }, + [MT8365_MEMIF_TDM_IN] = { + .name = "TDM_IN", + .id = MT8365_MEMIF_TDM_IN, + .reg_ofs_base = AFE_HDMI_IN_2CH_BASE, + .reg_ofs_cur = AFE_HDMI_IN_2CH_CUR, + .reg_ofs_end = AFE_HDMI_IN_2CH_END, + .fs_reg = -1, + .fs_shift = 0, + .fs_maskbit = 0, + .mono_reg = AFE_HDMI_IN_2CH_CON0, + .mono_shift = 1, + .enable_reg = AFE_HDMI_IN_2CH_CON0, + .enable_shift = 0, + .hd_reg = AFE_MEMIF_PBUF2_SIZE, + .hd_shift = 8, + .agent_disable_reg = -1, + .agent_disable_shift = 0, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_MEMIF_MSB, + .msb_shift = 28, + .msb2_reg = -1, + .msb2_shift = 0, + }, +}; + +struct mt8365_afe_rate { + unsigned int rate; + unsigned int reg_value; +}; + +static const struct mt8365_afe_rate mt8365_afe_rates[] = { + { + .rate = 8000, + .reg_value = 0, + }, + { + .rate = 11025, + .reg_value = 1, + }, + { + .rate = 12000, + .reg_value = 2, + }, + { + .rate = 16000, + .reg_value = 4, + }, + { + .rate = 22050, + .reg_value = 5, + }, + { + .rate = 24000, + .reg_value = 6, + }, + { + .rate = 32000, + .reg_value = 8, + }, + { + .rate = 44100, + .reg_value = 9, + }, + { + .rate = 48000, + .reg_value = 10, + }, + { + .rate = 88200, + .reg_value = 11, + }, + { + .rate = 96000, + .reg_value = 12, + }, + { + .rate = 176400, + .reg_value = 13, + }, + { + .rate = 192000, + .reg_value = 14, + }, +}; + +static unsigned int mt8365_afe_fs_timing(unsigned int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mt8365_afe_rates); i++) + if (mt8365_afe_rates[i].rate == rate) + return mt8365_afe_rates[i].reg_value; + + return -EINVAL; +} + +static unsigned int mt8365_afe_fs(unsigned int rate, int aud_blk) +{ + return mt8365_afe_fs_timing(rate); +} + +static unsigned int mt8365_afe2adsp_addr(unsigned int addr) +{ + /*TODO : Need apply the address remap */ + return addr; +} + +static unsigned int mt8365_adsp2afe_addr(unsigned int addr) +{ + /* TODO : Need apply the address remap */ + return addr; +} + +struct mtk_base_afe_platform mtk_afe_platform = { + .base_addr = AFE_REG_BASE, + .memif_datas = memif_data, + .memif_size = MT8365_MEMIF_NUM, + .memif_dl_num = MT8365_MEMIF_DL_NUM, + .memif_32bit_supported = 0, + .irq_datas = NULL, + .irqs_size = 0, + .dais_size = MT8365_DAI_NUM, + .afe2adsp_addr = mt8365_afe2adsp_addr, + .adsp2afe_addr = mt8365_adsp2afe_addr, + .afe_fs = mt8365_afe_fs, + .irq_fs = mt8365_afe_fs_timing, +}; diff --git a/src/platform/mt8365/include/platform/mt8365-afe-common.h b/src/platform/mt8365/include/platform/mt8365-afe-common.h new file mode 100644 index 000000000000..f597f6980da2 --- /dev/null +++ b/src/platform/mt8365/include/platform/mt8365-afe-common.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifndef _MT_8365_AFE_COMMON_H_ +#define _MT_8365_AFE_COMMON_H_ + +/* AFE: the abbreviation for Audio Front End */ + +enum { + MT8365_MEMIF_START, + MT8365_MEMIF_DL_START = MT8365_MEMIF_START, + MT8365_MEMIF_DL1 = MT8365_MEMIF_DL_START, + MT8365_MEMIF_DL2, + MT8365_MEMIF_TDM_OUT, + MT8365_MEMIF_DL_END, + MT8365_MEMIF_UL_START = MT8365_MEMIF_DL_END, + MT8365_MEMIF_AWB = MT8365_MEMIF_UL_START, + MT8365_MEMIF_VUL, + MT8365_MEMIF_VUL2, + MT8365_MEMIF_VUL3, + MT8365_MEMIF_TDM_IN, + MT8365_MEMIF_UL_END, + MT8365_MEMIF_END = MT8365_MEMIF_UL_END, + MT8365_MEMIF_DL_NUM = (MT8365_MEMIF_DL_END - MT8365_MEMIF_DL_START), + MT8365_MEMIF_UL_NUM = (MT8365_MEMIF_UL_END - MT8365_MEMIF_UL_START), + MT8365_MEMIF_NUM = (MT8365_MEMIF_END - MT8365_MEMIF_START), +}; + +enum { + MT8365_AFE_IRQ_1, + MT8365_AFE_IRQ_2, + MT8365_AFE_IRQ_3, + MT8365_AFE_IRQ_4, + MT8365_AFE_IRQ_5, + MT8365_AFE_IRQ_6, + MT8365_AFE_IRQ_7, + MT8365_AFE_IRQ_8, + MT8365_AFE_IRQ_9, + MT8365_AFE_IRQ_10, + MT8365_AFE_IRQ_NUM, +}; + +enum { + MT8365_AFE_IO_INT_ADDA_OUT, + MT8365_AFE_IO_2ND_I2S, + MT8365_AFE_IO_INT_ADDA_IN, + MT8365_AFE_IO_DMIC, + MT8365_DAI_NUM, +}; + +#endif /* _MT_8365_AFE_COMMON_H_ */ diff --git a/src/platform/mt8365/include/platform/mt8365-afe-regs.h b/src/platform/mt8365/include/platform/mt8365-afe-regs.h new file mode 100644 index 000000000000..8bd7163434dc --- /dev/null +++ b/src/platform/mt8365/include/platform/mt8365-afe-regs.h @@ -0,0 +1,1207 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#ifndef _MT8365_AFE_REGS_H_ +#define _MT8365_AFE_REGS_H_ + +#define AFE_REG_BASE 0x11220000 +#define AFE_REG_SIZE 0x1000 +#define AFE_SRAM_BASE 0x11221000 +#define AFE_SRAM_SIZE 0xA000 + +/***************************************************************************** + * R E G I S T E R D E F I N I T I O N + *****************************************************************************/ +#define AUDIO_TOP_CON0 (0x0000) +#define AUDIO_TOP_CON1 (0x0004) +#define AUDIO_TOP_CON2 (0x0008) +#define AUDIO_TOP_CON3 (0x000c) + +#define AFE_DAC_CON0 (0x0010) +#define AFE_DAC_CON1 (0x0014) +#define AFE_I2S_CON (0x0018) +#define AFE_CONN0 (0x0020) +#define AFE_CONN1 (0x0024) +#define AFE_CONN2 (0x0028) +#define AFE_CONN3 (0x002c) +#define AFE_CONN4 (0x0030) +#define AFE_I2S_CON1 (0x0034) +#define AFE_I2S_CON2 (0x0038) +#define AFE_MRGIF_CON (0x003c) +#define AFE_DL1_BASE (0x0040) +#define AFE_DL1_CUR (0x0044) +#define AFE_DL1_END (0x0048) +#define AFE_I2S_CON3 (0x004c) +#define AFE_DL2_BASE (0x0050) +#define AFE_DL2_CUR (0x0054) +#define AFE_DL2_END (0x0058) +#define AFE_CONN5 (0x005c) +#define AFE_AWB_BASE (0x0070) +#define AFE_AWB_END (0x0078) +#define AFE_AWB_CUR (0x007c) +#define AFE_VUL_BASE (0x0080) +#define AFE_VUL_END (0x0088) +#define AFE_VUL_CUR (0x008c) +#define AFE_CONN6 (0x00bc) +#define AFE_MEMIF_MSB (0x00cc) +#define AFE_MEMIF_MON0 (0x00d0) +#define AFE_MEMIF_MON1 (0x00d4) +#define AFE_MEMIF_MON2 (0x00d8) +#define AFE_MEMIF_MON3 (0x00dc) +#define AFE_MEMIF_MON4 (0x00e0) +#define AFE_MEMIF_MON5 (0x00e4) +#define AFE_MEMIF_MON6 (0x00e8) +#define AFE_MEMIF_MON7 (0x00ec) +#define AFE_MEMIF_MON8 (0x00f0) +#define AFE_MEMIF_MON9 (0x00f4) +#define AFE_MEMIF_MON10 (0x00f8) +#define AFE_MEMIF_MON11 (0x00fc) +#define AFE_ADDA_DL_SRC2_CON0 (0x0108) +#define AFE_ADDA_DL_SRC2_CON1 (0x010c) +#define AFE_ADDA_UL_SRC_CON0 (0x0114) +#define AFE_ADDA_UL_SRC_CON1 (0x0118) +#define AFE_ADDA_TOP_CON0 (0x0120) +#define AFE_ADDA_UL_DL_CON0 (0x0124) +#define AFE_ADDA_SRC_DEBUG (0x012c) +#define AFE_ADDA_SRC_DEBUG_MON0 (0x0130) +#define AFE_ADDA_SRC_DEBUG_MON1 (0x0134) +#define AFE_ADDA_UL_SRC_MON0 (0x0148) +#define AFE_ADDA_UL_SRC_MON1 (0x014c) +#define AFE_SRAM_BOUND (0x0170) +#define AFE_SECURE_CON (0x0174) +#define AFE_SECURE_CONN0 (0x0178) +#define AFE_SIDETONE_DEBUG (0x01d0) +#define AFE_SIDETONE_MON (0x01d4) +#define AFE_SIDETONE_CON0 (0x01e0) +#define AFE_SIDETONE_COEFF (0x01e4) +#define AFE_SIDETONE_CON1 (0x01e8) +#define AFE_SIDETONE_GAIN (0x01ec) +#define AFE_SGEN_CON0 (0x01f0) +#define AFE_SINEGEN_CON_TDM (0x01f8) +#define AFE_SINEGEN_CON_TDM_IN (0x01fc) +#define AFE_TOP_CON0 (0x0200) +#define AFE_BUS_CFG (0x0240) +#define AFE_BUS_MON0 (0x0244) +#define AFE_ADDA_PREDIS_CON0 (0x0260) +#define AFE_ADDA_PREDIS_CON1 (0x0264) +#define AFE_CONN_MON0 (0x0280) +#define AFE_CONN_MON1 (0x0284) +#define AFE_CONN_MON2 (0x0288) +#define AFE_CONN_MON3 (0x028c) +#define AFE_ADDA_IIR_COEF_02_01 (0x0290) +#define AFE_ADDA_IIR_COEF_04_03 (0x0294) +#define AFE_ADDA_IIR_COEF_06_05 (0x0298) +#define AFE_ADDA_IIR_COEF_08_07 (0x029c) +#define AFE_ADDA_IIR_COEF_10_09 (0x02a0) +#define AFE_VUL_D2_BASE (0x0350) +#define AFE_VUL_D2_END (0x0358) +#define AFE_VUL_D2_CUR (0x035c) +#define AFE_HDMI_OUT_CON0 (0x0370) +#define AFE_HDMI_OUT_BASE (0x0374) +#define AFE_HDMI_OUT_CUR (0x0378) +#define AFE_HDMI_OUT_END (0x037c) +#define AFE_SPDIF_OUT_CON0 (0x0380) +#define AFE_SPDIF_OUT_BASE (0x0384) +#define AFE_SPDIF_OUT_CUR (0x0388) +#define AFE_SPDIF_OUT_END (0x038c) +#define AFE_HDMI_CONN0 (0x0390) +#define AFE_HDMI_CONN1 (0x0398) +#define AFE_CONN_TDMIN_CON (0x039c) +#define AFE_IRQ_MCU_CON (0x03a0) +#define AFE_IRQ_MCU_STATUS (0x03a4) +#define AFE_IRQ_MCU_CLR (0x03a8) +#define AFE_IRQ_MCU_CNT1 (0x03ac) +#define AFE_IRQ_MCU_CNT2 (0x03b0) +#define AFE_IRQ_MCU_EN (0x03b4) +#define AFE_IRQ_MCU_MON2 (0x03b8) +#define AFE_IRQ_MCU_CNT5 (0x03bc) +#define AFE_IRQ1_MCU_CNT_MON (0x03c0) +#define AFE_IRQ2_MCU_CNT_MON (0x03c4) +#define AFE_IRQ1_MCU_EN_CNT_MON (0x03c8) +#define AFE_IRQ5_MCU_CNT_MON (0x03cc) +#define AFE_MEMIF_MINLEN (0x03d0) +#define AFE_MEMIF_MAXLEN (0x03d4) +#define AFE_MEMIF_PBUF_SIZE (0x03d8) +#define AFE_IRQ_MCU_CNT7 (0x03dc) +#define AFE_IRQ7_MCU_CNT_MON (0x03e0) +#define AFE_MEMIF_PBUF2_SIZE (0x03ec) +#define AFE_APLL_TUNER_CFG (0x03f0) +#define AFE_APLL_TUNER_CFG1 (0x03f4) +#define AFE_IRQ_MCU_CON2 (0x03f8) +#define IRQ13_MCU_CNT (0x0408) +#define IRQ13_MCU_CNT_MON (0x040c) +#define AFE_GAIN1_CON0 (0x0410) +#define AFE_GAIN1_CON1 (0x0414) +#define AFE_GAIN1_CON2 (0x0418) +#define AFE_GAIN1_CON3 (0x041c) +#define AFE_GAIN2_CON0 (0x0428) +#define AFE_GAIN2_CON1 (0x042c) +#define AFE_GAIN2_CON2 (0x0430) +#define AFE_GAIN2_CON3 (0x0434) +#define AFE_GAIN2_CUR (0x043c) +#define AFE_CONN11 (0x0448) +#define AFE_CONN12 (0x044c) +#define AFE_CONN13 (0x0450) +#define AFE_CONN14 (0x0454) +#define AFE_CONN15 (0x0458) +#define AFE_CONN16 (0x045c) +#define AFE_CONN7 (0x0460) +#define AFE_CONN8 (0x0464) +#define AFE_CONN9 (0x0468) +#define AFE_CONN10 (0x046c) +#define AFE_CONN21 (0x0470) +#define AFE_CONN22 (0x0474) +#define AFE_CONN23 (0x0478) +#define AFE_CONN24 (0x047c) +#define AFE_IEC_CFG (0x0480) +#define AFE_IEC_NSNUM (0x0484) +#define AFE_IEC_BURST_INFO (0x0488) +#define AFE_IEC_BURST_LEN (0x048c) +#define AFE_IEC_NSADR (0x0490) +#define AFE_CONN_RS (0x0494) +#define AFE_CONN_DI (0x0498) +#define AFE_IEC_CHL_STAT0 (0x04a0) +#define AFE_IEC_CHL_STAT1 (0x04a4) +#define AFE_IEC_CHR_STAT0 (0x04a8) +#define AFE_IEC_CHR_STAT1 (0x04ac) +#define AFE_CONN25 (0x04b0) +#define AFE_CONN26 (0x04b4) +#define FPGA_CFG2 (0x04b8) +#define FPGA_CFG3 (0x04bc) +#define FPGA_CFG0 (0x04c0) +#define FPGA_CFG1 (0x04c4) +#define AFE_SRAM_DELSEL_CON0 (0x04f0) +#define AFE_SRAM_DELSEL_CON1 (0x04f4) +#define AFE_SRAM_DELSEL_CON2 (0x04f8) +#define FPGA_CFG4 (0x04fc) +#define AFE_TDM_GASRC4_ASRC_2CH_CON0 (0x0500) +#define AFE_TDM_GASRC4_ASRC_2CH_CON1 (0x0504) +#define AFE_TDM_GASRC4_ASRC_2CH_CON2 (0x0508) +#define AFE_TDM_GASRC4_ASRC_2CH_CON3 (0x050c) +#define AFE_TDM_GASRC4_ASRC_2CH_CON4 (0x0510) +#define AFE_TDM_GASRC4_ASRC_2CH_CON5 (0x0514) +#define AFE_TDM_GASRC4_ASRC_2CH_CON6 (0x0518) +#define AFE_TDM_GASRC4_ASRC_2CH_CON7 (0x051c) +#define AFE_TDM_GASRC4_ASRC_2CH_CON8 (0x0520) +#define AFE_TDM_GASRC4_ASRC_2CH_CON9 (0x0524) +#define AFE_TDM_GASRC4_ASRC_2CH_CON10 (0x0528) +#define AFE_TDM_GASRC4_ASRC_2CH_CON12 (0x0530) +#define AFE_TDM_GASRC4_ASRC_2CH_CON13 (0x0534) +#define PCM_INTF_CON2 (0x0538) +#define PCM2_INTF_CON (0x053c) +#define AFE_APB_MON (0x0540) +#define AFE_CONN34 (0x0544) +#define AFE_TDM_CON1 (0x0548) +#define AFE_TDM_CON2 (0x054c) +#define PCM_INTF_CON1 (0x0550) +#define AFE_SECURE_MASK_CONN47_1 (0x0554) +#define AFE_SECURE_MASK_CONN48_1 (0x0558) +#define AFE_SECURE_MASK_CONN49_1 (0x055c) +#define AFE_SECURE_MASK_CONN50_1 (0x0560) +#define AFE_SECURE_MASK_CONN51_1 (0x0564) +#define AFE_SECURE_MASK_CONN52_1 (0x0568) +#define AFE_SECURE_MASK_CONN53_1 (0x056c) +#define AFE_SE_SECURE_CON (0x0570) +#define AFE_TDM_IN_CON1 (0x0588) +#define AFE_TDM_IN_CON2 (0x058c) +#define AFE_TDM_IN_MON1 (0x0590) +#define AFE_TDM_IN_MON2 (0x0594) +#define AFE_TDM_IN_MON3 (0x0598) +#define AFE_DMIC0_UL_SRC_CON0 (0x05b4) +#define AFE_DMIC0_UL_SRC_CON1 (0x05b8) +#define AFE_DMIC0_SRC_DEBUG (0x05bc) +#define AFE_DMIC0_SRC_DEBUG_MON0 (0x05c0) +#define AFE_DMIC0_UL_SRC_MON0 (0x05c8) +#define AFE_DMIC0_UL_SRC_MON1 (0x05cc) +#define AFE_DMIC0_IIR_COEF_02_01 (0x05d0) +#define AFE_DMIC0_IIR_COEF_04_03 (0x05d4) +#define AFE_DMIC0_IIR_COEF_06_05 (0x05d8) +#define AFE_DMIC0_IIR_COEF_08_07 (0x05dc) +#define AFE_DMIC0_IIR_COEF_10_09 (0x05e0) +#define AFE_DMIC1_UL_SRC_CON0 (0x0620) +#define AFE_DMIC1_UL_SRC_CON1 (0x0624) +#define AFE_DMIC1_SRC_DEBUG (0x0628) +#define AFE_DMIC1_SRC_DEBUG_MON0 (0x062c) +#define AFE_DMIC1_UL_SRC_MON0 (0x0634) +#define AFE_DMIC1_UL_SRC_MON1 (0x0638) +#define AFE_DMIC1_IIR_COEF_02_01 (0x063c) +#define AFE_DMIC1_IIR_COEF_04_03 (0x0640) +#define AFE_DMIC1_IIR_COEF_06_05 (0x0644) +#define AFE_DMIC1_IIR_COEF_08_07 (0x0648) +#define AFE_DMIC1_IIR_COEF_10_09 (0x064c) +#define AFE_SECURE_MASK_CONN39_1 (0x068c) +#define AFE_SECURE_MASK_CONN40_1 (0x0690) +#define AFE_SECURE_MASK_CONN41_1 (0x0694) +#define AFE_SECURE_MASK_CONN42_1 (0x0698) +#define AFE_SECURE_MASK_CONN43_1 (0x069c) +#define AFE_SECURE_MASK_CONN44_1 (0x06a0) +#define AFE_SECURE_MASK_CONN45_1 (0x06a4) +#define AFE_SECURE_MASK_CONN46_1 (0x06a8) +#define AFE_TDM_GASRC1_ASRC_2CH_CON0 (0x06c0) +#define AFE_TDM_GASRC1_ASRC_2CH_CON1 (0x06c4) +#define AFE_TDM_GASRC1_ASRC_2CH_CON2 (0x06c8) +#define AFE_TDM_GASRC1_ASRC_2CH_CON3 (0x06cc) +#define AFE_TDM_GASRC1_ASRC_2CH_CON4 (0x06d0) +#define AFE_TDM_GASRC1_ASRC_2CH_CON5 (0x06d4) +#define AFE_TDM_GASRC1_ASRC_2CH_CON6 (0x06d8) +#define AFE_TDM_GASRC1_ASRC_2CH_CON7 (0x06dc) +#define AFE_TDM_GASRC1_ASRC_2CH_CON8 (0x06e0) +#define AFE_TDM_GASRC1_ASRC_2CH_CON9 (0x06e4) +#define AFE_TDM_GASRC1_ASRC_2CH_CON10 (0x06e8) +#define AFE_TDM_GASRC1_ASRC_2CH_CON12 (0x06f0) +#define AFE_TDM_GASRC1_ASRC_2CH_CON13 (0x06f4) +#define AFE_TDM_ASRC_CON0 (0x06f8) +#define AFE_TDM_GASRC2_ASRC_2CH_CON0 (0x0700) +#define AFE_TDM_GASRC2_ASRC_2CH_CON1 (0x0704) +#define AFE_TDM_GASRC2_ASRC_2CH_CON2 (0x0708) +#define AFE_TDM_GASRC2_ASRC_2CH_CON3 (0x070c) +#define AFE_TDM_GASRC2_ASRC_2CH_CON4 (0x0710) +#define AFE_TDM_GASRC2_ASRC_2CH_CON5 (0x0714) +#define AFE_TDM_GASRC2_ASRC_2CH_CON6 (0x0718) +#define AFE_TDM_GASRC2_ASRC_2CH_CON7 (0x071c) +#define AFE_TDM_GASRC2_ASRC_2CH_CON8 (0x0720) +#define AFE_TDM_GASRC2_ASRC_2CH_CON9 (0x0724) +#define AFE_TDM_GASRC2_ASRC_2CH_CON10 (0x0728) +#define AFE_TDM_GASRC2_ASRC_2CH_CON12 (0x0730) +#define AFE_TDM_GASRC2_ASRC_2CH_CON13 (0x0734) +#define AFE_TDM_GASRC3_ASRC_2CH_CON0 (0x0740) +#define AFE_TDM_GASRC3_ASRC_2CH_CON1 (0x0744) +#define AFE_TDM_GASRC3_ASRC_2CH_CON2 (0x0748) +#define AFE_TDM_GASRC3_ASRC_2CH_CON3 (0x074c) +#define AFE_TDM_GASRC3_ASRC_2CH_CON4 (0x0750) +#define AFE_TDM_GASRC3_ASRC_2CH_CON5 (0x0754) +#define AFE_TDM_GASRC3_ASRC_2CH_CON6 (0x0758) +#define AFE_TDM_GASRC3_ASRC_2CH_CON7 (0x075c) +#define AFE_TDM_GASRC3_ASRC_2CH_CON8 (0x0760) +#define AFE_TDM_GASRC3_ASRC_2CH_CON9 (0x0764) +#define AFE_TDM_GASRC3_ASRC_2CH_CON10 (0x0768) +#define AFE_TDM_GASRC3_ASRC_2CH_CON12 (0x0770) +#define AFE_TDM_GASRC3_ASRC_2CH_CON13 (0x0774) +#define AFE_DMIC2_UL_SRC_CON0 (0x0780) +#define AFE_DMIC2_UL_SRC_CON1 (0x0784) +#define AFE_DMIC2_SRC_DEBUG (0x0788) +#define AFE_DMIC2_SRC_DEBUG_MON0 (0x078c) +#define AFE_DMIC2_UL_SRC_MON0 (0x0794) +#define AFE_DMIC2_UL_SRC_MON1 (0x0798) +#define AFE_DMIC2_IIR_COEF_02_01 (0x079c) +#define AFE_DMIC2_IIR_COEF_04_03 (0x07a0) +#define AFE_DMIC2_IIR_COEF_06_05 (0x07a4) +#define AFE_DMIC2_IIR_COEF_08_07 (0x07a8) +#define AFE_DMIC2_IIR_COEF_10_09 (0x07ac) +#define AFE_DMIC3_UL_SRC_CON0 (0x07ec) +#define AFE_DMIC3_UL_SRC_CON1 (0x07f0) +#define AFE_DMIC3_SRC_DEBUG (0x07f4) +#define AFE_DMIC3_SRC_DEBUG_MON0 (0x07f8) +#define AFE_DMIC3_UL_SRC_MON0 (0x0800) +#define AFE_DMIC3_UL_SRC_MON1 (0x0804) +#define AFE_DMIC3_IIR_COEF_02_01 (0x0808) +#define AFE_DMIC3_IIR_COEF_04_03 (0x080c) +#define AFE_DMIC3_IIR_COEF_06_05 (0x0810) +#define AFE_DMIC3_IIR_COEF_08_07 (0x0814) +#define AFE_DMIC3_IIR_COEF_10_09 (0x0818) +#define AFE_SECURE_MASK_CONN25_1 (0x0858) +#define AFE_SECURE_MASK_CONN26_1 (0x085c) +#define AFE_SECURE_MASK_CONN27_1 (0x0860) +#define AFE_SECURE_MASK_CONN28_1 (0x0864) +#define AFE_SECURE_MASK_CONN29_1 (0x0868) +#define AFE_SECURE_MASK_CONN30_1 (0x086c) +#define AFE_SECURE_MASK_CONN31_1 (0x0870) +#define AFE_SECURE_MASK_CONN32_1 (0x0874) +#define AFE_SECURE_MASK_CONN33_1 (0x0878) +#define AFE_SECURE_MASK_CONN34_1 (0x087c) +#define AFE_SECURE_MASK_CONN35_1 (0x0880) +#define AFE_SECURE_MASK_CONN36_1 (0x0884) +#define AFE_SECURE_MASK_CONN37_1 (0x0888) +#define AFE_SECURE_MASK_CONN38_1 (0x088c) +#define AFE_IRQ_MCU_SCP_EN (0x0890) +#define AFE_IRQ_MCU_DSP_EN (0x0894) +#define AFE_IRQ3_MCU_CNT_MON (0x0898) +#define AFE_IRQ4_MCU_CNT_MON (0x089c) +#define AFE_IRQ8_MCU_CNT_MON (0x08a0) +#define AFE_IRQ_MCU_CNT3 (0x08a4) +#define AFE_IRQ_MCU_CNT4 (0x08a8) +#define AFE_IRQ_MCU_CNT8 (0x08ac) +#define AFE_IRQ_MCU_CNT11 (0x08b0) +#define AFE_IRQ_MCU_CNT12 (0x08b4) +#define AFE_IRQ11_MCU_CNT_MON (0x08b8) +#define AFE_IRQ12_MCU_CNT_MON (0x08bc) +#define AFE_VUL3_BASE (0x08c0) +#define AFE_VUL3_CUR (0x08c4) +#define AFE_VUL3_END (0x08c8) +#define AFE_VUL3_BASE_MSB (0x08d0) +#define AFE_VUL3_END_MSB (0x08d4) +#define AFE_IRQ10_MCU_CNT_MON (0x08d8) +#define AFE_IRQ_MCU_CNT10 (0x08dc) +#define AFE_IRQ_ACC1_CNT (0x08e0) +#define AFE_IRQ_ACC2_CNT (0x08e4) +#define AFE_IRQ_ACC1_CNT_MON1 (0x08e8) +#define AFE_IRQ_ACC2_CNT_MON (0x08ec) +#define AFE_TSF_CON (0x08f0) +#define AFE_TSF_MON (0x08f4) +#define AFE_IRQ_ACC1_CNT_MON2 (0x08f8) +#define AFE_SPDIFIN_CFG0 (0x0900) +#define AFE_SPDIFIN_CFG1 (0x0904) +#define AFE_SPDIFIN_CHSTS1 (0x0908) +#define AFE_SPDIFIN_CHSTS2 (0x090c) +#define AFE_SPDIFIN_CHSTS3 (0x0910) +#define AFE_SPDIFIN_CHSTS4 (0x0914) +#define AFE_SPDIFIN_CHSTS5 (0x0918) +#define AFE_SPDIFIN_CHSTS6 (0x091c) +#define AFE_SPDIFIN_DEBUG1 (0x0920) +#define AFE_SPDIFIN_DEBUG2 (0x0924) +#define AFE_SPDIFIN_DEBUG3 (0x0928) +#define AFE_SPDIFIN_DEBUG4 (0x092c) +#define AFE_SPDIFIN_EC (0x0930) +#define AFE_SPDIFIN_CKLOCK_CFG (0x0934) +#define AFE_SPDIFIN_BR (0x093c) +#define AFE_SPDIFIN_BR_DBG1 (0x0940) +#define AFE_SPDIFIN_INT_EXT (0x0948) +#define AFE_SPDIFIN_INT_EXT2 (0x094c) +#define SPDIFIN_FREQ_INFO (0x0950) +#define SPDIFIN_FREQ_INFO_2 (0x0954) +#define SPDIFIN_FREQ_INFO_3 (0x0958) +#define SPDIFIN_FREQ_STATUS (0x095c) +#define SPDIFIN_USERCODE1 (0x0960) +#define SPDIFIN_USERCODE2 (0x0964) +#define SPDIFIN_USERCODE3 (0x0968) +#define SPDIFIN_USERCODE4 (0x096c) +#define SPDIFIN_USERCODE5 (0x0970) +#define SPDIFIN_USERCODE6 (0x0974) +#define SPDIFIN_USERCODE7 (0x0978) +#define SPDIFIN_USERCODE8 (0x097c) +#define SPDIFIN_USERCODE9 (0x0980) +#define SPDIFIN_USERCODE10 (0x0984) +#define SPDIFIN_USERCODE11 (0x0988) +#define SPDIFIN_USERCODE12 (0x098c) +#define SPDIFIN_MEMIF_CON0 (0x0990) +#define SPDIFIN_BASE_ADR (0x0994) +#define SPDIFIN_END_ADR (0x0998) +#define SPDIFIN_APLL_TUNER_CFG (0x09a0) +#define SPDIFIN_APLL_TUNER_CFG1 (0x09a4) +#define SPDIFIN_APLL2_TUNER_CFG (0x09a8) +#define SPDIFIN_APLL2_TUNER_CFG1 (0x09ac) +#define SPDIFIN_TYPE_DET (0x09b0) +#define MPHONE_MULTI_CON0 (0x09b4) +#define SPDIFIN_CUR_ADR (0x09b8) +#define AFE_SINEGEN_CON_SPDIFIN (0x09bc) +#define AFE_HDMI_IN_2CH_CON0 (0x09c0) +#define AFE_HDMI_IN_2CH_BASE (0x09c4) +#define AFE_HDMI_IN_2CH_END (0x09c8) +#define AFE_HDMI_IN_2CH_CUR (0x09cc) +#define AFE_MEMIF_BUF_MON0 (0x09d0) +#define AFE_MEMIF_BUF_MON1 (0x09d4) +#define AFE_MEMIF_BUF_MON2 (0x09d8) +#define AFE_MEMIF_BUF_MON3 (0x09dc) +#define AFE_MEMIF_BUF_MON6 (0x09e8) +#define AFE_MEMIF_BUF_MON7 (0x09ec) +#define AFE_MEMIF_BUF_MON8 (0x09f0) +#define AFE_MEMIF_BUF_MON10 (0x09f8) +#define AFE_MEMIF_BUF_MON11 (0x09fc) +#define SYSTOP_STC_CONFIG (0x0a00) +#define AUDIO_STC_STATUS (0x0a04) +#define SYSTOP_W_STC_H (0x0a08) +#define SYSTOP_W_STC_L (0x0a0c) +#define SYSTOP_R_STC_H (0x0a10) +#define SYSTOP_R_STC_L (0x0a14) +#define AUDIO_W_STC_H (0x0a18) +#define AUDIO_W_STC_L (0x0a1c) +#define AUDIO_R_STC_H (0x0a20) +#define AUDIO_R_STC_L (0x0a24) +#define SYSTOP_W_STC2_H (0x0a28) +#define SYSTOP_W_STC2_L (0x0a2c) +#define SYSTOP_R_STC2_H (0x0a30) +#define SYSTOP_R_STC2_L (0x0a34) +#define AUDIO_W_STC2_H (0x0a38) +#define AUDIO_W_STC2_L (0x0a3c) +#define AUDIO_R_STC2_H (0x0a40) +#define AUDIO_R_STC2_L (0x0a44) + +#define AFE_CONN17 (0x0a48) +#define AFE_CONN18 (0x0a4c) +#define AFE_CONN19 (0x0a50) +#define AFE_CONN20 (0x0a54) +#define AFE_CONN27 (0x0a58) +#define AFE_CONN28 (0x0a5c) +#define AFE_CONN29 (0x0a60) +#define AFE_CONN30 (0x0a64) +#define AFE_CONN31 (0x0a68) +#define AFE_CONN32 (0x0a6c) +#define AFE_CONN33 (0x0a70) +#define AFE_CONN35 (0x0a74) +#define AFE_CONN36 (0x0a78) +#define AFE_CONN37 (0x0a7c) +#define AFE_CONN38 (0x0a80) +#define AFE_CONN39 (0x0a84) +#define AFE_CONN40 (0x0a88) +#define AFE_CONN41 (0x0a8c) +#define AFE_CONN42 (0x0a90) +#define AFE_CONN44 (0x0a94) +#define AFE_CONN45 (0x0a98) +#define AFE_CONN46 (0x0a9c) +#define AFE_CONN47 (0x0aa0) +#define AFE_CONN_24BIT (0x0aa4) +#define AFE_CONN0_1 (0x0aa8) +#define AFE_CONN1_1 (0x0aac) +#define AFE_CONN2_1 (0x0ab0) +#define AFE_CONN3_1 (0x0ab4) +#define AFE_CONN4_1 (0x0ab8) +#define AFE_CONN5_1 (0x0abc) +#define AFE_CONN6_1 (0x0ac0) +#define AFE_CONN7_1 (0x0ac4) +#define AFE_CONN8_1 (0x0ac8) +#define AFE_CONN9_1 (0x0acc) +#define AFE_CONN10_1 (0x0ad0) +#define AFE_CONN11_1 (0x0ad4) +#define AFE_CONN12_1 (0x0ad8) +#define AFE_CONN13_1 (0x0adc) +#define AFE_CONN14_1 (0x0ae0) +#define AFE_CONN15_1 (0x0ae4) +#define AFE_CONN16_1 (0x0ae8) +#define AFE_CONN17_1 (0x0aec) +#define AFE_CONN18_1 (0x0af0) +#define AFE_CONN19_1 (0x0af4) +#define AFE_CONN43 (0x0af8) +#define AFE_CONN43_1 (0x0afc) +#define AFE_CONN21_1 (0x0b00) +#define AFE_CONN22_1 (0x0b04) +#define AFE_CONN23_1 (0x0b08) +#define AFE_CONN24_1 (0x0b0c) +#define AFE_CONN25_1 (0x0b10) +#define AFE_CONN26_1 (0x0b14) +#define AFE_CONN27_1 (0x0b18) +#define AFE_CONN28_1 (0x0b1c) +#define AFE_CONN29_1 (0x0b20) +#define AFE_CONN30_1 (0x0b24) +#define AFE_CONN31_1 (0x0b28) +#define AFE_CONN32_1 (0x0b2c) +#define AFE_CONN33_1 (0x0b30) +#define AFE_CONN34_1 (0x0b34) +#define AFE_CONN35_1 (0x0b38) +#define AFE_CONN36_1 (0x0b3c) +#define AFE_CONN37_1 (0x0b40) +#define AFE_CONN38_1 (0x0b44) +#define AFE_CONN39_1 (0x0b48) +#define AFE_CONN40_1 (0x0b4c) +#define AFE_CONN41_1 (0x0b50) +#define AFE_CONN42_1 (0x0b54) +#define AFE_CONN44_1 (0x0b58) +#define AFE_CONN45_1 (0x0b5c) +#define AFE_CONN46_1 (0x0b60) +#define AFE_CONN47_1 (0x0b64) +#define AFE_CONN_RS_1 (0x0b68) +#define AFE_CONN_DI_1 (0x0b6c) +#define AFE_CONN_24BIT_1 (0x0b70) +#define AFE_GAIN1_CUR (0x0b78) +#define AFE_CONN20_1 (0x0b7c) +#define AFE_DL1_BASE_MSB (0x0b80) +#define AFE_DL1_END_MSB (0x0b84) +#define AFE_DL2_BASE_MSB (0x0b88) +#define AFE_DL2_END_MSB (0x0b8c) +#define AFE_AWB_BASE_MSB (0x0b90) +#define AFE_AWB_END_MSB (0x0b94) +#define AFE_VUL_BASE_MSB (0x0ba0) +#define AFE_VUL_END_MSB (0x0ba4) +#define AFE_VUL_D2_BASE_MSB (0x0ba8) +#define AFE_VUL_D2_END_MSB (0x0bac) +#define AFE_HDMI_OUT_BASE_MSB (0x0bb8) +#define AFE_HDMI_OUT_END_MSB (0x0bbc) +#define AFE_HDMI_IN_2CH_BASE_MSB (0x0bc0) +#define AFE_HDMI_IN_2CH_END_MSB (0x0bc4) +#define AFE_SPDIF_OUT_BASE_MSB (0x0bc8) +#define AFE_SPDIF_OUT_END_MSB (0x0bcc) +#define SPDIFIN_BASE_MSB (0x0bd0) +#define SPDIFIN_END_MSB (0x0bd4) +#define AFE_DL1_CUR_MSB (0x0bd8) +#define AFE_DL2_CUR_MSB (0x0bdc) +#define AFE_AWB_CUR_MSB (0x0be8) +#define AFE_VUL_CUR_MSB (0x0bf8) +#define AFE_VUL_D2_CUR_MSB (0x0c04) +#define AFE_HDMI_OUT_CUR_MSB (0x0c0c) +#define AFE_HDMI_IN_2CH_CUR_MSB (0x0c10) +#define AFE_SPDIF_OUT_CUR_MSB (0x0c14) +#define SPDIFIN_CUR_MSB (0x0c18) +#define AFE_CONN_REG (0x0c20) +#define AFE_SECURE_MASK_CONN14_1 (0x0c24) +#define AFE_SECURE_MASK_CONN15_1 (0x0c28) +#define AFE_SECURE_MASK_CONN16_1 (0x0c2c) +#define AFE_SECURE_MASK_CONN17_1 (0x0c30) +#define AFE_SECURE_MASK_CONN18_1 (0x0c34) +#define AFE_SECURE_MASK_CONN19_1 (0x0c38) +#define AFE_SECURE_MASK_CONN20_1 (0x0c3c) +#define AFE_SECURE_MASK_CONN21_1 (0x0c40) +#define AFE_SECURE_MASK_CONN22_1 (0x0c44) +#define AFE_SECURE_MASK_CONN23_1 (0x0c48) +#define AFE_SECURE_MASK_CONN24_1 (0x0c4c) +#define AFE_ADDA_DL_SDM_DCCOMP_CON (0x0c50) +#define AFE_ADDA_DL_SDM_TEST (0x0c54) +#define AFE_ADDA_DL_DC_COMP_CFG0 (0x0c58) +#define AFE_ADDA_DL_DC_COMP_CFG1 (0x0c5c) +#define AFE_ADDA_DL_SDM_FIFO_MON (0x0c60) +#define AFE_ADDA_DL_SRC_LCH_MON (0x0c64) +#define AFE_ADDA_DL_SRC_RCH_MON (0x0c68) +#define AFE_ADDA_DL_SDM_OUT_MON (0x0c6c) +#define AFE_ADDA_DL_SDM_DITHER_CON (0x0c70) + +#define AFE_VUL3_CUR_MSB (0x0c78) +#define AFE_ASRC_2CH_CON0 (0x0c80) +#define AFE_ASRC_2CH_CON1 (0x0c84) +#define AFE_ASRC_2CH_CON2 (0x0c88) +#define AFE_ASRC_2CH_CON3 (0x0c8c) +#define AFE_ASRC_2CH_CON4 (0x0c90) +#define AFE_ASRC_2CH_CON5 (0x0c94) +#define AFE_ASRC_2CH_CON6 (0x0c98) +#define AFE_ASRC_2CH_CON7 (0x0c9c) +#define AFE_ASRC_2CH_CON8 (0x0ca0) +#define AFE_ASRC_2CH_CON9 (0x0ca4) +#define AFE_ASRC_2CH_CON10 (0x0ca8) +#define AFE_ASRC_2CH_CON12 (0x0cb0) +#define AFE_ASRC_2CH_CON13 (0x0cb4) + +#define AFE_PCM_TX_ASRC_2CH_CON0 (0x0cc0) +#define AFE_PCM_TX_ASRC_2CH_CON1 (0x0cc4) +#define AFE_PCM_TX_ASRC_2CH_CON2 (0x0cc8) +#define AFE_PCM_TX_ASRC_2CH_CON3 (0x0ccc) +#define AFE_PCM_TX_ASRC_2CH_CON4 (0x0cd0) +#define AFE_PCM_TX_ASRC_2CH_CON5 (0x0cd4) +#define AFE_PCM_TX_ASRC_2CH_CON6 (0x0cd8) +#define AFE_PCM_TX_ASRC_2CH_CON7 (0x0cdc) +#define AFE_PCM_TX_ASRC_2CH_CON8 (0x0ce0) +#define AFE_PCM_TX_ASRC_2CH_CON9 (0x0ce4) +#define AFE_PCM_TX_ASRC_2CH_CON10 (0x0ce8) +#define AFE_PCM_TX_ASRC_2CH_CON12 (0x0cf0) +#define AFE_PCM_TX_ASRC_2CH_CON13 (0x0cf4) +#define AFE_PCM_RX_ASRC_2CH_CON0 (0x0d00) +#define AFE_PCM_RX_ASRC_2CH_CON1 (0x0d04) +#define AFE_PCM_RX_ASRC_2CH_CON2 (0x0d08) +#define AFE_PCM_RX_ASRC_2CH_CON3 (0x0d0c) +#define AFE_PCM_RX_ASRC_2CH_CON4 (0x0d10) +#define AFE_PCM_RX_ASRC_2CH_CON5 (0x0d14) +#define AFE_PCM_RX_ASRC_2CH_CON6 (0x0d18) +#define AFE_PCM_RX_ASRC_2CH_CON7 (0x0d1c) +#define AFE_PCM_RX_ASRC_2CH_CON8 (0x0d20) +#define AFE_PCM_RX_ASRC_2CH_CON9 (0x0d24) +#define AFE_PCM_RX_ASRC_2CH_CON10 (0x0d28) +#define AFE_PCM_RX_ASRC_2CH_CON12 (0x0d30) +#define AFE_PCM_RX_ASRC_2CH_CON13 (0x0d34) + +#define AFE_ADDA_PREDIS_CON2 (0x0d40) +#define AFE_ADDA_PREDIS_CON3 (0x0d44) +#define AFE_SECURE_MASK_CONN4_1 (0x0d48) +#define AFE_SECURE_MASK_CONN5_1 (0x0d4c) +#define AFE_SECURE_MASK_CONN6_1 (0x0d50) +#define AFE_SECURE_MASK_CONN7_1 (0x0d54) +#define AFE_SECURE_MASK_CONN8_1 (0x0d58) +#define AFE_SECURE_MASK_CONN9_1 (0x0d5c) +#define AFE_SECURE_MASK_CONN10_1 (0x0d60) +#define AFE_SECURE_MASK_CONN11_1 (0x0d64) +#define AFE_SECURE_MASK_CONN12_1 (0x0d68) +#define AFE_SECURE_MASK_CONN13_1 (0x0d6c) +#define AFE_MEMIF_MON12 (0x0d70) +#define AFE_MEMIF_MON13 (0x0d74) +#define AFE_MEMIF_MON14 (0x0d78) +#define AFE_MEMIF_MON15 (0x0d7c) +#define AFE_SECURE_MASK_CONN42 (0x0dbc) +#define AFE_SECURE_MASK_CONN43 (0x0dc0) +#define AFE_SECURE_MASK_CONN44 (0x0dc4) +#define AFE_SECURE_MASK_CONN45 (0x0dc8) +#define AFE_SECURE_MASK_CONN46 (0x0dcc) +#define AFE_HD_ENGEN_ENABLE (0x0dd0) +#define AFE_SECURE_MASK_CONN47 (0x0dd4) +#define AFE_SECURE_MASK_CONN48 (0x0dd8) +#define AFE_SECURE_MASK_CONN49 (0x0ddc) +#define AFE_SECURE_MASK_CONN50 (0x0de0) +#define AFE_SECURE_MASK_CONN51 (0x0de4) +#define AFE_SECURE_MASK_CONN52 (0x0de8) +#define AFE_SECURE_MASK_CONN53 (0x0dec) +#define AFE_SECURE_MASK_CONN0_1 (0x0df0) +#define AFE_SECURE_MASK_CONN1_1 (0x0df4) +#define AFE_SECURE_MASK_CONN2_1 (0x0df8) +#define AFE_SECURE_MASK_CONN3_1 (0x0dfc) + +#define AFE_ADDA_MTKAIF_CFG0 (0x0e00) +#define AFE_ADDA_MTKAIF_SYNCWORD_CFG (0x0e14) +#define AFE_ADDA_MTKAIF_RX_CFG0 (0x0e20) +#define AFE_ADDA_MTKAIF_RX_CFG1 (0x0e24) +#define AFE_ADDA_MTKAIF_RX_CFG2 (0x0e28) +#define AFE_ADDA_MTKAIF_MON0 (0x0e34) +#define AFE_ADDA_MTKAIF_MON1 (0x0e38) +#define AFE_AUD_PAD_TOP (0x0e40) + +#define AFE_CM1_CON4 (0x0e48) +#define AFE_CM2_CON4 (0x0e4c) +#define AFE_CM1_CON0 (0x0e50) +#define AFE_CM1_CON1 (0x0e54) +#define AFE_CM1_CON2 (0x0e58) +#define AFE_CM1_CON3 (0x0e5c) +#define AFE_CM2_CON0 (0x0e60) +#define AFE_CM2_CON1 (0x0e64) +#define AFE_CM2_CON2 (0x0e68) +#define AFE_CM2_CON3 (0x0e6c) +#define AFE_CM2_CONN0 (0x0e70) +#define AFE_CM2_CONN1 (0x0e74) +#define AFE_CM2_CONN2 (0x0e78) + +#define AFE_GENERAL1_ASRC_2CH_CON0 (0x0e80) +#define AFE_GENERAL1_ASRC_2CH_CON1 (0x0e84) +#define AFE_GENERAL1_ASRC_2CH_CON2 (0x0e88) +#define AFE_GENERAL1_ASRC_2CH_CON3 (0x0e8c) +#define AFE_GENERAL1_ASRC_2CH_CON4 (0x0e90) +#define AFE_GENERAL1_ASRC_2CH_CON5 (0x0e94) +#define AFE_GENERAL1_ASRC_2CH_CON6 (0x0e98) +#define AFE_GENERAL1_ASRC_2CH_CON7 (0x0e9c) +#define AFE_GENERAL1_ASRC_2CH_CON8 (0x0ea0) +#define AFE_GENERAL1_ASRC_2CH_CON9 (0x0ea4) +#define AFE_GENERAL1_ASRC_2CH_CON10 (0x0ea8) +#define AFE_GENERAL1_ASRC_2CH_CON12 (0x0eb0) +#define AFE_GENERAL1_ASRC_2CH_CON13 (0x0eb4) +#define GENERAL_ASRC_MODE (0x0eb8) +#define GENERAL_ASRC_EN_ON (0x0ebc) + +#define AFE_CONN48 (0x0ec0) +#define AFE_CONN49 (0x0ec4) +#define AFE_CONN50 (0x0ec8) +#define AFE_CONN51 (0x0ecc) +#define AFE_CONN52 (0x0ed0) +#define AFE_CONN53 (0x0ed4) +#define AFE_CONN48_1 (0x0ee0) +#define AFE_CONN49_1 (0x0ee4) +#define AFE_CONN50_1 (0x0ee8) +#define AFE_CONN51_1 (0x0eec) +#define AFE_CONN52_1 (0x0ef0) +#define AFE_CONN53_1 (0x0ef4) + +#define AFE_GENERAL2_ASRC_2CH_CON0 (0x0f00) +#define AFE_GENERAL2_ASRC_2CH_CON1 (0x0f04) +#define AFE_GENERAL2_ASRC_2CH_CON2 (0x0f08) +#define AFE_GENERAL2_ASRC_2CH_CON3 (0x0f0c) +#define AFE_GENERAL2_ASRC_2CH_CON4 (0x0f10) +#define AFE_GENERAL2_ASRC_2CH_CON5 (0x0f14) +#define AFE_GENERAL2_ASRC_2CH_CON6 (0x0f18) +#define AFE_GENERAL2_ASRC_2CH_CON7 (0x0f1c) +#define AFE_GENERAL2_ASRC_2CH_CON8 (0x0f20) +#define AFE_GENERAL2_ASRC_2CH_CON9 (0x0f24) +#define AFE_GENERAL2_ASRC_2CH_CON10 (0x0f28) +#define AFE_GENERAL2_ASRC_2CH_CON12 (0x0f30) +#define AFE_GENERAL2_ASRC_2CH_CON13 (0x0f34) + +#define AFE_SECURE_MASK_CONN28 (0x0f48) +#define AFE_SECURE_MASK_CONN29 (0x0f4c) +#define AFE_SECURE_MASK_CONN30 (0x0f50) +#define AFE_SECURE_MASK_CONN31 (0x0f54) +#define AFE_SECURE_MASK_CONN32 (0x0f58) +#define AFE_SECURE_MASK_CONN33 (0x0f5c) +#define AFE_SECURE_MASK_CONN34 (0x0f60) +#define AFE_SECURE_MASK_CONN35 (0x0f64) +#define AFE_SECURE_MASK_CONN36 (0x0f68) +#define AFE_SECURE_MASK_CONN37 (0x0f6c) +#define AFE_SECURE_MASK_CONN38 (0x0f70) +#define AFE_SECURE_MASK_CONN39 (0x0f74) +#define AFE_SECURE_MASK_CONN40 (0x0f78) +#define AFE_SECURE_MASK_CONN41 (0x0f7c) +#define AFE_SIDEBAND0 (0x0f80) +#define AFE_SIDEBAND1 (0x0f84) +#define AFE_SECURE_SIDEBAND0 (0x0f88) +#define AFE_SECURE_SIDEBAND1 (0x0f8c) +#define AFE_SECURE_MASK_CONN0 (0x0f90) +#define AFE_SECURE_MASK_CONN1 (0x0f94) +#define AFE_SECURE_MASK_CONN2 (0x0f98) +#define AFE_SECURE_MASK_CONN3 (0x0f9c) +#define AFE_SECURE_MASK_CONN4 (0x0fa0) +#define AFE_SECURE_MASK_CONN5 (0x0fa4) +#define AFE_SECURE_MASK_CONN6 (0x0fa8) +#define AFE_SECURE_MASK_CONN7 (0x0fac) +#define AFE_SECURE_MASK_CONN8 (0x0fb0) +#define AFE_SECURE_MASK_CONN9 (0x0fb4) +#define AFE_SECURE_MASK_CONN10 (0x0fb8) +#define AFE_SECURE_MASK_CONN11 (0x0fbc) +#define AFE_SECURE_MASK_CONN12 (0x0fc0) +#define AFE_SECURE_MASK_CONN13 (0x0fc4) +#define AFE_SECURE_MASK_CONN14 (0x0fc8) +#define AFE_SECURE_MASK_CONN15 (0x0fcc) +#define AFE_SECURE_MASK_CONN16 (0x0fd0) +#define AFE_SECURE_MASK_CONN17 (0x0fd4) +#define AFE_SECURE_MASK_CONN18 (0x0fd8) +#define AFE_SECURE_MASK_CONN19 (0x0fdc) +#define AFE_SECURE_MASK_CONN20 (0x0fe0) +#define AFE_SECURE_MASK_CONN21 (0x0fe4) +#define AFE_SECURE_MASK_CONN22 (0x0fe8) +#define AFE_SECURE_MASK_CONN23 (0x0fec) +#define AFE_SECURE_MASK_CONN24 (0x0ff0) +#define AFE_SECURE_MASK_CONN25 (0x0ff4) +#define AFE_SECURE_MASK_CONN26 (0x0ff8) +#define AFE_SECURE_MASK_CONN27 (0x0ffc) + +#define MAX_REGISTER AFE_SECURE_MASK_CONN27 + +#define AFE_IRQ_STATUS_BITS 0x3ff + +/* AUDIO_TOP_CON0 (0x0000) */ +#define AUD_TCON0_PDN_TML BIT(27) +#define AUD_TCON0_PDN_DAC_PREDIS BIT(26) +#define AUD_TCON0_PDN_DAC BIT(25) +#define AUD_TCON0_PDN_ADC BIT(24) +#define AUD_TCON0_PDN_TDM_IN BIT(23) +#define AUD_TCON0_PDN_TDM_OUT BIT(22) +#define AUD_TCON0_PDN_SPDIF BIT(21) +#define AUD_TCON0_PDN_APLL_TUNER BIT(19) +#define AUD_TCON0_PDN_APLL2_TUNER BIT(18) +#define AUD_TCON0_PDN_INTDIR BIT(15) +#define AUD_TCON0_PDN_24M BIT(9) +#define AUD_TCON0_PDN_22M BIT(8) +#define AUD_TCON0_PDN_I2S_IN BIT(6) +#define AUD_TCON0_PDN_AFE BIT(2) + +/* AUDIO_TOP_CON1 (0x0004) */ +#define AUD_TCON1_PDN_TDM_ASRC BIT(15) +#define AUD_TCON1_PDN_GENERAL2_ASRC BIT(14) +#define AUD_TCON1_PDN_GENERAL1_ASRC BIT(13) +#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC BIT(12) +#define AUD_TCON1_PDN_DMIC3_ADC BIT(11) +#define AUD_TCON1_PDN_DMIC2_ADC BIT(10) +#define AUD_TCON1_PDN_DMIC1_ADC BIT(9) +#define AUD_TCON1_PDN_DMIC0_ADC BIT(8) +#define AUD_TCON1_PDN_I2S4_BCLK BIT(7) +#define AUD_TCON1_PDN_I2S3_BCLK BIT(6) +#define AUD_TCON1_PDN_I2S2_BCLK BIT(5) +#define AUD_TCON1_PDN_I2S1_BCLK BIT(4) + +/* AUDIO_TOP_CON3 (0x000C) */ +#define AUD_TCON3_HDMI_BCK_INV BIT(3) + +/* AFE_I2S_CON (0x0018) */ +#define AFE_I2S_CON_PHASE_SHIFT_FIX BIT(31) +#define AFE_I2S_CON_FROM_IO_MUX BIT(28) +#define AFE_I2S_CON_LOW_JITTER_CLK BIT(12) +#define AFE_I2S_CON_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON_FORMAT_I2S BIT(3) +#define AFE_I2S_CON_SRC_SLAVE BIT(2) + +/* AFE_ASRC_2CH_CON0 */ +#define ONE_HEART_MASK (0x1 << 31) +#define CHSET_STR_CLR (0x1<<4) +#define ASM_ON_MASK (0x1<<0) +#define ASM_ON (0x1<<0) + +/* CON2 */ +#define O16BIT_MASK (0x1<<19) +#define CLR_IIR_HISTORY_MASK (0x1<<17) +#define CLR_IIR_HISTORY (0x1<<17) +#define IS_MONO_MASK (0x1<<16) +#define IIR_EN_MASK (0x1<<11) +#define IIR_EN (0x1<<11) +#define IIR_DIS (0x0<<11) +#define IIR_STAGE_MASK (0x7<<8) +#define IIR_STAGE_8 (0x7<<8) + +/* CON5 */ +#define CALI_CYCLE_MASK (0xFFFF << 16) +#define CALI_64_CYCLE (0x3F << 16) +#define CALI_96_CYCLE (0x5F << 16) +#define CALI_441_CYCLE (0x1B8 << 16) + +#define CALI_AUTORST_MASK (0x1 << 15) +#define CALI_AUTORST_ENABLE (0x1 << 15) +#define CALI_AUTORST_DISABLE (0x0 << 15) + +#define AUTO_TUNE_FREQ5_MASK (0x1 << 12) +#define AUTO_TUNE_FREQ5_ENABLE (0x1 << 12) +#define AUTO_TUNE_FREQ5_DISABLE (0x0 << 12) + +#define COMP_FREQ_RES_MASK (0x1 << 11) +#define COMP_FREQ_RES_ENABLE (0x1 << 11) + +#define CALI_SEL_MASK (0x3 << 8) +#define CALI_SEL_00 (0x0 << 8) +#define CALI_SEL_01 (0x1 << 8) + +#define CALI_BP_DGL_MASK (0x1 << 7) +#define CALI_BP_DGL_BYPASS (0x1 << 7) + +#define AUTO_TUNE_FREQ4_MASK (0x1 << 3) +#define AUTO_TUNE_FREQ4_ENABLE (0x1 << 3) +#define AUTO_TUNE_FREQ4_DISABLE (0x0 << 3) + +#define CALI_AUTO_RESTART_MASK (0x1 << 2) +#define CALI_AUTO_RESTART_ENABLE (0x1 << 2) + +#define CALI_USE_FREQ_OUT_MASK (0x1 << 1) +#define CALI_USE_FREQ (0x1 << 1) +#define CALI_USE_PERIOD (0x0 << 1) + +#define CALI_ON_MASK (0x1 << 0) +#define CALI_ON (0x1 << 0) +#define CALI_OFF (0x0 << 0) + + +#define AFE_I2S_CON_WLEN_32BIT BIT(1) +#define AFE_I2S_CON_EN BIT(0) + +#define AFE_CONN3_I03_O03_S BIT(3) +#define AFE_CONN4_I04_O04_S BIT(4) +#define AFE_CONN4_I03_O04_S BIT(3) + +/* AFE_I2S_CON1 (0x0034) */ +#define AFE_I2S_CON1_I2S2_TO_PAD (1 << 18) +#define AFE_I2S_CON1_TDMOUT_TO_PAD (0 << 18) +#define AFE_I2S_CON1_TDMOUT_MUX_MASK GENMASK(18, 18) +#define AFE_I2S_CON1_LOW_JITTER_CLK BIT(12) +#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON1_FORMAT_I2S BIT(3) +#define AFE_I2S_CON1_WLEN_32BIT BIT(1) +#define AFE_I2S_CON1_EN BIT(0) + +/* AFE_I2S_CON2 (0x0038) */ +#define AFE_I2S_CON2_LOW_JITTER_CLK BIT(12) +#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON2_FORMAT_I2S BIT(3) +#define AFE_I2S_CON2_WLEN_32BIT BIT(1) +#define AFE_I2S_CON2_EN BIT(0) + +/* AFE_I2S_CON3 (0x004C) */ +#define AFE_I2S_CON3_LOW_JITTER_CLK BIT(12) +#define AFE_I2S_CON3_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON3_FORMAT_I2S BIT(3) +#define AFE_I2S_CON3_WLEN_32BIT BIT(1) +#define AFE_I2S_CON3_EN BIT(0) + +/* AFE_ADDA_DL_SRC2_CON0 (0x0108) */ +#define AFE_ADDA_DL_8X_UPSAMPLE (BIT(25) | BIT(24)) +#define AFE_ADDA_DL_MUTE_OFF (BIT(12) | BIT(11)) +#define AFE_ADDA_DL_VOICE_DATA BIT(5) +#define AFE_ADDA_DL_DEGRADE_GAIN BIT(1) + +/* AFE_ADDA_UL_DL_CON0 */ +#define AFE_ADDA_UL_DL_ADDA_AFE_ON_MASK BIT(0) +#define AFE_ADDA_UL_DL_ADDA_AFE_ON (1 << 0) +#define AFE_ADDA_UL_DL_ADDA_AFE_OFF (0 << 0) +#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON_MASK BIT(1) +#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON (1 << 1) +#define AFE_ADDA_UL_DL_DMIC_CLKDIV_OFF (0 << 1) + +/* AFE_SINEGEN_CON0 (0x01f0) */ +#define AFE_SINEGEN_CON0_EN BIT(26) +#define AFE_SINEGEN_CON0_IN_OUT_SEL BIT(27) +#define AFE_SINEGEN_CON0_MODE_MASK GENMASK(31, 28) +#define AFE_SINEGEN_CON0_AMP_DIV_CH2_MASK GENMASK(19, 17) +#define AFE_SINEGEN_CON0_AMP_DIV_CH1_MASK GENMASK(7, 5) +#define AFE_SINEGEN_CON0_AMP_DIV_CH2(x) (((x) & 0x7) << 17) +#define AFE_SINEGEN_CON0_AMP_DIV_CH1(x) (((x) & 0x7) << 5) +#define AFE_SINEGEN_CON0_FREQ_DIV_CH2_MASK GENMASK(16, 12) +#define AFE_SINEGEN_CON0_FREQ_DIV_CH1_MASK GENMASK(4, 0) +#define AFE_SINEGEN_CON0_FREQ_DIV_CH2(x) (((x) & 0x1f) << 12) +#define AFE_SINEGEN_CON0_FREQ_DIV_CH1(x) (((x) & 0x1f) << 0) +#define AFE_SINEGEN_CON0_TIMING_CH2_MASK GENMASK(23, 20) +#define AFE_SINEGEN_CON0_TIMING_CH1_MASK GENMASK(11, 8) +#define AFE_SINEGEN_CON0_TIMING_CH2(x) (((x) & 0xf) << 20) +#define AFE_SINEGEN_CON0_TIMING_CH1(x) (((x) & 0xf) << 8) +#define AFE_SINEGEN_CON0_TIMING_8K (0) +#define AFE_SINEGEN_CON0_TIMING_11D025K (1) +#define AFE_SINEGEN_CON0_TIMING_12K (2) +#define AFE_SINEGEN_CON0_TIMING_16K (4) +#define AFE_SINEGEN_CON0_TIMING_22D05K (5) +#define AFE_SINEGEN_CON0_TIMING_24K (6) +#define AFE_SINEGEN_CON0_TIMING_32K (8) +#define AFE_SINEGEN_CON0_TIMING_44D1K (9) +#define AFE_SINEGEN_CON0_TIMING_48K (10) +#define AFE_SINEGEN_CON0_TIMING_88D2K (11) +#define AFE_SINEGEN_CON0_TIMING_96K (12) +#define AFE_SINEGEN_CON0_TIMING_176D4K (13) +#define AFE_SINEGEN_CON0_TIMING_192K (14) + +/* AFE_HDMI_OUT_CON0 (0x0370) */ +#define AFE_HDMI_OUT_CON0_CH_MASK GENMASK(7, 4) + +/* AFE_HDMI_CONN0 (0x0390) */ +#define AFE_HDMI_CONN0_O35_I35 (0x7 << 21) +#define AFE_HDMI_CONN0_O34_I34 (0x6 << 18) +#define AFE_HDMI_CONN0_O33_I33 (0x5 << 15) +#define AFE_HDMI_CONN0_O32_I32 (0x4 << 12) +#define AFE_HDMI_CONN0_O31_I30 (0x2 << 9) +#define AFE_HDMI_CONN0_O31_I31 (0x3 << 9) +#define AFE_HDMI_CONN0_O30_I31 (0x3 << 6) +#define AFE_HDMI_CONN0_O30_I30 (0x2 << 6) +#define AFE_HDMI_CONN0_O29_I29 (0x1 << 3) +#define AFE_HDMI_CONN0_O28_I28 (0x0 << 0) + +/* AFE_CONN_TDMIN_CON (0x039c) */ +#define AFE_CONN_TDMIN_O41_I41 (0x1 << 3) +#define AFE_CONN_TDMIN_O41_I40 (0x0 << 3) +#define AFE_CONN_TDMIN_O40_I41 (0x1 << 0) +#define AFE_CONN_TDMIN_O40_I40 (0x0 << 0) +#define AFE_CONN_TDMIN_CON0_MASK GENMASK(5, 0) + +/* AFE_APLL_TUNER_CFG (0x03f0) */ +#define AFE_APLL_TUNER_CFG_MASK GENMASK(15, 1) +#define AFE_APLL_TUNER_CFG_EN_MASK GENMASK(0, 0) + +/* AFE_APLL_TUNER_CFG1 (0x03f4) */ +#define AFE_APLL_TUNER_CFG1_MASK GENMASK(15, 1) +#define AFE_APLL_TUNER_CFG1_EN_MASK GENMASK(0, 0) + +/* AFE_TDM_CON1 (0x0548) */ +#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) +#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12) +#define AFE_TDM_CON1_16_BCK_CYCLES (0x0 << 12) +#define AFE_TDM_CON1_8CH_PER_SDATA (0x2 << 10) +#define AFE_TDM_CON1_4CH_PER_SDATA (0x1 << 10) +#define AFE_TDM_CON1_2CH_PER_SDATA (0x0 << 10) +#define AFE_TDM_CON1_WLEN_32BIT BIT(9) +#define AFE_TDM_CON1_WLEN_16BIT BIT(8) +#define AFE_TDM_CON1_MSB_ALIGNED BIT(4) +#define AFE_TDM_CON1_1_BCK_DELAY BIT(3) +#define AFE_TDM_CON1_LRCK_INV BIT(2) +#define AFE_TDM_CON1_EN BIT(0) + +/* AFE_TDM_CON2 (0x054c) */ +#define AFE_TDM_CON2_SOUT_MASK GENMASK(14, 0) + +/* PCM_INTF_CON1 (0x0550) */ +#define PCM_INTF_CON1_EXT_MODEM (1 << 17) +#define PCM_INTF_CON1_16BIT (0 << 16) +#define PCM_INTF_CON1_24BIT (1 << 16) +#define PCM_INTF_CON1_32BCK (0 << 14) +#define PCM_INTF_CON1_64BCK (1 << 14) +#define PCM_INTF_CON1_MASTER_MODE (0 << 5) +#define PCM_INTF_CON1_SLAVE_MODE (1 << 5) +#define PCM_INTF_CON1_FS_8K (0 << 3) +#define PCM_INTF_CON1_FS_16K (1 << 3) +#define PCM_INTF_CON1_FS_32K (2 << 3) +#define PCM_INTF_CON1_FS_48K (3 << 3) +#define PCM_INTF_CON1_SYNC_LEN(x) (((x) - 1) << 9) +#define PCM_INTF_CON1_FORMAT(x) ((x) << 1) +#define PCM_INTF_CON1_SYNC_OUT_INV BIT(23) +#define PCM_INTF_CON1_BCLK_OUT_INV BIT(22) +#define PCM_INTF_CON1_SYNC_IN_INV BIT(21) +#define PCM_INTF_CON1_BCLK_IN_INV BIT(20) +#define PCM_INTF_CON1_BYPASS_ASRC BIT(6) +#define PCM_INTF_CON1_EN BIT(0) +#define PCM_INTF_CON1_CONFIG_MASK (0xf3fffe) + +/* AFE_TDM_IN_CON1 (0x0588) */ +#define AFE_TDM_IN_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) +#define AFE_TDM_IN_CON1_FAST_LRCK_CYCLE_32BCK (0x2 << 16) +#define AFE_TDM_IN_CON1_FAST_LRCK_CYCLE_16BCK (0x0 << 16) +#define AFE_TDM_IN_CON1_8CH_PER_SDATA (0x2 << 12) +#define AFE_TDM_IN_CON1_4CH_PER_SDATA (0x1 << 12) +#define AFE_TDM_IN_CON1_2CH_PER_SDATA (0x0 << 12) +#define AFE_TDM_IN_CON1_WLEN_32BIT (0x3 << 8) +#define AFE_TDM_IN_CON1_WLEN_24BIT (0x2 << 8) +#define AFE_TDM_IN_CON1_WLEN_16BIT (0x1 << 8) +#define AFE_TDM_IN_CON1_I2S BIT(3) +#define AFE_TDM_IN_CON1_LRCK_INV BIT(2) +#define AFE_TDM_IN_CON1_BCK_INV BIT(1) +#define AFE_TDM_IN_CON1_EN BIT(0) + +/* AFE_TDM_IN_CON2 (0x058c) */ +#define AFE_TDM_IN_CON2_DISABLE_CH01 BIT(0) +#define AFE_TDM_IN_CON2_DISABLE_CH23 BIT(1) +#define AFE_TDM_IN_CON2_DISABLE_CH45 BIT(2) +#define AFE_TDM_IN_CON2_DISABLE_CH67 BIT(3) + +/* AFE_DMIC0_UL_SRC_CON0 (0x05b4) + * AFE_DMIC0_UL_SRC_CON0 (0x0620) + * AFE_DMIC0_UL_SRC_CON0 (0x0780) + * AFE_DMIC0_UL_SRC_CON0 (0x07ec) + */ +#define DMIC_TOP_CON_DMIC_TWO_WIRE_MODE BIT(23) +#define DMIC_TOP_CON_DMIC_CK_PHASE_SEL_CH2(x) ((x) << 24) +#define DMIC_TOP_CON_DMIC_CK_PHASE_SEL_CH1(x) ((x) << 27) +#define DMIC_TOP_CON_DMIC_CH2_ON_MASK BIT(22) +#define DMIC_TOP_CON_DMIC_CH2_ON (1 << 22) +#define DMIC_TOP_CON_DMIC_CH2_OFF (0 << 22) +#define DMIC_TOP_CON_DMIC_CH1_ON_MASK BIT(21) +#define DMIC_TOP_CON_DMIC_CH1_ON (1 << 21) +#define DMIC_TOP_CON_DMIC_CH1_OFF (0 << 21) +#define DMIC_TOP_CON_DMIC_VOICE_MODE_8K (0 << 17) +#define DMIC_TOP_CON_DMIC_VOICE_MODE_16K (1 << 17) +#define DMIC_TOP_CON_DMIC_VOICE_MODE_32K (2 << 17) +#define DMIC_TOP_CON_DMIC_VOICE_MODE_48K (3 << 17) +#define DMIC_TOP_CON_DMIC_NO_LOW_POWER_MODE (0 << 14) +#define DMIC_TOP_CON_DMIC_LOW_POWER_MODE(x) ((x) << 14) +#define DMIC_TOP_CON_DMIC_IIR_ON BIT(10) +#define DMIC_TOP_CON_DMIC_INPUT_MODE(x) ((x) << 5) +#define DMIC_TOP_CON_DMIC_IIR_MODE(x) ((x) << 7) +#define DMIC_TOP_CON_DMIC_SDM3_LEVEL_MODE BIT(1) +#define DMIC_TOP_CON_DMIC_SRC_ON_MASK BIT(0) +#define DMIC_TOP_CON_DMIC_SRC_ON (1 << 0) +#define DMIC_TOP_CON_DMIC_SRC_OFF (0 << 0) +#define DMIC_TOP_CON_DMIC_SDM3_DE_SELECT (0 << 1) +#define DMIC_TOP_CON_CONFIG_MASK (0x3f8ed7a6) + +/* AFE_TDM_ASRC_CON0 (0x06f8)*/ +#define TDM_ASRC_OUT_MODE(x) ((x) << 4) +#define TDM_ASRC_OUT_MODE_MASK GENMASK(7, 4) +#define TDM_ASRC_OUT_SEL BIT(2) +#define TDM_ASRC_OUT_SEL_TO_CM1 (0 << 2) +#define TDM_ASRC_OUT_SEL_TO_CM2 (1 << 2) +#define TDM_ASRC_IN_SEL_FROM_TDMIN (0 << 1) +#define TDM_ASRC_IN_SEL_FROM_TDMOUT (1 << 1) +#define TDM_ASRC_IN_SEL_MASK BIT(1) +#define TDM_ASRC_EN_ON BIT(0) + +/* AFE_CONN_24BIT (0x0AA4) */ +#define AFE_CONN_24BIT_O10 BIT(10) +#define AFE_CONN_24BIT_O09 BIT(9) +#define AFE_CONN_24BIT_O06 BIT(6) +#define AFE_CONN_24BIT_O05 BIT(5) +#define AFE_CONN_24BIT_O04 BIT(4) +#define AFE_CONN_24BIT_O03 BIT(3) +#define AFE_CONN_24BIT_O02 BIT(2) +#define AFE_CONN_24BIT_O01 BIT(1) +#define AFE_CONN_24BIT_O00 BIT(0) + +/* AFE_HD_ENGEN_ENABLE */ +#define AFE_22M_PLL_EN BIT(0) +#define AFE_22M_PLL_ON (1 << 0) +#define AFE_22M_PLL_OFF (0 << 0) +#define AFE_24M_PLL_EN BIT(1) +#define AFE_24M_PLL_ON (1 << 1) +#define AFE_24M_PLL_OFF (0 << 1) + +/* AFE_GAIN1_CON0 (0x0410) */ +#define AFE_GAIN1_CON0_EN_MASK GENMASK(0, 0) +#define AFE_GAIN1_CON0_MODE_MASK GENMASK(7, 4) +#define AFE_GAIN1_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8) + +/* AFE_GAIN1_CON1 (0x0414) */ +#define AFE_GAIN1_CON1_MASK GENMASK(19, 0) + +/* AFE_GAIN1_CUR (0x0B78) */ +#define AFE_GAIN1_CUR_MASK GENMASK(19, 0) + +/* AFE_CM1_CON0 (0x0e50) */ +/* AFE_CM2_CON0 (0x0e60) */ +#define CM_AFE_CM_CH_NUM(x) (((x) - 1) << 0) +#define CM_AFE_CM_CH_NUM_MASK GENMASK(3, 0) +#define CM_AFE_CM_ON BIT(4) +#define CM_AFE_CM_OFF (0 << 4) +#define CM_AFE_CM_START_DATA(x) ((x) << 8) +#define CM_AFE_CM_START_DATA_MASK GENMASK(11, 8) + +#define CM_AFE_CM1_VUL_SEL_CM1_OUTPUT (0 << 12) +#define CM_AFE_CM1_VUL_SEL_O17_O18 (1 << 12) +#define CM_AFE_CM1_VUL_SEL BIT(12) +#define CM_AFE_CM1_IN_MODE(x) ((x) << 16) +#define CM_AFE_CM1_IN_MODE_MASK GENMASK(19, 16) +#define CM_AFE_CM2_TDM_SEL_CM2_OUTPUT (1 << 12) +#define CM_AFE_CM2_TDM_SEL_TDM (0 << 12) +#define CM_AFE_CM2_TDM_SEL BIT(12) +#define CM_AFE_CM2_CLK_SEL_24M (0 << 13) +#define CM_AFE_CM2_CLK_SEL_22M (1 << 13) +#define CM_AFE_CM2_CLK_SEL BIT(13) +#define CM_AFE_CM2_GASRC1_OUT_SEL BIT(17) +#define CM_AFE_CM2_GASRC2_OUT_SEL BIT(16) +#define GASRC1_OUT_TO_TDM_OUT_EN (0 << 17) +#define GASRC1_OUT_TO_ENGEN_OUT_EN (1 << 17) +#define GASRC2_OUT_TO_TDM_OUT_EN (0 << 16) +#define GASRC2_OUT_TO_ENGEN_OUT_EN (1 << 16) + +/* AFE_CM2_CONN* */ +#define CM2_AFE_CM2_CONN_CFG1(x) ((x) << 0) +#define CM2_AFE_CM2_CONN_CFG1_MASK GENMASK(4, 0) +#define CM2_AFE_CM2_CONN_CFG2(x) ((x) << 5) +#define CM2_AFE_CM2_CONN_CFG2_MASK GENMASK(9, 5) +#define CM2_AFE_CM2_CONN_CFG3(x) ((x) << 10) +#define CM2_AFE_CM2_CONN_CFG3_MASK GENMASK(14, 10) +#define CM2_AFE_CM2_CONN_CFG4(x) ((x) << 15) +#define CM2_AFE_CM2_CONN_CFG4_MASK GENMASK(19, 15) +#define CM2_AFE_CM2_CONN_CFG5(x) ((x) << 20) +#define CM2_AFE_CM2_CONN_CFG5_MASK GENMASK(24, 20) +#define CM2_AFE_CM2_CONN_CFG6(x) ((x) << 25) +#define CM2_AFE_CM2_CONN_CFG6_MASK GENMASK(29, 25) +#define CM2_AFE_CM2_CONN_CFG7(x) ((x) << 0) +#define CM2_AFE_CM2_CONN_CFG7_MASK GENMASK(4, 0) +#define CM2_AFE_CM2_CONN_CFG8(x) ((x) << 5) +#define CM2_AFE_CM2_CONN_CFG8_MASK GENMASK(9, 5) +#define CM2_AFE_CM2_CONN_CFG9(x) ((x) << 10) +#define CM2_AFE_CM2_CONN_CFG9_MASK GENMASK(14, 10) +#define CM2_AFE_CM2_CONN_CFG10(x) ((x) << 15) +#define CM2_AFE_CM2_CONN_CFG10_MASK GENMASK(19, 15) +#define CM2_AFE_CM2_CONN_CFG11(x) ((x) << 20) +#define CM2_AFE_CM2_CONN_CFG11_MASK GENMASK(24, 20) +#define CM2_AFE_CM2_CONN_CFG12(x) ((x) << 25) +#define CM2_AFE_CM2_CONN_CFG12_MASK GENMASK(29, 25) +#define CM2_AFE_CM2_CONN_CFG13(x) ((x) << 0) +#define CM2_AFE_CM2_CONN_CFG13_MASK GENMASK(4, 0) +#define CM2_AFE_CM2_CONN_CFG14(x) ((x) << 5) +#define CM2_AFE_CM2_CONN_CFG14_MASK GENMASK(9, 5) +#define CM2_AFE_CM2_CONN_CFG15(x) ((x) << 10) +#define CM2_AFE_CM2_CONN_CFG15_MASK GENMASK(14, 10) +#define CM2_AFE_CM2_CONN_CFG16(x) ((x) << 15) +#define CM2_AFE_CM2_CONN_CFG16_MASK GENMASK(19, 15) + +/* AFE_CM1_CON* */ +#define CM_AFE_CM_UPDATE_CNT1(x) (((x) & (0xffff)) << 0) +#define CM_AFE_CM_UPDATE_CNT2(x) (((x) & (0xffff)) << 16) +#define CM_AFE_CM_UPDATE_CNT1_MASK GENMASK(15, 0) +#define CM_AFE_CM_UPDATE_CNT2_MASK GENMASK(31, 16) +#define CM_AFE_CM_UPDATE_CNT_MASK GENMASK(31, 0) + +/* AFE_CM2_CON0 (0x0e60)*/ +#define GASRC_ASRC1_OUT_EN_SEL BIT(17) +#define GASRC_ASRC2_OUT_EN_SEL BIT(16) + + +/* AFE_GENERAL1_ASRC_2CH_CON0 (0x0e80) + * AFE_GENERAL2_ASRC_2CH_CON0 (0x0f00) + */ +#define GASRC_CON0_CHSET0_CLR_IIR_HISTORY BIT(17) +#define GASRC_NEW_CON0_CHSET0_OFS_SEL_MASK GENMASK(15, 14) +#define GASRC_NEW_CON0_CHSET0_OFS_SEL_TX (0 << 14) +#define GASRC_NEW_CON0_CHSET0_OFS_SEL_RX (1 << 14) +#define GASRC_NEW_CON0_CHSET0_IFS_SEL_MASK GENMASK(13, 12) +#define GASRC_NEW_CON0_CHSET0_IFS_SEL_TX (3 << 12) +#define GASRC_NEW_CON0_CHSET0_IFS_SEL_RX (2 << 12) +#define GASRC_CON0_CHSET_IIR_EN BIT(11) +#define GASRC_CON0_CHSET_IIR_STAGE(x) ((x) << 8) +#define GASRC_CON0_CHSET_IIR_STAGE_MASK GENMASK(10, 8) +#define GASRC_CON0_CHSET_STR_CLR BIT(4) +#define GASRC_CON0_COEFF_SRAM_CTRL BIT(1) +#define GASRC_CON0_ASM_ON BIT(0) + +/* GENERAL_ASRC_MODE (0x0eb8) */ +#define GASRC_MODE_GASRC1_IN_MODE(x) (((x) & 0xf) << 0) +#define GASRC_MODE_GASRC2_IN_MODE(x) (((x) & 0xf) << 8) +#define GASRC_MODE_GASRC1_IN_MODE_MASK GENMASK(3, 0) +#define GASRC_MODE_GASRC2_IN_MODE_MASK GENMASK(11, 8) +#define GASRC_MODE_GASRC1_OUT_MODE(x) (((x) & 0xf) << 4) +#define GASRC_MODE_GASRC2_OUT_MODE(x) (((x) & 0xf) << 12) +#define GASRC_MODE_GASRC1_OUT_MODE_MASK GENMASK(7, 4) +#define GASRC_MODE_GASRC2_OUT_MODE_MASK GENMASK(15, 12) + +/* GENERAL_ASRC_EN_ON (0x0ebc) */ +#define GASRC_EN_ON_MASK(x) (0x1 << (x)) +#define GASRC_EN_ON(x) (0x1 << (x)) +#define GASRC_EN_OFF(x) (0x0 << (x)) + +/* AFE_GENERAL1_ASRC_2CH_CON5 (0x0e94) + * AFE_GENERAL2_ASRC_2CH_CON5 (0x0f14) + */ +#define GASRC_CON5_CALI_CYCLE_MASK GENMASK(31, 16) +#define GASRC_CON5_CALI_64_CYCLE (0x3F << 16) +#define GASRC_CON5_CALI_96_CYCLE (0x5F << 16) +#define GASRC_CON5_CALI_441_CYCLE (0x1B8 << 16) +#define GASRC_CON5_CALI_AUTORST_ENABLE BIT(15) +#define GASRC_CON5_AUTO_TUNE_FREQ5_ENABLE BIT(12) +#define GASRC_CON5_AUTO_TUNE_FREQ5_DISABLE (0x0 << 12) +#define GASRC_CON5_COMP_FREQ_RES_ENABLE BIT(11) +#define GASRC_CON5_CALI_BP_DGL_BYPASS BIT(7) +#define GASRC_CON5_AUTO_TUNE_FREQ4_ENABLE BIT(3) +#define GASRC_CON5_AUTO_TUNE_FREQ4_DISABLE (0x0 << 3) +#define GASRC_CON5_CALI_AUTO_RESTART_ENABLE BIT(2) +#define GASRC_CON5_CALI_USE_FREQ BIT(1) +#define GASRC_CON5_CALI_USE_PERIOD (0x0 << 1) +#define GASRC_CON5_CALI_ON BIT(0) +#define GASRC_CON5_CALI_OFF (0x0 << 0) +#define GASRC_CON5_CALI_SEL_MASK GENMASK(9, 8) +#define GASRC_CON5_CALI_SEL_00 (0x0 << 8) +#define GASRC_CON5_CALI_SEL_01 (0x1 << 8) + +/* AFE_TDM_GASRC*_ASRC_2CH_CON0 */ +#define TDM_ASRC_CON0_ONE_HEART BIT(31) + +#endif /* _MT8365_AFE_REGS_H_ */ From f27385a08048473e76cb39eb605ba40d90f6cf93 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 19:35:05 -0800 Subject: [PATCH 07/14] config: Add default config for mt8365 Add default config for mt8365 platform. Signed-off-by: Andrew Perepech --- src/arch/xtensa/configs/mt8365_defconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 src/arch/xtensa/configs/mt8365_defconfig diff --git a/src/arch/xtensa/configs/mt8365_defconfig b/src/arch/xtensa/configs/mt8365_defconfig new file mode 100644 index 000000000000..3631692a10ff --- /dev/null +++ b/src/arch/xtensa/configs/mt8365_defconfig @@ -0,0 +1,15 @@ +CONFIG_MT8365=y +CONFIG_CORE_COUNT=1 +CONFIG_XT_VIRTUAL_OPS=1 +CONFIG_COMP_VOLUME=y +CONFIG_COMP_SRC=n +CONFIG_COMP_FIR=n +CONFIG_COMP_IIR=n +CONFIG_COMP_DCBLOCK=n +CONFIG_COMP_TDFB=n +CONFIG_COMP_TONE=n +CONFIG_COMP_MIXER=n +CONFIG_COMP_MUX=n +CONFIG_COMP_KPB=n +CONFIG_COMP_SEL=n +CONFIG_COMP_ASRC=n From 095507200c38f90642c79ae73eacfb6a58ec1baa Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 19:36:34 -0800 Subject: [PATCH 08/14] platform: Add build support for MediaTek mt8365 platform Add CMakefile for MediaTek mt8365 platform to build it. Signed-off-by: Andrew Perepech --- src/arch/xtensa/CMakeLists.txt | 4 +++- src/platform/CMakeLists.txt | 2 ++ src/platform/mt8365/CMakeLists.txt | 7 +++++++ src/platform/mt8365/lib/CMakeLists.txt | 7 +++++++ 4 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 src/platform/mt8365/CMakeLists.txt create mode 100644 src/platform/mt8365/lib/CMakeLists.txt diff --git a/src/arch/xtensa/CMakeLists.txt b/src/arch/xtensa/CMakeLists.txt index 0bc510e22330..0b91a132d376 100644 --- a/src/arch/xtensa/CMakeLists.txt +++ b/src/arch/xtensa/CMakeLists.txt @@ -28,6 +28,8 @@ elseif(CONFIG_MT8195) set(platform_folder mt8195) elseif(CONFIG_MT8196) set(platform_folder mt8196) +elseif(CONFIG_MT8365) + set(platform_folder mt8365) else() message(FATAL_ERROR "Platform not defined, check your Kconfiguration?") endif() @@ -479,7 +481,7 @@ set(UNSIGNED_RI imx8 imx8x imx8m imx8ulp) # AMD list(APPEND UNSIGNED_RI rn rmb vangogh acp_6_3 acp_7_0) # MediaTek -list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195 mt8196) +list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195 mt8196 mt8365) if(${fw_name} IN_LIST UNSIGNED_RI) # mere copy add_custom_command(OUTPUT reproducible.ri diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt index 56ff5b94c21f..1d0d7596cf3b 100644 --- a/src/platform/CMakeLists.txt +++ b/src/platform/CMakeLists.txt @@ -23,4 +23,6 @@ elseif(CONFIG_MT8195) add_subdirectory(mt8195) elseif(CONFIG_MT8196) add_subdirectory(mt8196) +elseif(CONFIG_MT8365) + add_subdirectory(mt8365) endif() diff --git a/src/platform/mt8365/CMakeLists.txt b/src/platform/mt8365/CMakeLists.txt new file mode 100644 index 000000000000..4091be2eeaff --- /dev/null +++ b/src/platform/mt8365/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_subdirectory(lib) + +add_local_sources(sof platform.c afe-platform.c) +target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8365/include/arch) +target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8365/include/platform) diff --git a/src/platform/mt8365/lib/CMakeLists.txt b/src/platform/mt8365/lib/CMakeLists.txt new file mode 100644 index 000000000000..63d0f657cbd0 --- /dev/null +++ b/src/platform/mt8365/lib/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof + clk.c + dma.c + memory.c +) From c3e1a7a388574c9b99761f6b073a20e2d391bf1a Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 20 Dec 2024 19:50:04 -0800 Subject: [PATCH 09/14] platform: Add mt8365 to Kconfig Add mt8365 to Kconfig. Signed-off-by: Andrew Perepech --- scripts/set_xtensa_params.sh | 6 ++++++ scripts/xtensa-build-all.sh | 3 +++ src/platform/Kconfig | 15 +++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/scripts/set_xtensa_params.sh b/scripts/set_xtensa_params.sh index e7af75d037fd..b4e506d1b52f 100644 --- a/scripts/set_xtensa_params.sh +++ b/scripts/set_xtensa_params.sh @@ -140,6 +140,12 @@ case "$platform" in HOST="xtensa-mt8196-elf" TOOLCHAIN_VER="RI-2023.11-linux" ;; + mt8365) + PLATFORM="mt8365" + XTENSA_CORE="hifi4_Aquila_E2_PROD" + HOST="xtensa-mt8365-elf" + TOOLCHAIN_VER="RG-2018.9-linux" + ;; *) >&2 printf 'Unknown xtensa platform=%s\n' "$platform" return 1 diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index ffcdafe450a0..b48ee2c1ff3b 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -17,6 +17,9 @@ DEFAULT_PLATFORMS=( # the -a option for everyone. SUPPORTED_PLATFORMS=( "${DEFAULT_PLATFORMS[@]}" ) +# Waiting for container work in progress +SUPPORTED_PLATFORMS+=( mt8365 ) + # Container work is in progress SUPPORTED_PLATFORMS+=( acp_6_3 acp_7_0 mt8196) diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 2ebc868e627a..aab9fddd8409 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -275,6 +275,19 @@ config MT8195 Select if your target platform is mt8195-compatible Builds legacy/xtos firmware +config MT8365 + bool "Build for MTK MT8365" + select XT_INTERRUPT_LEVEL_1 + select XT_INTERRUPT_LEVEL_2 + select XT_INTERRUPT_LEVEL_3 + select DUMMY_DMA + select HOST_PTABLE + select MEDIATEK + select XTENSA_EXCLUSIVE + select SCHEDULE_DMA_MULTI_CHANNEL + help + Select if your target platform is mt8365-compatible + config MTK bool "Build for Mediatek (Zephyr)" select SCHEDULE_DMA_MULTI_CHANNEL @@ -507,6 +520,7 @@ config RIMAGE_SIGNING_SCHEMA default "mt8188" if MT8188 default "mt8195" if MT8195 default "mt8196" if MT8196 + default "mt8365" if MT8365 default "" help Signing schema name used by rimage to decide how to build final binary @@ -556,6 +570,7 @@ config XTENSA_EXCLUSIVE config FORCE_DMA_COPY_WHOLE_BLOCK bool default y if MT8195 + default y if MT8365 default n depends on HOST_PTABLE help From 6c22015cc32027aed436fcd5e976c50e5af2a5cc Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 3 Jan 2025 14:48:52 -0800 Subject: [PATCH 10/14] drivers: mtk: Add mt8365 AFE sinegen support Add MT8365 sinegen driver for debug purpose. Signed-off-by: Andrew Perepech --- src/drivers/mediatek/afe/CMakeLists.txt | 3 + .../mediatek/afe/mt8365/CMakeLists.txt | 5 + src/drivers/mediatek/afe/mt8365/afe-sgen.c | 241 ++++++++++++++++++ uuid-registry.txt | 1 + 4 files changed, 250 insertions(+) create mode 100644 src/drivers/mediatek/afe/mt8365/CMakeLists.txt create mode 100644 src/drivers/mediatek/afe/mt8365/afe-sgen.c diff --git a/src/drivers/mediatek/afe/CMakeLists.txt b/src/drivers/mediatek/afe/CMakeLists.txt index 0646a839cce1..228a6555d2c8 100644 --- a/src/drivers/mediatek/afe/CMakeLists.txt +++ b/src/drivers/mediatek/afe/CMakeLists.txt @@ -13,3 +13,6 @@ endif() if(CONFIG_MT8196) add_subdirectory(mt8196) endif() +if(CONFIG_MT8365) + add_subdirectory(mt8365) +endif() diff --git a/src/drivers/mediatek/afe/mt8365/CMakeLists.txt b/src/drivers/mediatek/afe/mt8365/CMakeLists.txt new file mode 100644 index 000000000000..3f0653684edf --- /dev/null +++ b/src/drivers/mediatek/afe/mt8365/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_TEST_SGEN) +add_local_sources(sof afe-sgen.c) +endif() diff --git a/src/drivers/mediatek/afe/mt8365/afe-sgen.c b/src/drivers/mediatek/afe/mt8365/afe-sgen.c new file mode 100644 index 000000000000..e632f7ca6676 --- /dev/null +++ b/src/drivers/mediatek/afe/mt8365/afe-sgen.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include + +#include +#include +#include +#include + +#include +#include + +SOF_DEFINE_REG_UUID(sgen_mt8365); + +DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_mt8365_uuid), LOG_LEVEL_INFO); + +/* + * Note: TEST_SGEN for test only + * Define this TEST_SGEN to enable sine tone generator + * then output data to audio memory interface(memif), + * you can set TEST_SGEN_ID to choose output to which memif. + * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8365_MEMIF_DL1", + * the data source of DL2 will from sine generator. + */ +#define TEST_SGEN_ID MT8365_MEMIF_DL1 +#define AUDIO_TML_PD_MASK 1 +#define AUDIO_TML_PD_SHIFT 27 + +#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f +#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0 +#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f +#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12 +#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7 +#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5 +#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7 +#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17 +#define AFE_SGEN_MUTE_CH1_MASK 0x1 +#define AFE_SGEN_MUTE_CH1_SHIFT 24 +#define AFE_SGEN_MUTE_CH2_MASK 0x1 +#define AFE_SGEN_MUTE_CH2_SHIFT 25 +#define AFE_SGEN_ENABLE_MASK 0x1 +#define AFE_SGEN_ENABLE_SHIFT 26 + +#define AFE_SGEN_TIMING_CH1_MASK 0x0f +#define AFE_SGEN_TIMING_CH1_SHIFT 8 +#define AFE_SGEN_TIMING_CH2_MASK 0x0f +#define AFE_SGEN_TIMING_CH2_SHIFT 20 + +#define AFE_SINEGEN_LB_MODE_MSK 0x1f +#define AFE_SINEGEN_LB_MODE_SHIFT 27 + +enum { + MT8365_SGEN_AWB = (0x3 << 1) | 1, // o5 + o6 + SGEN to out + MT8365_SGEN_VUL = (0x5 << 1) | 1, // o9 + o10 + SGEN to out + MT8365_SGEN_DL1 = (0x3 << 1) | 0, // i5 + i6 + SGEN to in + MT8365_SGEN_DL2 = (0x4 << 1) | 0 // i7 + i8 + SGEN to in +}; + +/*sgen freq div*/ +enum { + SGEN_FREQ_64D1 = 1, + SGEN_FREQ_64D2 = 2, + SGEN_FREQ_64D3 = 3, + SGEN_FREQ_64D4 = 4, + SGEN_FREQ_64D5 = 5, + SGEN_FREQ_64D6 = 6, + SGEN_FREQ_64D7 = 7, + SGEN_FREQ_64D8 = 8, +}; + +/*sgen amp div*/ +enum { + SGEN_AMP_D1 = 0, + SGEN_AMP_D2 = 1, + SGEN_AMP_D4 = 2, + SGEN_AMP_D8 = 3, + SGEN_AMP_D16 = 4, + SGEN_AMP_D32 = 5, + SGEN_AMP_D64 = 6, + SGEN_AMP_D128 = 7, +}; + +enum { + SGEN_CH_TIMING_8K = 0, + SGEN_CH_TIMING_11P025K = 1, + SGEN_CH_TIMING_12K = 2, + SGEN_CH_TIMING_16K = 4, + SGEN_CH_TIMING_22P05K = 5, + SGEN_CH_TIMING_24K = 6, + SGEN_CH_TIMING_32K = 8, + SGEN_CH_TIMING_44P1K = 9, + SGEN_CH_TIMING_48K = 10, + SGEN_CH_TIMING_88P2K = 11, + SGEN_CH_TIMING_96K = 12, + SGEN_CH_TIMING_176P4K = 13, + SGEN_CH_TIMING_192K = 14, +}; + +static uint32_t mt8365_sinegen_timing(uint32_t rate) +{ + uint32_t sinegen_timing; + + switch (rate) { + case 8000: + sinegen_timing = SGEN_CH_TIMING_8K; + break; + case 11025: + sinegen_timing = SGEN_CH_TIMING_11P025K; + break; + case 12000: + sinegen_timing = SGEN_CH_TIMING_12K; + break; + case 16000: + sinegen_timing = SGEN_CH_TIMING_16K; + break; + case 22050: + sinegen_timing = SGEN_CH_TIMING_22P05K; + break; + case 24000: + sinegen_timing = SGEN_CH_TIMING_24K; + break; + case 32000: + sinegen_timing = SGEN_CH_TIMING_32K; + break; + case 44100: + sinegen_timing = SGEN_CH_TIMING_44P1K; + break; + case 48000: + sinegen_timing = SGEN_CH_TIMING_48K; + break; + case 88200: + sinegen_timing = SGEN_CH_TIMING_88P2K; + break; + case 96000: + sinegen_timing = SGEN_CH_TIMING_96K; + break; + case 176400: + sinegen_timing = SGEN_CH_TIMING_176P4K; + break; + case 192000: + sinegen_timing = SGEN_CH_TIMING_192K; + break; + default: + sinegen_timing = SGEN_CH_TIMING_48K; + tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate); + } + tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing); + return sinegen_timing; +} + +static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift) +{ + io_reg_update_bits(AFE_REG_BASE + addr_offset, mask << shift, val << shift); +} + +static uint32_t mtk_afe_reg_read(uint32_t addr_offset) +{ + return io_reg_read(AFE_REG_BASE + addr_offset); +} + +static void mt8365_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable) +{ + uint32_t loopback_mode, reg_1, sinegen_timing; + + tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable); + + sinegen_timing = mt8365_sinegen_timing(rate); + + if (enable == 1) { + /* set loopback mode */ + switch (sgen_id) { + case MT8365_MEMIF_AWB: + loopback_mode = MT8365_SGEN_AWB; + break; + case MT8365_MEMIF_VUL: + loopback_mode = MT8365_SGEN_VUL; + break; + case MT8365_MEMIF_DL1: + loopback_mode = MT8365_SGEN_DL1; + break; + case MT8365_MEMIF_DL2: + loopback_mode = MT8365_SGEN_DL2; + break; + default: + tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id); + return; + } + /* enable sinegen clock*/ + mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT); + + /*loopback source*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SINEGEN_LB_MODE_MSK, loopback_mode, + AFE_SINEGEN_LB_MODE_SHIFT); + + /* sine gen timing*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_TIMING_CH1_MASK, + sinegen_timing, AFE_SGEN_TIMING_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_TIMING_CH2_MASK, + sinegen_timing, AFE_SGEN_TIMING_CH2_SHIFT); + + /*freq div*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK, + SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK, + SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT); + + /*amp div*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2, + AFE_SGEN_AMP_DIV_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2, + AFE_SGEN_AMP_DIV_CH2_SHIFT); + /* enable sgen*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_ENABLE_MASK, 1, + AFE_SGEN_ENABLE_SHIFT); + } else { + /* disable sgen*/ + mtk_afe_reg_update_bits(AFE_SGEN_CON0, AFE_SGEN_ENABLE_MASK, 0, + AFE_SGEN_ENABLE_SHIFT); + + /* disable sgen clock */ + mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT); + } + + reg_1 = mtk_afe_reg_read(AFE_SGEN_CON0); + tr_dbg(&sgen_tr, "AFE_SGEN_CON0 0x%x", reg_1); +} + +void afe_sinegen_enable(void) +{ + mt8365_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1); +} + +void afe_sinegen_disable(void) +{ + mt8365_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0); +} diff --git a/uuid-registry.txt b/uuid-registry.txt index 3b60a926c03b..47710cce88ff 100644 --- a/uuid-registry.txt +++ b/uuid-registry.txt @@ -142,6 +142,7 @@ cf90d851-68a2-4987-a2de85aed0c8531c sgen_mt8186 99316bd9-07b9-4665-81796e048d67cb45 sgen_mt8188 9eb1a55b-fc20-4442-96131ff1023be493 sgen_mt8195 bcf54c06-5702-4a60-ac4abb509123c649 sgen_mt8196 +654ef011-6d79-414a-9c1b15e72c0be321 sgen_mt8365 dabe8814-47e8-11ed-a58bb309974fecce shmread e2b6031c-47e8-11ed-07a97f801b6efa6c shmwrite 167a961e-8ae4-11ea-89f1000c29ce1635 smart_amp_test From 4bd2fbeef002b822728bbaa671a756271f6349e6 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 3 Jan 2025 13:50:27 -0800 Subject: [PATCH 11/14] platform: mtk: Add platform driver for mt8365 Add mt8365 dai and dma platform driver. Signed-off-by: Andrew Perepech --- src/platform/mt8365/lib/dai.c | 71 +++++++++++++++++++++++++++++++++++ src/platform/mt8365/lib/dma.c | 14 +++++++ 2 files changed, 85 insertions(+) create mode 100644 src/platform/mt8365/lib/dai.c diff --git a/src/platform/mt8365/lib/dai.c b/src/platform/mt8365/lib/dai.c new file mode 100644 index 000000000000..6700e3257ac2 --- /dev/null +++ b/src/platform/mt8365/lib/dai.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Andrew Perepech + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* MEMIF specified IRQs set in the Linux driver: + * + * [MT8365_AFE_MEMIF_DL1] = MT8365_AFE_IRQ1, + * [MT8365_AFE_MEMIF_DL2] = MT8365_AFE_IRQ2, + * [MT8365_AFE_MEMIF_TDM_OUT] = MT8365_AFE_IRQ5, + * // [MT8365_AFE_MEMIF_SPDIF_OUT] = MT8365_AFE_IRQ6, + * [MT8365_AFE_MEMIF_AWB] = MT8365_AFE_IRQ3, + * [MT8365_AFE_MEMIF_VUL] = MT8365_AFE_IRQ4, + * [MT8365_AFE_MEMIF_VUL2] = MT8365_AFE_IRQ7, + * [MT8365_AFE_MEMIF_VUL3] = MT8365_AFE_IRQ8, + * // [MT8365_AFE_MEMIF_SPDIF_IN] = MT8365_AFE_IRQ9, + * [MT8365_AFE_MEMIF_TDM_IN] = MT8365_AFE_IRQ10, + */ + +static int afe_dai_handshake[MT8365_DAI_NUM] = { + AFE_HANDSHAKE(MT8365_AFE_IO_INT_ADDA_OUT, MT8365_AFE_IRQ_1, MT8365_MEMIF_DL1), + AFE_HANDSHAKE(MT8365_AFE_IO_2ND_I2S, MT8365_AFE_IRQ_2, MT8365_MEMIF_DL2), + AFE_HANDSHAKE(MT8365_AFE_IO_INT_ADDA_IN, MT8365_AFE_IRQ_3, MT8365_MEMIF_AWB), + AFE_HANDSHAKE(MT8365_AFE_IO_DMIC, MT8365_AFE_IRQ_4, MT8365_MEMIF_VUL), +}; + +static SHARED_DATA struct dai afe_dai[MT8365_DAI_NUM]; + +const struct dai_type_info dti[] = { + { + .type = SOF_DAI_MEDIATEK_AFE, + .dai_array = afe_dai, + .num_dais = ARRAY_SIZE(afe_dai), + }, +}; + +const struct dai_info lib_dai = { + .dai_type_array = dti, + .num_dai_types = ARRAY_SIZE(dti), +}; + +int dai_init(struct sof *sof) +{ + int i; + + /* initialize spin locks early to enable ref counting */ + for (i = 0; i < ARRAY_SIZE(afe_dai); i++) { + k_spinlock_init(&afe_dai[i].lock); + afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]); + afe_dai[i].drv = &afe_dai_driver; + /* TODO, fifo[0] change to target playback or capture */ + afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i]; + } + + sof->dai_info = &lib_dai; + + return 0; +} diff --git a/src/platform/mt8365/lib/dma.c b/src/platform/mt8365/lib/dma.c index 8eb2bf5938b4..9e6209790731 100644 --- a/src/platform/mt8365/lib/dma.c +++ b/src/platform/mt8365/lib/dma.c @@ -6,12 +6,16 @@ */ #include +#include #include #include #include #include #include +#include +#include + extern const struct dma_ops dummy_dma_ops; static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { @@ -24,6 +28,16 @@ static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { }, .ops = &dummy_dma_ops, }, +{ + .plat_data = { + .id = DMA_ID_AFE_MEMIF, + .dir = DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM, + .devs = DMA_DEV_AFE_MEMIF, + .base = AFE_REG_BASE, + .channels = MT8365_MEMIF_NUM, + }, + .ops = &memif_ops, +}, }; static const struct dma_info lib_dma = { From 56f38c89307a9d9bde57d02659325a339545febf Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 3 Jan 2025 16:31:07 -0800 Subject: [PATCH 12/14] platform: mtk: Add platform dai support for mt8365 Add platform dai_init() to platform_init(). Add platform dai to build list. Signed-off-by: Andrew Perepech --- src/platform/mt8365/lib/CMakeLists.txt | 1 + src/platform/mt8365/platform.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/platform/mt8365/lib/CMakeLists.txt b/src/platform/mt8365/lib/CMakeLists.txt index 63d0f657cbd0..ef71f8eea6cd 100644 --- a/src/platform/mt8365/lib/CMakeLists.txt +++ b/src/platform/mt8365/lib/CMakeLists.txt @@ -4,4 +4,5 @@ add_local_sources(sof clk.c dma.c memory.c + dai.c ) diff --git a/src/platform/mt8365/platform.c b/src/platform/mt8365/platform.c index 989bdc2312d5..d57edc2f8431 100644 --- a/src/platform/mt8365/platform.c +++ b/src/platform/mt8365/platform.c @@ -192,7 +192,9 @@ int platform_init(struct sof *sof) /* initialize the host IPC mechanims */ ipc_init(sof); - /* TO-DO: dai init */ + ret = dai_init(sof); + if (ret < 0) + return ret; #if CONFIG_TRACE /* Initialize DMA for Trace*/ From 314dc16606e89633d4ffd6aaf31858c6f0b0665f Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Fri, 3 Jan 2025 17:31:59 -0800 Subject: [PATCH 13/14] topology1: Add mt8365 related pipelines and components Add topology files for mt8365 including mt8365.m4 and sof-mt8365-mt6357.m4. Signed-off-by: Andrew Perepech --- tools/topology/topology1/CMakeLists.txt | 2 + .../topology1/platform/mediatek/mt8365.m4 | 23 ++++ tools/topology/topology1/sof-mt8365-mt6357.m4 | 128 ++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 tools/topology/topology1/platform/mediatek/mt8365.m4 create mode 100644 tools/topology/topology1/sof-mt8365-mt6357.m4 diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index af6b5dc63a35..a1118a69e9ae 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -101,6 +101,8 @@ set(TPLGS "sof-mt8196-mt6681\;sof-mt8196" "sof-mt8196-mt6681\;sof-mt8196-waves\;-DWAVES=1" "sof-mt8196-mt6681\;sof-mt8196-dts\;-DDTS=`DTS'" + "sof-mt8365-mt6357\;sof-mt8365" + "sof-mt8365-mt6357\;sof-mt8365-waves\;-DWAVES=1" "sof-acp-renoir\;sof-acp" "sof-rn-rt5682-rt1019\;sof-rn-rt5682-rt1019" diff --git a/tools/topology/topology1/platform/mediatek/mt8365.m4 b/tools/topology/topology1/platform/mediatek/mt8365.m4 new file mode 100644 index 000000000000..fa7eca700d68 --- /dev/null +++ b/tools/topology/topology1/platform/mediatek/mt8365.m4 @@ -0,0 +1,23 @@ +# +# MT8365 differentiation for pipelines and components +# + +include(`memory.m4') + +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + +# Low Latency PCM Configuration +W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) +W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens) + +# Media PCM Configuration +W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"')) +W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens) + +# DAI schedule Configuration - scheduled by IRQ +W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"')) +W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens) + diff --git a/tools/topology/topology1/sof-mt8365-mt6357.m4 b/tools/topology/topology1/sof-mt8365-mt6357.m4 new file mode 100644 index 000000000000..7ba3420d57f9 --- /dev/null +++ b/tools/topology/topology1/sof-mt8365-mt6357.m4 @@ -0,0 +1,128 @@ +# +# Topology for MT8365 board with mt6357 +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`afe.m4') +include(`pcm.m4') +include(`buffer.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include DSP configuration +include(`platform/mediatek/mt8365.m4') + +# +# Define the pipelines +# +# PCM16 ---> AFE (Speaker - rt1019) +# PCM17 ---> AFE (Headset playback - rt5682) +# PCM18 <--- AFE (DMIC - MT6365) +# PCM19 <--- AFE (Headset record - rt5682) + + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate, +dnl time_domain, sched_comp) + +define(`ENDPOINT_NAME', `Speakers') +# Low Latency playback pipeline 1 on PCM 16 using max 2 channels of s16le +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(ifdef(`WAVES', sof/pipe-waves-codec-playback.m4, sof/pipe-passthrough-playback.m4), + 1, 16, 2, s16le, + 1000, 0, 0, + 48000, 48000, 48000) +undefine(`ENDPOINT_NAME') + +define(`ENDPOINT_NAME', `Headphones') +# Low Latency playback pipeline 2 on PCM 17 using max 2 channels of s16le +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(ifdef(`WAVES', sof/pipe-waves-codec-playback.m4, sof/pipe-passthrough-playback.m4), + 2, 17, 2, s16le, + 1000, 0, 0, + 48000, 48000, 48000) +undefine(`ENDPOINT_NAME') + +# Low Latency capture pipeline 3 on PCM 18 using max 2 channels of s16le +# Set 2000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 3, 18, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 4 on PCM 19 using max 2 channels of s16le +# Set 2000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 19, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core) + + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, AFE, 0, AFE_SOF_DL1, + PIPELINE_SOURCE_1, 2, s16le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 2, AFE, 1, AFE_SOF_DL2, + PIPELINE_SOURCE_2, 2, s16le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 2000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 3, AFE, 2, AFE_SOF_AWB, + PIPELINE_SINK_3, 2, s16le, + 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 2000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 4, AFE, 3, AFE_SOF_VUL, + PIPELINE_SINK_4, 2, s16le, + 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +#SCHEDULE_TIME_DOMAIN_DMA +dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) + +# PCM Low Latency, id 0 +PCM_PLAYBACK_ADD(SOF_DL1, 16, PIPELINE_PCM_1) +PCM_PLAYBACK_ADD(SOF_DL2, 17, PIPELINE_PCM_2) +PCM_CAPTURE_ADD(SOF_AWB, 18, PIPELINE_PCM_3) +PCM_CAPTURE_ADD(SOF_VUL, 19, PIPELINE_PCM_4) + +dnl DAI_CONFIG(type, dai_index, link_id, name, afe_config) + +DAI_CONFIG(AFE, 0, 0, AFE_SOF_DL1, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 0, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 1, 0, AFE_SOF_DL2, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 1, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 2, 0, AFE_SOF_AWB, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 2, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 3, 0, AFE_SOF_VUL, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 3, 48000, 2, s16le))) From ef83791c3f934f7c2a5518e20fbab6d5544b8743 Mon Sep 17 00:00:00 2001 From: Andrew Perepech Date: Wed, 19 Feb 2025 12:04:35 -0800 Subject: [PATCH 14/14] drivers: mediatek: mt8365: Add a comment to timer.c Add a comment explaining that the CNTCV_L register must be read before the CNTCV_H to get a valid 64-bit timestamp value Signed-off-by: Andrew Perepech --- src/drivers/mediatek/mt8365/timer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/mediatek/mt8365/timer.c b/src/drivers/mediatek/mt8365/timer.c index 222fd85b7275..40d33a6d1b50 100644 --- a/src/drivers/mediatek/mt8365/timer.c +++ b/src/drivers/mediatek/mt8365/timer.c @@ -80,7 +80,9 @@ uint64_t platform_timer_get(struct timer *timer) if (timer->id >= NR_TMRS) return -EINVAL; - /* must read 'low' first, and 'high' next */ + /* CNTCV_H is only updated when the CNTCV_L is read. + * Always read CNTCV_L before CNTCV_H to get a valid 64-bit timestamp. + */ low = io_reg_read(CNTCV_L); high = io_reg_read(CNTCV_H); time = ((uint64_t)high << 32) | low;