diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100755 index 0000000..4452e08 --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1,75 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as +contributors and maintainers pledge to making participation in our project and +our community a harassment-free experience for everyone, regardless of age, body +size, disability, ethnicity, sex characteristics, gender identity and expression, +level of experience, education, socio-economic status, nationality, personal +appearance, race, religion, or sexual identity and orientation. + +## Our Standards + +Examples of behavior that contributes to creating a positive environment +include: + +* Using welcoming and inclusive language +* Being respectful of differing viewpoints and experiences +* Gracefully accepting constructive criticism +* Focusing on what is best for the community +* Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +* The use of sexualized language or imagery and unwelcome sexual attention or + advances +* Trolling, insulting/derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or electronic + address, without explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Our Responsibilities + +Project maintainers are responsible for clarifying the standards of acceptable +behavior and are expected to take appropriate and fair corrective action in +response to any instances of unacceptable behavior. + +Project maintainers have the right and responsibility to remove, edit, or +reject comments, commits, code, wiki edits, issues, and other contributions +that are not aligned to this Code of Conduct, or to ban temporarily or +permanently any contributor for other behaviors that they deem inappropriate, +threatening, offensive, or harmful. + +## Scope + +This Code of Conduct applies both within project spaces and in public spaces +when an individual is representing the project or its community. Examples of +representing a project or community include using an official project e-mail +address, posting via an official social media account, or acting as an appointed +representative at an online or offline event. Representation of a project may be +further defined and clarified by project maintainers. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported by contacting the project team at https://www.st.com/content/st_com/en/contact-us.html. All +complaints will be reviewed and investigated and will result in a response that +is deemed necessary and appropriate to the circumstances. The project team is +obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good +faith may face temporary or permanent repercussions as determined by other +members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, +available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html). + +[homepage]: https://www.contributor-covenant.org + +For answers to common questions about this code of conduct, refer to the FAQ section [here](https://www.contributor-covenant.org/faq). diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100755 index 0000000..329b45a --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,5 @@ +## Contributing guide + +The issues and the pull-requests are not supported to submit problems or suggestions related to the software delivered in this repository. The STM32MPU_SDK_HELPER is being delivered as-is, not necessarily supported by ST. + +For any question related to the product, the hardware performance or characteristics, the tools, the environment, you can submit it to the ST Community on the STM32 MCUs related page. diff --git a/FLASH_LAYOUT/flash.bat b/FLASH_LAYOUT/flash.bat new file mode 100644 index 0000000..659f5e8 --- /dev/null +++ b/FLASH_LAYOUT/flash.bat @@ -0,0 +1,6 @@ + + +"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=USB1 -w FLASH_LAYOUT\flash_layout_emmc.tsv + +rem "C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=USB1 -w FLASH_LAYOUT\flash_layout_sdcard.tsv + diff --git a/FLASH_LAYOUT/flash.sh b/FLASH_LAYOUT/flash.sh new file mode 100644 index 0000000..75e6bed --- /dev/null +++ b/FLASH_LAYOUT/flash.sh @@ -0,0 +1,7 @@ +#!/bin/bash -e + +STORAGE="emmc" +# STORAGE="sdcard" + +STM32_Programmer_CLI -c port=USB1 -w FLASH_LAYOUT/flash_layout_${STORAGE}.tsv + diff --git a/FLASH_LAYOUT/flash_layout_emmc.tsv b/FLASH_LAYOUT/flash_layout_emmc.tsv new file mode 100644 index 0000000..b9e541e --- /dev/null +++ b/FLASH_LAYOUT/flash_layout_emmc.tsv @@ -0,0 +1,15 @@ +#Opt Id Name Type IP Offset Binary +- 0x01 fsbl-boot Binary none 0x0 tfa/tfa_usb.stm32 +- 0x02 fip-ddr FIP none 0x0 fip/fip-ddr.bin +- 0x03 fip-boot FIP none 0x0 fip/fip.bin +P 0x04 fsbla1 Binary mmc1 boot1 tfa/tfa_emmc.stm32 +P 0x05 fsbla2 Binary mmc1 boot2 tfa/tfa_emmc.stm32 +PE 0x06 metadata1 FWU_MDATA mmc1 0x00080000 tfa/metadata.bin +PE 0x07 metadata2 FWU_MDATA mmc1 0x00100000 tfa/metadata.bin +P 0x08 fip-a FIP mmc1 0x00180000 fip/fip.bin +PED 0x09 fip-b FIP mmc1 0x00580000 fip/fip.bin +PED 0x0A u-boot-env ENV mmc1 0x00980000 none +PE 0x10 bootfs System mmc1 0x00A00000 none +PE 0x11 vendorfs FileSystem mmc1 0x04A00000 none +PE 0x12 rootfs FileSystem mmc1 0x10100000 none +PE 0x13 userfs FileSystem mmc1 0xD0100000 none diff --git a/FLASH_LAYOUT/flash_layout_sdcard.tsv b/FLASH_LAYOUT/flash_layout_sdcard.tsv new file mode 100644 index 0000000..8950bd7 --- /dev/null +++ b/FLASH_LAYOUT/flash_layout_sdcard.tsv @@ -0,0 +1,15 @@ +#Opt Id Name Type IP Offset Binary +- 0x01 fsbl-boot Binary none 0x0 tfa/tfa_usb.stm32 +- 0x02 fip-ddr FIP none 0x0 fip/fip-ddr.bin +- 0x03 fip-boot FIP none 0x0 fip/fip.bin +P 0x04 fsbla1 Binary mmc0 0x00004400 tfa/tfa_sdcard.stm32 +P 0x05 fsbla2 Binary mmc0 0x00044400 tfa/tfa_sdcard.stm32 +PE 0x06 metadata1 FWU_MDATA mmc0 0x00084400 tfa/metadata.bin +PE 0x07 metadata2 FWU_MDATA mmc0 0x000C4400 tfa/metadata.bin +P 0x08 fip-a FIP mmc0 0x00104400 fip/fip.bin +PED 0x09 fip-b FIP mmc0 0x00504400 fip/fip.bin +PED 0x0A u-boot-env ENV mmc1 0x00980000 none +PE 0x10 bootfs System mmc1 0x00A00000 none +PE 0x11 vendorfs FileSystem mmc1 0x04A00000 none +PE 0x12 rootfs FileSystem mmc1 0x10100000 none +PE 0x13 userfs FileSystem mmc1 0xD0100000 none diff --git a/FLASH_LAYOUT/metadata.bin b/FLASH_LAYOUT/metadata.bin new file mode 100644 index 0000000..9a1f633 Binary files /dev/null and b/FLASH_LAYOUT/metadata.bin differ diff --git a/KERNEL/fragment_minimal.config b/KERNEL/fragment_minimal.config new file mode 100644 index 0000000..7ce6322 --- /dev/null +++ b/KERNEL/fragment_minimal.config @@ -0,0 +1,1040 @@ +# CONFIG_HW_RANDOM is not set +# CONFIG_IPV6 is not set +# CONFIG_ARM_PMU is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +# CONFIG_BLK_DEBUG_FS is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=19 +CONFIG_COMMON_CLK_XGENE=y +CONFIG_CRC7=y +CONFIG_CRC8=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DMA_CMA=y +CONFIG_DNS_RESOLVER=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_EFI is not set +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_EXT4_FS=y +CONFIG_FAILOVER=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_GENERIC_PHY=y +# CONFIG_HID_SUPPORT is not set +CONFIG_HOTPLUG_CPU=y +# CONFIG_HWMON is not set +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_STM32F7=y +CONFIG_I3C=y +CONFIG_INDIRECT_PIO=y +CONFIG_INET=y +# CONFIG_INET_DIAG is not set +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IRQ_POLL=y +CONFIG_KEYS=y +CONFIG_KPROBES=y +CONFIG_MAILBOX=y +CONFIG_MAILBOX_CDEV=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MMC_CQHCI=y +CONFIG_MODVERSIONS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NR_CPUS=2 +CONFIG_OF_OVERLAY=y +CONFIG_PACKING=y +CONFIG_PAGE_REPORTING=y +# CONFIG_PCPU_DEV_REFCNT is not set +# CONFIG_PINCTRL_STM32MP215 is not set +# CONFIG_PINCTRL_STM32MP235 is not set +# CONFIG_PINCTRL_STM32_HDP is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +CONFIG_PPS=y +CONFIG_REGULATOR=y +# CONFIG_RESET_SCMI is not set +CONFIG_SCMI_STM32MP_OSTL_V5=y +CONFIG_SCSI=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SECURITYFS=y +# CONFIG_SERIO is not set +CONFIG_SPI_MEM=y +CONFIG_STM=y +# CONFIG_STM32MP_EXTI is not set +# CONFIG_STM32_DDR_PMU is not set +CONFIG_STM32_DMA3=y +CONFIG_STM32_IPCC=y +# CONFIG_STM32_RISAB is not set +# CONFIG_STM32_RISAF is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_SURFACE_PLATFORMS is not set +# CONFIG_SUSPEND is not set +CONFIG_SYNC_FILE=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_THERMAL=y +CONFIG_TMPFS=y +CONFIG_UNIX=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_VIRTIO_MENU is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_FW_LOADER=n +CONFIG_FW_LOADER_DEBUG=n +CONFIG_CDNS_I3C_MASTER=n +CONFIG_SENSORS_LIS3_SPI=n +CONFIG_I2C_ALGOPCF=n +CONFIG_I2C_ALGOPCA=n +CONFIG_DW_I3C_MASTER=n +CONFIG_STM32_I3C_MASTER=n +CONFIG_SVC_I3C_MASTER=n +CONFIG_MIPI_I3C_HCI=n +CONFIG_DEBUG_CGROUP_REF=n +CONFIG_FUNCTION_ERROR_INJECTION=n +CONFIG_TEST_DYNAMIC_DEBUG=n +CONFIG_CPU_FREQ_GOV_POWERSAVE=n +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=n +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=n +CONFIG_ARM_IMX_CPUFREQ_DT=n +CONFIG_ARM_MEDIATEK_CPUFREQ_HW=n +CONFIG_ARM_RASPBERRYPI_CPUFREQ=n +CONFIG_BRIDGE_NETFILTER=n +CONFIG_NF_CONNTRACK=n +CONFIG_NF_LOG_SYSLOG=n +CONFIG_NF_NAT=n +CONFIG_NETFILTER_XTABLES=n +CONFIG_NETFILTER_XT_MARK=n +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=n +CONFIG_NETFILTER_XT_TARGET_LOG=n +CONFIG_NETFILTER_XT_NAT=n +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=n +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=n +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=n +CONFIG_NETFILTER_XT_MATCH_IPVS=n +CONFIG_IP_VS=n +CONFIG_NF_DEFRAG_IPV4=n +CONFIG_NF_REJECT_IPV4=n +CONFIG_IP_NF_IPTABLES=n +CONFIG_IP_NF_FILTER=n +CONFIG_IP_NF_TARGET_REJECT=n +CONFIG_IP_NF_NAT=n +CONFIG_IP_NF_TARGET_MASQUERADE=n +CONFIG_IP_NF_MANGLE=n +CONFIG_STP=n +CONFIG_GARP=n +CONFIG_MRP=n +CONFIG_BRIDGE=n +CONFIG_NET_DSA=n +CONFIG_NET_DSA_TAG_NONE=n +CONFIG_NET_DSA_TAG_BRCM_COMMON=n +CONFIG_NET_DSA_TAG_BRCM=n +CONFIG_NET_DSA_TAG_BRCM_LEGACY=n +CONFIG_NET_DSA_TAG_BRCM_PREPEND=n +CONFIG_NET_DSA_TAG_OCELOT=n +CONFIG_NET_DSA_TAG_OCELOT_8021Q=n +CONFIG_VLAN_8021Q=n +CONFIG_LLC=n +CONFIG_NET_SCH_CBS=n +CONFIG_NET_SCH_ETF=n +CONFIG_NET_SCH_MQPRIO_LIB=n +CONFIG_NET_SCH_TAPRIO=n +CONFIG_NET_SCH_MQPRIO=n +CONFIG_NET_SCH_INGRESS=n +CONFIG_NET_CLS_BASIC=n +CONFIG_NET_CLS_FLOWER=n +CONFIG_NET_ACT_GACT=n +CONFIG_NET_ACT_MIRRED=n +CONFIG_NET_ACT_GATE=n +CONFIG_QRTR=n +CONFIG_QRTR_SMD=n +CONFIG_QRTR_TUN=n +CONFIG_QRTR_MHI=n +CONFIG_CAN=n +CONFIG_CAN_RAW=n +CONFIG_CAN_BCM=n +CONFIG_CAN_GW=n +CONFIG_BT=n +CONFIG_BT_BCM=n +CONFIG_BT_QCA=n +CONFIG_BT_HCIUART=n +CONFIG_BT_MRVL=n +CONFIG_BT_MRVL_SDIO=n +CONFIG_BT_QCOMSMD=n +CONFIG_BT_HCIRSI=n +CONFIG_BT_NXPUART=n +CONFIG_CFG80211=n +CONFIG_MAC80211=n +CONFIG_RFKILL=n +CONFIG_NFC=n +CONFIG_NFC_NCI=n +CONFIG_NFC_S3FWRN5=n +CONFIG_NFC_S3FWRN5_I2C=n +CONFIG_PCIE_BRCMSTB=n +CONFIG_PCIE_MEDIATEK_GEN3=n +CONFIG_PCIE_ROCKCHIP_HOST=n +CONFIG_PCI_MESON=n +CONFIG_PCIE_TEGRA194=n +CONFIG_PCIE_TEGRA194_HOST=n +CONFIG_PCI_EPF_TEST=n +CONFIG_REGMAP_SLIMBUS=n +CONFIG_REGMAP_SOUNDWIRE=n +CONFIG_REGMAP_I3C=n +CONFIG_TEGRA_ACONNECT=n +CONFIG_MHI_BUS=n +CONFIG_MHI_BUS_PCI_GENERIC=n +CONFIG_INTEL_STRATIX10_RSU=n +CONFIG_GNSS=n +CONFIG_GNSS_SERIAL=n +CONFIG_GNSS_MTK_SERIAL=n +CONFIG_MTD_NAND_BRCMNAND=n +CONFIG_MTD_NAND_BRCMNAND_BCMBCA=n +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=n +CONFIG_MTD_NAND_BRCMNAND_IPROC=n +CONFIG_MTD_UBI=n +CONFIG_BLK_DEV_NBD=n +CONFIG_NVME_CORE=n +CONFIG_BLK_DEV_NVME=n +CONFIG_QCOM_COINCELL=n +CONFIG_QCOM_FASTRPC=n +CONFIG_PCI_ENDPOINT_TEST=n +CONFIG_EEPROM_AT24=n +CONFIG_EEPROM_AT25=n +CONFIG_UACCE=n +CONFIG_RAID_ATTRS=n +CONFIG_SCSI_MPT3SAS=n +CONFIG_AHCI_BRCM=n +CONFIG_AHCI_DWC=n +CONFIG_BLK_DEV_MD=n +CONFIG_BLK_DEV_DM=n +CONFIG_DM_MIRROR=n +CONFIG_DM_ZERO=n +CONFIG_MACVLAN=n +CONFIG_MACVTAP=n +CONFIG_TAP=n +CONFIG_VETH=n +CONFIG_MHI_NET=n +CONFIG_B53=n +CONFIG_B53_SRAB_DRIVER=n +CONFIG_NET_DSA_BCM_SF2=n +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=n +CONFIG_NET_DSA_MSCC_FELIX=n +CONFIG_MDIO=n +CONFIG_ATL1C=n +CONFIG_BCMGENET=n +CONFIG_BNX2X=n +CONFIG_SYSTEMPORT=n +CONFIG_MLX4_EN=n +CONFIG_MLX4_CORE=n +CONFIG_MLX5_CORE=n +CONFIG_MSCC_OCELOT_SWITCH_LIB=n +CONFIG_QCOM_EMAC=n +CONFIG_RMNET=n +CONFIG_R8169=n +CONFIG_STMMAC_ETH=n +CONFIG_STMMAC_PLATFORM=n +CONFIG_DWMAC_GENERIC=n +CONFIG_DWMAC_IPQ806X=n +CONFIG_DWMAC_MESON=n +CONFIG_DWMAC_QCOM_ETHQOS=n +CONFIG_DWMAC_ROCKCHIP=n +CONFIG_DWMAC_SOCFPGA=n +CONFIG_DWMAC_STM32=n +CONFIG_DWMAC_SUNXI=n +CONFIG_DWMAC_SUN8I=n +CONFIG_DWMAC_IMX8=n +CONFIG_DWMAC_TEGRA=n +CONFIG_DWMAC_VISCONTI=n +CONFIG_TI_ICSS_IEP=n +CONFIG_QCOM_IPA=n +CONFIG_MESON_GXL_PHY=n +CONFIG_AX88796B_PHY=n +CONFIG_BROADCOM_PHY=n +CONFIG_BCM54140_PHY=n +CONFIG_BCM7XXX_PHY=n +CONFIG_BCM_NET_PHYLIB=n +CONFIG_MARVELL_PHY=n +CONFIG_MICROCHIP_PHY=n +CONFIG_SMSC_PHY=n +CONFIG_DP83869_PHY=n +CONFIG_CAN_DEV=n +CONFIG_CAN_FLEXCAN=n +CONFIG_CAN_M_CAN=n +CONFIG_CAN_M_CAN_PLATFORM=n +CONFIG_CAN_RCAR=n +CONFIG_CAN_RCAR_CANFD=n +CONFIG_CAN_MCP251XFD=n +CONFIG_MDIO_REGMAP=n +CONFIG_MDIO_BUS_MUX_MESON_G12A=n +CONFIG_MDIO_BUS_MUX_MESON_GXL=n +CONFIG_PCS_XPCS=n +CONFIG_ATH_COMMON=n +CONFIG_ATH10K=n +CONFIG_ATH10K_PCI=n +CONFIG_ATH10K_SDIO=n +CONFIG_ATH10K_SNOC=n +CONFIG_WCN36XX=n +CONFIG_ATH11K=n +CONFIG_ATH11K_AHB=n +CONFIG_ATH11K_PCI=n +CONFIG_BRCMUTIL=n +CONFIG_BRCMFMAC=n +CONFIG_MWIFIEX=n +CONFIG_MWIFIEX_SDIO=n +CONFIG_MWIFIEX_PCIE=n +CONFIG_MT76_CORE=n +CONFIG_MT76_CONNAC_LIB=n +CONFIG_MT792x_LIB=n +CONFIG_MT7921_COMMON=n +CONFIG_MT7921E=n +CONFIG_RTL_CARDS=n +CONFIG_RSI_91X=n +CONFIG_RSI_SDIO=n +CONFIG_WL18XX=n +CONFIG_WLCORE=n +CONFIG_WLCORE_SDIO=n +CONFIG_WWAN=n +CONFIG_MHI_WWAN_CTRL=n +CONFIG_MHI_WWAN_MBIM=n +CONFIG_TOUCHSCREEN_ATMEL_MXT=n +CONFIG_TOUCHSCREEN_GOODIX=n +CONFIG_TOUCHSCREEN_ELAN=n +CONFIG_TOUCHSCREEN_EDT_FT5X06=n +CONFIG_INPUT_BBNSM_PWRKEY=n +CONFIG_INPUT_PM8XXX_VIBRATOR=n +CONFIG_INPUT_TPS65219_PWRBUTTON=n +CONFIG_INPUT_PWM_BEEPER=n +CONFIG_INPUT_PWM_VIBRA=n +CONFIG_INPUT_RK805_PWRKEY=n +CONFIG_IPMI_HANDLER=n +CONFIG_IPMI_DEVICE_INTERFACE=n +CONFIG_IPMI_SI=n +CONFIG_HW_RANDOM=n +CONFIG_HW_RANDOM_BCM2835=n +CONFIG_HW_RANDOM_IPROC_RNG200=n +CONFIG_HW_RANDOM_OMAP=n +CONFIG_HW_RANDOM_VIRTIO=n +CONFIG_HW_RANDOM_HISI=n +CONFIG_HW_RANDOM_HISTB=n +CONFIG_HW_RANDOM_XGENE=n +CONFIG_HW_RANDOM_STM32=n +CONFIG_HW_RANDOM_MESON=n +CONFIG_HW_RANDOM_CAVIUM=n +CONFIG_HW_RANDOM_MTK=n +CONFIG_HW_RANDOM_EXYNOS=n +CONFIG_HW_RANDOM_OPTEE=n +CONFIG_HW_RANDOM_NPCM=n +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=n +CONFIG_HW_RANDOM_CN10K=n +CONFIG_TCG_TIS_CORE=n +CONFIG_TCG_TIS=n +CONFIG_TCG_TIS_SPI=n +CONFIG_TCG_TIS_I2C_CR50=n +CONFIG_I2C_BCM2835=n +CONFIG_I2C_CADENCE=n +CONFIG_I2C_GPIO=n +CONFIG_I2C_QCOM_CCI=n +CONFIG_I2C_QCOM_GENI=n +CONFIG_I2C_RZV2M=n +CONFIG_SPI_BCM2835=n +CONFIG_SPI_BCM2835AUX=n +CONFIG_SPI_DESIGNWARE=n +CONFIG_SPI_DW_MMIO=n +CONFIG_SPI_IMX=n +CONFIG_SPI_MESON_SPICC=n +CONFIG_SPI_MESON_SPIFC=n +CONFIG_SPI_MTK_NOR=n +CONFIG_SPI_OMAP24XX=n +CONFIG_SPI_ROCKCHIP_SFC=n +CONFIG_SPI_RPCIF=n +CONFIG_SPI_RSPI=n +CONFIG_SPI_RZV2M_CSI=n +CONFIG_SPI_QCOM_QSPI=n +CONFIG_SPI_QCOM_GENI=n +CONFIG_SPI_SH_MSIOF=n +CONFIG_SPI_TEGRA210_QUAD=n +CONFIG_SPI_TEGRA114=n +CONFIG_SPI_SPIDEV=n +CONFIG_SPMI_MTK_PMIF=n +CONFIG_PINCTRL_RK805=n +CONFIG_PINCTRL_LPASS_LPI=n +CONFIG_PINCTRL_SC7280_LPASS_LPI=n +CONFIG_PINCTRL_SM8250_LPASS_LPI=n +CONFIG_PINCTRL_SM8450_LPASS_LPI=n +CONFIG_PINCTRL_SC8280XP_LPASS_LPI=n +CONFIG_PINCTRL_SM8550_LPASS_LPI=n +CONFIG_GPIO_REGMAP=n +CONFIG_GPIO_ALTERA=n +CONFIG_GPIO_WCD934X=n +CONFIG_GPIO_BD9571MWV=n +CONFIG_GPIO_SL28CPLD=n +CONFIG_POWER_RESET_QCOM_PON=n +CONFIG_NVMEM_REBOOT_MODE=n +CONFIG_BATTERY_SBS=n +CONFIG_BATTERY_MAX17042=n +CONFIG_CHARGER_MT6360=n +CONFIG_CHARGER_BQ25890=n +CONFIG_CHARGER_BQ25980=n +CONFIG_CHARGER_RK817=n +CONFIG_IMX_SC_THERMAL=n +CONFIG_IMX8MM_THERMAL=n +CONFIG_K3_THERMAL=n +CONFIG_QORIQ_THERMAL=n +CONFIG_ROCKCHIP_THERMAL=n +CONFIG_BCM2711_THERMAL=n +CONFIG_BCM2835_THERMAL=n +CONFIG_BRCMSTB_THERMAL=n +CONFIG_TEGRA_SOCTHERM=n +CONFIG_TEGRA_BPMP_THERMAL=n +CONFIG_GENERIC_ADC_THERMAL=n +CONFIG_QCOM_SPMI_ADC_TM5=n +CONFIG_QCOM_SPMI_TEMP_ALARM=n +CONFIG_QCOM_LMH=n +CONFIG_SL28CPLD_WATCHDOG=n +CONFIG_K3_RTI_WATCHDOG=n +CONFIG_SUNXI_WATCHDOG=n +CONFIG_IMX_SC_WDT=n +CONFIG_IMX7ULP_WDT=n +CONFIG_QCOM_WDT=n +CONFIG_MESON_GXBB_WATCHDOG=n +CONFIG_MESON_WATCHDOG=n +CONFIG_PM8916_WATCHDOG=n +CONFIG_BCM7038_WDT=n +CONFIG_MFD_EXYNOS_LPASS=n +CONFIG_MFD_TI_AM335X_TSCADC=n +CONFIG_MFD_WM8994=n +CONFIG_MFD_WCD934X=n +CONFIG_REGULATOR_MT6315=n +CONFIG_REGULATOR_TPS65132=n +CONFIG_REGULATOR_VCTRL=n +CONFIG_RC_CORE=n +CONFIG_RC_MAP=n +CONFIG_IR_GPIO_CIR=n +CONFIG_IR_MESON=n +CONFIG_IR_SUNXI=n +CONFIG_CEC_CORE=n +CONFIG_MEDIA_SUPPORT=n +CONFIG_VIDEO_DEV=n +CONFIG_DVB_CORE=n +CONFIG_V4L2_JPEG_HELPER=n +CONFIG_V4L2_H264=n +CONFIG_V4L2_VP9=n +CONFIG_V4L2_MEM2MEM_DEV=n +CONFIG_V4L2_FWNODE=n +CONFIG_V4L2_ASYNC=n +CONFIG_V4L2_CCI=n +CONFIG_V4L2_CCI_I2C=n +CONFIG_VIDEO_MEDIATEK_JPEG=n +CONFIG_VIDEO_MEDIATEK_VCODEC=n +CONFIG_VIDEO_IMX7_CSI=n +CONFIG_VIDEO_IMX_MIPI_CSIS=n +CONFIG_VIDEO_IMX8_ISI=n +CONFIG_VIDEO_QCOM_CAMSS=n +CONFIG_VIDEO_QCOM_VENUS=n +CONFIG_VIDEO_RCAR_ISP=n +CONFIG_VIDEO_RCAR_CSI2=n +CONFIG_VIDEO_RCAR_VIN=n +CONFIG_VIDEO_RZG2L_CSI2=n +CONFIG_VIDEO_RZG2L_CRU=n +CONFIG_VIDEO_RENESAS_FCP=n +CONFIG_VIDEO_RENESAS_FDP1=n +CONFIG_VIDEO_RENESAS_VSP1=n +CONFIG_VIDEO_RCAR_DRIF=n +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=n +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=n +CONFIG_VIDEO_SAMSUNG_S5P_MFC=n +CONFIG_VIDEO_SUN6I_CSI=n +CONFIG_VIDEO_HANTRO=n +CONFIG_VIDEOBUF2_CORE=n +CONFIG_VIDEOBUF2_V4L2=n +CONFIG_VIDEOBUF2_MEMOPS=n +CONFIG_VIDEOBUF2_DMA_CONTIG=n +CONFIG_VIDEOBUF2_VMALLOC=n +CONFIG_VIDEOBUF2_DMA_SG=n +CONFIG_VIDEO_IR_I2C=n +CONFIG_VIDEO_IMX219=n +CONFIG_VIDEO_IMX412=n +CONFIG_VIDEO_OV5640=n +CONFIG_VIDEO_OV5645=n +CONFIG_MEDIA_TUNER=n +CONFIG_MEDIA_TUNER_MC44S803=n +CONFIG_MEDIA_TUNER_MT20XX=n +CONFIG_MEDIA_TUNER_SIMPLE=n +CONFIG_MEDIA_TUNER_TDA18271=n +CONFIG_MEDIA_TUNER_TDA827X=n +CONFIG_MEDIA_TUNER_TDA8290=n +CONFIG_MEDIA_TUNER_TDA9887=n +CONFIG_MEDIA_TUNER_XC2028=n +CONFIG_MEDIA_TUNER_XC4000=n +CONFIG_MEDIA_TUNER_XC5000=n +CONFIG_TEGRA_HOST1X=n +CONFIG_DRM=n +CONFIG_DRM_KMS_HELPER=n +CONFIG_DRM_DP_AUX_BUS=n +CONFIG_DRM_DISPLAY_HELPER=n +CONFIG_DRM_TTM=n +CONFIG_DRM_EXEC=n +CONFIG_DRM_VRAM_HELPER=n +CONFIG_DRM_TTM_HELPER=n +CONFIG_DRM_GEM_DMA_HELPER=n +CONFIG_DRM_GEM_SHMEM_HELPER=n +CONFIG_DRM_SCHED=n +CONFIG_DRM_I2C_CH7006=n +CONFIG_DRM_I2C_SIL164=n +CONFIG_DRM_I2C_NXP_TDA998X=n +CONFIG_DRM_HDLCD=n +CONFIG_DRM_MALI_DISPLAY=n +CONFIG_DRM_KOMEDA=n +CONFIG_DRM_NOUVEAU=n +CONFIG_DRM_EXYNOS=n +CONFIG_DRM_ROCKCHIP=n +CONFIG_DRM_RCAR_DU=n +CONFIG_DRM_RCAR_CMM=n +CONFIG_DRM_RCAR_DW_HDMI=n +CONFIG_DRM_RCAR_LVDS=n +CONFIG_DRM_RCAR_MIPI_DSI=n +CONFIG_DRM_RZG2L_MIPI_DSI=n +CONFIG_DRM_SUN4I=n +CONFIG_DRM_SUN6I_DSI=n +CONFIG_DRM_SUN8I_DW_HDMI=n +CONFIG_DRM_SUN8I_MIXER=n +CONFIG_DRM_SUN8I_TCON_TOP=n +CONFIG_DRM_MSM=n +CONFIG_DRM_TEGRA=n +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=n +CONFIG_DRM_PANEL_LVDS=n +CONFIG_DRM_PANEL_SIMPLE=n +CONFIG_DRM_PANEL_EDP=n +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=n +CONFIG_DRM_PANEL_RAYDIUM_RM67191=n +CONFIG_DRM_PANEL_SITRONIX_ST7703=n +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=n +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=n +CONFIG_DRM_DISPLAY_CONNECTOR=n +CONFIG_DRM_LONTIUM_LT8912B=n +CONFIG_DRM_LONTIUM_LT9611=n +CONFIG_DRM_LONTIUM_LT9611UXC=n +CONFIG_DRM_ITE_IT66121=n +CONFIG_DRM_NWL_MIPI_DSI=n +CONFIG_DRM_PARADE_PS8640=n +CONFIG_DRM_SAMSUNG_DSIM=n +CONFIG_DRM_SII902X=n +CONFIG_DRM_SIMPLE_BRIDGE=n +CONFIG_DRM_THINE_THC63LVD1024=n +CONFIG_DRM_TOSHIBA_TC358768=n +CONFIG_DRM_TI_TFP410=n +CONFIG_DRM_TI_SN65DSI83=n +CONFIG_DRM_TI_SN65DSI86=n +CONFIG_DRM_ANALOGIX_DP=n +CONFIG_DRM_ANALOGIX_ANX7625=n +CONFIG_DRM_I2C_ADV7511=n +CONFIG_DRM_CDNS_MHDP8546=n +CONFIG_DRM_DW_HDMI=n +CONFIG_DRM_DW_HDMI_AHB_AUDIO=n +CONFIG_DRM_DW_HDMI_I2S_AUDIO=n +CONFIG_DRM_DW_HDMI_CEC=n +CONFIG_DRM_DW_MIPI_DSI=n +CONFIG_DRM_IMX_DCSS=n +CONFIG_DRM_V3D=n +CONFIG_DRM_VC4=n +CONFIG_DRM_ETNAVIV=n +CONFIG_DRM_HISI_HIBMC=n +CONFIG_DRM_HISI_KIRIN=n +CONFIG_DRM_MEDIATEK=n +CONFIG_DRM_MEDIATEK_HDMI=n +CONFIG_DRM_MXSFB=n +CONFIG_DRM_IMX_LCDIF=n +CONFIG_DRM_MESON=n +CONFIG_DRM_MESON_DW_HDMI=n +CONFIG_DRM_MESON_DW_MIPI_DSI=n +CONFIG_DRM_PL111=n +CONFIG_DRM_LIMA=n +CONFIG_DRM_PANFROST=n +CONFIG_DRM_TIDSS=n +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=n +CONFIG_BACKLIGHT_CLASS_DEVICE=n +CONFIG_BACKLIGHT_PWM=n +CONFIG_BACKLIGHT_LP855X=n +CONFIG_SND_ALOOP=n +CONFIG_SND_HDA=n +CONFIG_SND_HDA_TEGRA=n +CONFIG_SND_HDA_CODEC_HDMI=n +CONFIG_SND_HDA_CORE=n +CONFIG_SND_BCM2835_SOC_I2S=n +CONFIG_SND_SOC_FSL_ASRC=n +CONFIG_SND_SOC_FSL_SAI=n +CONFIG_SND_SOC_FSL_AUDMIX=n +CONFIG_SND_SOC_FSL_SSI=n +CONFIG_SND_SOC_FSL_SPDIF=n +CONFIG_SND_SOC_FSL_ESAI=n +CONFIG_SND_SOC_FSL_MICFIL=n +CONFIG_SND_SOC_FSL_EASRC=n +CONFIG_SND_SOC_FSL_UTILS=n +CONFIG_SND_SOC_IMX_PCM_DMA=n +CONFIG_SND_SOC_IMX_AUDMUX=n +CONFIG_SND_IMX_SOC=n +CONFIG_SND_SOC_IMX_SGTL5000=n +CONFIG_SND_SOC_IMX_SPDIF=n +CONFIG_SND_SOC_FSL_ASOC_CARD=n +CONFIG_SND_SOC_IMX_AUDMIX=n +CONFIG_SND_SOC_MEDIATEK=n +CONFIG_SND_SOC_MT8183=n +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=n +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=n +CONFIG_SND_SOC_MT8192=n +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=n +CONFIG_SND_MESON_AIU=n +CONFIG_SND_MESON_AXG_FIFO=n +CONFIG_SND_MESON_AXG_FRDDR=n +CONFIG_SND_MESON_AXG_TODDR=n +CONFIG_SND_MESON_AXG_TDM_FORMATTER=n +CONFIG_SND_MESON_AXG_TDM_INTERFACE=n +CONFIG_SND_MESON_AXG_TDMIN=n +CONFIG_SND_MESON_AXG_TDMOUT=n +CONFIG_SND_MESON_AXG_SOUND_CARD=n +CONFIG_SND_MESON_AXG_SPDIFOUT=n +CONFIG_SND_MESON_AXG_SPDIFIN=n +CONFIG_SND_MESON_AXG_PDM=n +CONFIG_SND_MESON_CARD_UTILS=n +CONFIG_SND_MESON_CODEC_GLUE=n +CONFIG_SND_MESON_GX_SOUND_CARD=n +CONFIG_SND_MESON_G12A_TOACODEC=n +CONFIG_SND_MESON_G12A_TOHDMITX=n +CONFIG_SND_SOC_MESON_T9015=n +CONFIG_SND_SOC_QCOM=n +CONFIG_SND_SOC_LPASS_CPU=n +CONFIG_SND_SOC_LPASS_HDMI=n +CONFIG_SND_SOC_LPASS_PLATFORM=n +CONFIG_SND_SOC_LPASS_CDC_DMA=n +CONFIG_SND_SOC_LPASS_APQ8016=n +CONFIG_SND_SOC_LPASS_SC7180=n +CONFIG_SND_SOC_LPASS_SC7280=n +CONFIG_SND_SOC_APQ8016_SBC=n +CONFIG_SND_SOC_QCOM_COMMON=n +CONFIG_SND_SOC_QCOM_SDW=n +CONFIG_SND_SOC_QDSP6_COMMON=n +CONFIG_SND_SOC_QDSP6_CORE=n +CONFIG_SND_SOC_QDSP6_AFE=n +CONFIG_SND_SOC_QDSP6_AFE_DAI=n +CONFIG_SND_SOC_QDSP6_AFE_CLOCKS=n +CONFIG_SND_SOC_QDSP6_ADM=n +CONFIG_SND_SOC_QDSP6_ROUTING=n +CONFIG_SND_SOC_QDSP6_ASM=n +CONFIG_SND_SOC_QDSP6_ASM_DAI=n +CONFIG_SND_SOC_QDSP6_APM_DAI=n +CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI=n +CONFIG_SND_SOC_QDSP6_APM=n +CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS=n +CONFIG_SND_SOC_QDSP6_PRM=n +CONFIG_SND_SOC_QDSP6=n +CONFIG_SND_SOC_MSM8996=n +CONFIG_SND_SOC_SDM845=n +CONFIG_SND_SOC_SM8250=n +CONFIG_SND_SOC_SC7180=n +CONFIG_SND_SOC_SC7280=n +CONFIG_SND_SOC_ROCKCHIP=n +CONFIG_SND_SOC_ROCKCHIP_I2S=n +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=n +CONFIG_SND_SOC_ROCKCHIP_SPDIF=n +CONFIG_SND_SOC_ROCKCHIP_RT5645=n +CONFIG_SND_SOC_RK3399_GRU_SOUND=n +CONFIG_SND_SOC_RCAR=n +CONFIG_SND_SOC_RZ=n +CONFIG_SND_SUN8I_CODEC=n +CONFIG_SND_SUN8I_CODEC_ANALOG=n +CONFIG_SND_SUN50I_CODEC_ANALOG=n +CONFIG_SND_SUN4I_I2S=n +CONFIG_SND_SUN4I_SPDIF=n +CONFIG_SND_SUN8I_ADDA_PR_REGMAP=n +CONFIG_SND_SOC_TEGRA=n +CONFIG_SND_SOC_TEGRA210_AHUB=n +CONFIG_SND_SOC_TEGRA210_DMIC=n +CONFIG_SND_SOC_TEGRA210_I2S=n +CONFIG_SND_SOC_TEGRA210_OPE=n +CONFIG_SND_SOC_TEGRA186_ASRC=n +CONFIG_SND_SOC_TEGRA186_DSPK=n +CONFIG_SND_SOC_TEGRA210_ADMAIF=n +CONFIG_SND_SOC_TEGRA210_MVC=n +CONFIG_SND_SOC_TEGRA210_SFC=n +CONFIG_SND_SOC_TEGRA210_AMX=n +CONFIG_SND_SOC_TEGRA210_ADX=n +CONFIG_SND_SOC_TEGRA210_MIXER=n +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=n +CONFIG_SND_SOC_TI_EDMA_PCM=n +CONFIG_SND_SOC_TI_SDMA_PCM=n +CONFIG_SND_SOC_TI_UDMA_PCM=n +CONFIG_SND_SOC_DAVINCI_MCASP=n +CONFIG_SND_SOC_J721E_EVM=n +CONFIG_SND_SOC_WM_HUBS=n +CONFIG_SND_SOC_ADAU7002=n +CONFIG_SND_SOC_AK4613=n +CONFIG_SND_SOC_BT_SCO=n +CONFIG_SND_SOC_CROS_EC_CODEC=n +CONFIG_SND_SOC_DA7213=n +CONFIG_SND_SOC_DA7219=n +CONFIG_SND_SOC_DMIC=n +CONFIG_SND_SOC_HDMI_CODEC=n +CONFIG_SND_SOC_ES7134=n +CONFIG_SND_SOC_ES7241=n +CONFIG_SND_SOC_ES8316=n +CONFIG_SND_SOC_GTM601=n +CONFIG_SND_SOC_MAX98357A=n +CONFIG_SND_SOC_MAX98927=n +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=n +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=n +CONFIG_SND_SOC_PCM3168A=n +CONFIG_SND_SOC_PCM3168A_I2C=n +CONFIG_SND_SOC_RK817=n +CONFIG_SND_SOC_RL6231=n +CONFIG_SND_SOC_RT1015=n +CONFIG_SND_SOC_RT1015P=n +CONFIG_SND_SOC_RT5514=n +CONFIG_SND_SOC_RT5514_SPI=n +CONFIG_SND_SOC_RT5640=n +CONFIG_SND_SOC_RT5645=n +CONFIG_SND_SOC_RT5659=n +CONFIG_SND_SOC_RT5663=n +CONFIG_SND_SOC_RT5682=n +CONFIG_SND_SOC_RT5682_I2C=n +CONFIG_SND_SOC_RT5682S=n +CONFIG_SND_SOC_SGTL5000=n +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=n +CONFIG_SND_SOC_SIMPLE_MUX=n +CONFIG_SND_SOC_SPDIF=n +CONFIG_SND_SOC_TAS2552=n +CONFIG_SND_SOC_TAS571X=n +CONFIG_SND_SOC_TLV320AIC31XX=n +CONFIG_SND_SOC_TLV320AIC32X4=n +CONFIG_SND_SOC_TLV320AIC32X4_I2C=n +CONFIG_SND_SOC_TLV320AIC3X=n +CONFIG_SND_SOC_TLV320AIC3X_I2C=n +CONFIG_SND_SOC_TS3A227E=n +CONFIG_SND_SOC_WCD_CLASSH=n +CONFIG_SND_SOC_WCD9335=n +CONFIG_SND_SOC_WCD_MBHC=n +CONFIG_SND_SOC_WCD934X=n +CONFIG_SND_SOC_WCD938X=n +CONFIG_SND_SOC_WCD938X_SDW=n +CONFIG_SND_SOC_WM8524=n +CONFIG_SND_SOC_WM8904=n +CONFIG_SND_SOC_WM8960=n +CONFIG_SND_SOC_WM8962=n +CONFIG_SND_SOC_WM8978=n +CONFIG_SND_SOC_WM8994=n +CONFIG_SND_SOC_WSA881X=n +CONFIG_SND_SOC_MT6358=n +CONFIG_SND_SOC_MT6359=n +CONFIG_SND_SOC_NAU8822=n +CONFIG_SND_SOC_LPASS_MACRO_COMMON=n +CONFIG_SND_SOC_LPASS_WSA_MACRO=n +CONFIG_SND_SOC_LPASS_VA_MACRO=n +CONFIG_SND_SOC_LPASS_RX_MACRO=n +CONFIG_SND_SOC_LPASS_TX_MACRO=n +CONFIG_SND_SIMPLE_CARD_UTILS=n +CONFIG_SND_SIMPLE_CARD=n +CONFIG_SND_AUDIO_GRAPH_CARD=n +CONFIG_SND_AUDIO_GRAPH_CARD2=n +CONFIG_SCSI_UFS_CDNS_PLATFORM=n +CONFIG_SCSI_UFS_QCOM=n +CONFIG_SCSI_UFS_RENESAS=n +CONFIG_SCSI_UFS_TI_J721E=n +CONFIG_LEDS_CLASS_MULTICOLOR=n +CONFIG_LEDS_LM3692X=n +CONFIG_LEDS_PCA9532=n +CONFIG_LEDS_QCOM_LPG=n +CONFIG_EDAC_LAYERSCAPE=n +CONFIG_RTC_DRV_DS1307=n +CONFIG_RTC_DRV_HYM8563=n +CONFIG_RTC_DRV_RK808=n +CONFIG_RTC_DRV_ISL1208=n +CONFIG_RTC_DRV_PCF85063=n +CONFIG_RTC_DRV_PCF85363=n +CONFIG_RTC_DRV_M41T80=n +CONFIG_RTC_DRV_BQ32K=n +CONFIG_RTC_DRV_RX8581=n +CONFIG_RTC_DRV_RV3028=n +CONFIG_RTC_DRV_RV8803=n +CONFIG_RTC_DRV_PCF2127=n +CONFIG_RTC_DRV_FSL_FTM_ALARM=n +CONFIG_RTC_DRV_MESON_VRTC=n +CONFIG_RTC_DRV_PM8XXX=n +CONFIG_RTC_DRV_SNVS=n +CONFIG_RTC_DRV_BBNSM=n +CONFIG_RTC_DRV_IMX_SC=n +CONFIG_RTC_DRV_MT6397=n +CONFIG_RTC_DRV_TI_K3=n +CONFIG_BCM_SBA_RAID=n +CONFIG_DMA_SUN6I=n +CONFIG_IMX_SDMA=n +CONFIG_TEGRA210_ADMA=n +CONFIG_QCOM_GPI_DMA=n +CONFIG_RENESAS_USB_DMAC=n +CONFIG_XEN_PCIDEV_STUB=n +CONFIG_VIDEO_MAX96712=n +CONFIG_CROS_EC_RPMSG=n +CONFIG_CROS_EC_CHARDEV=n +CONFIG_COMMON_CLK_BD718XX=n +CONFIG_CLK_RASPBERRYPI=n +CONFIG_COMMON_CLK_MESON_PHASE=n +CONFIG_COMMON_CLK_MESON_SCLK_DIV=n +CONFIG_COMMON_CLK_AXG_AUDIO=n +CONFIG_MSM_MMCC_8994=n +CONFIG_MSM_MMCC_8996=n +CONFIG_MSM_MMCC_8998=n +CONFIG_QCM_DISPCC_2290=n +CONFIG_SC_DISPCC_8280XP=n +CONFIG_SA_GPUCC_8775P=n +CONFIG_SC_GPUCC_8280XP=n +CONFIG_SC_LPASSCC_8280XP=n +CONFIG_SDM_CAMCC_845=n +CONFIG_SDM_LPASSCC_845=n +CONFIG_SM_CAMCC_8250=n +CONFIG_SM_DISPCC_6115=n +CONFIG_SM_DISPCC_8450=n +CONFIG_SM_DISPCC_8550=n +CONFIG_SM_GPUCC_6115=n +CONFIG_CLK_GFM_LPASS_SM8250=n +CONFIG_OMAP2PLUS_MBOX=n +CONFIG_BCM_FLEXRM_MBOX=n +CONFIG_MTK_CMDQ_MBOX=n +CONFIG_MTK_SCP=n +CONFIG_PRU_REMOTEPROC=n +CONFIG_QCOM_PIL_INFO=n +CONFIG_QCOM_RPROC_COMMON=n +CONFIG_QCOM_Q6V5_COMMON=n +CONFIG_QCOM_Q6V5_ADSP=n +CONFIG_QCOM_Q6V5_MSS=n +CONFIG_QCOM_Q6V5_PAS=n +CONFIG_QCOM_SYSMON=n +CONFIG_QCOM_WCNSS_PIL=n +CONFIG_TI_K3_DSP_REMOTEPROC=n +CONFIG_TI_K3_R5_REMOTEPROC=n +CONFIG_RPMSG_CHAR=n +CONFIG_RPMSG_CTRL=n +CONFIG_RPMSG_MTK_SCP=n +CONFIG_RPMSG_QCOM_GLINK_SMEM=n +CONFIG_SOUNDWIRE=n +CONFIG_SOUNDWIRE_QCOM=n +CONFIG_MESON_CANVAS=n +CONFIG_MTK_CMDQ=n +CONFIG_MTK_DEVAPC=n +CONFIG_MTK_MMSYS=n +CONFIG_MTK_SVS=n +CONFIG_QCOM_LLCC=n +CONFIG_QCOM_MDT_LOADER=n +CONFIG_QCOM_OCMEM=n +CONFIG_QCOM_PDR_HELPERS=n +CONFIG_QCOM_QMI_HELPERS=n +CONFIG_QCOM_RMTFS_MEM=n +CONFIG_QCOM_SOCINFO=n +CONFIG_QCOM_SPM=n +CONFIG_QCOM_STATS=n +CONFIG_QCOM_WCNSS_CTRL=n +CONFIG_QCOM_APR=n +CONFIG_QCOM_ICC_BWMON=n +CONFIG_TI_PRUSS=n +CONFIG_DEVFREQ_GOV_PASSIVE=n +CONFIG_ARM_IMX8M_DDRC_DEVFREQ=n +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=n +CONFIG_EXTCON_PTN5150=n +CONFIG_RENESAS_RPCIF=n +CONFIG_IIO_KFIFO_BUF=n +CONFIG_IIO_TRIGGERED_BUFFER=n +CONFIG_IMX93_ADC=n +CONFIG_MAX9611=n +CONFIG_MEDIATEK_MT6577_AUXADC=n +CONFIG_QCOM_VADC_COMMON=n +CONFIG_QCOM_SPMI_VADC=n +CONFIG_QCOM_SPMI_ADC5=n +CONFIG_ROCKCHIP_SARADC=n +CONFIG_RZG2L_ADC=n +CONFIG_TI_ADS1015=n +CONFIG_TI_AM335X_ADC=n +CONFIG_IIO_CROS_EC_SENSORS_CORE=n +CONFIG_IIO_CROS_EC_SENSORS=n +CONFIG_IIO_ST_SENSORS_I2C=n +CONFIG_IIO_ST_SENSORS_SPI=n +CONFIG_IIO_ST_SENSORS_CORE=n +CONFIG_IIO_ST_LSM6DSX=n +CONFIG_IIO_ST_LSM6DSX_I2C=n +CONFIG_IIO_ST_LSM6DSX_SPI=n +CONFIG_IIO_ST_LSM6DSX_I3C=n +CONFIG_IIO_CROS_EC_LIGHT_PROX=n +CONFIG_SENSORS_ISL29018=n +CONFIG_VCNL4000=n +CONFIG_IIO_ST_MAGN_3AXIS=n +CONFIG_IIO_ST_MAGN_I2C_3AXIS=n +CONFIG_IIO_ST_MAGN_SPI_3AXIS=n +CONFIG_IIO_CROS_EC_BARO=n +CONFIG_MPL3115=n +CONFIG_PWM_BCM2835=n +CONFIG_PWM_BRCMSTB=n +CONFIG_PWM_CROS_EC=n +CONFIG_PWM_IMX27=n +CONFIG_PWM_MESON=n +CONFIG_PWM_MTK_DISP=n +CONFIG_PWM_MEDIATEK=n +CONFIG_PWM_RCAR=n +CONFIG_PWM_RENESAS_TPU=n +CONFIG_PWM_RZ_MTU3=n +CONFIG_PWM_SL28CPLD=n +CONFIG_PWM_SUN4I=n +CONFIG_PWM_TEGRA=n +CONFIG_PWM_TIECAP=n +CONFIG_PWM_TIEHRPWM=n +CONFIG_PWM_VISCONTI=n +CONFIG_IMX_MU_MSI=n +CONFIG_TI_PRUSS_INTC=n +CONFIG_RESET_BERLIN=n +CONFIG_RESET_MESON_AUDIO_ARB=n +CONFIG_RESET_QCOM_PDC=n +CONFIG_RESET_RASPBERRYPI=n +CONFIG_PHY_CAN_TRANSCEIVER=n +CONFIG_PHY_SUN6I_MIPI_DPHY=n +CONFIG_PHY_CADENCE_TORRENT=n +CONFIG_PHY_CADENCE_SIERRA=n +CONFIG_PHY_MIXEL_MIPI_DPHY=n +CONFIG_PHY_MTK_HDMI=n +CONFIG_PHY_MTK_MIPI_DSI=n +CONFIG_PHY_QCOM_EDP=n +CONFIG_PHY_QCOM_PCIE2=n +CONFIG_PHY_QCOM_QMP=n +CONFIG_PHY_QCOM_QMP_COMBO=n +CONFIG_PHY_QCOM_QMP_PCIE=n +CONFIG_PHY_QCOM_QMP_PCIE_8996=n +CONFIG_PHY_QCOM_QMP_UFS=n +CONFIG_PHY_QCOM_QMP_USB=n +CONFIG_PHY_QCOM_QUSB2=n +CONFIG_PHY_QCOM_SNPS_EUSB2=n +CONFIG_PHY_QCOM_EUSB2_REPEATER=n +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=n +CONFIG_PHY_QCOM_USB_HS_28NM=n +CONFIG_PHY_QCOM_USB_SS=n +CONFIG_PHY_QCOM_SGMII_ETH=n +CONFIG_PHY_RCAR_GEN3_USB3=n +CONFIG_PHY_ROCKCHIP_INNO_HDMI=n +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=n +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=n +CONFIG_PHY_ROCKCHIP_PCIE=n +CONFIG_PHY_TEGRA194_P2U=n +CONFIG_PHY_AM654_SERDES=n +CONFIG_PHY_J721E_WIZ=n +CONFIG_ARM_CCI_PMU=n +CONFIG_ARM_CCN=n +CONFIG_ARM_CMN=n +CONFIG_ARM_SMMU_V3_PMU=n +CONFIG_ARM_DSU_PMU=n +CONFIG_FSL_IMX8_DDR_PMU=n +CONFIG_ARM_SPE_PMU=n +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=n +CONFIG_NVMEM_LAYOUT_SL28_VPD=n +CONFIG_NVMEM_IMX_OCOTP_ELE=n +CONFIG_NVMEM_LAYERSCAPE_SFP=n +CONFIG_NVMEM_MESON_EFUSE=n +CONFIG_NVMEM_RMEM=n +CONFIG_NVMEM_SPMI_SDAM=n +CONFIG_FPGA_MGR_ALTERA_CVP=n +CONFIG_FPGA_MGR_STRATIX10_SOC=n +CONFIG_FPGA_BRIDGE=n +CONFIG_ALTERA_FREEZE_BRIDGE=n +CONFIG_FPGA_REGION=n +CONFIG_OF_FPGA_REGION=n +CONFIG_MUX_GPIO=n +CONFIG_SLIMBUS=n +CONFIG_SLIM_QCOM_CTRL=n +CONFIG_SLIM_QCOM_NGD_CTRL=n +CONFIG_INTERCONNECT_IMX8MM=n +CONFIG_INTERCONNECT_IMX8MN=n +CONFIG_INTERCONNECT_IMX8MQ=n +CONFIG_INTERCONNECT_QCOM_MSM8916=n +CONFIG_INTERCONNECT_QCOM_MSM8996=n +CONFIG_INTERCONNECT_QCOM_OSM_L3=n +CONFIG_INTERCONNECT_QCOM_QCM2290=n +CONFIG_INTERCONNECT_QCOM_QCS404=n +CONFIG_INTERCONNECT_QCOM_SM8150=n +CONFIG_INTERCONNECT_QCOM_SM8250=n +CONFIG_INTERCONNECT_QCOM_SM8350=n +CONFIG_INTERCONNECT_QCOM_SMD_RPM=n +CONFIG_COUNTER=n +CONFIG_RZ_MTU3_CNT=n +CONFIG_HTE_TEGRA194_TEST=n +CONFIG_BTRFS_FS=n +CONFIG_FUSE_FS=n +CONFIG_CUSE=n +CONFIG_OVERLAY_FS=n +CONFIG_XOR_BLOCKS=n +CONFIG_CRYPTO_KPP=n +CONFIG_CRYPTO_AUTHENC=n +CONFIG_CRYPTO_TEST=n +CONFIG_CRYPTO_ENGINE=n +CONFIG_CRYPTO_DH=n +CONFIG_CRYPTO_ECC=n +CONFIG_CRYPTO_ECDH=n +CONFIG_CRYPTO_CURVE25519=n +CONFIG_CRYPTO_DES=n +CONFIG_CRYPTO_SM4=n +CONFIG_CRYPTO_SM4_GENERIC=n +CONFIG_CRYPTO_CBC=n +CONFIG_CRYPTO_CTR=n +CONFIG_CRYPTO_ECB=n +CONFIG_CRYPTO_XTS=n +CONFIG_CRYPTO_CCM=n +CONFIG_CRYPTO_GCM=n +CONFIG_CRYPTO_BLAKE2B=n +CONFIG_CRYPTO_CMAC=n +CONFIG_CRYPTO_GHASH=n +CONFIG_CRYPTO_MD5=n +CONFIG_CRYPTO_MICHAEL_MIC=n +CONFIG_CRYPTO_SM3=n +CONFIG_CRYPTO_SM3_GENERIC=n +CONFIG_CRYPTO_XXHASH=n +CONFIG_CRYPTO_USER_API_RNG=n +CONFIG_CRYPTO_CHACHA20_NEON=n +CONFIG_CRYPTO_SHA512_ARM64=n +CONFIG_CRYPTO_SHA512_ARM64_CE=n +CONFIG_CRYPTO_SHA3_ARM64=n +CONFIG_CRYPTO_SM3_ARM64_CE=n +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=n +CONFIG_CRYPTO_AES_ARM64_BS=n +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=n +CONFIG_CRYPTO_DEV_SUN8I_CE=n +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=n +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=n +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=n +CONFIG_CRYPTO_DEV_FSL_CAAM=n +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=n +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=n +CONFIG_CRYPTO_DEV_QCE=n +CONFIG_CRYPTO_DEV_QCOM_RNG=n +CONFIG_CRYPTO_DEV_BCM_SPU=n +CONFIG_CRYPTO_DEV_CCREE=n +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=n +CONFIG_CRYPTO_DEV_SA2UL=n +CONFIG_RAID6_PQ=n +CONFIG_CRYPTO_LIB_ARC4=n +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=n +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=n +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=n +CONFIG_CRYPTO_LIB_DES=n +CONFIG_LIBCRC32C=n +CONFIG_CORESIGHT=n +CONFIG_CORESIGHT_LINKS_AND_SINKS=n +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=n +CONFIG_CORESIGHT_CATU=n +CONFIG_CORESIGHT_SINK_TPIU=n +CONFIG_CORESIGHT_SINK_ETBV10=n +CONFIG_CORESIGHT_STM=n +CONFIG_CORESIGHT_CPU_DEBUG=n +CONFIG_CORESIGHT_CTI=n diff --git a/KERNEL/minimal_defconfig b/KERNEL/minimal_defconfig new file mode 100644 index 0000000..df3e2cc --- /dev/null +++ b/KERNEL/minimal_defconfig @@ -0,0 +1,197 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PROFILING=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_ARCH_STM32=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=2 +CONFIG_HOTPLUG_CPU=y +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +# CONFIG_EFI is not set +# CONFIG_SUSPEND is not set +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_PAGE_REPORTING=y +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=19 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_PCPU_DEV_REFCNT is not set +CONFIG_FAILOVER=y +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_SCMI_STM32MP_OSTL_V5=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_STM32F7=y +CONFIG_I3C=y +CONFIG_SPI=y +CONFIG_SPI_MEM=y +CONFIG_PPS=y +CONFIG_PINCTRL_SINGLE=y +# CONFIG_PINCTRL_STM32MP215 is not set +# CONFIG_PINCTRL_STM32MP235 is not set +# CONFIG_PINCTRL_STM32_HDP is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_REGULATOR=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_CQHCI=y +CONFIG_DMADEVICES=y +CONFIG_STM32_DMA3=y +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_SURFACE_PLATFORMS is not set +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_RS9_PCIE=y +CONFIG_COMMON_CLK_VC5=y +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=y +CONFIG_PLATFORM_MHU=y +CONFIG_STM32_IPCC=y +CONFIG_MAILBOX_CDEV=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_STM32_RISAB is not set +# CONFIG_STM32_RISAF is not set +# CONFIG_STM32MP_EXTI is not set +# CONFIG_RESET_SCMI is not set +CONFIG_GENERIC_PHY=y +# CONFIG_ARM_PMU is not set +# CONFIG_STM32_DDR_PMU is not set +CONFIG_STM=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_KEYS=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS7_MESSAGE_PARSER=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_PACKING=y +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_CRC8=y +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_IRQ_POLL=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_MEMTEST=y diff --git a/LICENSE.md b/LICENSE.md new file mode 100755 index 0000000..c213a3f --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,9 @@ +| Component | Copyright | License | +|:--------- |:---------- |:------- | +| make_mp25x_FIP.sh | STMicroelectronics | BSD-3-Clause | +| make_mp25x_KERNEL.sh | STMicroelectronics | BSD-3-Clause | +| unpack.sh | STMicroelectronics | BSD-3-Clause | +| FLASH_LAYOUT | STMicroelectronics | BSD-3-Clause | +| KERNEL | STMicroelectronics | BSD-3-Clause | +| YOCTO | STMicroelectronics | BSD-3-Clause | +| pdf_slides | STMicroelectronics | BSD-3-Clause | diff --git a/README.md b/README.md index ef9904b..6acdd3b 100644 --- a/README.md +++ b/README.md @@ -1 +1,50 @@ -# STM32MPU-OSTL-DEV-helper \ No newline at end of file +# SDK_helper
+OpenSTLinux SDK tools
+##############################
+ +CONTENTS:
+ - folder FLASH_LAYOUT: flashlayout examples for writing tfa and FIP partitions;
+ - folder KERNEL: an example of minimal Linux KERNEL configuration for STM32MP2;
+ - folder YOCTO: a simple example of meta-layer that defines mymachine, myboard and external custom dts files;
+ - unpack.sh, make_mp25x_FIP.sh, make_mp25x_KERNEL.sh: set of scripts to simplify the usage of STM32MP2Dev OpenSTLinux Developer Package. + + +HOW TO USE the BUILD scripts::
+ Prerequisite:
+ - Download and extract STM32MP2Dev OpenSTLinux Developer Package
+    [Rif. https://www.st.com/en/embedded-software/stm32mp2dev.html]
+    [Rif. https://wiki.st.com/stm32mpu/wiki/STM32MPU_Developer_Package]
+ + Inside the folder where MP2-DEV-SRC package has been extracted
+ - Edit make_mp25x_FIP.sh and run ./make_mp25x_FIP.sh
+ - Edit make_mp25x_KERNEL.sh and run ./make_mp25x_KERNEL.sh
+ +
+Update uSDCard from Linux HOST PC::
+ - u-boot (FIP):
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/ conv=sync
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/ conv=sync
+ + - Arm-Trusted-Firmware (TF-A):
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/ conv=sync
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/ conv=sync + +
+ +Update eMMC from target board using the serial console command line:
+ - u-boot (FIP):
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/mmcblk0p3 conv=sync
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/mmcblk0p4 conv=sync + + - Arm-Trusted-Firmware (TF-A):
+ echo 0 > /sys/block/mmcblk0boot0/force_ro
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/mmcblk0boot0 conv=sync
+ echo 1 > /sys/block/mmcblk0boot0/force_ro + + echo 0 > /sys/block/mmcblk0boot1/force_ro
+ dd if=FIP_artifacts/fip-stm32mp257f-ev1-optee.bin of=/dev/mmcblk0boot1 conv=sync
+ echo 1 > /sys/block/mmcblk0boot1/force_ro + +
+Update Linux kernel and devicetree DTS file from target board using the serial console command line:
+ - Overwrite files in the /boot/ and /lib/modules/ folders on the target board. diff --git a/SECURITY.md b/SECURITY.md new file mode 100755 index 0000000..9b04420 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,15 @@ +# Report potential product security vulnerabilities + +ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations and solutions when applicable. + +If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html** + + + +### IMPORTANT - READ CAREFULLY: + +STMicroelectronics International N.V., on behalf of itself, its affiliates and subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”) seriously. In order to review Your Report (the terms “You” and “Yours” include your employer, and all affiliates, subsidiaries and related persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so. + +As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function. + +By submitting Your Report, You agree that ST’s [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications. diff --git a/YOCTO/meta-mylayer/COPYING.MIT b/YOCTO/meta-mylayer/COPYING.MIT new file mode 100644 index 0000000..fb950dc --- /dev/null +++ b/YOCTO/meta-mylayer/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/YOCTO/meta-mylayer/README b/YOCTO/meta-mylayer/README new file mode 100644 index 0000000..b53d181 --- /dev/null +++ b/YOCTO/meta-mylayer/README @@ -0,0 +1,41 @@ +This README file contains information on the contents of the meta-mylayer layer. + +Please see the corresponding sections below for details. + +Dependencies +============ + + URI: + branch: + + URI: + branch: + + . + . + . + +Patches +======= + +Please submit any patches against the meta-mylayer layer to the xxxx mailing list (xxxx@zzzz.org) +and cc: the maintainer: + +Maintainer: XXX YYYYYY + +Table of Contents +================= + + I. Adding the meta-mylayer layer to your build + II. Misc + + +I. Adding the meta-mylayer layer to your build +================================================= + +Run 'bitbake-layers add-layer meta-mylayer' + +II. Misc +======== + +--- replace with specific information about the meta-mylayer layer --- diff --git a/YOCTO/meta-mylayer/conf/eula/ST_EULA_SLA b/YOCTO/meta-mylayer/conf/eula/ST_EULA_SLA new file mode 100644 index 0000000..5fbc604 --- /dev/null +++ b/YOCTO/meta-mylayer/conf/eula/ST_EULA_SLA @@ -0,0 +1,97 @@ +SLA0048 Rev4/March 2018 + +BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met: +1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission. +4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics. +5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below). +6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license. +7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. 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Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license. + +THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. 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WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED. diff --git a/YOCTO/meta-mylayer/conf/eula/stm32mp25-myboard b/YOCTO/meta-mylayer/conf/eula/stm32mp25-myboard new file mode 120000 index 0000000..ab103d9 --- /dev/null +++ b/YOCTO/meta-mylayer/conf/eula/stm32mp25-myboard @@ -0,0 +1 @@ +ST_EULA_SLA \ No newline at end of file diff --git a/YOCTO/meta-mylayer/conf/layer.conf b/YOCTO/meta-mylayer/conf/layer.conf new file mode 100644 index 0000000..f969067 --- /dev/null +++ b/YOCTO/meta-mylayer/conf/layer.conf @@ -0,0 +1,13 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-mylayer" +BBFILE_PATTERN_meta-mylayer = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-mylayer = "6" + +LAYERDEPENDS_meta-mylayer = "core" +LAYERSERIES_COMPAT_meta-mylayer = "scarthgap" diff --git a/YOCTO/meta-mylayer/conf/machine/stm32mp25-myboard.conf b/YOCTO/meta-mylayer/conf/machine/stm32mp25-myboard.conf new file mode 100644 index 0000000..c61d4c0 --- /dev/null +++ b/YOCTO/meta-mylayer/conf/machine/stm32mp25-myboard.conf @@ -0,0 +1,125 @@ +#@TYPE: Machine +#@NAME: stm32mp25-myboard +#@DESCRIPTION: Configuration for all STM32MP25 myboard boards (MYBOARD) +#@NEEDED_BSPLAYERS: layers/meta-openembedded/meta-oe layers/meta-openembedded/meta-python + +# Define specific familly common machine name +MACHINEOVERRIDES =. "stm32mp2common:stm32mp25common:" + +include conf/machine/include/st-machine-common-stm32mp.inc +include conf/machine/include/st-machine-providers-stm32mp.inc + +# ========================================================================= +# Chip architecture +# ========================================================================= +DEFAULTTUNE = "cortexa35" +include conf/machine/include/arm/armv8a/tune-cortexa35.inc + +# ========================================================================= +# boot scheme +# ========================================================================= +BOOTSCHEME_LABELS = "optee" + +# ========================================================================= +# boot device +# ========================================================================= +# Define the boot device supported +BOOTDEVICE_LABELS += "emmc" +# BOOTDEVICE_LABELS += "nor-sdcard" +# BOOTDEVICE_LABELS += "sdcard" + +# ========================================================================= +# Machine settings +# ========================================================================= +# activate external dt +EXTERNAL_DT_ENABLED = "1" + +# Define list of devicetree per supported storage +STM32MP_DT_FILES_EMMC = "stm32mp257f-myboard" +# STM32MP_DT_FILES_SDCARD = "stm32mp257f-myboard" +# STM32MP_DT_FILES_NOR = "stm32mp257f-myboard" + +# EXTERNAL_DEVICETREE_SDCARD = "stm32mp257f-myboard" + +EXTERNAL_DEVICETREE_EMMC = "stm32mp257f-myboard" + +UBOOT_CONFIG[default_stm32mp25] = "stm32mp25_myboard_defconfig,,u-boot.dtb" + +# ========================================================================= +# Machine features +# ========================================================================= +# MACHINE_FEATURES += "splashscreen" +# MACHINE_FEATURES += "watchdog" +# MACHINE_FEATURES += "bluetooth" +# MACHINE_FEATURES += "wifi" + +# GPU +# MACHINE_FEATURES += "${@'gpu' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}" +# MACHINE_FEATURES += "${@'openvx' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}" +# MACHINE_FEATURES += "${@'opencl' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}" +# MACHINE_FEATURES += "${@'vulkan' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}" + +# M33 +# MACHINE_FEATURES += "m33copro" + +# Bluetooth +# BLUETOOTH_LIST += "linux-firmware-bluetooth-bcm43xx" +# Wifi +# WIFI_LIST += "linux-firmware-bcm43439" +# PCIe +# PCI_LIST += "linux-firmware-rtl8168" + +# ========================================================================== +# M33 Boards +# ========================================================================== +# Lists of boards/devicetree on which the m33 service MUST be started +# M33_BOARDS_START_AT_STARTUP = "stm32mp257f-myboard" +# M33_BOARDS_START_AT_STARTUP =+ "${@bb.utils.contains('EXTERNAL_DT_ENABLED', '1', 'stm32mp257f-myboard', '', d)}" + +# ========================================================================= +# OPTEE +# ========================================================================= +# For sdk generation, declare the default board configuration to use. +ST_OPTEE_EXPORT_TA_REF_BOARD:stm32mp2common = "stm32mp257f-myboard.dts" + +# ========================================================================= +# WIC for sdcard raw image +# ========================================================================= +WIC_CREATE_EXTRA_ARGS = "--no-fstab-update" +WKS_FILE_DEPENDS ?= " \ + virtual/bootloader \ + virtual/trusted-firmware-a \ + virtual-optee-os \ + ${@bb.utils.contains('ST_BOOTFS','1','st-image-bootfs', '', d)} \ + ${@bb.utils.contains('ST_VENDORFS','1','st-image-vendorfs', '', d)} \ + ${@bb.utils.contains('ST_USERFS','1','st-image-userfs', '', d)} \ +" + +FLASHLAYOUT_DEFAULT_SRC = "files/flashlayouts/FlashLayout_stm32mp25_ramfs.tsv" + +EXTRA_IMAGEDEPENDS:append = " \ + ramfs-tools-native \ + " + +ST_BOOTFS = "0" +ST_VENDORFS = "0" +ST_USERFS = "0" +IMAGE_ROOTFS_MAXSIZE = "33554432" + +OPTEE_WIC_FILE = "${@bb.utils.contains('ST_VENDORFS','1','sdcard-stm32mp257f-myboard-optee-vendorfs-2GB.wks.in','sdcard-stm32mp257f-myboard-optee-2GB.wks.in',d)}" + +# for generated a WIC file, please uncomment the 2 following lines or add them to local.conf +#WKS_IMAGE_FSTYPES += "wic wic.bz2 wic.bmap" +#WKS_FILE += "${OPTEE_WIC_FILE}" +# DISTRO_FEATURES:remove = "alsa argp ext2 ext4 largefile ipv4 ipv6 multiarch pci wifi nfs usbgadget usbhost xattr zeroconf bluetooth bluez5 gstreamer optee splashscreen wayland pam kde systemd polkit usrmerge efi initrd autoresize pipewire opengl gplv3 pulseaudio gobject-introspection-data ldconfig" + +DISTRO_FEATURES_DEFAULT:remove = "acl alsa bluetooth debuginfod ext2 ipv4 ipv6 pcmcia usbgadget usbhost wifi xattr nfs zeroconf pci 3g nfc x11 vfat seccomp locale " +CORE_IMAGE_BASE_INSTALL:remove = " packagegroup-base-extended locale " +GTK3DISTROFEATURES:remove = "x11 wayland" +# IMAGE_INSTALL:remove = " python3 weston pango wayland weston-cube dbus dbus-broker " +IMAGE_INSTALL:remove = " python3 weston pango wayland weston-cube dbus dbus-broker locale locale-base locale-base-en_us " +DISTRO_FEATURES:remove = " wayland x11 dbus dbus-broker python3 systemd locale " +DISTRO_FEATURES:remove = "alsa largefile ipv6 multiarch pci wifi nfs usbgadget usbhost xattr zeroconf bluetooth bluez5 gstreamer optee splashscreen wayland kde polkit efi autoresize pipewire opengl pulseaudio gobject-introspection-data ldconfig systemd " +DISTRO_FEATURES:append = " udev " +VIRTUAL-RUNTIME_init_manager = "" +VIRTUAL-RUNTIME_init_manager:remove = " systemd " diff --git a/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0001-Load-kernel-from-rootfs.patch b/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0001-Load-kernel-from-rootfs.patch new file mode 100644 index 0000000..c5a0450 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0001-Load-kernel-from-rootfs.patch @@ -0,0 +1,25 @@ +From 73b1f13970ea10fea5a1a5b34596c139a553e2f1 Mon Sep 17 00:00:00 2001 +From: gpaga +Date: Sun, 3 Nov 2024 01:46:49 +0100 +Subject: [PATCH] Load kernel from rootfs + +--- + include/configs/stm32mp25_st_common.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h +index ab5a4a9164..3fcd0f7db7 100644 +--- a/include/configs/stm32mp25_st_common.h ++++ b/include/configs/stm32mp25_st_common.h +@@ -28,6 +28,11 @@ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ ++ "setenv bootargs \"root=/dev/mmcblk0p6 rootwait\"; " \ ++ "setenv customdtname stm32mp257f-myboard.dtb; " \ ++ "load mmc 1:6 ${kernel_addr_r} boot/Image.gz; " \ ++ "load mmc 1:6 ${fdt_addr_r} boot/${customdtname}; " \ ++ "booti ${kernel_addr_r} - ${fdt_addr_r}; " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ diff --git a/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0002-v2023.10-stm32mp-r1-rc8.patch b/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0002-v2023.10-stm32mp-r1-rc8.patch new file mode 100644 index 0000000..a61a919 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-bsp/u-boot/files/0002-v2023.10-stm32mp-r1-rc8.patch @@ -0,0 +1,210 @@ +From 7a51375e07984fe3622a77a0b7b1df3fb6a48f03 Mon Sep 17 00:00:00 2001 +From: Christophe Priouzeau +Date: Fri, 12 Jul 2024 14:28:46 +0200 +Subject: [PATCH] v2023.10-stm32mp-r1-rc8 + +--- + configs/stm32mp25_myboard_defconfig | 191 + + 1 file changed, 191 insertions(+), 0 deletions(-) + create mode 100644 configs/stm32mp25_myboard_defconfig + +diff --git a/configs/stm32mp25_myboard_defconfig b/configs/stm32mp25_myboard_defconfig +new file mode 100644 +index 0000000000..3613088792 +--- /dev/null ++++ b/configs/stm32mp25_myboard_defconfig +@@ -0,0 +1,191 @@ ++CONFIG_ARM=y ++CONFIG_USE_ARCH_MEMCPY=y ++CONFIG_ARCH_STM32MP=y ++CONFIG_SYS_MALLOC_F_LEN=0x500000 ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 ++CONFIG_ENV_OFFSET=0x900000 ++CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1" ++CONFIG_STM32MP25X=y ++CONFIG_CMD_STM32KEY=y ++CONFIG_ENV_OFFSET_REDUND=0x940000 ++CONFIG_TARGET_ST_STM32MP25X=y ++CONFIG_CMD_STM32PROG=y ++CONFIG_SYS_LOAD_ADDR=0x84000000 ++CONFIG_ENV_ADDR=0x60900000 ++CONFIG_FWU_NUM_IMAGES_PER_BANK=1 ++CONFIG_OF_BOARD_FIXUP=y ++CONFIG_SYS_MEMTEST_START=0x84000000 ++CONFIG_SYS_MEMTEST_END=0x88000000 ++CONFIG_API=y ++CONFIG_SYS_MMC_MAX_DEVICE=3 ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_BOOTDELAY=1 ++CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" ++CONFIG_FDT_SIMPLEFB=n ++CONFIG_SYS_PROMPT="STM32MP> " ++CONFIG_CMD_BDINFO_EXTRA=y ++CONFIG_CMD_FWU_METADATA=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_SYS_BOOTM_LEN=0x2000000 ++CONFIG_CMD_BOOTEFI_SELFTEST=y ++CONFIG_CMD_ADTIMG=y ++# CONFIG_CMD_ELF is not set ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_NVEDIT_EFI=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MEMTEST=y ++CONFIG_CMD_CLK=y ++CONFIG_CMD_DFU=y ++CONFIG_CMD_FUSE=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_LSBLK=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_REMOTEPROC=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_SYS_DISABLE_AUTOLOAD=y ++CONFIG_CMD_BMP=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_EFIDEBUG=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_RNG=y ++CONFIG_CMD_TIMER=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_CMD_LOG=y ++CONFIG_CMD_UBI=y ++CONFIG_OF_LIVE=y ++CONFIG_ENV_IS_NOWHERE=y ++CONFIG_ENV_IS_IN_FLASH=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_ADDR_REDUND=0x60940000 ++CONFIG_ENV_UBI_PART="UBI" ++CONFIG_ENV_UBI_VOLUME="uboot_config" ++CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" ++CONFIG_SYS_MMC_ENV_DEV=-1 ++CONFIG_SYS_64BIT_LBA=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_DFU_TFTP=y ++CONFIG_USB_FUNCTION_FASTBOOT=y ++CONFIG_FASTBOOT_BUF_ADDR=0x84000000 ++CONFIG_FASTBOOT_BUF_SIZE=0x2000000 ++CONFIG_FASTBOOT_FLASH=y ++CONFIG_FASTBOOT_FLASH_MMC_DEV=1 ++CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y ++CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" ++CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" ++CONFIG_FASTBOOT_MMC_USER_SUPPORT=y ++CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y ++CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y ++CONFIG_GPIO_HOG=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_STM32F7=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_STM32_FMC2_EBI=y ++CONFIG_STM32_OMI=y ++CONFIG_STM32_OMM=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_STM32_SDMMC2=y ++CONFIG_DM_MAILBOX=y ++CONFIG_STM32_IPCC=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_NOR_FLASH=y ++CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y ++CONFIG_CFI_FLASH=y ++CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y ++CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y ++CONFIG_FLASH_CFI_MTD=y ++CONFIG_FLASH_CFI_SFDP=y ++CONFIG_SYS_FLASH_CFI=y ++CONFIG_STM32_HYPERBUS=y ++CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_USE_FLASH_BBT=y ++CONFIG_NAND_STM32_FMC2=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_SOFT_RESET=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_PHY=y ++CONFIG_PHY_STM32_USB2PHY=y ++CONFIG_PINCONF=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y ++# CONFIG_STM32MP1_DDR is not set ++CONFIG_REMOTEPROC_OPTEE=y ++CONFIG_REMOTEPROC_STM32_COPRO=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_STM32=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_STM32=y ++CONFIG_SERIAL_RX_BUFFER=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_STM32_OSPI=y ++CONFIG_STM32_SPI=y ++# CONFIG_OPTEE_TA_AVB is not set ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_STM32_USBH=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" ++CONFIG_USB_GADGET_VENDOR_NUM=0x0483 ++CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 ++CONFIG_VIDEO=n ++# CONFIG_VIDEO_LOGO is not set ++CONFIG_BACKLIGHT_GPIO=y ++CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=n ++CONFIG_VIDEO_LCD_RAYDIUM_RM68200=n ++CONFIG_VIDEO_LCD_ROCKTECH_HX8394=n ++CONFIG_VIDEO_STM32=n ++CONFIG_VIDEO_STM32_DSI=n ++CONFIG_VIDEO_STM32_LVDS=n ++CONFIG_VIDEO_STM32_MAX_XRES=1920 ++CONFIG_VIDEO_STM32_MAX_YRES=1200 ++CONFIG_VIDEO_BMP_RLE8=n ++CONFIG_BMP_16BPP=n ++CONFIG_BMP_24BPP=n ++CONFIG_BMP_32BPP=n ++CONFIG_WDT=y ++CONFIG_WDT_STM32MP=y ++CONFIG_WDT_ARM_SMC=y ++CONFIG_ERRNO_STR=y ++CONFIG_EFI_SET_TIME=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y ++CONFIG_EFI_SECURE_BOOT=y ++# CONFIG_LMB_USE_MAX_REGIONS is not set ++CONFIG_LMB_MEMORY_REGIONS=2 ++CONFIG_LMB_RESERVED_REGIONS=32 ++CONFIG_FWU_MULTI_BANK_UPDATE=y ++CONFIG_FWU_MDATA_V2=y ++# CONFIG_TOOLS_MKEFICAPSULE is not set ++# CONFIG_TOOLS_MKFWUMDATA is not set +-- +2.34.1 + diff --git a/YOCTO/meta-mylayer/recipes-bsp/u-boot/u-boot-stm32mp_%.bbappend b/YOCTO/meta-mylayer/recipes-bsp/u-boot/u-boot-stm32mp_%.bbappend new file mode 100644 index 0000000..90d646c --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-bsp/u-boot/u-boot-stm32mp_%.bbappend @@ -0,0 +1,7 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +SRC_URI += "\ + file://0001-Load-kernel-from-rootfs.patch \ + file://0002-v2023.10-stm32mp-r1-rc8.patch \ + " + diff --git a/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/Flashlayout_ramfs.tsv b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/Flashlayout_ramfs.tsv new file mode 100755 index 0000000..61b6fbc --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/Flashlayout_ramfs.tsv @@ -0,0 +1,4 @@ +#Opt Id Name Type IP Offset Binary +P 0x10 kernel System ram0 0x8A000000 kernel/Image.gz-stm32mp25-myboard.bin +P 0x11 dtb FileSystem ram0 0x90000000 kernel/stm32mp257f-myboard.dtb +P 0x12 initrd Binary ram0 0x90400000 myimage-openstlinux-weston-stm32mp25-myboard.rootfs.cpio.gz diff --git a/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/run_ramfs.bat b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/run_ramfs.bat new file mode 100755 index 0000000..16e44de --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/run_ramfs.bat @@ -0,0 +1,8 @@ + +"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=USB1 -d arm-trusted-firmware\tf-a-stm32mp257f-myboard-optee-programmer-usb.stm32 0x1 -s 0x1 -d fip\fip-stm32mp257f-myboard-ddr-optee-programmer-usb.bin 0x2 -s 0x2 -d fip\fip-stm32mp257f-myboard-optee-emmc.bin 0x3 -s 0x3 -d scripts\script.bin 0x0 -s 0x0 --detach + +timeout /t 2 + +"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=USB1 -w scripts\Flashlayout_ramfs.tsv + +"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=USB1 --detach diff --git a/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.cmd b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.cmd new file mode 100755 index 0000000..4354150 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.cmd @@ -0,0 +1,3 @@ +stm32prog usb 0; +setenv bootargs "root=/dev/ram0 rootfstype=ramfs rw initrd=0x90400000,128M init=/bin/sh rootwait quiet"; +booti ${kernel_addr_r} - ${fdt_addr_r}; diff --git a/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.txt b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.txt new file mode 100755 index 0000000..34f1fe1 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/files/script.txt @@ -0,0 +1 @@ +mkimage -C none -A arm -T script -d script.cmd script.bin diff --git a/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/ramfs-tools.bb b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/ramfs-tools.bb new file mode 100644 index 0000000..3fdbffa --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-devtools/ramfs-tools/ramfs-tools.bb @@ -0,0 +1,52 @@ +# Copyright (C) 2017, STMicroelectronics - All Rights Reserved +# Released under the MIT license (see COPYING.MIT for the terms) + +SUMMARY = "Script for running a ramfs STM32MP2 system" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" +DEPENDS += "u-boot-tools " + +SRC_URI = "file://Flashlayout_ramfs.tsv \ + file://run_ramfs.bat \ + file://script.cmd \ + file://script.txt" + +BBCLASSEXTEND = "native nativesdk" + +RDEPENDS:${PN}:append = " bash " + +# RRECOMMENDS:${PN}:append:class-nativesdk = " nativesdk-gptfdisk " + +inherit deploy + +SCRIPT_DEPLOYDIR ?= "scripts" + +do_compile () { + cd ${WORKDIR} + mkimage -C none -A arm -T script -d script.cmd script.bin +} + +do_install() { + install -d ${D}/${bindir} + install -m 0755 ${WORKDIR}/Flashlayout_ramfs.tsv ${D}/${bindir} + install -m 0755 ${WORKDIR}/run_ramfs.bat ${D}/${bindir} + install -m 0755 ${WORKDIR}/script.bin ${D}/${bindir} + install -m 0755 ${WORKDIR}/script.cmd ${D}/${bindir} + install -m 0755 ${WORKDIR}/script.txt ${D}/${bindir} +} + +do_deploy() { + : +} + +do_deploy:class-native() { + install -d ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR} + install -m 0755 ${WORKDIR}/Flashlayout_ramfs.tsv ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR}/ + install -m 0755 ${WORKDIR}/run_ramfs.bat ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR}/ + install -m 0755 ${WORKDIR}/script.bin ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR}/ + install -m 0755 ${WORKDIR}/script.cmd ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR}/ + install -m 0755 ${WORKDIR}/script.txt ${DEPLOYDIR}/${SCRIPT_DEPLOYDIR}/ +} +addtask deploy before do_build after do_compile diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/external-dt_%.bbappend b/YOCTO/meta-mylayer/recipes-extended/external-dt/external-dt_%.bbappend new file mode 100644 index 0000000..0d5446f --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/external-dt_%.bbappend @@ -0,0 +1,28 @@ +## SUMMARY = "Provides Device Tree files for STM32MP257 myboard" +## LICENSE = "GPL-2.0-only" +## LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0-only;md5=801f80980d171dd6425610833a22dbe6" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" +SRC_URI = " \ + file://devicetree/License.md \ + file://devicetree/README.md \ + file://devicetree/SECURITY.md \ + file://devicetree/linux/Makefile \ + file://devicetree/linux/stm32mp257f-myboard.dts \ + file://devicetree/linux/stm32mp257f-myboard-resmem.dtsi \ + file://devicetree/optee/conf.mk \ + file://devicetree/optee/stm32mp257f-myboard.dts \ + file://devicetree/optee/stm32mp257f-myboard-rcc.dtsi \ + file://devicetree/optee/stm32mp257f-myboard-resmem.dtsi \ + file://devicetree/optee/stm32mp257f-myboard-rif.dtsi \ + file://devicetree/tf-a/stm32mp257f-myboard.dts \ + file://devicetree/tf-a/stm32mp257f-myboard-fw-config.dts \ + file://devicetree/tf-a/stm32mp257f-myboard-fw-config.dtsi \ + file://devicetree/tf-a/stm32mp257f-myboard-rcc.dtsi \ + file://devicetree/u-boot/Makefile \ + file://devicetree/u-boot/stm32mp257f-myboard.dts \ + file://devicetree/u-boot/stm32mp257f-myboard-resmem.dtsi \ + file://devicetree/u-boot/stm32mp257f-myboard-u-boot.dtsi \ + " + +S = "${WORKDIR}/devicetree" diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CODE_OF_CONDUCT.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..bf0ca35 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CODE_OF_CONDUCT.md @@ -0,0 +1,73 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as +contributors and maintainers pledge to making participation in our project and +our community a harassment-free experience for everyone, regardless of age, body +size, disability, ethnicity, sex characteristics, gender identity and expression, +level of experience, education, socio-economic status, nationality, personal +appearance, race, religion, or sexual identity and orientation. + +## Our Standards + +Examples of behavior that contributes to creating a positive environment +include: + +* Using welcoming and inclusive language +* Being respectful of differing viewpoints and experiences +* Gracefully accepting constructive criticism +* Focusing on what is best for the community +* Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +* The use of sexualized language or imagery and unwelcome sexual attention or + advances +* Trolling, insulting/derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or electronic + address, without explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Our Responsibilities + +Project maintainers are responsible for clarifying the standards of acceptable +behavior and are expected to take appropriate and fair corrective action in +response to any instances of unacceptable behavior. + +Project maintainers have the right and responsibility to remove, edit, or +reject comments, commits, code, wiki edits, issues, and other contributions +that are not aligned to this Code of Conduct, or to ban temporarily or +permanently any contributor for other behaviors that they deem inappropriate, +threatening, offensive, or harmful. + +## Scope + +This Code of Conduct applies both within project spaces and in public spaces +when an individual is representing the project or its community. Examples of +representing a project or community include using an official project e-mail +address, posting via an official social media account, or acting as an appointed +representative at an online or offline event. Representation of a project may be +further defined and clarified by project maintainers. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported by contacting the project team via this [link](https://www.st.com/content/st_com/en/contact-us.html). +All complaints will be reviewed and investigated and will result in a response that +is deemed necessary and appropriate to the circumstances. The project team is +obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good +faith may face temporary or permanent repercussions as determined by other +members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant](https://www.contributor-covenant.org), version 1.4, +available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html). + +For answers to common questions about this code of conduct, refer to the FAQ section [here](https://www.contributor-covenant.org/faq). diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CONTRIBUTING.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CONTRIBUTING.md new file mode 100644 index 0000000..3d1bacd --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/CONTRIBUTING.md @@ -0,0 +1,30 @@ +# Contributing guide + +This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you. + +This guide mainly focuses on the proper use of Git. + +## 1. Issues + +STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus). + +## 2. Pull Requests + +STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. + +* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). +* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. +* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com). + +Please note that: +* The Corporate CLA will always take precedence over the Individual CLA. +* One CLA submission is sufficient, for any project proposed by STMicroelectronics. + +__How to proceed__ + +* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version. +* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted. + +__Note__ + +Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered. diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/License.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/License.md new file mode 100644 index 0000000..07c1aff --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/License.md @@ -0,0 +1 @@ +http://wiki.st.com/stm32mpu/index.php/OpenSTLinux_licenses diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/README.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/README.md new file mode 100644 index 0000000..69cf731 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/README.md @@ -0,0 +1,72 @@ +## Summary + +**meta-st-stm32mp BSP layer** is a layer containing the STMicroelectronics bsp metadata for current versions +of stm32mp. + +This layer relies on OpenEmbedded/Yocto build system that is provided through +Bitbake and OpenEmbedded-Core layers or Poky layer all part of the Yocto Project + +The Yocto Project has extensive documentation about OE including a reference manual +which can be found at: + + * **http://yoctoproject.org/documentation** + +For information about OpenEmbedded, see the OpenEmbedded website: + + * **http://www.openembedded.org/** + +This layer depends on: + +``` +[OECORE] +URI: https://github.com/openembedded/openembedded-core.git +layers: meta +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +[BITBAKE] +URI: https://github.com/openembedded/bitbake.git +branch: branch associated to oecore branch +revision: HEAD +``` +or +``` +[OECORE] +URI: git://git.yoctoproject.org/poky +layers: meta +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +``` + +``` +[META-OPENEMBEDDED] +URI: git://github.com/openembedded/meta-openembedded.git +layers: meta-python meta-oe +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +``` + +The dependency (meta-python) are due to the usage of OPTEE which require to use some python packages. + +## EULA + +Some SoC depends on firmware and/or packages that are covered by + STMicroelectronics EULA. To have the right to use those binaries in your images you need to read and accept the EULA available as: + +conf/eula/$MACHINE, e.g. conf/eula/stm32mp1 + +In order to accept it, you should add, in your local.conf file: + +ACCEPT_EULA_$MACHINE = "1", e.g.: ACCEPT_EULA_stm32mp1 = "1" + +If you do not accept the EULA the generated image will be missing some +components and features. + +## Contributing +If you want to contribute changes, you can send Github pull requests at +**https://github.com/stmicroelectronics/meta-st-stm32mp/pulls**. + + +## Maintainers + - Christophe Priouzeau + - Sebastien Gandon + - Bernard Puel diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/SECURITY.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/SECURITY.md new file mode 100644 index 0000000..4b3e4e6 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/SECURITY.md @@ -0,0 +1,8 @@ +# Report potential product security vulnerabilities +ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations and solutions when applicable. +If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html** + +### IMPORTANT - READ CAREFULLY: +STMicroelectronics International N.V., on behalf of itself, its affiliates and subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”) seriously. In order to review Your Report (the terms “You” and “Yours” include your employer, and all affiliates, subsidiaries and related persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so. +As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function. +By submitting Your Report, You agree that ST’s [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications. diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CODE_OF_CONDUCT.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..bf0ca35 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CODE_OF_CONDUCT.md @@ -0,0 +1,73 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as +contributors and maintainers pledge to making participation in our project and +our community a harassment-free experience for everyone, regardless of age, body +size, disability, ethnicity, sex characteristics, gender identity and expression, +level of experience, education, socio-economic status, nationality, personal +appearance, race, religion, or sexual identity and orientation. + +## Our Standards + +Examples of behavior that contributes to creating a positive environment +include: + +* Using welcoming and inclusive language +* Being respectful of differing viewpoints and experiences +* Gracefully accepting constructive criticism +* Focusing on what is best for the community +* Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +* The use of sexualized language or imagery and unwelcome sexual attention or + advances +* Trolling, insulting/derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or electronic + address, without explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Our Responsibilities + +Project maintainers are responsible for clarifying the standards of acceptable +behavior and are expected to take appropriate and fair corrective action in +response to any instances of unacceptable behavior. + +Project maintainers have the right and responsibility to remove, edit, or +reject comments, commits, code, wiki edits, issues, and other contributions +that are not aligned to this Code of Conduct, or to ban temporarily or +permanently any contributor for other behaviors that they deem inappropriate, +threatening, offensive, or harmful. + +## Scope + +This Code of Conduct applies both within project spaces and in public spaces +when an individual is representing the project or its community. Examples of +representing a project or community include using an official project e-mail +address, posting via an official social media account, or acting as an appointed +representative at an online or offline event. Representation of a project may be +further defined and clarified by project maintainers. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported by contacting the project team via this [link](https://www.st.com/content/st_com/en/contact-us.html). +All complaints will be reviewed and investigated and will result in a response that +is deemed necessary and appropriate to the circumstances. The project team is +obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good +faith may face temporary or permanent repercussions as determined by other +members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant](https://www.contributor-covenant.org), version 1.4, +available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html). + +For answers to common questions about this code of conduct, refer to the FAQ section [here](https://www.contributor-covenant.org/faq). diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CONTRIBUTING.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CONTRIBUTING.md new file mode 100644 index 0000000..3d1bacd --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/CONTRIBUTING.md @@ -0,0 +1,30 @@ +# Contributing guide + +This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you. + +This guide mainly focuses on the proper use of Git. + +## 1. Issues + +STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest) or [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus). + +## 2. Pull Requests + +STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. + +* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). +* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. +* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com). + +Please note that: +* The Corporate CLA will always take precedence over the Individual CLA. +* One CLA submission is sufficient, for any project proposed by STMicroelectronics. + +__How to proceed__ + +* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version. +* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted. + +__Note__ + +Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered. diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/License.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/License.md new file mode 100644 index 0000000..07c1aff --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/License.md @@ -0,0 +1 @@ +http://wiki.st.com/stm32mpu/index.php/OpenSTLinux_licenses diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/README.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/README.md new file mode 100644 index 0000000..69cf731 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/README.md @@ -0,0 +1,72 @@ +## Summary + +**meta-st-stm32mp BSP layer** is a layer containing the STMicroelectronics bsp metadata for current versions +of stm32mp. + +This layer relies on OpenEmbedded/Yocto build system that is provided through +Bitbake and OpenEmbedded-Core layers or Poky layer all part of the Yocto Project + +The Yocto Project has extensive documentation about OE including a reference manual +which can be found at: + + * **http://yoctoproject.org/documentation** + +For information about OpenEmbedded, see the OpenEmbedded website: + + * **http://www.openembedded.org/** + +This layer depends on: + +``` +[OECORE] +URI: https://github.com/openembedded/openembedded-core.git +layers: meta +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +[BITBAKE] +URI: https://github.com/openembedded/bitbake.git +branch: branch associated to oecore branch +revision: HEAD +``` +or +``` +[OECORE] +URI: git://git.yoctoproject.org/poky +layers: meta +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +``` + +``` +[META-OPENEMBEDDED] +URI: git://github.com/openembedded/meta-openembedded.git +layers: meta-python meta-oe +branch: same dedicated branch as meta-st-stm32mp +revision: HEAD +``` + +The dependency (meta-python) are due to the usage of OPTEE which require to use some python packages. + +## EULA + +Some SoC depends on firmware and/or packages that are covered by + STMicroelectronics EULA. To have the right to use those binaries in your images you need to read and accept the EULA available as: + +conf/eula/$MACHINE, e.g. conf/eula/stm32mp1 + +In order to accept it, you should add, in your local.conf file: + +ACCEPT_EULA_$MACHINE = "1", e.g.: ACCEPT_EULA_stm32mp1 = "1" + +If you do not accept the EULA the generated image will be missing some +components and features. + +## Contributing +If you want to contribute changes, you can send Github pull requests at +**https://github.com/stmicroelectronics/meta-st-stm32mp/pulls**. + + +## Maintainers + - Christophe Priouzeau + - Sebastien Gandon + - Bernard Puel diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/SECURITY.md b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/SECURITY.md new file mode 100644 index 0000000..4b3e4e6 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/SECURITY.md @@ -0,0 +1,8 @@ +# Report potential product security vulnerabilities +ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations and solutions when applicable. +If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html** + +### IMPORTANT - READ CAREFULLY: +STMicroelectronics International N.V., on behalf of itself, its affiliates and subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”) seriously. In order to review Your Report (the terms “You” and “Yours” include your employer, and all affiliates, subsidiaries and related persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so. +As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function. +By submitting Your Report, You agree that ST’s [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications. diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/external-dts.tar.gz b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/external-dts.tar.gz new file mode 100644 index 0000000..17c6dc6 Binary files /dev/null and b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/external-dts.tar.gz differ diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/.gitkeep b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/Makefile b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/Makefile new file mode 100644 index 0000000..f9fedc2 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +dtb-$(TARGET_ARM64) += \ + stm32mp257f-myboard.dtb diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard-resmem.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard-resmem.dtsi new file mode 100644 index 0000000..243df32 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard-resmem.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. + */ + +/* + * STM32MP25 reserved memory device tree configuration + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:05 AM + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Internal RAM reserved memory declaration */ + tfa_bl31: tfa-bl31@a000000 { + reg = <0x0 0xa000000 0x0 0x20000>; + no-map; + }; + + hpdma1_lli: hpdma1-lli@a020000 { + reg = <0x0 0xa020000 0x0 0xf0f0>; + no-map; + }; + + hpdma2_lli: hpdma2-lli@a02f0f0 { + reg = <0x0 0xa02f0f0 0x0 0xf0f0>; + no-map; + }; + + hpdma3_lli: hpdma3-lli@a03e1e0 { + reg = <0x0 0xa03e1e0 0x0 0x1e20>; + no-map; + }; + + bsec_mirror: bsec-mirror@a040000 { + reg = <0x0 0xa040000 0x0 0x1000>; + no-map; + }; + + cm33_sram1: cm33-sram1@a041000 { + reg = <0x0 0xa041000 0x0 0x1f000>; + no-map; + }; + + cm33_sram2: cm33-sram2@a060000 { + reg = <0x0 0xa060000 0x0 0x20000>; + no-map; + }; + + cm33_retram: cm33-retram@a080000 { + reg = <0x0 0xa080000 0x0 0x1f000>; + no-map; + }; + + ddr_param: ddr-param@a09f000 { + reg = <0x0 0xa09f000 0x0 0x1000>; + no-map; + }; + + cm0_cube_fw: cm0-cube-fw@200C0000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C0000 0x0 0x4000>; + no-map; + }; + + cm0_cube_data: cm0-cube-data@200C4000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C4000 0x0 0x2000>; + no-map; + }; + + ipc_shmem_2: ipc-shmem-2@200C6000{ + compatible = "shared-dma-pool"; + reg = <0x0 0x200C6000 0x0 0x2000>; + no-map; + }; + + /* Backup RAM reserved memory declaration */ + bl31_lowpower: bl31-lowpower@42000000 { + reg = <0x0 0x42000000 0x0 0x1000>; + no-map; + }; + + tfm_its: tfm-its@42001000 { + reg = <0x0 0x42001000 0x0 0x1000>; + no-map; + }; + + /* Octo Memory Manager reserved memory declaration */ + mm_ospi1: mm-ospi@60000000 { + reg = <0x0 0x60000000 0x0 0x10000000>; + no-map; + }; + + /* DDR reserved memory declaration */ + tfm_code: tfm-code@80000000 { + reg = <0x0 0x80000000 0x0 0x100000>; + no-map; + }; + + cm33_cube_fw: cm33-cube-fw@80100000 { + reg = <0x0 0x80100000 0x0 0x800000>; + no-map; + }; + + tfm_data: tfm-data@80900000 { + reg = <0x0 0x80900000 0x0 0x100000>; + no-map; + }; + + cm33_cube_data: cm33-cube-data@80a00000 { + reg = <0x0 0x80a00000 0x0 0x800000>; + no-map; + }; + + ipc_shmem_1: ipc-shmem-1@81200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x81200000 0x0 0xf8000>; + no-map; + }; + + vdev0vring0: vdev0vring0@812f8000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f8000 0x0 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@812f9000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f9000 0x0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@812fa000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812fa000 0x0 0x6000>; + no-map; + }; + + spare1: spare1@81300000 { + reg = <0x0 0x81300000 0x0 0xcc0000>; + no-map; + }; + + bl31_context: bl31-context@81fc0000 { + reg = <0x0 0x81fc0000 0x0 0x40000>; + no-map; + }; + + op_tee: op-tee@82000000 { + reg = <0x0 0x82000000 0x0 0x2000000>; + no-map; + }; + + gpu_reserved: gpu-reserved@fa800000 { + reg = <0x0 0xfa800000 0x0 0x4000000>; + no-map; + }; + + ltdc_sec_layer: ltdc-sec-layer@fe800000 { + reg = <0x0 0xfe800000 0x0 0x800000>; + no-map; + }; + + ltdc_sec_rotation: ltdc-sec-rotation@ff000000 { + reg = <0x0 0xff000000 0x0 0x1000000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x80000000>; + size = <0x0 0x8000000>; + alignment = <0x0 0x2000>; + linux,cma-default; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard.dts b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard.dts new file mode 100644 index 0000000..ee170c4 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/linux/stm32mp257f-myboard.dts @@ -0,0 +1,892 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" +#include "stm32mp257f-myboard-resmem.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-MYBOARD"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc1; + serial0 = &usart2; + serial1 = &usart6; + serial2 = &usart1; + ethernet0 = ð1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, + <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + status = "disabled"; + }; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_ext_cec: clk-ext-cec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + dmic0: dmic-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic0"; + status = "okay"; + + port { + dmic0_endpoint: endpoint { + remote-endpoint = <&mdf_endpoint0>; + }; + }; + }; + + dmic1: dmic-1 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic1"; + status = "okay"; + + port { + dmic1_endpoint: endpoint { + remote-endpoint = <&mdf_endpoint1>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-wake-up { + label = "wake-up"; + linux,code = ; + interrupts-extended = <&optee 0>; + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + hdmi-pwr-supply = <&scmi_v5v_hdmi>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + imx335_2v9: imx335-2v9 { + compatible = "regulator-fixed"; + regulator-name = "imx335-avdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + imx335_1v8: imx335-1v8 { + compatible = "regulator-fixed"; + regulator-name = "imx335-ovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + imx335_1v2: imx335-1v2 { + compatible = "regulator-fixed"; + regulator-name = "imx335-dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + panel_lvds: panel-lvds { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + default-on; + status = "okay"; + + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: panel-lvds-backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + default-on; + default-brightness-level = <1>; + status = "okay"; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP25-DK"; + dais = <&i2s2_port &mdf1_port0 &mdf1_port1>; + status = "okay"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; +}; + +&a35ss_syscfg { + status = "okay"; +}; + +&ahbsr { + mbox_client: mailbox-client@1 { + compatible = "mbox-cdev"; + reg = <1 0>; + memory-region = <&ipc_shmem_2>; + mboxes = <&ipcc2 0>; + mbox-names = "rx-tx"; + status = "okay"; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&combophy { + st,ssc-on; + status = "okay"; +}; + +&crc { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&cs_cpu_debug0 { + status = "okay"; +}; + +&cs_cpu_debug1 { + status = "okay"; +}; + +&cs_cti0 { + status = "okay"; +}; + +&cs_cti1 { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_etr { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_replicator { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&csi { + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi_sink: endpoint { + remote-endpoint = <&imx335_ep>; + data-lanes = <0 1>; + bus-type = <4>; + }; + }; + port@1 { + reg = <1>; + csi_source: endpoint { + remote-endpoint = <&dcmipp_0>; + }; + }; + }; +}; + +&dcmipp { + status = "okay"; + port { + dcmipp_0: endpoint { + remote-endpoint = <&csi_source>; + bus-type = <4>; + }; + }; +}; + +&dsi { + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out1: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +ð1 { + status = "okay"; + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy1_eth1>; + st,eth-ptp-from-rcc; + + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,eee-disable; + reg = <1>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&hpdma { + memory-region = <&hpdma1_lli>; +}; + +&hpdma2 { + memory-region = <&hpdma2_lli>; +}; + +&hpdma3 { + memory-region = <&hpdma3_lli>; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + imx335: imx335@1a { + compatible = "sony,imx335"; + reg = <0x1a>; + clocks = <&clk_ext_camera>; + avdd-supply = <&imx335_2v9>; + ovdd-supply = <&imx335_1v8>; + dvdd-supply = <&imx335_1v2>; + reset-gpios = <&gpiob 1 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + powerdown-gpios = <&gpiob 11 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + status = "okay"; + + port { + imx335_ep: endpoint { + remote-endpoint = <&csi_sink>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <594000000>; + }; + }; + }; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3f>, <0x38>; + reg-names = "main", "cec", "edid", "packet"; + status = "okay"; + adi,dsi-lanes = <4>; + clocks = <&clk_ext_cec>; + clock-names = "cec"; + interrupt-parent = <&gpiob>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; + avdd-supply = <&scmi_v1v8>; + dvdd-supply = <&scmi_v1v8>; + pvdd-supply = <&scmi_v1v8>; + a2vdd-supply = <&scmi_v1v8>; + v3p3-supply = <&scmi_v3v3>; + v1p2-supply = <&scmi_v1v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out1>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + port@2 { + reg = <2>; + adv7535_tx_endpoint: endpoint { + remote-endpoint = <&i2s2_endpoint>; + }; + }; + }; + }; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2s2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_b>; + pinctrl-1 = <&i2s2_sleep_pins_b>; + status = "okay"; + + i2s2_port: port { + i2s2_endpoint: endpoint { + remote-endpoint = <&adv7535_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + }; + }; +}; + +&ipcc1 { + status = "okay"; +}; + +&ipcc2 { + status = "okay"; +}; + +/* use LPTIMER with tick broadcast for suspend mode */ +&lptimer3 { + status = "okay"; + timer { + status = "okay"; + }; +}; + +<dc { + default-on; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + default-on; + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + +&m0_rproc { + mboxes = <&ipcc2 0>, <&ipcc2 1>, <&ipcc2 2>; + mbox-names = "rx", "tx", "shutdown"; + memory-region = <&cm0_cube_fw>, <&cm0_cube_data>; + clocks = <&rcc CK_CPU3>, + <&rcc CK_CPU3_AM>, + <&scmi_clk CK_SCMI_IPCC2>, + <&scmi_clk CK_SCMI_IPCC2_AM>; + status = "okay"; +}; + +&m33_rproc { + mboxes = <&ipcc1 0x100>, <&ipcc1 0x101>, <&ipcc1 2>; + mbox-names = "vq0", "vq1", "shutdown"; + memory-region = <&cm33_cube_fw>, <&cm33_cube_data>, + <&ipc_shmem_1>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>, + <&cm33_sram2>; + st,syscfg-nsvtor = <&a35ss_syscfg 0xa8 0xffffff80>; + status = "okay"; +}; + +&mdf1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdf_cck0_pins_a>; + pinctrl-1 = <&mdf_cck0_sleep_pins_a>; + #clock-cells = <1>; + clock-output-names = "cck0"; + clock-frequency = <1536000>; + status = "okay"; + + sitf6: sitf@380 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdf_sdi6_pins_a>; + pinctrl-1 = <&mdf_sdi6_sleep_pins_a>; + st,sitf-mode = "spi"; + clocks = <&mdf1 0>; + status = "okay"; + }; + + filter0: filter@84 { + st,cic-mode = <4>; + st,sitf = <&sitf6 0>; + st,hpf-filter-cutoff-bp = <625>; + status = "okay"; + + asoc_pdm0: mdf-dai { + compatible = "st,stm32mp25-mdf-dai"; + #sound-dai-cells = <0>; + io-channels = <&filter0 0>; + power-domains = <&RET_PD>; + status = "okay"; + + mdf1_port0: port { + mdf_endpoint0: endpoint { + remote-endpoint = <&dmic0_endpoint>; + }; + }; + }; + }; + + filter1: filter@104 { + st,cic-mode = <4>; + st,sitf = <&sitf6 1>; + st,hpf-filter-cutoff-bp = <625>; + status = "okay"; + + asoc_pdm1: mdf-dai { + compatible = "st,stm32mp25-mdf-dai"; + #sound-dai-cells = <0>; + io-channels = <&filter1 0>; + power-domains = <&RET_PD>; + status = "okay"; + + mdf1_port1: port { + mdf_endpoint1: endpoint { + remote-endpoint = <&dmic1_endpoint>; + }; + }; + }; + }; +}; + +&mlahb { + intc_rpmsg: interrupt-controller@1 { + compatible = "rpmsg,intc"; + reg = <1 0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + i2c_rpmsg: i2c@2 { + compatible = "rpmsg,i2c-controller"; + reg = <2 0>; + rpmsg,dev-id = "rpmsg_i2c"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + typec@35 { + compatible = "st,stm32mp25-typec"; + reg = <0x35>; + interrupts-extended = <&intc_rpmsg 0>; + status = "okay"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + typec_ep: endpoint { + remote-endpoint = <&dwc3_ep>; + }; + }; + }; + }; + }; +}; + +&rtc { + st,lsco = ; + pinctrl-0 = <&rtc_out2_rmp_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&scmi_vdd_emmc>; + vqmmc-supply = <&scmi_vddio2>; + mmc-ddr-1_8v; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + status = "disabled"; + }; +}; + +&spi6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_pins_a>; + pinctrl-1 = <&spi6_sleep_pins_a>; + status = "disabled"; +}; + +/* Bluetooth */ +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 4 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&scmi_v3v3>; + vddio-supply = <&scmi_v3v3>; + }; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_idle_pins_a>; + pinctrl-2 = <&usart6_sleep_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +&usb2_phy1 { + vdd33-supply = <&scmi_vdd3v3_usb>; + status = "okay"; +}; + +&usb2_phy2 { + vdd33-supply = <&scmi_vdd3v3_usb>; + status = "okay"; +}; + +&usbh { + status = "okay"; + + usbh_ehci: usb@482f0000 { + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&scmi_v3v3>; + }; + }; + + usbh_ohci: usb@482e0000 { + status = "disabled"; + }; +}; + +&usb3dr { + status = "okay"; + + dwc3: usb@48300000 { + phys = <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; + port { + dwc3_ep: endpoint { + remote-endpoint = <&typec_ep>; + }; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/conf.mk b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/conf.mk new file mode 100644 index 0000000..9b516d1 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/conf.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: BSD-2-Clause + +# MP25 boards +flavor_dts_file-257F_EV1_OSTL = stm32mp257f-myboard.dts +flavorlist-MP25 += $(flavor_dts_file-257F_EV1_OSTL) + diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rcc.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rcc.dtsi new file mode 100644 index 0000000..e935534 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rcc.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2024, STMicroelectronics + */ + +&clk_hse { + clock-frequency = <40000000>; +}; + +&clk_hsi { + clock-frequency = <64000000>; +}; + +&clk_lse { + clock-frequency = <32768>; +}; + +&clk_lsi { + clock-frequency = <32000>; +}; + +&clk_msi { + clock-frequency = <16000000>; +}; + +&rcc { + st,busclk = < + DIV_CFG(DIV_LSMCU, 1) + DIV_CFG(DIV_APB1, 0) + DIV_CFG(DIV_APB2, 0) + DIV_CFG(DIV_APB3, 0) + DIV_CFG(DIV_APB4, 0) + DIV_CFG(DIV_APBDBG, 0) + >; + + st,flexgen = < + FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) + FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) + FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1) + FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16) + FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23) + FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(21, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(22, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16) + FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16) + FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16) + FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3) + FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21) + FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1) + FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1) + FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19) + FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19) + FLEXGEN_CFG(33, XBAR_SRC_PLL4, 0, 23) + FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59) + FLEXGEN_CFG(35, XBAR_SRC_HSI_KER, 0, 3) + FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0) + FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0) + FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11) + FLEXGEN_CFG(42, XBAR_SRC_PLL7, 0, 16) + FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23) + FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(49, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3) + FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3) + FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1) + FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) + FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1) + FLEXGEN_CFG(60, XBAR_SRC_PLL4, 0, 23) + FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7) + FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7) + FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) + >; + + st,kerclk = < + MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46) + MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) + MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) + MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE) + MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28) + MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY) + MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32) + MUX_CFG(MUX_DTS, MUX_DTS_HSE) + MUX_CFG(MUX_RTC, MUX_RTC_LSE) + MUX_CFG(MUX_D3PER, MUX_D3PER_MSI) + MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF) + MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF) + >; + + pll1: st,pll-1 { + st,pll = <&pll1_cfg_1200Mhz>; + + pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + + pll1_cfg_1500Mhz: pll1-cfg-1500Mhz { + cfg = <75 2 1 1>; + src = ; + }; + }; + + pll2: st,pll-2 { + st,pll = <&pll2_cfg_600Mhz>; + + pll2_cfg_600Mhz: pll2-cfg-600Mhz { + cfg = <30 1 1 2>; + src = ; + }; + }; + + pll3: st,pll-3 { + st,pll = <&pll3_cfg_800Mhz>; + + pll3_cfg_800Mhz: pll3-cfg-800Mhz { + cfg = <20 1 1 1>; + src = ; + }; + + pll3_cfg_900Mhz: pll3-cfg-900Mhz { + cfg = <45 2 1 1>; + src = ; + }; + }; + + pll4: st,pll-4 { + st,pll = <&pll4_cfg_1200Mhz>; + + pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + }; + + pll5: st,pll-5 { + st,pll = <&pll5_cfg_532Mhz>; + + pll5_cfg_532Mhz: pll5-cfg-532Mhz { + cfg = <133 5 1 2>; + src = ; + }; + }; + + pll6: st,pll-6 { + st,pll = <&pll6_cfg_500Mhz>; + + pll6_cfg_500Mhz: pll6-cfg-500Mhz { + cfg = <25 1 1 2>; + src = ; + }; + }; + + pll7: st,pll-7 { + st,pll = <&pll7_cfg_835_51172Mhz>; + + pll7_cfg_835_51172Mhz: pll7-cfg-835-51172Mhz { + cfg = <167 4 1 2>; + src = ; + frac = < 0x1A3337 >; + }; + }; + + pll8: st,pll-8 { + st,pll = <&pll8_cfg_594Mhz>; + + pll8_cfg_594Mhz: pll8-cfg-594Mhz { + cfg = <297 5 1 4>; + src = ; + }; + }; +}; + diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-resmem.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-resmem.dtsi new file mode 100644 index 0000000..2453d59 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-resmem.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2024, STMicroelectronics + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Internal RAM reserved memory declaration */ + tfa_bl31: tfa-bl31@a000000 { + reg = <0x0 0xa000000 0x0 0x20000>; + no-map; + }; + + hpdma_lli: hpdma-lli@a020000 { + reg = <0x0 0xa020000 0x0 0x20000>; + no-map; + }; + + bsec_mirror: bsec-mirror@a040000 { + reg = <0x0 0xa040000 0x0 0x1000>; + no-map; + }; + + cm33_sram1: cm33-sram1@a041000 { + reg = <0x0 0xa041000 0x0 0x1f000>; + no-map; + }; + + cm33_sram2: cm33-sram2@a060000 { + reg = <0x0 0xa060000 0x0 0x20000>; + no-map; + }; + + cm33_retram: cm33-retram@a080000 { + reg = <0x0 0xa080000 0x0 0x1f000>; + no-map; + }; + + ddr_param: ddr-param@a09f000 { + reg = <0x0 0xa09f000 0x0 0x1000>; + no-map; + }; + + /* PCIe reserved memory declaration */ + pcie_device: pcie-device@10000000 { + reg = <0x0 0x10000000 0x0 0x10000000>; + no-map; + }; + + /* Backup RAM reserved memory declaration */ + bl31_lowpower: bl31-lowpower@42000000 { + reg = <0x0 0x42000000 0x0 0x1000>; + no-map; + }; + + tfm_its: tfm-its@42001000 { + reg = <0x0 0x42001000 0x0 0x1000>; + no-map; + }; + + /* Octo Memory Manager reserved memory declaration */ + mm_ospi1: mm-ospi@60000000 { + reg = <0x0 0x60000000 0x0 0x10000000>; + no-map; + }; + + /* DDR reserved memory declaration */ + tfm_code: tfm-code@80000000 { + reg = <0x0 0x80000000 0x0 0x100000>; + no-map; + }; + + cm33_cube_fw: cm33-cube-fw@80100000 { + reg = <0x0 0x80100000 0x0 0x800000>; + no-map; + }; + + tfm_data: tfm-data@80900000 { + reg = <0x0 0x80900000 0x0 0x100000>; + no-map; + }; + + cm33_cube_data: cm33-cube-data@80a00000 { + reg = <0x0 0x80a00000 0x0 0x800000>; + no-map; + }; + + ipc_shmem: ipc-shmem@81200000 { + reg = <0x0 0x81200000 0x0 0x100000>; + no-map; + }; + + spare1: spare1@81300000 { + reg = <0x0 0x81300000 0x0 0xcc0000>; + no-map; + }; + + bl31_context: bl31-context@81fc0000 { + reg = <0x0 0x81fc0000 0x0 0x40000>; + no-map; + }; + + op_tee: op-tee@82000000 { + reg = <0x0 0x82000000 0x0 0x2000000>; + no-map; + }; + + linuxkernel1: linuxkernel1@84000000 { + reg = <0x0 0x84000000 0x0 0x76800000>; + no-map; + }; + + gpu_reserved: gpu-reserved@fa800000 { + reg = <0x0 0xfa800000 0x0 0x4000000>; + no-map; + }; + + ltdc_sec_layer: ltdc-sec-layer@fe800000 { + reg = <0x0 0xfe800000 0x0 0x800000>; + no-map; + }; + + ltdc_sec_rotation: ltdc-sec-rotation@ff000000 { + reg = <0x0 0xff000000 0x0 0x1000000>; + no-map; + }; + + linuxkernel2: linuxkernel2@100000000 { + reg = <0x1 0x00000000 0x0 0x80000000>; + no-map; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rif.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rif.dtsi new file mode 100644 index 0000000..bcdafc6 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard-rif.dtsi @@ -0,0 +1,998 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2024, STMicroelectronics + */ + +&rifsc { + st,protreg = < + RIFPROT(STM32MP25_RIFSC_TIM1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM6_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM7_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM8_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM10_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM11_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM12_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM13_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM14_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM15_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM16_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM17_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_TIM20_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LPTIM1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_LPTIM2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LPTIM3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LPTIM4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LPTIM5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI6_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI7_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPI8_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SPDIFRX_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USART1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USART2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USART3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UART4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UART5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USART6_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UART7_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UART8_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UART9_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LPUART1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C6_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I2C7_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_I2C8_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SAI1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SAI2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SAI3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SAI4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_MDF1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ADF1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_FDCAN_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_HDP_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ADC12_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ADC3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ETH1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ETH2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ETHSW_DEIP_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ETHSW_ACM_MSGBUF_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ETHSW_ACM_CFG_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USBH_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_USB3DR_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_COMBOPHY_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_PCIE_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_UCPD1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_STGEN_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_SDMMC1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SDMMC2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SDMMC3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_GPU_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LTDC_CMN_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LTDC_L0L1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LTDC_L2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LTDC_ROT_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_DSI_CMN_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_DSI_TRIG_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_DSI_RDFIFO_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_LVDS_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_CSI_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_DCMIPP_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_DCMI_PSSI_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_VDEC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_VENC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_RNG_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_PKA_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_SAES_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_HASH_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_CRYP1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_CRYP2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_IWDG1_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_IWDG2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_IWDG3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_IWDG4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_IWDG5_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_WWDG1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_WWDG2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_VREFBUF_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_DTS_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_RAMCFG_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_CRC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_SERC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(STM32MP25_RIFSC_GICV2M_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I3C1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I3C2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I3C3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_I3C4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(STM32MP25_RIFSC_ICACHE_DCACHE_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; + st,glocked = ; +}; + +&fmc { + st,protreg = < + RIFPROT(RIF_FMC_CTRL(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_FMC_CTRL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_FMC_CTRL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_FMC_CTRL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_FMC_CTRL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_FMC_CTRL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&rtc { + st,protreg = < + RIFPROT(RIF_RTC_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RTC_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RTC_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RTC_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RTC_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RTC_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&tamp { + st,protreg = < + RIFPROT(RIF_TAMP_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_TAMP_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_TAMP_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + >; + st,backup-zones = <24 24 24 24 12 12 8>; +}; + +&pwr { + st,protreg = < + RIFPROT(RIF_PWR_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE(6), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_PWR_RESOURCE_WIO(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_PWR_RESOURCE_WIO(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_PWR_RESOURCE_WIO(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_PWR_RESOURCE_WIO(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_PWR_RESOURCE_WIO(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_PWR_RESOURCE_WIO(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&exti1 { + st,proccid = <1 RIF_CID1>, <2 RIF_CID2>; + st,protreg = < + RIFPROT(RIF_EXTI1_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(16), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(17), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(18), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(19), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(21), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(22), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(23), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(24), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(25), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(26), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(27), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(28), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(29), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(30), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(31), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(32), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(33), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(34), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(36), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(37), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(38), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(39), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(40), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(41), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(42), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(43), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(44), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(45), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(46), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(47), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(48), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(49), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(50), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(52), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(53), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(54), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(55), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(56), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(57), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(59), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(60), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(61), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(62), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(64), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(65), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(67), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(68), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(69), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(70), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(71), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(72), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(73), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(74), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(75), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(76), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(77), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(78), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(79), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(80), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(81), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(82), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI1_RESOURCE(83), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI1_RESOURCE(84), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&exti2 { + st,proccid = <1 RIF_CID1>, <2 RIF_CID2>, <3 RIF_CID3>; + st,protreg = < + RIFPROT(RIF_EXTI2_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(16), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(17), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(18), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(19), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(20), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(21), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(22), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(23), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(24), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(25), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(26), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(27), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(29), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(30), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(31), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(33), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(34), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(35), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(36), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(37), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(38), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(40), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(41), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(42), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(43), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(44), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(46), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(47), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(48), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(49), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(50), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(51), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(52), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(53), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(54), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(55), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(56), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(59), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(60), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(61), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(62), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(63), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(64), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(65), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(66), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(67), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(68), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_EXTI2_RESOURCE(69), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(70), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_EXTI2_RESOURCE(76), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&gpioa { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiob { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioc { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiod { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&gpioe { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiof { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiog { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioh { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioi { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioj { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiok { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioz { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&hpdma1 { + st,protreg = < + RIFPROT(RIF_HPDMA_CHANNEL(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&hpdma2 { + st,protreg = < + RIFPROT(RIF_HPDMA_CHANNEL(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&hpdma3 { + st,protreg = < + RIFPROT(RIF_HPDMA_CHANNEL(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_HPDMA_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&rifsc { + st,rimu = < + RIMUPROT(RIMU_ID(0), RIF_CID1, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_M) + RIMUPROT(RIMU_ID(1), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(2), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(3), RIF_UNUSED, RIF_NSEC, RIF_NPRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(4), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(5), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(6), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(7), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(8), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(9), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(10), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(11), RIF_CID0, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_M) + RIMUPROT(RIMU_ID(12), RIF_CID0, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_M) + RIMUPROT(RIMU_ID(13), RIF_CID0, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_M) + RIMUPROT(RIMU_ID(14), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + RIMUPROT(RIMU_ID(15), RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CIDSEL_P) + >; +}; + +&rifsc { + st,risal = < + RISALPROT(RISAL_ID(1), RIFSC_RISAL_BLOCK_A, RIF_CID1, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + RISALPROT(RISAL_ID(2), RIFSC_RISAL_BLOCK_A, RIF_CID1, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + RISALPROT(RISAL_ID(3), RIFSC_RISAL_BLOCK_A, RIF_CID1, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + RISALPROT(RISAL_ID(1), RIFSC_RISAL_BLOCK_B, RIF_CID3, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + RISALPROT(RISAL_ID(2), RIFSC_RISAL_BLOCK_B, RIF_CID3, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + RISALPROT(RISAL_ID(3), RIFSC_RISAL_BLOCK_B, RIF_CID3, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIFSC_RISAL_SREN) + >; +}; + +&rcc { + st,protreg = < + RIFPROT(RIF_RCC_RESOURCE(69), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(64), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(65), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(66), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(67), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(68), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(70), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(71), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(72), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(73), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(74), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(75), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(76), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(77), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(78), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(79), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(80), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(81), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(82), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(83), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(84), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(85), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(86), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(87), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(88), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(89), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(90), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(91), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(92), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(93), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(94), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(95), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(96), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(97), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(98), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(99), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(100), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(101), RIF_CID1_BF, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(102), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(103), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(104), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(105), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(106), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(108), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(109), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(110), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(111), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(112), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_RCC_RESOURCE(113), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(6), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(7), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(8), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(9), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(10), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(11), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(12), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(13), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(14), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(15), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(16), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(17), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(18), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(19), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(20), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(21), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(22), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(23), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(24), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(25), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(26), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(27), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(28), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(29), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(30), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(31), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(32), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(33), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(34), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(35), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(36), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(37), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(38), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(39), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(40), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(41), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(42), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(43), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(44), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(45), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(46), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(47), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(48), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(49), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(50), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(51), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(52), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(53), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(54), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(55), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(56), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(57), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(58), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(59), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(60), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(61), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(62), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_RCC_RESOURCE(63), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&ipcc1 { + st,protreg = < + RIFPROT(RIF_IPCC_CPU1_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(16), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(16), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&ipcc2 { + st,protreg = < + RIFPROT(RIF_IPCC_CPU1_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID3, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID3, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID3, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU1_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID3, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IPCC_CPU2_CHANNEL(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + >; +}; + +&hsem { + st,proccid = <1 RIF_CID1>, <2 RIF_CID2>, <3 RIF_CID3>; + st,protreg = < + RIFPROT(RIF_HSEM_RESOURCE(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(2), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(3), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(4), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(6), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(7), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(8), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(9), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(10), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_HSEM_RESOURCE(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&tfa_bl31 { + st,protreg = ; +}; + +&hpdma_lli { + st,protreg = ; +}; + +&bsec_mirror { + st,protreg = ; +}; + +&cm33_sram1 { + st,protreg = ; +}; + +&cm33_sram2 { + st,protreg = ; +}; + +&cm33_retram { + st,protreg = ; +}; + +&ddr_param { + st,protreg = ; +}; + +&risab1 { + memory-region = <&tfa_bl31>; +}; + +&risab2 { + memory-region = <&hpdma_lli>; +}; + +&risab3 { + st,srwiad; + memory-region = <&bsec_mirror>, <&cm33_sram1>; +}; + +&risab4 { + st,srwiad; + memory-region = <&cm33_sram2>; +}; + +&risab5 { + st,srwiad; + memory-region = <&cm33_retram>, <&ddr_param>; +}; + +&mm_ospi1 { + st,protreg = ; +}; + +&risaf2 { + memory-region= <&mm_ospi1>; +}; + +&ommanager { + access-controllers-conf-default = + <&rifsc RIFPROT(STM32MP25_RIFSC_OCTOSPI1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)>, + <&rifsc RIFPROT(STM32MP25_RIFSC_OCTOSPI2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)>, + <&rifsc RIFPROT(STM32MP25_RIFSC_OCTOSPIM_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)>, + <&rifsc RIFPROT(STM32MP25_RIFSC_OTFDEC1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)>, + <&rifsc RIFPROT(STM32MP25_RIFSC_OTFDEC2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_DIS, RIF_CFDIS)>; + + st,omm-mux = <0x0>; + + spi@40430000 { + memory-region = <&mm_ospi1>; + /* insert flash definition here */ + }; +}; + +&pcie_device { + st,protreg = ; +}; + +&risaf5 { + memory-region= <&pcie_device>; +}; + +&bl31_lowpower { + st,protreg = ; +}; + +&tfm_its { + st,protreg = ; +}; + +&risaf1 { + memory-region= <&bl31_lowpower>, <&tfm_its>; +}; + +&tfm_code { + st,protreg = ; +}; + +&cm33_cube_fw { + st,protreg = ; +}; + +&tfm_data { + st,protreg = ; +}; + +&cm33_cube_data { + st,protreg = ; +}; + +&ipc_shmem { + st,protreg = ; +}; + +&spare1 { + st,protreg = ; +}; + +&bl31_context { + st,protreg = ; +}; + +&op_tee { + st,protreg = ; +}; + +&linuxkernel1 { + st,protreg = ; +}; + +&gpu_reserved { + st,protreg = ; +}; + +<dc_sec_layer { + st,protreg = ; +}; + +<dc_sec_rotation { + st,protreg = ; +}; + +&linuxkernel2 { + st,protreg = ; +}; + +&risaf4 { + memory-region= <&tfm_code>, <&cm33_cube_fw>, <&tfm_data>, <&cm33_cube_data>, <&ipc_shmem>, <&spare1>, <&bl31_context>, <&op_tee>, <&linuxkernel1>, <&gpu_reserved>, <<dc_sec_layer>, <<dc_sec_rotation>, <&linuxkernel2>; +}; + diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard.dts b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard.dts new file mode 100644 index 0000000..9397e73 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/optee/stm32mp257f-myboard.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp257f-dk-ca35tdcid-rcc.dtsi" +#include "stm32mp257f-dk-ca35tdcid-resmem.dtsi" +#include "stm32mp257f-dk-ca35tdcid-rif.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxal-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x00000000>; + }; + + shadow-prov { + compatible = "st,provisioning"; + hconf1_prov { + nvmem-cells = <&hconf1_otp>; + st,shadow-value = <0x00018DB6>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&hash { + status = "okay"; +}; + +&hsi_calibration { + status = "okay"; +}; + +&i2c7 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c7_pins_a>; + pinctrl-1 = <&i2c7_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pmic2: stpmic2@33 { + compatible = "st,stpmic2"; + reg = <0x33>; + st,wakeup-pin-number = <1>; + st,pmic-it-id = ; + st,notif-it-id = <0 1>; + wakeup-parent = <&pwr>; + status = "okay"; + + regulators { + compatible = "st,stpmic2-regulators"; + + ldo1-supply = <&vddio_pmic>; + vddcpu: buck1 { + regulator-name = "vddcpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <910000>; + regulator-always-on; + st,pwrctrl-sel = <2>; + st,pwrctrl-enable; + + default { + regulator-off-in-suspend; + }; + lplv { + regulator-off-in-suspend; + }; + standby { + regulator-off-in-suspend; + }; + off { + regulator-off-in-suspend; + }; + }; + vddcore: buck2 { + regulator-name = "vddcore"; + regulator-min-microvolt = <820000>; + regulator-max-microvolt = <820000>; + regulator-always-on; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <820000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <670000>; + }; + standby { + regulator-off-in-suspend; + }; + off { + regulator-off-in-suspend; + }; + }; + vddgpu_pmic: buck3 { + regulator-name = "vddgpu_pmic"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-over-current-protection; + }; + vddio_pmic: buck4 { + regulator-name = "vddio_pmic"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + off { + /* ToDo: switch to LP */ + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + v1v8: buck5 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + standby { + regulator-off-in-suspend; + }; + off { + regulator-off-in-suspend; + }; + }; + vdd2_ddr: buck6 { + regulator-name = "vdd2_ddr"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + off { + regulator-off-in-suspend; + }; + }; + v3v3: buck7 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + standby { + regulator-off-in-suspend; + }; + off { + regulator-off-in-suspend; + }; + }; + vdda1v8_aon: ldo1 { + regulator-name = "vdda1v8_aon"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,alternate-input-source; + st,mask-reset; + }; + vdd_emmc: ldo2 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-over-current-protection; + st,pwrctrl-sel = <3>; + st,pwrctrl-reset; + }; + vdd1_ddr: ldo3 { + regulator-name = "vdd1_ddr"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,pwrctrl-sel = <1>; + st,pwrctrl-enable; + + default { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + lplv { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + off { + regulator-off-in-suspend; + }; + }; + vdd3v3_usb: ldo4 { + regulator-name = "vdd3v3_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + }; + v5v_hdmi: ldo5 { + regulator-name = "v5v_hdmi"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + st,regulator-bypass-microvolt = <5000000>; + st,pwrctrl-sel = <0>; + st,pwrctrl-enable; + }; + v5v_vconn: ldo6 { + regulator-name = "v5v_vconn"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-always-on; + st,regulator-bypass-microvolt = <4000000>; + st,pwrctrl-sel = <0>; + st,pwrctrl-reset; + }; + vdd_sdcard: ldo7 { + regulator-name = "vdd_sdcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-over-current-protection; + st,regulator-bypass-microvolt = <3300000>; + st,pwrctrl-sel = <3>; + st,pwrctrl-reset; + }; + vddio_sdcard: ldo8 { + regulator-name = "vddio_sdcard"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-over-current-protection; + st,regulator-bypass-microvolt = <3300000>; + st,pwrctrl-sel = <3>; + st,pwrctrl-reset; + }; + }; + }; +}; + +&iwdg1 { + timeout-sec = <32>; + status = "okay"; +}; + +&m33_rproc { + status = "okay"; +}; + +&pka { + status = "okay"; +}; + +&pwr { + status = "okay"; + wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>, <0>, <0>, <0>, <0>, <0>; + + vdd33ucpd: vdd33ucpd { + status = "okay"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vdd33ucpd-supply = <&vdd3v3_usb>; + regulator-always-on; + }; + + vdda18adc: vdda18adc { + status = "okay"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vdda18adc-supply = <&v1v8>; + regulator-always-on; + }; + + vddgpu: vddgpu { + status = "okay"; + vddgpu-supply = <&vddgpu_pmic>; + }; + + vddio1: vddio1 { + status = "okay"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vddio1-supply = <&vddio_sdcard>; + }; + + vddio2: vddio2 { + status = "okay"; + vddio2-supply = <&v1v8>; + regulator-always-on; + }; + + vddio3: vddio3 { + status = "okay"; + vddio3-supply = <&vddio_pmic>; + regulator-always-on; + }; + + vddio4: vddio4 { + status = "okay"; + vddio4-supply = <&vddio_pmic>; + regulator-always-on; + }; + + vddio: vddio { + status = "okay"; + vdd-supply = <&vddio_pmic>; + }; +}; + +&rcc { + st,c1msrd = <2>; + st,clk_opp { + st,ck_cpu1 { + cfg_1 { + hz = <1500000000>; + st,pll = <&pll1_cfg_1500Mhz>; + }; + + cfg_2 { + hz = <1200000000>; + st,pll = <&pll1_cfg_1200Mhz>; + }; + }; + }; +}; + +&risaf2 { + status = "okay"; +}; + +&risaf5 { + status = "okay"; +}; + +&saes { + status = "okay"; +}; + +&scmi_regu { + voltd-vddcore { + reg = ; + voltd-supply = <&vddcore>; + }; + voltd-v1v8 { + reg = ; + voltd-supply = <&v1v8>; + }; + voltd-v3v3 { + reg = ; + voltd-supply = <&v3v3>; + }; + voltd-v5v-hdmi { + reg = ; + voltd-supply = <&v5v_hdmi>; + }; + voltd-v5v-vconn { + reg = ; + voltd-supply = <&v5v_vconn>; + }; + voltd-vdd-emmc { + reg = ; + voltd-supply = <&vdd_emmc>; + }; + voltd-vdd3v3-usb { + reg = ; + voltd-supply = <&vdd3v3_usb>; + }; + voltd-vdd-sdcard { + reg = ; + voltd-supply = <&vdd_sdcard>; + }; +}; + +&tamp { + wakeup-source; + wakeup-parent = <&exti2>; + st,tamp-passive-precharge = <2>; + st,tamp-passive-nb-sample = <4>; + st,tamp-passive-sample-clk-div = <16384>; + + /* Tamper button */ + tamp-button { + status = "okay"; + tamper-gpios = <&gpioz 2 0>; + st,tamp-mode = ; + st,tamp-id = <3>; + }; +}; + +&usart2 { + pinctrl-names = "default"; + pinctrl-0 = <&usart2_pins_a>; + status = "okay"; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dts b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dts new file mode 100644 index 0000000..9e79cd5 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved + */ + +#include "stm32mp25-fw-config.dtsi" +#include "stm32mp257f-myboard-fw-config.dtsi" diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dtsi new file mode 100644 index 0000000..9b05f00 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-fw-config.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ + +/* + * STM32MP25 tf-a firmware config + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:07 AM + */ + +/ { + dtb-registry { + soc_fw-config { + load-address = <0x0 0x81fc0000>; + max-size = <0x40000>; + }; + tos_fw { + load-address = <0x0 0x82000000>; + max-size = <0x2000000>; + }; + }; + + st-mem-firewall { + bl31_context: bl31-context@81fc0000 { + reg = <0x0 0x81fc0000 0x0 0x40000>; + st,protreg = ; + }; + op_tee: op-tee@82000000 { + reg = <0x0 0x82000000 0x0 0x2000000>; + st,protreg = ; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-rcc.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-rcc.dtsi new file mode 100644 index 0000000..837abb4 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard-rcc.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. + */ + +/* + * STM32MP25 Clock tree device tree configuration + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:05 AM + */ + +&clk_hse { + clock-frequency = <40000000>; +}; + +&clk_hsi { + clock-frequency = <64000000>; +}; + +&clk_lse { + clock-frequency = <32768>; +}; + +&clk_lsi { + clock-frequency = <32000>; +}; + +&clk_msi { + clock-frequency = <16000000>; +}; + +&rcc { + st,busclk = < + DIV_CFG(DIV_LSMCU, 1) + DIV_CFG(DIV_APB1, 0) + DIV_CFG(DIV_APB2, 0) + DIV_CFG(DIV_APB3, 0) + DIV_CFG(DIV_APB4, 0) + DIV_CFG(DIV_APBDBG, 0) + >; + + st,flexgen = < + FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) + FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) + FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) + FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) + FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) + FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) + FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) + FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) + >; + + st,kerclk = < + MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) + MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) + >; + + pll1: st,pll-1 { + st,pll = <&pll1_cfg_1200Mhz>; + + pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + }; + + pll2: st,pll-2 { + st,pll = <&pll2_cfg_600Mhz>; + + pll2_cfg_600Mhz: pll2-cfg-600Mhz { + cfg = <30 1 1 2>; + src = ; + }; + }; + + pll4: st,pll-4 { + st,pll = <&pll4_cfg_1200Mhz>; + + pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { + cfg = <30 1 1 1>; + src = ; + }; + }; + + pll5: st,pll-5 { + st,pll = <&pll5_cfg_532Mhz>; + + pll5_cfg_532Mhz: pll5-cfg-532Mhz { + cfg = <133 5 1 2>; + src = ; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard.dts b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard.dts new file mode 100644 index 0000000..7d17d05 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/tf-a/stm32mp257f-myboard.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp257f-dk-ca35tdcid-rcc.dtsi" +#include "stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxal-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-MyBoard"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x00000000>; + }; + + shadow-prov { + compatible = "st,provisioning"; + + hconf1_prov { + nvmem-cells = <&hconf1_otp>; + st,shadow-value = <0x00018000>; + }; + }; +}; + +&bsec { + board_id: board_id@3d8 { + reg = <0x3d8 0x4>; + }; +}; + +&ddr { + vdd1-supply = <&vdd1_ddr>; + vdd2-supply = <&vdd2_ddr>; + vddq-supply = <&vdd2_ddr>; +}; + +&hash { + status = "okay"; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pmic2: stpmic@33 { + compatible = "st,stpmic2"; + reg = <0x33>; + status = "okay"; + + regulators { + compatible = "st,stpmic2-regulators"; + + vddcpu: buck1 { + regulator-name = "vddcpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <910000>; + regulator-always-on; + }; + vddcore: buck2 { + regulator-name = "vddcore"; + regulator-min-microvolt = <820000>; + regulator-max-microvolt = <820000>; + regulator-always-on; + }; + vddgpu: buck3 { + regulator-name = "vddgpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + vddio_pmic: buck4 { + regulator-name = "vddio_pmic"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + v1v8: buck5 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vdd2_ddr: buck6 { + regulator-name = "vdd2_ddr"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + v3v3: buck7 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdda1v8_aon: ldo1 { + regulator-name = "vdda1v8_aon"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vdd_emmc: ldo2 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd1_ddr: ldo3 { + regulator-name = "vdd1_ddr"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + }; + vdd3v3_usb: ldo4 { + regulator-name = "vdd3v3_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + v5v_hdmi: ldo5 { + regulator-name = "v5v_hdmi"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + vdd_sdcard: ldo7 { + regulator-name = "vdd_sdcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vddio_sdcard: ldo8 { + regulator-name = "vddio_sdcard"; + st,regulator-bypass-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iwdg1 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr { + vddio1: vddio1 { + vddio1-supply = <&vddio_sdcard>; + }; + vddio2: vddio2 { + vddio2-supply = <&v1v8>; + }; + vddio3: vddio3 { + vddio3-supply = <&vddio_pmic>; + }; + vddio4: vddio4 { + vddio4-supply = <&vddio_pmic>; + }; + vddio: vddio { + vdd-supply = <&vddio_pmic>; + }; +}; + +&pka { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&saes { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sdcard>; + vqmmc-supply = <&vddio1>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&vdd_emmc>; + vqmmc-supply = <&vddio2>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default"; + pinctrl-0 = <&usart2_pins_a>; + status = "okay"; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/Makefile b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/Makefile new file mode 100644 index 0000000..6e041a1 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) + +dtb-$(CONFIG_STM32MP25X) += \ + stm32mp257f-myboard.dtb + +#include $(srctree)/scripts/Makefile.dts + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += -a 0x8 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb *.dtbo *_HS diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-resmem.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-resmem.dtsi new file mode 100644 index 0000000..243df32 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-resmem.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. + */ + +/* + * STM32MP25 reserved memory device tree configuration + * Project : open + * Generated by XLmx tool version 2.2 - 3/6/2024 11:20:05 AM + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Internal RAM reserved memory declaration */ + tfa_bl31: tfa-bl31@a000000 { + reg = <0x0 0xa000000 0x0 0x20000>; + no-map; + }; + + hpdma1_lli: hpdma1-lli@a020000 { + reg = <0x0 0xa020000 0x0 0xf0f0>; + no-map; + }; + + hpdma2_lli: hpdma2-lli@a02f0f0 { + reg = <0x0 0xa02f0f0 0x0 0xf0f0>; + no-map; + }; + + hpdma3_lli: hpdma3-lli@a03e1e0 { + reg = <0x0 0xa03e1e0 0x0 0x1e20>; + no-map; + }; + + bsec_mirror: bsec-mirror@a040000 { + reg = <0x0 0xa040000 0x0 0x1000>; + no-map; + }; + + cm33_sram1: cm33-sram1@a041000 { + reg = <0x0 0xa041000 0x0 0x1f000>; + no-map; + }; + + cm33_sram2: cm33-sram2@a060000 { + reg = <0x0 0xa060000 0x0 0x20000>; + no-map; + }; + + cm33_retram: cm33-retram@a080000 { + reg = <0x0 0xa080000 0x0 0x1f000>; + no-map; + }; + + ddr_param: ddr-param@a09f000 { + reg = <0x0 0xa09f000 0x0 0x1000>; + no-map; + }; + + cm0_cube_fw: cm0-cube-fw@200C0000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C0000 0x0 0x4000>; + no-map; + }; + + cm0_cube_data: cm0-cube-data@200C4000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C4000 0x0 0x2000>; + no-map; + }; + + ipc_shmem_2: ipc-shmem-2@200C6000{ + compatible = "shared-dma-pool"; + reg = <0x0 0x200C6000 0x0 0x2000>; + no-map; + }; + + /* Backup RAM reserved memory declaration */ + bl31_lowpower: bl31-lowpower@42000000 { + reg = <0x0 0x42000000 0x0 0x1000>; + no-map; + }; + + tfm_its: tfm-its@42001000 { + reg = <0x0 0x42001000 0x0 0x1000>; + no-map; + }; + + /* Octo Memory Manager reserved memory declaration */ + mm_ospi1: mm-ospi@60000000 { + reg = <0x0 0x60000000 0x0 0x10000000>; + no-map; + }; + + /* DDR reserved memory declaration */ + tfm_code: tfm-code@80000000 { + reg = <0x0 0x80000000 0x0 0x100000>; + no-map; + }; + + cm33_cube_fw: cm33-cube-fw@80100000 { + reg = <0x0 0x80100000 0x0 0x800000>; + no-map; + }; + + tfm_data: tfm-data@80900000 { + reg = <0x0 0x80900000 0x0 0x100000>; + no-map; + }; + + cm33_cube_data: cm33-cube-data@80a00000 { + reg = <0x0 0x80a00000 0x0 0x800000>; + no-map; + }; + + ipc_shmem_1: ipc-shmem-1@81200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x81200000 0x0 0xf8000>; + no-map; + }; + + vdev0vring0: vdev0vring0@812f8000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f8000 0x0 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@812f9000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f9000 0x0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@812fa000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812fa000 0x0 0x6000>; + no-map; + }; + + spare1: spare1@81300000 { + reg = <0x0 0x81300000 0x0 0xcc0000>; + no-map; + }; + + bl31_context: bl31-context@81fc0000 { + reg = <0x0 0x81fc0000 0x0 0x40000>; + no-map; + }; + + op_tee: op-tee@82000000 { + reg = <0x0 0x82000000 0x0 0x2000000>; + no-map; + }; + + gpu_reserved: gpu-reserved@fa800000 { + reg = <0x0 0xfa800000 0x0 0x4000000>; + no-map; + }; + + ltdc_sec_layer: ltdc-sec-layer@fe800000 { + reg = <0x0 0xfe800000 0x0 0x800000>; + no-map; + }; + + ltdc_sec_rotation: ltdc-sec-rotation@ff000000 { + reg = <0x0 0xff000000 0x0 0x1000000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x80000000>; + size = <0x0 0x8000000>; + alignment = <0x0 0x2000>; + linux,cma-default; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-u-boot.dtsi b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-u-boot.dtsi new file mode 100644 index 0000000..74a8c61 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ + +#include "stm32mp25-u-boot.dtsi" + +/ { + config { + u-boot,boot-led = "led-blue"; + u-boot,mmc-env-partition = "u-boot-env"; + st,stm32prog-gpios = <&gpioc 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&sdmmc1>; + }; +}; + +&dwc3 { + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + /delete-node/ port; +}; + +&i2c_rpmsg { + /delete-node/ typec@35; +}; + +&sdmmc3 { + status = "disabled"; +}; + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard.dts b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard.dts new file mode 100644 index 0000000..44c171d --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-extended/external-dt/files/devicetree/u-boot/stm32mp257f-myboard.dts @@ -0,0 +1,890 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" +#include "stm32mp257f-myboard-resmem.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-MYBOARD"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + serial1 = &usart6; + serial2 = &usart1; + ethernet0 = ð1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, + <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + status = "disabled"; + }; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_ext_cec: clk-ext-cec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + dmic0: dmic-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic0"; + status = "okay"; + + port { + dmic0_endpoint: endpoint { + remote-endpoint = <&mdf_endpoint0>; + }; + }; + }; + + dmic1: dmic-1 { + compatible = "dmic-codec"; + #sound-dai-cells = <1>; + sound-name-prefix = "dmic1"; + status = "okay"; + + port { + dmic1_endpoint: endpoint { + remote-endpoint = <&mdf_endpoint1>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-wake-up { + label = "wake-up"; + linux,code = ; + interrupts-extended = <&optee 0>; + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + hdmi-pwr-supply = <&scmi_v5v_hdmi>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + imx335_2v9: imx335-2v9 { + compatible = "regulator-fixed"; + regulator-name = "imx335-avdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + imx335_1v8: imx335-1v8 { + compatible = "regulator-fixed"; + regulator-name = "imx335-ovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + imx335_1v2: imx335-1v2 { + compatible = "regulator-fixed"; + regulator-name = "imx335-dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + panel_lvds: panel-lvds { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + default-on; + status = "okay"; + + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: panel-lvds-backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + default-on; + default-brightness-level = <1>; + status = "okay"; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP25-DK"; + dais = <&i2s2_port &mdf1_port0 &mdf1_port1>; + status = "okay"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; +}; + +&a35ss_syscfg { + status = "okay"; +}; + +&ahbsr { + mbox_client: mailbox-client@1 { + compatible = "mbox-cdev"; + reg = <1 0>; + memory-region = <&ipc_shmem_2>; + mboxes = <&ipcc2 0>; + mbox-names = "rx-tx"; + status = "okay"; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&combophy { + st,ssc-on; + status = "okay"; +}; + +&crc { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&cs_cpu_debug0 { + status = "okay"; +}; + +&cs_cpu_debug1 { + status = "okay"; +}; + +&cs_cti0 { + status = "okay"; +}; + +&cs_cti1 { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_etr { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_replicator { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&csi { + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi_sink: endpoint { + remote-endpoint = <&imx335_ep>; + data-lanes = <0 1>; + bus-type = <4>; + }; + }; + port@1 { + reg = <1>; + csi_source: endpoint { + remote-endpoint = <&dcmipp_0>; + }; + }; + }; +}; + +&dcmipp { + status = "okay"; + port { + dcmipp_0: endpoint { + remote-endpoint = <&csi_source>; + bus-type = <4>; + }; + }; +}; + +&dsi { + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out1: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +ð1 { + status = "okay"; + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy1_eth1>; + st,eth-ptp-from-rcc; + + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,eee-disable; + reg = <1>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&hpdma { + memory-region = <&hpdma1_lli>; +}; + +&hpdma2 { + memory-region = <&hpdma2_lli>; +}; + +&hpdma3 { + memory-region = <&hpdma3_lli>; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + imx335: imx335@1a { + compatible = "sony,imx335"; + reg = <0x1a>; + clocks = <&clk_ext_camera>; + avdd-supply = <&imx335_2v9>; + ovdd-supply = <&imx335_1v8>; + dvdd-supply = <&imx335_1v2>; + reset-gpios = <&gpiob 1 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + powerdown-gpios = <&gpiob 11 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; + status = "okay"; + + port { + imx335_ep: endpoint { + remote-endpoint = <&csi_sink>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <594000000>; + }; + }; + }; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3f>, <0x38>; + reg-names = "main", "cec", "edid", "packet"; + status = "okay"; + adi,dsi-lanes = <4>; + clocks = <&clk_ext_cec>; + clock-names = "cec"; + interrupt-parent = <&gpiob>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; + avdd-supply = <&scmi_v1v8>; + dvdd-supply = <&scmi_v1v8>; + pvdd-supply = <&scmi_v1v8>; + a2vdd-supply = <&scmi_v1v8>; + v3p3-supply = <&scmi_v3v3>; + v1p2-supply = <&scmi_v1v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out1>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + port@2 { + reg = <2>; + adv7535_tx_endpoint: endpoint { + remote-endpoint = <&i2s2_endpoint>; + }; + }; + }; + }; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2s2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_b>; + pinctrl-1 = <&i2s2_sleep_pins_b>; + status = "okay"; + + i2s2_port: port { + i2s2_endpoint: endpoint { + remote-endpoint = <&adv7535_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + }; + }; +}; + +&ipcc1 { + status = "okay"; +}; + +&ipcc2 { + status = "okay"; +}; + +/* use LPTIMER with tick broadcast for suspend mode */ +&lptimer3 { + status = "okay"; + timer { + status = "okay"; + }; +}; + +<dc { + default-on; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + default-on; + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + +&m0_rproc { + mboxes = <&ipcc2 0>, <&ipcc2 1>, <&ipcc2 2>; + mbox-names = "rx", "tx", "shutdown"; + memory-region = <&cm0_cube_fw>, <&cm0_cube_data>; + clocks = <&rcc CK_CPU3>, + <&rcc CK_CPU3_AM>, + <&scmi_clk CK_SCMI_IPCC2>, + <&scmi_clk CK_SCMI_IPCC2_AM>; + status = "okay"; +}; + +&m33_rproc { + mboxes = <&ipcc1 0x100>, <&ipcc1 0x101>, <&ipcc1 2>; + mbox-names = "vq0", "vq1", "shutdown"; + memory-region = <&cm33_cube_fw>, <&cm33_cube_data>, + <&ipc_shmem_1>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>, + <&cm33_sram2>; + st,syscfg-nsvtor = <&a35ss_syscfg 0xa8 0xffffff80>; + status = "okay"; +}; + +&mdf1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdf_cck0_pins_a>; + pinctrl-1 = <&mdf_cck0_sleep_pins_a>; + #clock-cells = <1>; + clock-output-names = "cck0"; + clock-frequency = <1536000>; + status = "okay"; + + sitf6: sitf@380 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdf_sdi6_pins_a>; + pinctrl-1 = <&mdf_sdi6_sleep_pins_a>; + st,sitf-mode = "spi"; + clocks = <&mdf1 0>; + status = "okay"; + }; + + filter0: filter@84 { + st,cic-mode = <4>; + st,sitf = <&sitf6 0>; + st,hpf-filter-cutoff-bp = <625>; + status = "okay"; + + asoc_pdm0: mdf-dai { + compatible = "st,stm32mp25-mdf-dai"; + #sound-dai-cells = <0>; + io-channels = <&filter0 0>; + power-domains = <&RET_PD>; + status = "okay"; + + mdf1_port0: port { + mdf_endpoint0: endpoint { + remote-endpoint = <&dmic0_endpoint>; + }; + }; + }; + }; + + filter1: filter@104 { + st,cic-mode = <4>; + st,sitf = <&sitf6 1>; + st,hpf-filter-cutoff-bp = <625>; + status = "okay"; + + asoc_pdm1: mdf-dai { + compatible = "st,stm32mp25-mdf-dai"; + #sound-dai-cells = <0>; + io-channels = <&filter1 0>; + power-domains = <&RET_PD>; + status = "okay"; + + mdf1_port1: port { + mdf_endpoint1: endpoint { + remote-endpoint = <&dmic1_endpoint>; + }; + }; + }; + }; +}; + +&mlahb { + intc_rpmsg: interrupt-controller@1 { + compatible = "rpmsg,intc"; + reg = <1 0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + i2c_rpmsg: i2c@2 { + compatible = "rpmsg,i2c-controller"; + reg = <2 0>; + rpmsg,dev-id = "rpmsg_i2c"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + typec@35 { + compatible = "st,stm32mp25-typec"; + reg = <0x35>; + interrupts-extended = <&intc_rpmsg 0>; + status = "okay"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + typec_ep: endpoint { + remote-endpoint = <&dwc3_ep>; + }; + }; + }; + }; + }; +}; + +&rtc { + st,lsco = ; + pinctrl-0 = <&rtc_out2_rmp_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&scmi_vdd_emmc>; + vqmmc-supply = <&scmi_vddio2>; + mmc-ddr-1_8v; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + status = "disabled"; + }; +}; + +&spi6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_pins_a>; + pinctrl-1 = <&spi6_sleep_pins_a>; + status = "disabled"; +}; + +/* Bluetooth */ +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 4 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&scmi_v3v3>; + vddio-supply = <&scmi_v3v3>; + }; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_idle_pins_a>; + pinctrl-2 = <&usart6_sleep_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +&usb2_phy1 { + vdd33-supply = <&scmi_vdd3v3_usb>; + status = "okay"; +}; + +&usb2_phy2 { + vdd33-supply = <&scmi_vdd3v3_usb>; + status = "okay"; +}; + +&usbh { + status = "okay"; + + usbh_ehci: usb@482f0000 { + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&scmi_v3v3>; + }; + }; + + usbh_ohci: usb@482e0000 { + status = "disabled"; + }; +}; + +&usb3dr { + status = "okay"; + + dwc3: usb@48300000 { + phys = <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; + port { + dwc3_ep: endpoint { + remote-endpoint = <&typec_ep>; + }; + }; + }; +}; diff --git a/YOCTO/meta-mylayer/recipes-kernel/linux/files/fragment-06-minimal.config b/YOCTO/meta-mylayer/recipes-kernel/linux/files/fragment-06-minimal.config new file mode 100644 index 0000000..944b094 --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-kernel/linux/files/fragment-06-minimal.config @@ -0,0 +1,261 @@ +# CONFIG_HW_RANDOM is not set +# CONFIG_IPV6 is not set +# CONFIG_ARM_PMU is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +# CONFIG_BLK_DEBUG_FS is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=19 +CONFIG_COMMON_CLK_XGENE=y +CONFIG_CRC7=y +CONFIG_CRC8=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DMA_CMA=y +CONFIG_DNS_RESOLVER=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_EXT4_FS=y +CONFIG_FAILOVER=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_GENERIC_PHY=y +# CONFIG_HID_SUPPORT is not set +CONFIG_HOTPLUG_CPU=y +# CONFIG_HWMON is not set +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_STM32F7=y +CONFIG_I3C=y +CONFIG_INDIRECT_PIO=y +CONFIG_INET=y +# CONFIG_INET_DIAG is not set +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IRQ_POLL=y +CONFIG_KEYS=y +CONFIG_KPROBES=y +CONFIG_MAILBOX=y +CONFIG_MAILBOX_CDEV=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MMC_CQHCI=y +CONFIG_MODVERSIONS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NR_CPUS=2 +CONFIG_OF_OVERLAY=y +CONFIG_PACKING=y +CONFIG_PAGE_REPORTING=y +# CONFIG_PCPU_DEV_REFCNT is not set +# CONFIG_PINCTRL_STM32MP215 is not set +# CONFIG_PINCTRL_STM32MP235 is not set +# CONFIG_PINCTRL_STM32_HDP is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +CONFIG_PPS=y +CONFIG_REGULATOR=y +# CONFIG_RESET_SCMI is not set +CONFIG_SCMI_STM32MP_OSTL_V5=y +CONFIG_SCSI=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SECURITYFS=y +# CONFIG_SERIO is not set +CONFIG_SPI_MEM=y +CONFIG_STM=y +# CONFIG_STM32_DDR_PMU is not set +CONFIG_STM32_DMA3=y +CONFIG_STM32_IPCC=y +# CONFIG_STM32_RISAB is not set +# CONFIG_STM32_RISAF is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_SURFACE_PLATFORMS is not set +# CONFIG_SUSPEND is not set +CONFIG_SYNC_FILE=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_THERMAL=y +CONFIG_TMPFS=y +CONFIG_UNIX=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_VIRTIO_MENU is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_FW_LOADER=n +CONFIG_FW_LOADER_DEBUG=n +CONFIG_CDNS_I3C_MASTER=n +CONFIG_SENSORS_LIS3_SPI=n +CONFIG_I2C_ALGOPCF=n +CONFIG_I2C_ALGOPCA=n +CONFIG_DW_I3C_MASTER=n +CONFIG_STM32_I3C_MASTER=n +CONFIG_SVC_I3C_MASTER=n +CONFIG_MIPI_I3C_HCI=n +CONFIG_DEBUG_CGROUP_REF=n +CONFIG_FUNCTION_ERROR_INJECTION=n +CONFIG_TEST_DYNAMIC_DEBUG=n +CONFIG_PCIEASPM_POWERSAVE=n +CONFIG_NET_SCHED=n +CONFIG_BT=n +CONFIG_DRM=n +CONFIG_SPI=n +CONFIG_SPIDEV=n +CONFIG_SPI_MUX=n +CONFIG_SAMPLES=n +CONFIG_CORESIGHT=n +CONFIG_MTD_COMPLEX_MAPPINGS=n +CONFIG_V4L_TEST_DRIVERS=n +CONFIG_MTD_PHYSMAP=n +CONFIG_ABP060MG=n +# CONFIG_PM is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_VIRTUALIZATION is not set +CONFIG_NO_IOPORT_MAP=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NUMA is not set +# CONFIG_BINFMT_SCRIPT is not set +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_PNP is not set +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DNS_RESOLVER is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_QRTR_TUN is not set +# CONFIG_CAN is not set +# CONFIG_CFG80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_NFC is not set +# CONFIG_PCI is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_XEN_BLKDEV_FRONTEND is not set +# CONFIG_RAID_ATTRS is not set +# CONFIG_BLK_DEV_SD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_MATRIXKMAP is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_HVC_XEN is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_SPMI is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_THERMAL is not set +CONFIG_MFD_CORE=n +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_STM32_LPTIMER is not set +# CONFIG_MFD_VEXPRESS_SYSREG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# CONFIG_SOUND is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MTK is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_MV_XOR_V2 is not set +# CONFIG_PL330_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_SYNC_FILE is not set +# CONFIG_VFIO is not set +# CONFIG_XEN_BALLOON is not set +# CONFIG_XEN_DEV_EVTCHN is not set +# CONFIG_XEN_BACKEND is not set +# CONFIG_XENFS is not set +# CONFIG_XEN_SYS_HYPERVISOR is not set +# CONFIG_XEN_GNTDEV is not set +# CONFIG_XEN_GRANT_DEV_ALLOC is not set +# CONFIG_XEN_PRIVCMD is not set +# CONFIG_STAGING is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_HWSPINLOCK is not set +# CONFIG_REMOTEPROC is not set +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# CONFIG_SOUNDWIRE is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set +# CONFIG_NVMEM_RMEM is not set +# CONFIG_NVMEM_STM32_ROMEM is not set +# CONFIG_NVMEM_STM32_TAMP is not set +# CONFIG_STM is not set +# CONFIG_FPGA is not set +CONFIG_MULTIPLEXER=m +CONFIG_MUX_MMIO=m +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_HTE is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_BTRFS_FS is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set +# CONFIG_QRTR is not set +# CONFIG_WIRELESS is not set +# CONFIG_FAILOVER is not set +# CONFIG_PPS is not set +# CONFIG_MAILBOX is not set +# CONFIG_DEBUG_MISC is not set diff --git a/YOCTO/meta-mylayer/recipes-kernel/linux/linux-stm32mp_%.bbappend b/YOCTO/meta-mylayer/recipes-kernel/linux/linux-stm32mp_%.bbappend new file mode 100644 index 0000000..88475eb --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-kernel/linux/linux-stm32mp_%.bbappend @@ -0,0 +1,6 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +SRC_URI += "file://fragment-06-minimal.config;subdir=fragments" + +KERNEL_CONFIG_FRAGMENTS:append:stm32mp2common = " ${WORKDIR}/fragments/fragment-06-minimal.config" + diff --git a/YOCTO/meta-mylayer/recipes-st/images/myimage.bb b/YOCTO/meta-mylayer/recipes-st/images/myimage.bb new file mode 100644 index 0000000..189fb7c --- /dev/null +++ b/YOCTO/meta-mylayer/recipes-st/images/myimage.bb @@ -0,0 +1,15 @@ +SUMMARY = "My minimal image" +LICENSE = "MIT" + +include recipes-st/images/st-image.inc + +inherit core-image + +IMAGE_ROOTFS_MAXSIZE = "33554432" +IMAGE_FSTYPES += "${INITRAMFS_FSTYPES}" + +PACKAGE_INSTALL += " \ + kernel-imagebootfs \ +" +IMAGE_FEATURES = "" +CORE_IMAGE_EXTRA_INSTALL = "" diff --git a/make_mp25x_FIP.sh b/make_mp25x_FIP.sh new file mode 100755 index 0000000..821561b --- /dev/null +++ b/make_mp25x_FIP.sh @@ -0,0 +1,258 @@ +#!/bin/bash -e +# (-ex is verbose) +############################################################################################################## +############################################################################################################## +### ### +### Please customize the following VARIABLEs: ### +### SOC= ### +### CUSTOM_DTS_NAME= ### +### SOURCES_BASE_PATH= ### +### SDK_BUILD_ENV_BASE= ### +### ### +############################################################################################################## +############################################################################################################## + +############################################################################################################## +### ########## +### MANDATORY DEFINITIONs ########## +### ########## +############################################################################################################## + +SOC_BASE="stm32mp25" +SOC="${SOC_BASE}7f" + +########################################################################### +### DTS name (external dts, can be a custom name) ### +# CUSTOM_DTS_NAME="${SOC}-ev1" +## ST board DTS names +# CUSTOM_DTS_NAME="${SOC}-ev1" +# CUSTOM_DTS_NAME="${SOC}-dk" +## External DTS example name +# CUSTOM_DTS_NAME="${SOC}-ev1-ca35tdcid-ostl"" + +CUSTOM_DTS_NAME="${SOC}-dk" + +########################################################################### +# Build FIP and TF-A for this STORAGE_DEVICEs +# available STORAGE_DEVICEs = "emmc sdcard nor" +STORAGE_DEVICEs="emmc" + +########################################################################### +# OPTEE version: standard or min +# Available options: "optee" - "opteemin" +OPTEE_TYPE="opteemin" + +########################################################################### +# Programming channel +# Available options: "usb" - "uart" +PRG_BUS="usb" + +SOURCES_BASE_PATH="./" +SDK_BUILD_ENV_BASE="/opt/st/stm32mp2/5.0.3-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06" + +############################################################################################################## +### ########## +### OPTIONAL SETTINGs ########## +### ########## +############################################################################################################## + +BUILD_TFA="1" # Build tfa + FIP +BUILD_OPTEE="1" # Build optee + FIP +BUILD_UBOOT="1" # Build uboot + FIP + +DO_CLEAN="0" # Clean up the build folder & FIP_artifacts folder before build. +DO_CLEAN_DTB="0" # Clean up all DTBs before build. +DO_CLEAN_ALL="0" # Clean up FIP_artifacts folder. + +BUILD_HELPER_OUTPUT="1" # Copy final artifact in OUT folder and create tar.gz archive (under ./BUILD_OUTPUT) + +############################################################################################################## +### ########## +### SYSTEM ENVIRONMENT ########## +### ########## +############################################################################################################## + +SDK_BUILD_ENV_PATH="${SDK_BUILD_ENV_BASE}/environment-setup-cortexa35-ostl-linux" + +R0="-r0" +R1="-r1" +R2="-r2" +RC8="-rc8" + +optee_ver="4.0.0" +tfa_ver="v2.10.5" +ddr_ver="A2022.11" +uboot_ver="v2023.10" +devicetree_ver="6.0" + +TFA_VER="${tfa_ver}-stm32mp${R1}" +UBOOT_VER="${uboot_ver}-stm32mp${R1}" +OPTEE_VER="${optee_ver}-stm32mp${R1}" +DDR_VER="${ddr_ver}" +DEVICETREE_VER="${devicetree_ver}" + +TFA_DIR="tf-a-stm32mp-${TFA_VER}${R0}/tf-a-stm32mp-${TFA_VER}" +UBOOT_DIR="u-boot-stm32mp-${UBOOT_VER}${R0}/u-boot-stm32mp-${UBOOT_VER}" +OPTEE_DIR="optee-os-stm32mp-${OPTEE_VER}${R0}/optee-os-stm32mp-${OPTEE_VER}" +NUM_COREs=8 + +cd ${SOURCES_BASE_PATH} +CURDIR=`pwd` +EXTDT_DIR=${CURDIR}/external-dt-${DEVICETREE_VER}${R0}/external-dt-${DEVICETREE_VER} +FWDDR_DIR=${CURDIR}/stm32mp-ddr-phy-${DDR_VER}${R0}/stm32mp-ddr-phy-${DDR_VER} + +SDK_HELPER_OUTPUT="BUILD_OUTPUT" +SDK_HELPER_OUTPUT_FIP="${SDK_HELPER_OUTPUT}/fip" +SDK_HELPER_OUTPUT_TFA="${SDK_HELPER_OUTPUT}/tfa" + +FIP_DEPLOYDIR_ROOT="${CURDIR}/FIP_artifacts" + +# echo ${TFA_DIR} +# echo ${OPTEE_DIR} +# echo ${UBOOT_DIR} +# echo ${EXTDT_DIR} +# echo ${FWDDR_DIR} +# exit 0 + +############################################################################################################## +############################################################################################################## +### ########## +### START OF OPERATIONs ########## +### ########## +############################################################################################################## +############################################################################################################## + +if [[ "x${DO_CLEAN_ALL}" = "x1" ]]; then + DO_CLEAN="1" + rm -rf ${FIP_DEPLOYDIR_ROOT} +fi + +for storage in ${STORAGE_DEVICEs}; do + FIP_CONFIGs="${FIP_CONFIGs} ${OPTEE_TYPE}-${storage}" +done +FIP_CONFIGs="${FIP_CONFIGs} ${OPTEE_TYPE}-programmer-${PRG_BUS}" + +# Toolchain setup +source ${SDK_BUILD_ENV_PATH} +export EXTDT_DIR +export FWDDR_DIR + +function do_build_uboot() { + + export EXTDT_DIR + rm -rf ${FI25DEPLOYDIR_ROOT}/u-boot ${FIP_DEPLOYDIR_ROOT}/fip-${CUSTOM_DTS_NAME}-*.bin + mkdir -p ${FIP_DEPLOYDIR_ROOT}/u-boot + + cd ${UBOOT_DIR} + + [[ "x${DO_CLEAN}" = "x1" ]] && make -f ../Makefile.sdk UBOOT_DEFCONFIG=${SOC_BASE}_defconfig DEVICE_TREE=${CUSTOM_DTS_NAME} DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/u-boot clean + [[ "x${DO_CLEAN_DTB}" = "x1" ]] && rm -f ../build/stm32mp25_defconfig/arch/arm/dts/.stm32mp2* ../build/${SOC_BASE}_defconfig/arch/arm/dts/*dtb + [[ "x${DO_NOT_BUILD}" = "x1" ]] && cd - && return 0 + + make -f ../Makefile.sdk UBOOT_CONFIG=${SOC_BASE}_defconfig UBOOT_DEFCONFIG=${SOC_BASE}_defconfig DEVICE_TREE=${CUSTOM_DTS_NAME} DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/u-boot uboot + + cd - +} + +function do_build_optee() { + + export EXTDT_DIR + rm -rf ${FIP_DEPLOYDIR_ROOT}/optee ${FIP_DEPLOYDIR_ROOT}/fip-${CUSTOM_DTS_NAME}-*.bin + mkdir -p ${FIP_DEPLOYDIR_ROOT}/optee + + OPTEE_EXTRA_OEMAKE_OPTs="-j${NUM_COREs} PLATFORM=stm32mp2 CROSS_COMPILE_core=aarch64-ostl-linux- CROSS_COMPILE_ta_arm64=aarch64-ostl-linux- \ + ARCH=arm CFG_ARM64_core=y NOWERROR=1 LDFLAGS= CFG_EXT_DTS=${EXTDT_DIR}/optee \ + CFG_TEE_CORE_LOG_LEVEL=2 CFG_TEE_CORE_DEBUG=y CFG_SCMI_SCPFW=y" + + cd ${OPTEE_DIR} + + [[ "x${DO_CLEAN}" = "x1" ]] && make -f ../Makefile.sdk CFG_EMBED_DTB_SOURCE_FILE=${CUSTOM_DTS_NAME} DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/optee clean + [[ "x${DO_CLEAN_DTB}" = "x1" ]] && rm -f ../build/${CUSTOM_DTS_NAME}/core/arch/arm/dts/.stm32mp2* out/arm-plat-stm32mp2/core/arch/arm/dts/stm32mp2* + [[ "x${DO_NOT_BUILD}" = "x1" ]] && cd - && return 0 + + make -f ../Makefile.sdk CFG_EMBED_DTB_SOURCE_FILE=${CUSTOM_DTS_NAME} DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/optee EXTRA_OEMAKE="${OPTEE_EXTRA_OEMAKE_OPTs}" optee + + cd - +} + +function do_build_tfa() { + + export EXTDT_DIR + export FWDDR_DIR + rm -rf ${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware ${FIP_DEPLOYDIR_ROOT}/fip-${CUSTOM_DTS_NAME}-*.bin + + cd ${TFA_DIR} + + TFA_COMMON_OPTs="ELF_DEBUG_ENABLE=1 DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware" + TFA_EXTRA_OEMAKE_OPTs="-j${NUM_COREs} PLAT=stm32mp2 ARCH=aarch64 ARM_ARCH_MAJOR=8 CROSS_COMPILE=aarch64-ostl-linux- \ + DEBUG=0 LOG_LEVEL=40" + + for tfa_target in ${FIP_CONFIGs}; do + + TFA_SPECIFIC_OPTs="TF_A_CONFIG=${tfa_target} TF_A_DEVICETREE=${CUSTOM_DTS_NAME} TF_A_ENABLE_FWDDR=1" + + [[ "x${DO_CLEAN}" = "x1" ]] && make -f ../Makefile.sdk ${TFA_SPECIFIC_OPTs} clean + [[ "x${DO_CLEAN_DTB}" = "x1" ]] && rm -fr ../build/${tfa_target}${CUSTOM_DTS_NAME}/fdts + + # Build stm32 binary (foreach TF_A_CONFIG) + make -f ../Makefile.sdk ${TFA_COMMON_OPTs} ${TFA_SPECIFIC_OPTs} EXTRA_OEMAKE="${TFA_EXTRA_OEMAKE_OPTs}" stm32 + done + + make -f ../Makefile.sdk metadata DEPLOYDIR=${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware + + cd - +} + + +function do_build_fip() { + + export EXTDT_DIR + export FWDDR_DIR + cd ${UBOOT_DIR} + + make -f ../Makefile.sdk FIP_DEPLOYDIR_ROOT=${FIP_DEPLOYDIR_ROOT} UBOOT_CONFIG=${SOC_BASE}_defconfig \ + UBOOT_DEFCONFIG=${SOC_BASE}_defconfig DEVICE_TREE=${CUSTOM_DTS_NAME} \ + FIP_CONFIG=${OPTEE_TYPE}-programmer-${PRG_BUS} fip + for storage in ${STORAGE_DEVICEs}; do + device="${OPTEE_TYPE}-${storage}" + make -f ../Makefile.sdk FIP_DEPLOYDIR_ROOT=${FIP_DEPLOYDIR_ROOT} UBOOT_CONFIG=${SOC_BASE}_defconfig \ + UBOOT_DEFCONFIG=${SOC_BASE}_defconfig DEVICE_TREE=${CUSTOM_DTS_NAME} \ + FIP_CONFIG=${device} fip + done + + cd - +} + +[[ "x${BUILD_UBOOT}" = "x1" ]] && do_build_uboot +[[ "x${BUILD_OPTEE}" = "x1" ]] && do_build_optee +[[ "x${BUILD_TFA}" = "x1" ]] && do_build_tfa +do_build_fip # Assemble FIP file + +echo; echo; echo + +[[ "x${BUILD_HELPER_OUTPUT}" != "x1" ]] && exit 0 + +mkdir -p ${SDK_HELPER_OUTPUT_FIP} +mkdir -p ${SDK_HELPER_OUTPUT_TFA} + +cp -v ${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware/metadata.bin ${SDK_HELPER_OUTPUT_TFA}/metadata.bin + +for storage in ${STORAGE_DEVICEs}; do + + cp -v ${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware/tf-a-${CUSTOM_DTS_NAME}-${OPTEE_TYPE}-${storage}.stm32 ${SDK_HELPER_OUTPUT_TFA}/tfa_${storage}.stm32 + cp -v ${FIP_DEPLOYDIR_ROOT}/fip/fip-${CUSTOM_DTS_NAME}-ddr-${OPTEE_TYPE}-${storage}.bin ${SDK_HELPER_OUTPUT_FIP}/fip-ddr.bin + cp -v ${FIP_DEPLOYDIR_ROOT}/fip/fip-${CUSTOM_DTS_NAME}-${OPTEE_TYPE}-${storage}.bin ${SDK_HELPER_OUTPUT_FIP}/fip.bin +done +cp -v ${FIP_DEPLOYDIR_ROOT}/arm-trusted-firmware/tf-a-${CUSTOM_DTS_NAME}-${OPTEE_TYPE}-programmer-${PRG_BUS}.stm32 ${SDK_HELPER_OUTPUT_TFA}/tfa_${PRG_BUS}.stm32 + +cp -rv STM32MPU_SDK_helper/FLASH_LAYOUT ${SDK_HELPER_OUTPUT}/ +mv ${SDK_HELPER_OUTPUT}/FLASH_LAYOUT/flash.sh ${SDK_HELPER_OUTPUT}/ +mv ${SDK_HELPER_OUTPUT}/FLASH_LAYOUT/flash.bat ${SDK_HELPER_OUTPUT}/ + + +tar czf /tmp/${CUSTOM_DTS_NAME}_binaries.tar.gz ${SDK_HELPER_OUTPUT} +echo; echo +ls -lh /tmp/${CUSTOM_DTS_NAME}_binaries.tar.gz + +echo; echo; echo +exit 0 diff --git a/make_mp25x_KERNEL.sh b/make_mp25x_KERNEL.sh new file mode 100755 index 0000000..79548ea --- /dev/null +++ b/make_mp25x_KERNEL.sh @@ -0,0 +1,67 @@ +#!/bin/bash -e + +export PATH=/usr/local/bin:/usr/bin:/bin:/usr/local/games:/usr/games +export ARCH=arm64 +SDK_BUILD_ENV_PATH="/opt/st/stm32mp2/5.0.3-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06/environment-setup-cortexa35-ostl-linux" +source ${SDK_BUILD_ENV_PATH} + +SOC_BASE="stm32mp25" +SOC="${SOC_BASE}7f" +# CUSTOM_DTS_NAME="${SOC}-ev1" +CUSTOM_DTS_NAME="${SOC}-dk" + +MINIMAL_DEFCONFIG="0" + +R0="-r0" +R1="-r1" + +linux_ver="6.6.48" +devicetree_ver="6.0" + +EXTDT_DIR=${PWD}/external-dt-${devicetree_ver}${R0}/external-dt-${devicetree_ver} +LINUX_DIR="linux-stm32mp-${linux_ver}-stm32mp${R1}${R0}" +SDK_HELPER_OUT_KERNEL="BUILD_OUTPUT/kernel/" +mkdir -p ${SDK_HELPER_OUT_KERNEL} + +# echo ${EXTDT_DIR} +# echo ${LINUX_DIR} +# exit 0 + +FRAGMENT_LIST="fragment-03-systemd.config \ + fragment-04-modules.config" + +cd ${LINUX_DIR}/linux-${linux_ver} + +export K_BUILD_DIR="../build/" +mkdir -p ${K_BUILD_DIR} + + +if [ "x${MINIMAL_DEFCONFIG}" = "x0" ]; then + make O=${K_BUILD_DIR} defconfig fragment*.config + for frag in ${FRAGMENT_LIST}; do + ./scripts/kconfig/merge_config.sh -m -r -O ${K_BUILD_DIR} ${K_BUILD_DIR}/.config ../${frag} + done +else + make O=${K_BUILD_DIR} defconfig + ./scripts/kconfig/merge_config.sh -m -r -O ${K_BUILD_DIR} ${K_BUILD_DIR}/.config ../../STM32MPU_SDK_helper/KERNEL/fragment_minimal.config +fi + +# ./scripts/diffconfig -m ${K_BUILD_DIR}defconfig ../../STM32MPU_SDK_helper/KERNEL/minimal_defconfig > ../../STM32MPU_SDK_helper/KERNEL/fragment_minimal.config +# exit 0 + +# cp ../../STM32MPU_SDK_helper/KERNEL/minimal_defconfig arch/arm64/configs/stm32mp2_minimal_defconfig +# make O=${K_BUILD_DIR} stm32mp2_minimal_defconfig + +# make O=${K_BUILD_DIR} menuconfig +# make O=${K_BUILD_DIR} savedefconfig +# cp -v ${K_BUILD_DIR}/defconfig ${K_BUILD_DIR}/defconfig_`date +%Y%m%d%H%M` +# exit 0 + +make O=${K_BUILD_DIR} KBUILD_EXTDTS="${EXTDT_DIR}/linux" st/${CUSTOM_DTS_NAME}.dtb +make O=${K_BUILD_DIR} -j8 Image.gz +make O=${K_BUILD_DIR} -j8 modules +make O=${K_BUILD_DIR} INSTALL_MOD_PATH="../../${SDK_HELPER_OUT_KERNEL}" modules_install + +cp -v ${K_BUILD_DIR}arch/arm64/boot/Image.gz ../../${SDK_HELPER_OUT_KERNEL} +cp -v ${K_BUILD_DIR}arch/arm64/boot/dts/st/${CUSTOM_DTS_NAME}.dtb ../../${SDK_HELPER_OUT_KERNEL} +rm ../../${SDK_HELPER_OUT_KERNEL}/lib/modules/6.6.48/build diff --git a/pdf_slides/USE_DEV_HELPER_TO_BUILD_SDK_OSTL.pdf b/pdf_slides/USE_DEV_HELPER_TO_BUILD_SDK_OSTL.pdf new file mode 100755 index 0000000..6e5d4fa Binary files /dev/null and b/pdf_slides/USE_DEV_HELPER_TO_BUILD_SDK_OSTL.pdf differ diff --git a/unpack.sh b/unpack.sh new file mode 100755 index 0000000..f518526 --- /dev/null +++ b/unpack.sh @@ -0,0 +1,65 @@ +#!/bin/bash -e + + +gcnano_ver="6.4.19" +linux_ver="6.6.48" +optee_ver="4.0.0" +tfa_ver="v2.10.5" +ddr_ver="A2022.11" +uboot_ver="v2023.10" +devicetree_ver="6.0" + +R0="-r0" +R1="-r1" +R2="-r2" +RC8="-rc8" + +devicetree_dir="external-dt-${devicetree_ver}" +gcnano_dir="gcnano-driver-stm32mp-${gcnano_ver}-stm32mp2${R1}${RC8}" +linux_dir="linux-stm32mp-${linux_ver}-stm32mp${R1}" +optee_dir="optee-os-stm32mp-${optee_ver}-stm32mp${R1}" +tfa_dir="tf-a-stm32mp-${tfa_ver}-stm32mp${R1}" +uboot_dir="u-boot-stm32mp-${uboot_ver}-stm32mp${R1}" +ddr_dir="stm32mp-ddr-phy-${ddr_ver}" + +DO_CLEAN="1" +TRACK_ON_GIT="0" + +dry_run="" +# dry_run="--dry-run" + +if [ "x${DO_CLEAN}" == "x1" ]; then + rm -rf "${tfa_dir}${R0}/${tfa_dir}" + rm -rf "${optee_dir}${R0}/${optee_dir}" + rm -rf "${uboot_dir}${R0}/${uboot_dir}" + rm -rf "${linux_dir}${R0}/linux-${linux_ver}" +fi + +folders_list="${devicetree_dir} ${gcnano_dir} ${linux_dir} ${optee_dir} ${tfa_dir} ${uboot_dir} ${ddr_dir}" + +for folder in ${folders_list}; do + cd ${folder}${R0} + echo "Processing folder: ${folder}" + echo -n " Unpacking ..." + archivename=${folder}${R0} + + [[ "x${archivename}" == "x${linux_dir}${R0}" ]] && archivename="linux-${linux_ver}" + tar xJf ${archivename}.tar.xz + + [[ "x${archivename}" == "x${tfa_dir}${R0}" ]] && archivename=${folder} + [[ "x${archivename}" == "x${optee_dir}${R0}" ]] && archivename=${folder} + [[ "x${archivename}" == "x${uboot_dir}${R0}" ]] && archivename=${folder} + + echo -n " Patching ..." + if [ `ls *patch 2>/dev/null | wc -l` -gt 0 ]; then + cd ${archivename} + if [ "x${TRACK_ON_GIT}" = "x1" ]; then + test -d .git || git init . && git add . && git commit -m "${archivename} source code" && git checkout -b WORKING + fi + for patch in `ls ../*.patch`; do patch -p1 ${dry_run} < ${patch} >/dev/null 2>&1; echo -n "."; done + [[ "x${archivename}" == "x${optee_dir}" ]] && tar xzf ../fonts.tar.gz + cd .. + fi + echo -e " Done. \t--> Operation completed successfully." + cd .. +done