fpga workflow isn't important, I guess

SystemVerilog and moving to logic

moving to always_ff

run fpga workflow on each push

added harden.log to .gitignore

remove dead code, formatting and new comment

more SystemVerilog changes and style change for clk

beginning the full shift to SystemVerilog: change fpga Makefile, use …

use gclk only for formal tests, add it to the bmc options

add nettypes, remove been_reset, add better comment

formal method to ensure we can leave the TAP FSM

Merge branch 'main' of github.com:stevej/tt09-jtag-example-v2-stevej

Update README.md

add debug bits to see how far we're getting in the TAP state machine …

tell yosys that clk is the global clock

write to TDO on the negative edge. This adds a half-cycle delay to av…

TRST being high too early breaks GL simulation

explicit widths, switch to one-hot encoding for the TAP state machine

start with TRST and TCK high then low

fix a fencepost error by setting byte_transmitter_enable high a clock…

remove mux for simplicity, shuffle some bits around

fixing current_state to be the right number of bits, fixing an assert…

tighten up formal tests

stripping minipit down to basics

moving some signals into continuous assignment for clarity

test for bare minipit, more assertions, enable wire

make interrupt fire on 10 rather than 11, other fixes

fix linter issue

hacking on gate-level tests, trying to find an X

more X hunting