From b5ab962779fa5c734c9ca1bd18972dd3c4daf93d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 26 Mar 2024 10:15:30 -0700 Subject: [PATCH 1/5] bug fix for determining the Link status speed/width & Link Cap speed/width --- python/surf/xilinx/_AxiPciePhy.py | 139 +++++++++++++++--------------- 1 file changed, 69 insertions(+), 70 deletions(-) diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index 4cd76480ff..0eb8ffac98 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -202,86 +202,85 @@ def __init__( mode = 'RO', )) - self.add(pr.RemoteVariable( - name = 'Gen2Capable', - description = 'If set, underlying integrated block supports PCIe Gen2 speed.', - offset = 0x130, - bitSize = 1, + self.addRemoteVariables( + name = "DevSpecRegion", + description = "The memory range from offset 0x40 to 0xFF in the PCI configuration header is referred to as the 'Device Specific Region'. This area is reserved for use by the device vendor and can contain any vendor-specific configuration or control registers.", + offset = 0x40, + bitSize = 8, bitOffset = 0, - mode = 'RO', - hidden = True, - )) + base = pr.UInt, + mode = "RO", + number = 192, + stride = 1, + hidden = True, + ) - self.add(pr.RemoteVariable( - name = 'Gen3Capable', - description = 'If set, underlying integrated block supports PCIe Gen3 speed.', - offset = 0x130, - bitSize = 1, - bitOffset = 3, + self.add(pr.LinkVariable( + name = 'LinkStatus', mode = 'RO', - hidden = True, + linkedGet = self.updateLinkStatus, + dependencies = [self.CapabilitiesPointer], + hidden = True, )) - self.add(pr.RemoteVariable( - name = 'RootPortPresent', - description = 'Indicates the underlying integrated block is a Root Port when this bit is set. If set, Root Port registers are present in this interface.', - offset = 0x130, - bitSize = 1, - bitOffset = 1, - mode = 'RO', - )) + speedEnum = { + 0: 'UNDEFINED', + 1: '2.5', + 2: '5', + 3: '8', + 4: '16', + 5: '32', + 6: '64', + 7: '128', + } - self.add(pr.RemoteVariable( - name = 'UpConfigCapable', - description = 'Indicates the underlying integrated block is upconfig capable when this bit is set.', - offset = 0x130, - bitSize = 1, - bitOffset = 2, - mode = 'RO', + self.add(pr.LocalVariable( + name = 'LnkStaSpeed', + mode = 'RO', + value = 0, + units = 'GT/s', + enum = speedEnum )) - self.add(pr.RemoteVariable( - name = 'LnkStaSpeed', - offset = 0x70 + 0x12, - bitSize = 4, - bitOffset = 0, - mode = 'RO', - units = 'GT/s', - enum = { - 0: 'UNDEFINED', - 1: '2.5', - 2: '5', - 3: '8', - 4: '16', - 5: '32', - 6: '64', - } + self.add(pr.LocalVariable( + name = 'LnkStaWidth', + mode = 'RO', + value = 0, + units = 'lanes', + disp = '{:d}', )) - self.add(pr.RemoteVariable( - name = 'LnkStaWidth', - offset = 0x70 + 0x12, - bitSize = 8, - bitOffset = 4, - mode = 'RO', - units = 'lanes', - disp = '{:d}', + self.add(pr.LocalVariable( + name = 'LnkCapSpeed', + mode = 'RO', + value = 0, + units = 'GT/s', + enum = speedEnum )) - self.add(pr.RemoteVariable( - name = 'LnkCapSpeed', - offset = 0x70 + 0x30, - bitSize = 4, - bitOffset = 0, - mode = 'RO', - units = 'GT/s', - enum = { - 0: 'UNDEFINED', - 1: '2.5', - 2: '5', - 3: '8', - 4: '16', - 5: '32', - 6: '64', - } + self.add(pr.LocalVariable( + name = 'LnkCapWidth', + mode = 'RO', + value = 0, + units = 'lanes', + disp = '{:d}', )) + + def updateLinkStatus(self): + # Check if value points to the Device Specific Region + if (self.CapabilitiesPointer.value() >= 0x40): + + # Go to the Capabilities Pointer offset and get the Capabilities Express Endpoint offset + offset = self.DevSpecRegion[self.CapabilitiesPointer.value()-0x40+1].get() + + # Capabilities Express Endpoint offset + linkStatus = self.DevSpecRegion[offset-0x40+ 0x12].get() + linkCap = self.DevSpecRegion[offset-0x40+ 0x0C].get() + + # Set the link speed and width status + self.LnkStaSpeed.set( (linkStatus>>0) & 0xF ) + self.LnkStaWidth.set( (linkStatus>>4) & 0xF ) + + # Set the link speed and width status + self.LnkCapSpeed.set( (linkCap>>0) & 0xF ) + self.LnkCapWidth.set( (linkCap>>4) & 0xF ) From 52a0e87491aacc25d69af8407de2be71fd970a8c Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 26 Mar 2024 10:16:27 -0700 Subject: [PATCH 2/5] code clean up --- python/surf/xilinx/_AxiPciePhy.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index 0eb8ffac98..edd230f0c0 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -271,11 +271,11 @@ def updateLinkStatus(self): if (self.CapabilitiesPointer.value() >= 0x40): # Go to the Capabilities Pointer offset and get the Capabilities Express Endpoint offset - offset = self.DevSpecRegion[self.CapabilitiesPointer.value()-0x40+1].get() + offset = self.DevSpecRegion[(self.CapabilitiesPointer.value()-0x40) + 1].get() # Capabilities Express Endpoint offset - linkStatus = self.DevSpecRegion[offset-0x40+ 0x12].get() - linkCap = self.DevSpecRegion[offset-0x40+ 0x0C].get() + linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() + linkCap = self.DevSpecRegion[(offset-0x40) + 0x0C].get() # Set the link speed and width status self.LnkStaSpeed.set( (linkStatus>>0) & 0xF ) From 09d268920e6b4d41627fffd34a48017951ef08ac Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 26 Mar 2024 11:02:45 -0700 Subject: [PATCH 3/5] bug fix for >8 lanes --- python/surf/xilinx/_AxiPciePhy.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index edd230f0c0..f331169d56 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -274,13 +274,13 @@ def updateLinkStatus(self): offset = self.DevSpecRegion[(self.CapabilitiesPointer.value()-0x40) + 1].get() # Capabilities Express Endpoint offset - linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() - linkCap = self.DevSpecRegion[(offset-0x40) + 0x0C].get() + linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() | (self.DevSpecRegion[(offset-0x40) + 0x13].get() << 8) + linkCap = self.DevSpecRegion[(offset-0x40) + 0x0C].get() | (self.DevSpecRegion[(offset-0x40) + 0x0D].get() << 8) # Set the link speed and width status self.LnkStaSpeed.set( (linkStatus>>0) & 0xF ) - self.LnkStaWidth.set( (linkStatus>>4) & 0xF ) + self.LnkStaWidth.set( (linkStatus>>4) & 0xFF ) # Set the link speed and width status self.LnkCapSpeed.set( (linkCap>>0) & 0xF ) - self.LnkCapWidth.set( (linkCap>>4) & 0xF ) + self.LnkCapWidth.set( (linkCap>>4) & 0xFF ) From 8db6a88b999c0b8e7a9de162edaa199696b3e382 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 26 Mar 2024 11:06:07 -0700 Subject: [PATCH 4/5] hiding 'advance debugging' registers in the GUI --- python/surf/xilinx/_AxiPciePhy.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index f331169d56..80893dbcd6 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -47,6 +47,7 @@ def __init__( bitSize = 16, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -55,6 +56,7 @@ def __init__( bitSize = 16, bitOffset = 16, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -63,6 +65,7 @@ def __init__( bitSize = 8, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -71,6 +74,7 @@ def __init__( bitSize = 8, bitOffset = 8, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -79,6 +83,7 @@ def __init__( bitSize = 8, bitOffset = 16, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -87,6 +92,7 @@ def __init__( bitSize = 8, bitOffset = 24, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -95,6 +101,7 @@ def __init__( bitSize = 8, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -103,6 +110,7 @@ def __init__( bitSize = 8, bitOffset = 8, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -111,6 +119,7 @@ def __init__( bitSize = 8, bitOffset = 16, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -119,6 +128,7 @@ def __init__( bitSize = 8, bitOffset = 24, mode = 'RO', + hidden = True, )) for i in range(6): @@ -128,6 +138,7 @@ def __init__( bitSize = 32, bitOffset = 0, mode = 'RO', + hidden = (i!=0), )) self.add(pr.RemoteVariable( @@ -136,6 +147,7 @@ def __init__( bitSize = 32, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -160,6 +172,7 @@ def __init__( bitSize = 32, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -168,6 +181,7 @@ def __init__( bitSize = 8, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -176,6 +190,7 @@ def __init__( bitSize = 8, bitOffset = 0, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -184,6 +199,7 @@ def __init__( bitSize = 8, bitOffset = 8, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -192,6 +208,7 @@ def __init__( bitSize = 8, bitOffset = 16, mode = 'RO', + hidden = True, )) self.add(pr.RemoteVariable( @@ -200,6 +217,7 @@ def __init__( bitSize = 8, bitOffset = 24, mode = 'RO', + hidden = True, )) self.addRemoteVariables( From b2de7c86c3ad5a38c928d02cb5d0e7552db7a581 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 26 Mar 2024 12:03:36 -0700 Subject: [PATCH 5/5] swap the order of displaying LnkCap/LnkStat --- python/surf/xilinx/_AxiPciePhy.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index 80893dbcd6..11a56cb75a 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -253,7 +253,7 @@ def __init__( } self.add(pr.LocalVariable( - name = 'LnkStaSpeed', + name = 'LnkCapSpeed', mode = 'RO', value = 0, units = 'GT/s', @@ -261,7 +261,7 @@ def __init__( )) self.add(pr.LocalVariable( - name = 'LnkStaWidth', + name = 'LnkCapWidth', mode = 'RO', value = 0, units = 'lanes', @@ -269,7 +269,7 @@ def __init__( )) self.add(pr.LocalVariable( - name = 'LnkCapSpeed', + name = 'LnkStaSpeed', mode = 'RO', value = 0, units = 'GT/s', @@ -277,7 +277,7 @@ def __init__( )) self.add(pr.LocalVariable( - name = 'LnkCapWidth', + name = 'LnkStaWidth', mode = 'RO', value = 0, units = 'lanes', @@ -292,13 +292,13 @@ def updateLinkStatus(self): offset = self.DevSpecRegion[(self.CapabilitiesPointer.value()-0x40) + 1].get() # Capabilities Express Endpoint offset - linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() | (self.DevSpecRegion[(offset-0x40) + 0x13].get() << 8) linkCap = self.DevSpecRegion[(offset-0x40) + 0x0C].get() | (self.DevSpecRegion[(offset-0x40) + 0x0D].get() << 8) + linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() | (self.DevSpecRegion[(offset-0x40) + 0x13].get() << 8) + + # Set the link speed and width capabilities + self.LnkCapSpeed.set( (linkCap>>0) & 0xF ) + self.LnkCapWidth.set( (linkCap>>4) & 0xFF ) # Set the link speed and width status self.LnkStaSpeed.set( (linkStatus>>0) & 0xF ) self.LnkStaWidth.set( (linkStatus>>4) & 0xFF ) - - # Set the link speed and width status - self.LnkCapSpeed.set( (linkCap>>0) & 0xF ) - self.LnkCapWidth.set( (linkCap>>4) & 0xFF )