From e5286e2ccc712bebff6df50f97aa31891b13c21d Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 Mar 2024 13:50:32 -0800 Subject: [PATCH 01/22] Add recclkout to GTY cores --- .../coregen/TimingGty_extref.dcp | 4 +- .../coregen/TimingGty_extref.xci | 2356 +++++++--------- .../coregen/TimingGty_fixedlat.dcp | 4 +- .../coregen/TimingGty_fixedlat.xci | 2370 +++++++---------- .../rtl/TimingGtCoreWrapper.vhd | 20 +- LCLS-II/gtyUltraScale+/ruckus.tcl | 16 +- 6 files changed, 1872 insertions(+), 2898 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 9395115a..7c1250d4 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d29ee6efbb592706d37472577558c070b0834470dff19636c3bd63bd04306bc0 -size 470774 +oid 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"resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_BUFFER_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_DATA_ENCODING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_LINE_RATE": [ { "value": "3.7142857", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_MASTER_CHANNEL_IDX": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_OUTCLK_FREQUENCY": [ { "value": "371.4285700", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_OUTCLK_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_REFCLK_FREQUENCY": [ { "value": "371.42857", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "virtexuplus" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xcvu9p" } ], + "PACKAGE": [ { "value": "flgc2104" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-1" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "16" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../S30xlAPx_project.gen/sources_1/ip/TimingGty_fixedlat" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userclk_tx_active_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userclk_rx_active_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_clk_freerun_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_all_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_cdr_stable_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "cpllrefclksel_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], + "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drpen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpwe_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtrefclk0_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtyrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtyrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "loopback_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "rx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcommadeten_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxmcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "tx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "txinhibit_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdo_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drprdy_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtytxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtytxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyteisaligned_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyterealign_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcommadet_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxctrl0_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl1_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl2_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxctrl3_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxdlysresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 49ba0841..a6563870 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -45,8 +45,8 @@ entity TimingGtCoreWrapper is axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 - stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 + stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 + stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 -- GTY FPGA IO gtRefClk : in sl; gtRefClkDiv2 : in sl; -- Unused in GTYE3, but used in GTYE4 @@ -74,8 +74,8 @@ entity TimingGtCoreWrapper is -- Tx Ports txControl : in TimingPhyControlType; txStatus : out TimingPhyStatusType; - txUsrClk : in sl := '0'; - txUsrClkActive : in sl := '0'; + txUsrClk : in sl := '0'; + txUsrClkActive : in sl := '0'; txData : in slv(15 downto 0) := (others => '0'); txDataK : in slv(1 downto 0) := (others => '0'); txOutClk : out sl; @@ -155,7 +155,8 @@ architecture rtl of TimingGtCoreWrapper is rxsyncdone_out : out std_logic_vector(0 downto 0); txoutclk_out : out std_logic_vector(0 downto 0); txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0) + txresetdone_out : out std_logic_vector(0 downto 0); + rxrecclkout_out : out std_logic_vector(0 downto 0) ); end component; component TimingGty_extref @@ -226,7 +227,8 @@ architecture rtl of TimingGtCoreWrapper is rxsyncdone_out : out std_logic_vector(0 downto 0); txoutclk_out : out std_logic_vector(0 downto 0); txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0) + txresetdone_out : out std_logic_vector(0 downto 0); + rxrecclkout_out : out std_logic_vector(0 downto 0) ); end component; @@ -450,7 +452,8 @@ begin rxoutclk_out(0) => rxoutclk_out, rxpmaresetdone_out => open, txoutclk_out(0) => txoutclk_out, - txpmaresetdone_out => open); + txpmaresetdone_out => open, + rxrecclkout_out(0) => rxrecclk_out); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); @@ -544,7 +547,8 @@ begin rxoutclk_out(0) => rxoutclk_out, rxpmaresetdone_out => open, txoutclk_out(0) => txoutclk_out, - txpmaresetdone_out => open); + txpmaresetdone_out => open, + rxrecclkout_out(0) => rxrecclk_out); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index 1db36abc..68b0d914 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,19 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" + # loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadIpCore -path "${path}/TimingGty_extref.xci" - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" + # loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" + # loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadIpCore -path "${path}/TimingGty_extref.xci" - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" + # loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" From 57755a6ee2232049270bd0e4b005d5497483d989 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 Mar 2024 13:57:33 -0800 Subject: [PATCH 02/22] Update freerun frequencies to match GTH --- LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp | 4 ++-- LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci | 4 ++-- LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp | 4 ++-- LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 7c1250d4..09ae2336 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7e918a2aff904439e9f6800e2d04cda587e6f5375411b6d3f46d3f7cc28e962f -size 309595 +oid sha256:421afa693a98e84138f677602e2bc4b70b58258afa75ce1d2d3f5fcb661f946a +size 309085 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index bfc42030..e875ce05 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "185.714285", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp index 177f3012..99c573d9 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3072e08566279c3c20a35cb27565fb71b9c7218a4c4b1e7624acddf55fb30a1b -size 310581 +oid sha256:fd2de19c0f89548d2067570f11b514c27177ee9c010c6fa690691c682c05d260 +size 311419 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci index 1c2c2781..70e59226 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], From 68f47b2c3dab4d69134569bcf8fc044bbd0f121e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 4 Mar 2024 15:42:18 -0800 Subject: [PATCH 03/22] Fix signal names --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index a6563870..75aad213 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -70,6 +70,7 @@ entity TimingGtCoreWrapper is rxDispErr : out slv(1 downto 0); rxDecErr : out slv(1 downto 0); rxOutClk : out sl; + rxRecClk : out sl; -- Tx Ports txControl : in TimingPhyControlType; @@ -453,7 +454,7 @@ begin rxpmaresetdone_out => open, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, - rxrecclkout_out(0) => rxrecclk_out); + rxrecclkout_out(0) => rxRecClk); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); @@ -548,7 +549,7 @@ begin rxpmaresetdone_out => open, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, - rxrecclkout_out(0) => rxrecclk_out); + rxrecclkout_out(0) => rxRecClk); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); From 52f7ddc2ca65ae30c1d364c890478d27bfa7458e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 4 Mar 2024 15:42:29 -0800 Subject: [PATCH 04/22] Change back to DCP --- LCLS-II/gtyUltraScale+/ruckus.tcl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index 68b0d914..1db36abc 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,19 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - # loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - loadIpCore -path "${path}/TimingGty_extref.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + # loadIpCore -path "${path}/TimingGty_extref.xci" - # loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - loadIpCore -path "${path}/TimingGty_fixedlat.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + # loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - # loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - loadIpCore -path "${path}/TimingGty_extref.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + # loadIpCore -path "${path}/TimingGty_extref.xci" - # loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - loadIpCore -path "${path}/TimingGty_fixedlat.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + # loadIpCore -path "${path}/TimingGty_fixedlat.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" From 0d5b38aa6650ec9884be93086ad860ffa62b1411 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 6 Mar 2024 11:11:17 -0800 Subject: [PATCH 05/22] Fix compile errors --- LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd | 4 +--- LCLS-II/evr/rtl/EvrV2Module.vhd | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd b/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd index eb0bd2ed..310b522f 100644 --- a/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd +++ b/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd @@ -342,9 +342,7 @@ begin -- rtl Out_Trigger: for i in 0 to TriggerOutputs-1 generate U_Trig : entity lcls_timing_core.EvrV2Trigger generic map ( TPD_G => TPD_G, - CHANNELS_C => ReadoutChannels, - --DEBUG_C => (i<1) ) - DEBUG_C => false ) + CHANNELS_C => ReadoutChannels) port map ( clk => evrClk, rst => evrRst, config => triggerConfigS(i), diff --git a/LCLS-II/evr/rtl/EvrV2Module.vhd b/LCLS-II/evr/rtl/EvrV2Module.vhd index 82c570ce..a485319c 100644 --- a/LCLS-II/evr/rtl/EvrV2Module.vhd +++ b/LCLS-II/evr/rtl/EvrV2Module.vhd @@ -177,8 +177,7 @@ begin -- rtl U_Trig : entity lcls_timing_core.EvrV2Trigger generic map ( TPD_G => TPD_G, CHANNELS_C => NCHANNELS_G, - TRIG_DEPTH_C => TRIG_DEPTH_G, - DEBUG_C => false ) + TRIG_DEPTH_C => TRIG_DEPTH_G) port map ( clk => evrClk, rst => evrRst, config => triggerConfig(i), From b6ac1562035539c92f4a1b5e6b1413e1bfd308f2 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 26 Mar 2024 14:21:56 -0700 Subject: [PATCH 06/22] Use rxUsrClk to aligner rxUsrClk might have MMCM --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 75aad213..824672bc 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -308,7 +308,7 @@ begin port map ( -- Clock Monitoring txClk => txoutclkb, - rxClk => rxoutclkb, + rxClk => rxUsrClk, -- Should maybe be rxUsrClk -- GTH Status/Control Interface resetIn => rxControl.reset, resetDone => bypassdone, From 17947e64f53dd1698301d5512a421483d4c38c48 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 19 Jun 2024 12:26:19 -0700 Subject: [PATCH 07/22] Switch back to XCI and remove runtime_params from xci --- .../gtyUltraScale+/coregen/TimingGty_extref.xci | 15 --------------- .../coregen/TimingGty_fixedlat.xci | 15 --------------- LCLS-II/gtyUltraScale+/ruckus.tcl | 16 ++++++++-------- 3 files changed, 8 insertions(+), 38 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index e875ce05..335cf525 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -821,21 +821,6 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "virtexuplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xcvu9p" } ], - "PACKAGE": [ { "value": "flgc2104" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], - "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], - "USE_RDI_GENERATION": [ { "value": "TRUE" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci index 70e59226..51101626 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci @@ -821,21 +821,6 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "virtexuplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xcvu9p" } ], - "PACKAGE": [ { "value": "flgc2104" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], - "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], - "USE_RDI_GENERATION": [ { "value": "TRUE" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index 1db36abc..2db3d647 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,19 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" + #loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadIpCore -path "${path}/TimingGty_extref.xci" - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" + #loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" + #loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadIpCore -path "${path}/TimingGty_extref.xci" - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" + #loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" From 04ab0c8dafc0e7672564bcd21763b5fff7af0d86 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 20 Jun 2024 15:25:44 -0700 Subject: [PATCH 08/22] switch to surf-based align checker --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 824672bc..7491a42d 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -33,6 +33,7 @@ entity TimingGtCoreWrapper is TPD_G : time := 1 ns; DISABLE_TIME_GT_G : boolean := false; EXTREF_G : boolean := false; + AXI_CLK_FREQ_G : real := 156.25e6; AXIL_BASE_ADDR_G : slv(31 downto 0); ADDR_BITS_G : positive := 22; GTY_DRP_OFFSET_G : slv(31 downto 0) := x"00400000"); @@ -300,15 +301,17 @@ begin mAxiReadMasters => axilReadMasters, mAxiReadSlaves => axilReadSlaves); - U_AlignCheck : entity lcls_timing_core.GthRxAlignCheck + U_AlignCheck : entity surf.GtRxAlignCheck generic map ( - TPD_G => TPD_G, - GT_TYPE_G => "GTYE4", - DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) + TPD_G => TPD_G, + GT_TYPE_G => "GTYE4", + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) port map ( -- Clock Monitoring txClk => txoutclkb, - rxClk => rxUsrClk, -- Should maybe be rxUsrClk + rxClk => rxUsrClk, + refClk => axilClk, -- Could probably also be stableClk -- GTH Status/Control Interface resetIn => rxControl.reset, resetDone => bypassdone, From 073eb175b9a4f35c610b523e9d600cd5a711cf97 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 20 Jun 2024 16:17:45 -0700 Subject: [PATCH 09/22] add simulation generic to timing core wrapper (for align checker) --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 2 ++ 1 file changed, 2 insertions(+) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 7491a42d..070fcb43 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -31,6 +31,7 @@ use unisim.vcomponents.all; entity TimingGtCoreWrapper is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; DISABLE_TIME_GT_G : boolean := false; EXTREF_G : boolean := false; AXI_CLK_FREQ_G : real := 156.25e6; @@ -304,6 +305,7 @@ begin U_AlignCheck : entity surf.GtRxAlignCheck generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, GT_TYPE_G => "GTYE4", AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) From f8cc1bc21e3e10a8f99c7e89fbc426e93752f95f Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 24 Jun 2024 12:19:22 -0700 Subject: [PATCH 10/22] route pmaresetdone --- .../rtl/TimingGtCoreWrapper.vhd | 27 ++++++++++--------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 070fcb43..5e62f123 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -62,17 +62,18 @@ entity TimingGtCoreWrapper is cpllRefClkSel : in slv(2 downto 0) := "001"; -- Set for "111" for gtgRefClk -- Rx ports - rxControl : in TimingPhyControlType; - rxStatus : out TimingPhyStatusType; - rxUsrClkActive : in sl; - rxCdrStable : out sl; - rxUsrClk : in sl; - rxData : out slv(15 downto 0); - rxDataK : out slv(1 downto 0); - rxDispErr : out slv(1 downto 0); - rxDecErr : out slv(1 downto 0); - rxOutClk : out sl; - rxRecClk : out sl; + rxControl : in TimingPhyControlType; + rxStatus : out TimingPhyStatusType; + rxUsrClkActive : in sl; + rxCdrStable : out sl; + rxPmaRstDoneOut : out sl; + rxUsrClk : in sl; + rxData : out slv(15 downto 0); + rxDataK : out slv(1 downto 0); + rxDispErr : out slv(1 downto 0); + rxDecErr : out slv(1 downto 0); + rxOutClk : out sl; + rxRecClk : out sl; -- Tx Ports txControl : in TimingPhyControlType; @@ -456,7 +457,7 @@ begin rxctrl2_out => open, rxctrl3_out => rxCtrl3Out, rxoutclk_out(0) => rxoutclk_out, - rxpmaresetdone_out => open, + rxpmaresetdone_out => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, rxrecclkout_out(0) => rxRecClk); @@ -551,7 +552,7 @@ begin rxctrl2_out => open, rxctrl3_out => rxCtrl3Out, rxoutclk_out(0) => rxoutclk_out, - rxpmaresetdone_out => open, + rxpmaresetdone_out => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, rxrecclkout_out(0) => rxRecClk); From e5415c767ed74171c8372251e3c002225c191874 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 24 Jun 2024 12:24:25 -0700 Subject: [PATCH 11/22] bugfix (slv; not sl) --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 5e62f123..794f689c 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -457,7 +457,7 @@ begin rxctrl2_out => open, rxctrl3_out => rxCtrl3Out, rxoutclk_out(0) => rxoutclk_out, - rxpmaresetdone_out => rxPmaRstDoneOut, + rxpmaresetdone_out(0) => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, rxrecclkout_out(0) => rxRecClk); @@ -552,7 +552,7 @@ begin rxctrl2_out => open, rxctrl3_out => rxCtrl3Out, rxoutclk_out(0) => rxoutclk_out, - rxpmaresetdone_out => rxPmaRstDoneOut, + rxpmaresetdone_out(0) => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, txpmaresetdone_out => open, rxrecclkout_out(0) => rxRecClk); From 962225e3acae728c738a1d19f6e6102e2655a36f Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 24 Jun 2024 15:27:50 -0700 Subject: [PATCH 12/22] update dcp/xci and switch ruckus to dcp --- .../gtyUltraScale+/coregen/TimingGty_extref.dcp | 4 ++-- .../gtyUltraScale+/coregen/TimingGty_extref.xci | 6 +++--- .../coregen/TimingGty_fixedlat.dcp | 4 ++-- .../coregen/TimingGty_fixedlat.xci | 6 +++--- LCLS-II/gtyUltraScale+/ruckus.tcl | 16 ++++++++-------- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 09ae2336..0078ce13 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:421afa693a98e84138f677602e2bc4b70b58258afa75ce1d2d3f5fcb661f946a -size 309085 +oid sha256:a4b211c355503f9b01f455d03b7d95bbd469d64ef9c97cc1d2a5591224c2c080 +size 308963 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index 335cf525..9ab9acca 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -4,7 +4,7 @@ "xci_name": "TimingGty_extref", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", "ip_revision": "16", - "gen_directory": "../../../../S30xlAPx_project.gen/sources_1/ip/TimingGty_extref", + "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_extref", "parameters": { "component_parameters": { "GT_TYPE": [ { "value": "GTY", "value_src": "user", "resolve_type": "user", "usage": "all" } ], @@ -170,7 +170,7 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "26", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "9", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -825,7 +825,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../S30xlAPx_project.gen/sources_1/ip/TimingGty_extref" } ], + "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_extref" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2023.1" } ], diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp index 99c573d9..6c0b9c46 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fd2de19c0f89548d2067570f11b514c27177ee9c010c6fa690691c682c05d260 -size 311419 +oid sha256:0d203de3a3c9312b0fa4cc37c3f8cf918fc1906ed080cfe2d7ef8f935077614c +size 311342 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci index 51101626..cdb4ff80 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci @@ -4,7 +4,7 @@ "xci_name": "TimingGty_fixedlat", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", "ip_revision": "16", - "gen_directory": "../../../../S30xlAPx_project.gen/sources_1/ip/TimingGty_fixedlat", + "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_fixedlat", "parameters": { "component_parameters": { "GT_TYPE": [ { "value": "GTY", "value_src": "user", "resolve_type": "user", "usage": "all" } ], @@ -170,7 +170,7 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "26", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "9", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -825,7 +825,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../S30xlAPx_project.gen/sources_1/ip/TimingGty_fixedlat" } ], + "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_fixedlat" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2023.1" } ], diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index 2db3d647..cf36c751 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,19 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - #loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - loadIpCore -path "${path}/TimingGty_extref.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + #loadIpCore -path "${path}/TimingGty_extref.xci" - #loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - loadIpCore -path "${path}/TimingGty_fixedlat.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + #loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - #loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - loadIpCore -path "${path}/TimingGty_extref.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + #loadIpCore -path "${path}/TimingGty_extref.xci" - #loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - loadIpCore -path "${path}/TimingGty_fixedlat.xci" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + #loadIpCore -path "${path}/TimingGty_fixedlat.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" From f62390e8718ba562819f3355e7fd14692d86ba31 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 19 Jul 2024 12:15:19 -0700 Subject: [PATCH 13/22] fix core wrapper axilite bus --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 794f689c..a206f5b4 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -36,7 +36,6 @@ entity TimingGtCoreWrapper is EXTREF_G : boolean := false; AXI_CLK_FREQ_G : real := 156.25e6; AXIL_BASE_ADDR_G : slv(31 downto 0); - ADDR_BITS_G : positive := 22; GTY_DRP_OFFSET_G : slv(31 downto 0) := x"00400000"); port ( -- AXI-Lite Port @@ -239,11 +238,11 @@ architecture rtl of TimingGtCoreWrapper is constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(1 downto 0) := ( 0 => ( baseAddr => (AXIL_BASE_ADDR_G+x"00000000"), - addrBits => ADDR_BITS_G, + addrBits => 9, connectivity => x"FFFF"), 1 => ( baseAddr => (AXIL_BASE_ADDR_G+GTY_DRP_OFFSET_G), - addrBits => ADDR_BITS_G, + addrBits => 12, connectivity => x"FFFF")); signal rxCtrl0Out : slv(15 downto 0) := (others => '0'); From 2eaab4bc73cf8dcf167a110076cbf817461e7008 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 3 Sep 2024 14:09:43 -0700 Subject: [PATCH 14/22] update drp freq --- .../coregen/TimingGty_extref.dcp | 4 ++-- .../coregen/TimingGty_extref.xci | 24 +++++++++++++++---- .../coregen/TimingGty_fixedlat.dcp | 4 ++-- .../coregen/TimingGty_fixedlat.xci | 24 +++++++++++++++---- 4 files changed, 42 insertions(+), 14 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 0078ce13..22be92ce 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a4b211c355503f9b01f455d03b7d95bbd469d64ef9c97cc1d2a5591224c2c080 -size 308963 +oid sha256:56487beada8a723935e4bf982ae66e7041ce31044b6a2279b8690cabedca8f73 +size 267221 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index 9ab9acca..fb091306 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -3,7 +3,7 @@ "ip_inst": { "xci_name": "TimingGty_extref", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", - "ip_revision": "16", + "ip_revision": "18", "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_extref", "parameters": { "component_parameters": { @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "125.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "185.714285", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "125.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -821,14 +821,28 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "virtexuplus" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xcvu9p" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "fsgd2104" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ] + }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "16" } ], + "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_extref" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2023.1" } ], + "SWVERSION": [ { "value": "2024.1" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp index 6c0b9c46..e96afccc 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0d203de3a3c9312b0fa4cc37c3f8cf918fc1906ed080cfe2d7ef8f935077614c -size 311342 +oid sha256:dda194ef0100f74f512d246868c37c5eb175e5cfaeeb139c00cb5f21def5bc68 +size 267866 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci index cdb4ff80..5acf29b0 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci @@ -3,7 +3,7 @@ "ip_inst": { "xci_name": "TimingGty_fixedlat", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", - "ip_revision": "16", + "ip_revision": "18", "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_fixedlat", "parameters": { "component_parameters": { @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "125.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "125.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -821,14 +821,28 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "virtexuplus" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xcvu9p" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "fsgd2104" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ] + }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "16" } ], + "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/TimingGty_fixedlat" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2023.1" } ], + "SWVERSION": [ { "value": "2024.1" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, From f0d1cf73ae80a0d2a5e35874baf0042fabee3b85 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 16 Sep 2024 17:18:50 -0700 Subject: [PATCH 15/22] purge rxrecclk; rtl changes --- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index a206f5b4..7a20f11b 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -72,7 +72,6 @@ entity TimingGtCoreWrapper is rxDispErr : out slv(1 downto 0); rxDecErr : out slv(1 downto 0); rxOutClk : out sl; - rxRecClk : out sl; -- Tx Ports txControl : in TimingPhyControlType; @@ -158,8 +157,7 @@ architecture rtl of TimingGtCoreWrapper is rxsyncdone_out : out std_logic_vector(0 downto 0); txoutclk_out : out std_logic_vector(0 downto 0); txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0); - rxrecclkout_out : out std_logic_vector(0 downto 0) + txresetdone_out : out std_logic_vector(0 downto 0) ); end component; component TimingGty_extref @@ -230,8 +228,7 @@ architecture rtl of TimingGtCoreWrapper is rxsyncdone_out : out std_logic_vector(0 downto 0); txoutclk_out : out std_logic_vector(0 downto 0); txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0); - rxrecclkout_out : out std_logic_vector(0 downto 0) + txresetdone_out : out std_logic_vector(0 downto 0) ); end component; @@ -458,8 +455,7 @@ begin rxoutclk_out(0) => rxoutclk_out, rxpmaresetdone_out(0) => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, - txpmaresetdone_out => open, - rxrecclkout_out(0) => rxRecClk); + txpmaresetdone_out => open); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); @@ -553,8 +549,7 @@ begin rxoutclk_out(0) => rxoutclk_out, rxpmaresetdone_out(0) => rxPmaRstDoneOut, txoutclk_out(0) => txoutclk_out, - txpmaresetdone_out => open, - rxrecclkout_out(0) => rxRecClk); + txpmaresetdone_out => open); rxDataK <= rxCtrl0Out(1 downto 0); rxDispErr <= rxCtrl1Out(1 downto 0); From 361fb4cddac9275c3745e3f47f597184a4dcc5ff Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 16 Sep 2024 17:48:46 -0700 Subject: [PATCH 16/22] purge rxrecclk; update IP cores --- LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp | 4 ++-- LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci | 9 ++++----- LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp | 4 ++-- LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci | 9 ++++----- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 22be92ce..23edeb47 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:56487beada8a723935e4bf982ae66e7041ce31044b6a2279b8690cabedca8f73 -size 267221 +oid sha256:22fcc12ca31e79f7f7600d3f42fc758bc7a35a639b4985ff3c2482e5a5af9f8c +size 266926 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index fb091306..ea6ac467 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -155,7 +155,7 @@ "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "ENABLE_OPTIONAL_PORTS": [ { "value": "drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in loopback_in rxpolarity_in txinhibit_in txpolarity_in drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ENABLE_OPTIONAL_PORTS": [ { "value": "drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in loopback_in rxpolarity_in txinhibit_in txpolarity_in drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], @@ -170,10 +170,10 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "43", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "9", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -910,7 +910,6 @@ "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp index e96afccc..6a7b5633 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dda194ef0100f74f512d246868c37c5eb175e5cfaeeb139c00cb5f21def5bc68 -size 267866 +oid sha256:e361d39464fa4cd4211d9504ac5609b3fddfa8a277533a103a4e7ae1e2c70e0c +size 267674 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci index 5acf29b0..66952ded 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat.xci @@ -155,7 +155,7 @@ "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "ENABLE_OPTIONAL_PORTS": [ { "value": "cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxpolarity_in txinhibit_in txpolarity_in drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ENABLE_OPTIONAL_PORTS": [ { "value": "cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxpolarity_in txinhibit_in txpolarity_in drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], @@ -170,10 +170,10 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "43", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "9", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -912,7 +912,6 @@ "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], From 571bc0326662d38f10857de1bc799823b15c5e31 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 26 Sep 2024 13:24:32 -0700 Subject: [PATCH 17/22] get .xci/.dcp from pre-release --- .../coregen/TimingGty_extref.dcp | 4 +- .../coregen/TimingGty_extref.xci | 2354 +++++++++------- .../coregen/TimingGty_fixedlat.dcp | 4 +- .../coregen/TimingGty_fixedlat.xci | 2368 ++++++++++------- 4 files changed, 2882 insertions(+), 1848 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp index 23edeb47..9395115a 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:22fcc12ca31e79f7f7600d3f42fc758bc7a35a639b4985ff3c2482e5a5af9f8c -size 266926 +oid sha256:d29ee6efbb592706d37472577558c070b0834470dff19636c3bd63bd04306bc0 +size 470774 diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci index ea6ac467..ba61b6da 100644 --- a/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci +++ b/LCLS-II/gtyUltraScale+/coregen/TimingGty_extref.xci @@ -1,921 +1,1433 @@ -{ - "schema": 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false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + kintexuplus + + + xcku15p + ffva1156 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 10 + TRUE + ../../../../AmcCarrierKU15PEmpty_project.gen/sources_1/ip/TimingGty_fixedlat + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7f70bfb60004d1db125728bf69def83f69c52c28 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 2 Oct 2024 09:01:45 -0700 Subject: [PATCH 18/22] Add ruckus flag to optionally load XCI instead of DCP --- LCLS-II/gtyUltraScale+/ruckus.tcl | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index cf36c751..f7fb77de 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,25 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - #loadIpCore -path "${path}/TimingGty_extref.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "${path}/TimingGty_extref.xci" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" + puts "Loading XCI files for LCLS Timing" + } else { + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + } - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - #loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - #loadIpCore -path "${path}/TimingGty_extref.xci" - - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - #loadIpCore -path "${path}/TimingGty_fixedlat.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "${path}/TimingGty_extref.xci" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" + } else { + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + } } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" From 56dd7ae10387d80b313fd5dc5c8dd7e5ad6c1ec2 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 3 Oct 2024 13:54:56 -0700 Subject: [PATCH 19/22] differentiate between gth/gty .xcis to avoid vcs ruckus tcl fail when sourcing different arch gt --- LCLS-II/gthUltraScale+/ruckus.tcl | 2 +- LCLS-II/gthUltraScale/ruckus.tcl | 2 +- LCLS-II/gtyUltraScale+/ruckus.tcl | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/LCLS-II/gthUltraScale+/ruckus.tcl b/LCLS-II/gthUltraScale+/ruckus.tcl index 9895826d..15f24c59 100644 --- a/LCLS-II/gthUltraScale+/ruckus.tcl +++ b/LCLS-II/gthUltraScale+/ruckus.tcl @@ -4,7 +4,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl if { $::env(VIVADO_VERSION) >= 2022.2} { loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl" - if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } { loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" } else { diff --git a/LCLS-II/gthUltraScale/ruckus.tcl b/LCLS-II/gthUltraScale/ruckus.tcl index e3e3c88e..2faf0e78 100644 --- a/LCLS-II/gthUltraScale/ruckus.tcl +++ b/LCLS-II/gthUltraScale/ruckus.tcl @@ -5,7 +5,7 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } { loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl" - if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } { loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" } else { diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index f7fb77de..4b2fcd9c 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,7 +14,7 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + if { [info exists ::env(LCLS_TIMING_GTY_XCI)] != 0 && $::env(LCLS_TIMING_GTY_XCI) == 1 } { loadIpCore -path "${path}/TimingGty_extref.xci" loadIpCore -path "${path}/TimingGty_fixedlat.xci" puts "Loading XCI files for LCLS Timing" @@ -26,7 +26,7 @@ if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1 } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + if { [info exists ::env(LCLS_TIMING_GTY_XCI)] != 0 && $::env(LCLS_TIMING_GTY_XCI) == 1 } { loadIpCore -path "${path}/TimingGty_extref.xci" loadIpCore -path "${path}/TimingGty_fixedlat.xci" } else { From b6362ae99b1754e065de2870b5bb83ee4adb93fb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 10:13:18 -0700 Subject: [PATCH 20/22] Remove project specific parameters from XCI --- .../coregen/TimingGth_extref.xci | 19 ++----------------- .../coregen/TimingGth_fixedlat.xci | 17 +---------------- 2 files changed, 3 insertions(+), 33 deletions(-) diff --git a/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci b/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci index 69afab2c..43955b0d 100644 --- a/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci +++ b/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci @@ -821,28 +821,13 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "kintexuplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xcku15p" } ], - "PACKAGE": [ { "value": "ffva1156" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], - "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], - "USE_RDI_GENERATION": [ { "value": "TRUE" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "15" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ], + "OUTPUTDIR": [ { "value": "." } ], "SELECTEDSIMMODEL": [ { "value": "" } ], - "SHAREDDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ], + "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } diff --git a/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci b/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci index 0310ae45..853e5f55 100644 --- a/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci +++ b/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci @@ -821,26 +821,11 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "kintexuplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xcku15p" } ], - "PACKAGE": [ { "value": "ffva1156" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], - "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], - "USE_RDI_GENERATION": [ { "value": "TRUE" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "15" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_fixedlat" } ], + "OUTPUTDIR": [ { "value": "." } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2022.2" } ], From e4525efc21834ccb9046e9d39d5295ca4166a362 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 9 Jan 2025 10:08:21 -0800 Subject: [PATCH 21/22] Updating submodule lock for surf.GtRxAlignCheck --- ruckus.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ruckus.tcl b/ruckus.tcl index 4649b851..bed6ad18 100644 --- a/ruckus.tcl +++ b/ruckus.tcl @@ -9,7 +9,7 @@ if { [VersionCheck 2019.1 ] < 0 } { # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { if { [SubmoduleCheck {ruckus} {2.1.2} ] < 0 } {exit -1} - if { [SubmoduleCheck {surf} {2.8.0} ] < 0 } {exit -1} + if { [SubmoduleCheck {surf} {2.53.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0" From 3f1e5c237b999797bbe5c371b367ccbd4ae6d3be Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 9 Jan 2025 10:10:20 -0800 Subject: [PATCH 22/22] Update LICENSE.txt --- LICENSE.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LICENSE.txt b/LICENSE.txt index 9aa129c6..8b0998b1 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -1,5 +1,5 @@ -Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior +Copyright (c) 2025, The Board of Trustees of the Leland Stanford Junior University, through SLAC National Accelerator Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved. Redistribution and use in source and binary forms, with or without