From a845efa70ec3bc572107734ba8fec2e3911b8a41 Mon Sep 17 00:00:00 2001 From: Matt Weaver Date: Thu, 17 Aug 2023 12:42:31 -0700 Subject: [PATCH 01/11] Modify TimingStreamTx to be consistent with EVG output. EVRs can tell the difference. --- LCLS-II/core/rtl/TimingStreamTx.vhd | 44 +++++++++++++++++------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/LCLS-II/core/rtl/TimingStreamTx.vhd b/LCLS-II/core/rtl/TimingStreamTx.vhd index d0a9f13a..46469c8b 100644 --- a/LCLS-II/core/rtl/TimingStreamTx.vhd +++ b/LCLS-II/core/rtl/TimingStreamTx.vhd @@ -84,10 +84,17 @@ begin v := r; v.dataBuffEn := not r.dataBuffEn; - v.dbufData := D_215_C; - v.ecodData := K_COM_C; - v.dataK := "01"; + if r.dataBuffEn = '1' then + v.dbufData := x"00"; + v.ecodData := x"00"; + v.dataK := "00"; + else + v.dbufData := x"00"; + v.ecodData := K_COM_C; + v.dataK := "01"; + end if; + case (r.state) is when IDLE_S => v.wordCount := (others=>'0'); @@ -97,14 +104,14 @@ begin v.dataBuffEn := '0'; v.pulseId := pulseId; v.eventCodes := eventCodes; - v.dataK := "11"; + v.dataK(1) := '1'; v.dbufData := K_280_C; end if; when FRAME_S => if r.wordCount=NDATABUFF_WORDS then v.state := PULSEID_S; v.wordCount := (others=>'0'); - v.dataK := "11"; + v.dataK(1) := '1'; v.dbufData := K_281_C; elsif r.dataBuffEn='1' then v.dbufData := r.dataBuff(7 downto 0); @@ -112,27 +119,28 @@ begin v.wordCount := r.wordCount+1; end if; when PULSEID_S => - v.dataK := "00"; - if r.wordCount=toSlv(32,r.wordCount'length) then - v.state := ECODE_S; - v.wordCount := (others=>'0'); - v.ecodData := x"7D"; - else - v.wordCount := r.wordCount+1; - v.pulseId := r.pulseId(30 downto 0) & '0'; - if r.pulseId(31)='0' then - v.ecodData := x"70"; + if r.dataBuffEn='1' then + if r.wordCount=toSlv(32,r.wordCount'length) then + v.state := ECODE_S; + v.wordCount := (others=>'0'); + v.ecodData := x"7D"; else - v.ecodData := x"71"; + v.wordCount := r.wordCount+1; + v.pulseId := r.pulseId(30 downto 0) & '0'; + if r.pulseId(31)='0' then + v.ecodData := x"70"; + else + v.ecodData := x"71"; + end if; end if; end if; when ECODE_S => if r.wordCount = toSlv(255,r.wordCount'length) then v.state := IDLE_S; - else + elsif r.dataBuffEn = '1' then v.wordCount := r.wordCount+1; if r.eventCodes(conv_integer(r.wordCount))='1' then - v.dataK := "00"; + v.dataK(0) := '0'; v.ecodData := r.wordCount; end if; end if; From e61afd4205393ccaa531bf7adb17063e60a0db12 Mon Sep 17 00:00:00 2001 From: Matt Weaver Date: Mon, 11 Mar 2024 07:34:44 -0700 Subject: [PATCH 02/11] Add AC sampling configuration registers --- LCLS-II/core/rtl/TPGPkg.vhd | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/LCLS-II/core/rtl/TPGPkg.vhd b/LCLS-II/core/rtl/TPGPkg.vhd index 8a1ac539..60050c37 100644 --- a/LCLS-II/core/rtl/TPGPkg.vhd +++ b/LCLS-II/core/rtl/TPGPkg.vhd @@ -241,10 +241,11 @@ package TPGPkg is -- AC sync from analog or digital AMC acMaster : sl; -- Analog lookahead (master) or digital delay (us) - acDelay : slv(14 downto 0); + acTS1 : slv(1 downto 0); + acPolarity : sl; + acDelay : slv(12 downto 0); inpDelay : slv(8 downto 0); inpDelayLd : sl; - frameDelay : slv(15 downto 0); baseDivisor : slv(15 downto 0); pulseId : slv(63 downto 0); pulseIdWrEn : sl; @@ -293,11 +294,12 @@ package TPGPkg is txPolarity => '0', baseDivisor => x"00C8", acMaster => '1', - acDelay => toSlv(100, 15), + acTS1 => "00", + acPolarity => '0', + acDelay => toSlv(100, 13), -- acDelay => toSlv(733,15), inpDelay => (others => '0'), inpDelayLd => '0', - frameDelay => x"0000", pulseId => (others => '0'), pulseIdWrEn => '1', timeStamp => (others => '0'), From ef58f57119f6011f912b3280cdf72677c2d36294 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 19 Mar 2024 09:16:47 -0700 Subject: [PATCH 03/11] whitespace removal --- conda-recipe/build.sh | 2 +- generateDocumentationAndDeploy.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/conda-recipe/build.sh b/conda-recipe/build.sh index 50810c15..a6d812f2 100644 --- a/conda-recipe/build.sh +++ b/conda-recipe/build.sh @@ -1,4 +1,4 @@ #!/usr/bin/bash - + python setup.py install diff --git a/generateDocumentationAndDeploy.sh b/generateDocumentationAndDeploy.sh index 75dc85dd..5ff35e84 100644 --- a/generateDocumentationAndDeploy.sh +++ b/generateDocumentationAndDeploy.sh @@ -88,7 +88,7 @@ echo "" > .nojekyll echo 'Generating Doxygen code documentation...' doxygen -v -# Update the INPUT configuration +# Update the INPUT configuration echo "INPUT = $TRAVIS_BUILD_DIR" >> $DOXYFILE # # Update the EXCLUDE configuration From c6e9419e38224784cb0d83f2075a02617922765c Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 27 Jun 2024 15:30:55 -0700 Subject: [PATCH 04/11] Update timing_ci.yml ### Description - Using the reusable YAML CI scripts --- .github/workflows/timing_ci.yml | 95 ++++++--------------------------- 1 file changed, 15 insertions(+), 80 deletions(-) diff --git a/.github/workflows/timing_ci.yml b/.github/workflows/timing_ci.yml index b133c32b..bd786874 100644 --- a/.github/workflows/timing_ci.yml +++ b/.github/workflows/timing_ci.yml @@ -60,89 +60,24 @@ jobs: github_token: ${{ secrets.GH_TOKEN }} publish_dir: doxygen/html +# ---------------------------------------------------------------------------- + gen_release: - name: Generate Release - runs-on: ubuntu-20.04 needs: [test_and_document] - if: startsWith(github.ref, 'refs/tags/') - steps: - - - uses: actions/checkout@v2 - with: - fetch-depth: 0 - - - uses: actions/setup-python@v2 - with: - python-version: 3.8 - - - name: Get Image Information - id: get_image_info - run: | - echo ::set-output name=tag::`git describe --tags` + uses: slaclab/ruckus/.github/workflows/gen_release.yml@main + with: + version: '1.0.0' + secrets: + GH_TOKEN: ${{ secrets.GH_TOKEN }} - - name: Get Ruckus - run: | - git clone https://github.com/slaclab/ruckus.git - python -m pip install --upgrade pip - pip install -r ruckus/scripts/pip_requirements.txt - - - name: Gen Release - env: - TRAVIS_REPO_SLUG: ${{ github.repository }} - TRAVIS_TAG: ${{ steps.get_image_info.outputs.tag }} - GH_REPO_TOKEN: ${{ secrets.GH_TOKEN }} - run: | - python ruckus/scripts/releaseGen.py +# ---------------------------------------------------------------------------- - conda_build: - name: Anaconda Build + conda_build_lib: needs: [test_and_document] - if: startsWith(github.ref, 'refs/tags/') - strategy: - matrix: - os: - - ubuntu-20.04 - runs-on: ${{ matrix.os }} - steps: - - # This step checks out a copy of your repository. - - uses: actions/checkout@v2 - with: - fetch-depth: 0 - - - uses: actions/setup-python@v2 - with: - python-version: 3.8 - - - name: Setup anaconda - env: - OS_NAME: ${{ matrix.os }} - run: | - cd ${HOME} - wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh - bash miniconda.sh -b -p ${HOME}/miniconda - export PATH="${HOME}/miniconda/bin:$PATH" - source ${HOME}/miniconda/etc/profile.d/conda.sh - conda config --set always_yes yes - conda config --set channel_priority strict - conda install -n base conda-libmamba-solver - conda config --set solver libmamba - conda install conda-build anaconda-client conda-verify - conda update -q conda conda-build - conda update --all + uses: slaclab/ruckus/.github/workflows/conda_build_lib.yml@main + with: + version: '1.0.0' + secrets: + CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }} - - name: Get Image Information - id: get_image_info - env: - CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }} - OS_NAME: ${{ matrix.os }} - run: | - echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG - echo ::set-output name=os::linux-64 - - - name: Build And Upload - run: | - export PATH="${HOME}/miniconda/bin:$PATH" - source ${HOME}/miniconda/etc/profile.d/conda.sh - conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c tidair-packages -c conda-forge - anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/noarch/*.tar.bz2 +# ---------------------------------------------------------------------------- From f5da2ae465102565f06583f7f3ce36ad858bc405 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Tue, 13 Aug 2024 10:52:22 -0700 Subject: [PATCH 05/11] updated clktime_186MHz --- LCLS-II/core/rtl/ClockTime_186MHz.vhd | 8 ++++---- LCLS-II/core/rtl/TPGMini.vhd | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/LCLS-II/core/rtl/ClockTime_186MHz.vhd b/LCLS-II/core/rtl/ClockTime_186MHz.vhd index 3c015273..4a3a2590 100644 --- a/LCLS-II/core/rtl/ClockTime_186MHz.vhd +++ b/LCLS-II/core/rtl/ClockTime_186MHz.vhd @@ -22,7 +22,7 @@ use UNISIM.VCOMPONENTS.ALL; library surf; use surf.StdRtlPkg.all; -entity ClockTime is +entity ClockTime_186MHz is generic ( TPD_G : time := 1 ns); port ( @@ -37,10 +37,10 @@ entity ClockTime is wrEnB : in sl; dataO : out slv(63 downto 0) ); -end ClockTime; +end ClockTime_186MHz; -- Define architecture for top level module -architecture ClockTime_186MHz of ClockTime is +architecture rtl of ClockTime_186MHz is constant remainder : slv( 4 downto 0) := slv(conv_unsigned( 5,5)); constant divisor : slv( 4 downto 0) := slv(conv_unsigned(13,5)); @@ -101,4 +101,4 @@ begin dataO <= dataB; -end ClockTime_186MHz; +end rtl; diff --git a/LCLS-II/core/rtl/TPGMini.vhd b/LCLS-II/core/rtl/TPGMini.vhd index 5ab5b427..93cb664e 100644 --- a/LCLS-II/core/rtl/TPGMini.vhd +++ b/LCLS-II/core/rtl/TPGMini.vhd @@ -326,7 +326,7 @@ begin end if; end process; - U_ClockTime : entity lcls_timing_core.ClockTime + U_ClockTime : entity lcls_timing_core.ClockTime_186MHz generic map ( TPD_G => TPD_G) port map ( From aad43a1ab5c2087af33c8adaa3f43a2c5d0914d2 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Wed, 14 Aug 2024 09:58:09 -0700 Subject: [PATCH 06/11] added ClockTime ports --- LCLS-II/core/rtl/TPGMini.vhd | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/LCLS-II/core/rtl/TPGMini.vhd b/LCLS-II/core/rtl/TPGMini.vhd index 93cb664e..752c2a7c 100644 --- a/LCLS-II/core/rtl/TPGMini.vhd +++ b/LCLS-II/core/rtl/TPGMini.vhd @@ -326,10 +326,13 @@ begin end if; end process; - U_ClockTime : entity lcls_timing_core.ClockTime_186MHz + U_ClockTime : entity lcls_timing_core.ClockTime generic map ( TPD_G => TPD_G) port map ( + step => toSlv(8,5), + remainder => toSlv(2,5), + divisor => toSlv(5,5), rst => txRst, clkA => txClk, wrEnA => config.timeStampWrEn, @@ -338,7 +341,7 @@ begin clkB => txClk, wrEnB => baseEnable, dataO => frame.timeStamp); - + statusO <= status; config <= configI; From c897203b712321e21be03db0f1be371bef4eb909 Mon Sep 17 00:00:00 2001 From: Mudit Mishra Date: Fri, 16 Aug 2024 12:48:14 -0700 Subject: [PATCH 07/11] ClockTime ports go to defaults --- LCLS-II/core/rtl/TPGMini.vhd | 3 --- 1 file changed, 3 deletions(-) diff --git a/LCLS-II/core/rtl/TPGMini.vhd b/LCLS-II/core/rtl/TPGMini.vhd index 752c2a7c..75beb745 100644 --- a/LCLS-II/core/rtl/TPGMini.vhd +++ b/LCLS-II/core/rtl/TPGMini.vhd @@ -330,9 +330,6 @@ begin generic map ( TPD_G => TPD_G) port map ( - step => toSlv(8,5), - remainder => toSlv(2,5), - divisor => toSlv(5,5), rst => txRst, clkA => txClk, wrEnA => config.timeStampWrEn, From 8a628f4991cc4148d75d4d118153595326333842 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 16 Aug 2024 13:00:27 -0700 Subject: [PATCH 08/11] whitespace removal --- LCLS-II/core/rtl/TPGMini.vhd | 2 +- LCLS-II/core/rtl/TimingStreamTx.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/LCLS-II/core/rtl/TPGMini.vhd b/LCLS-II/core/rtl/TPGMini.vhd index 75beb745..5ab5b427 100644 --- a/LCLS-II/core/rtl/TPGMini.vhd +++ b/LCLS-II/core/rtl/TPGMini.vhd @@ -338,7 +338,7 @@ begin clkB => txClk, wrEnB => baseEnable, dataO => frame.timeStamp); - + statusO <= status; config <= configI; diff --git a/LCLS-II/core/rtl/TimingStreamTx.vhd b/LCLS-II/core/rtl/TimingStreamTx.vhd index 46469c8b..eaad64c4 100644 --- a/LCLS-II/core/rtl/TimingStreamTx.vhd +++ b/LCLS-II/core/rtl/TimingStreamTx.vhd @@ -94,7 +94,7 @@ begin v.ecodData := K_COM_C; v.dataK := "01"; end if; - + case (r.state) is when IDLE_S => v.wordCount := (others=>'0'); From e4925d30fd0576c94ec2914070d1b0f17cc384f4 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 20 Sep 2024 09:37:28 -0700 Subject: [PATCH 09/11] Update TimingGtCoreWrapper.vhd ### Description - Updating the RX RX_EQUALIZER_G from `DFE` to `LPM` - Related to https://github.com/slaclab/evr-card-g2/pull/11 --- LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd index ba7cbf50..dc9ded29 100644 --- a/LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd @@ -277,7 +277,7 @@ begin RX_OS_CFG_G => "0000010000000", RXCDR_CFG_G => RXCDR_CFG_C, RXDFEXYDEN_G => '1', - RX_EQUALIZER_G => "DFE", + RX_EQUALIZER_G => "LPM", RXSLIDE_MODE_G => "PMA", FIXED_COMMA_EN_G => "0011", FIXED_ALIGN_COMMA_0_G => "----------0101111100", -- Normal Comma From 2b793a778d4ec4322ab1f9b0fce050d4e1ab8aed Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 25 Sep 2024 09:00:10 -0700 Subject: [PATCH 10/11] Updating code comments for Ultrascale/Ultrascale+ GTs wrapper StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz) --- LCLS-II/core/rtl/TimingGthWrapper.vhd | 1 + LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd | 2 +- LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd | 2 +- LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/LCLS-II/core/rtl/TimingGthWrapper.vhd b/LCLS-II/core/rtl/TimingGthWrapper.vhd index 1746a74f..b2f7d6ad 100644 --- a/LCLS-II/core/rtl/TimingGthWrapper.vhd +++ b/LCLS-II/core/rtl/TimingGthWrapper.vhd @@ -25,6 +25,7 @@ entity TimingGthWrapper is TPD_G : time := 1 ns); port ( + -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz) stableClk : in sl; gtRefClk : in sl; diff --git a/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd b/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd index 8ba961aa..08f5aa54 100644 --- a/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd +++ b/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd @@ -44,7 +44,7 @@ entity TimingGthCoreWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - + -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz) stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 -- GTH FPGA IO diff --git a/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd index 36c3ad9b..528504a5 100644 --- a/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd @@ -44,7 +44,7 @@ entity TimingGtCoreWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - + -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz) stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 -- GTH FPGA IO diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd index 49ba0841..87edca76 100644 --- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd +++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd @@ -44,7 +44,7 @@ entity TimingGtCoreWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - + -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz) stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4 -- GTY FPGA IO From e3754a1b8a1c045508726c0b872f2bb8ac0bdbbe Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 2 Oct 2024 09:01:45 -0700 Subject: [PATCH 11/11] Add ruckus flag to optionally load XCI instead of DCP --- LCLS-II/gthUltraScale+/ruckus.tcl | 12 +++++++----- LCLS-II/gthUltraScale/ruckus.tcl | 12 +++++++----- LCLS-II/gtyUltraScale+/ruckus.tcl | 24 +++++++++++++++--------- 3 files changed, 29 insertions(+), 19 deletions(-) diff --git a/LCLS-II/gthUltraScale+/ruckus.tcl b/LCLS-II/gthUltraScale+/ruckus.tcl index 4635e03c..9895826d 100644 --- a/LCLS-II/gthUltraScale+/ruckus.tcl +++ b/LCLS-II/gthUltraScale+/ruckus.tcl @@ -4,11 +4,13 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl if { $::env(VIVADO_VERSION) >= 2022.2} { loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl" - loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp" - #loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" - - loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp" - #loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" + loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" + } else { + loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp" + loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp" + } } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2022.2 (or later)\n\n" } diff --git a/LCLS-II/gthUltraScale/ruckus.tcl b/LCLS-II/gthUltraScale/ruckus.tcl index de55f56f..e3e3c88e 100644 --- a/LCLS-II/gthUltraScale/ruckus.tcl +++ b/LCLS-II/gthUltraScale/ruckus.tcl @@ -5,11 +5,13 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } { loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl" - loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp" - # loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" - - loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp" - # loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci" + loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci" + } else { + loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_extref.dcp" + loadSource -lib lcls_timing_core -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp" + } } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2016.4 (or later)\n\n" diff --git a/LCLS-II/gtyUltraScale+/ruckus.tcl b/LCLS-II/gtyUltraScale+/ruckus.tcl index 1db36abc..f7fb77de 100644 --- a/LCLS-II/gtyUltraScale+/ruckus.tcl +++ b/LCLS-II/gtyUltraScale+/ruckus.tcl @@ -14,19 +14,25 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } { if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "${path}/TimingGty_extref.xci" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" + puts "Loading XCI files for LCLS Timing" + } else { + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + } - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" } elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } { - loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" - # loadIpCore -path "${path}/TimingGty_extref.xci" - - loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" - # loadIpCore -path "${path}/TimingGty_fixedlat.xci" + if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } { + loadIpCore -path "${path}/TimingGty_extref.xci" + loadIpCore -path "${path}/TimingGty_fixedlat.xci" + } else { + loadSource -lib lcls_timing_core -path "${path}/TimingGty_extref.dcp" + loadSource -lib lcls_timing_core -path "${path}/TimingGty_fixedlat.dcp" + } } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n"