montgomery_multiplier_tb.vhd

-- Entity name: montgomery_multiplier_tb
-- Author: Stephen Carter, Jacob Barnett
-- Contact: stephen.carter@mail.mcgill.ca, jacob.barnett@mail.mcgill.ca
-- Date: April 11, 2016
-- Description:
-- Testbench used to test the Montgomery Multiplier
-- Tests autogenerated from a python script

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity montgomery_multiplier_tb is
end entity;

architecture test of montgomery_multiplier_tb is

Component montgomery_multiplier is
 	Generic(
		WIDTH_IN : integer := 32
	);
	Port(	A :	in unsigned(WIDTH_IN-1 downto 0);
		B :	in unsigned(WIDTH_IN-1 downto 0);
		N :	in unsigned(WIDTH_IN-1 downto 0);
		latch : in std_logic;
		clk :	in std_logic;
		reset :	in std_logic;
		M : 	out unsigned(WIDTH_IN-1 downto 0)
	);
end component;

CONSTANT WIDTH_IN : integer := 32;

CONSTANT clk_period : time := 1 ns;

Signal N_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal A_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal B_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');

Signal clk : std_logic := '0';
Signal reset_t : std_logic := '0';
Signal latch_in : std_logic := '0';

Signal M_out : unsigned(WIDTH_IN-1 downto 0) := (others => '0');

Begin
-- device under test
dut: montgomery_multiplier PORT MAP(	A	=> 	A_in,
					B 	=> 	B_in,
					N 	=> 	N_in,
					latch	=>	latch_in,
					clk	=> 	clk,
					reset 	=>	reset_t,
					M	=>	M_out);
  
-- process for clock
clk_process : Process
Begin
	clk <= '0';
	wait for clk_period/2;
	clk <= '1';
	wait for clk_period/2;
end process;

stim_process: process
Begin


	reset_t <= '1';
	wait for 1 * clk_period;
	reset_t <= '0';
	wait for 1 * clk_period;


	REPORT "Begin test case for a=1328668589 (A=611933216), b=1328668589 (B=611933216), N=2157374201";
	REPORT "Expected output is 1602110260, 01011111011111100100001100110100";
	A_in <= "00100100011110010101110000100000";
	B_in <= "00100100011110010101110000100000";
	N_in <= "10000000100101101110101011111001";
	latch_in <= '1';
	wait for 2 * clk_period;
	latch_in <= '0';
	wait for 33 * clk_period;
	ASSERT(M_out = "01011111011111100100001100110100") REPORT "test failed" SEVERITY ERROR;



	wait;

end process;
end architecture;