diff --git a/src/adc.rs b/src/adc.rs
index ba68c8111..a80f7fb31 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -63,7 +63,7 @@ impl RegisterBlock {
 }
 #[doc = "CS (rw) register accessor: ADC Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@cs`]
 module"]
@@ -72,7 +72,7 @@ pub type CS = crate::Reg<cs::CS_SPEC>;
 pub mod cs;
 #[doc = "RESULT (r) register accessor: Result of most recent ADC conversion  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`result::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@result`]
 module"]
@@ -81,7 +81,7 @@ pub type RESULT = crate::Reg<result::RESULT_SPEC>;
 pub mod result;
 #[doc = "FCS (rw) register accessor: FIFO control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fcs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fcs`]
 module"]
@@ -90,7 +90,7 @@ pub type FCS = crate::Reg<fcs::FCS_SPEC>;
 pub mod fcs;
 #[doc = "FIFO (r) register accessor: Conversion result FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo`]
 module"]
@@ -102,7 +102,7 @@ pub mod fifo;
  The divider is reset when either of these fields are written.  
  Total period is 1 + INT + FRAC / 256  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div`]
 module"]
@@ -114,7 +114,7 @@ pub type DIV = crate::Reg<div::DIV_SPEC>;
 pub mod div;
 #[doc = "INTR (r) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -123,7 +123,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -132,7 +132,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -141,7 +141,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/adc/cs.rs b/src/adc/cs.rs
index 4f22e80f2..2bfdf482e 100644
--- a/src/adc/cs.rs
+++ b/src/adc/cs.rs
@@ -145,7 +145,7 @@ impl W {
 }
 #[doc = "ADC Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CS_SPEC;
 impl crate::RegisterSpec for CS_SPEC {
     type Ux = u32;
diff --git a/src/adc/div.rs b/src/adc/div.rs
index 4bd141132..a04a28eaf 100644
--- a/src/adc/div.rs
+++ b/src/adc/div.rs
@@ -41,7 +41,7 @@ impl W {
  The divider is reset when either of these fields are written.  
  Total period is 1 + INT + FRAC / 256  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SPEC;
 impl crate::RegisterSpec for DIV_SPEC {
     type Ux = u32;
diff --git a/src/adc/fcs.rs b/src/adc/fcs.rs
index 6889daa89..1493fbcd3 100644
--- a/src/adc/fcs.rs
+++ b/src/adc/fcs.rs
@@ -134,7 +134,7 @@ impl W {
 }
 #[doc = "FIFO control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fcs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FCS_SPEC;
 impl crate::RegisterSpec for FCS_SPEC {
     type Ux = u32;
diff --git a/src/adc/fifo.rs b/src/adc/fifo.rs
index 981838117..a86ec4aab 100644
--- a/src/adc/fifo.rs
+++ b/src/adc/fifo.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Conversion result FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_SPEC;
 impl crate::RegisterSpec for FIFO_SPEC {
     type Ux = u32;
diff --git a/src/adc/inte.rs b/src/adc/inte.rs
index 48ddb4a7f..c71feadcc 100644
--- a/src/adc/inte.rs
+++ b/src/adc/inte.rs
@@ -27,7 +27,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/adc/intf.rs b/src/adc/intf.rs
index aec4073f3..68f947eb6 100644
--- a/src/adc/intf.rs
+++ b/src/adc/intf.rs
@@ -27,7 +27,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/adc/intr.rs b/src/adc/intr.rs
index 1d93d17f0..4efc67b4f 100644
--- a/src/adc/intr.rs
+++ b/src/adc/intr.rs
@@ -13,7 +13,7 @@ impl R {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/adc/ints.rs b/src/adc/ints.rs
index e96b7e85e..8adebf040 100644
--- a/src/adc/ints.rs
+++ b/src/adc/ints.rs
@@ -13,7 +13,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/adc/result.rs b/src/adc/result.rs
index f7d77826f..af1eedb2d 100644
--- a/src/adc/result.rs
+++ b/src/adc/result.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Result of most recent ADC conversion  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESULT_SPEC;
 impl crate::RegisterSpec for RESULT_SPEC {
     type Ux = u32;
diff --git a/src/busctrl.rs b/src/busctrl.rs
index 308d0eda9..8941d95b9 100644
--- a/src/busctrl.rs
+++ b/src/busctrl.rs
@@ -66,7 +66,7 @@ impl RegisterBlock {
 }
 #[doc = "BUS_PRIORITY (rw) register accessor: Set the priority of each master for bus arbitration.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`bus_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bus_priority`]
 module"]
@@ -75,7 +75,7 @@ pub type BUS_PRIORITY = crate::Reg<bus_priority::BUS_PRIORITY_SPEC>;
 pub mod bus_priority;
 #[doc = "BUS_PRIORITY_ACK (r) register accessor: Bus priority acknowledge  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`bus_priority_ack::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bus_priority_ack`]
 module"]
@@ -84,7 +84,7 @@ pub type BUS_PRIORITY_ACK = crate::Reg<bus_priority_ack::BUS_PRIORITY_ACK_SPEC>;
 pub mod bus_priority_ack;
 #[doc = "PERFCTR0 (rw) register accessor: Bus fabric performance counter 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfctr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfctr0`]
 module"]
@@ -93,7 +93,7 @@ pub type PERFCTR0 = crate::Reg<perfctr0::PERFCTR0_SPEC>;
 pub mod perfctr0;
 #[doc = "PERFSEL0 (rw) register accessor: Bus fabric performance event select for PERFCTR0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfsel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfsel0`]
 module"]
@@ -102,7 +102,7 @@ pub type PERFSEL0 = crate::Reg<perfsel0::PERFSEL0_SPEC>;
 pub mod perfsel0;
 #[doc = "PERFCTR1 (rw) register accessor: Bus fabric performance counter 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfctr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfctr1`]
 module"]
@@ -111,7 +111,7 @@ pub type PERFCTR1 = crate::Reg<perfctr1::PERFCTR1_SPEC>;
 pub mod perfctr1;
 #[doc = "PERFSEL1 (rw) register accessor: Bus fabric performance event select for PERFCTR1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfsel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfsel1`]
 module"]
@@ -120,7 +120,7 @@ pub type PERFSEL1 = crate::Reg<perfsel1::PERFSEL1_SPEC>;
 pub mod perfsel1;
 #[doc = "PERFCTR2 (rw) register accessor: Bus fabric performance counter 2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfctr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfctr2`]
 module"]
@@ -129,7 +129,7 @@ pub type PERFCTR2 = crate::Reg<perfctr2::PERFCTR2_SPEC>;
 pub mod perfctr2;
 #[doc = "PERFSEL2 (rw) register accessor: Bus fabric performance event select for PERFCTR2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfsel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfsel2`]
 module"]
@@ -138,7 +138,7 @@ pub type PERFSEL2 = crate::Reg<perfsel2::PERFSEL2_SPEC>;
 pub mod perfsel2;
 #[doc = "PERFCTR3 (rw) register accessor: Bus fabric performance counter 3  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfctr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfctr3`]
 module"]
@@ -147,7 +147,7 @@ pub type PERFCTR3 = crate::Reg<perfctr3::PERFCTR3_SPEC>;
 pub mod perfctr3;
 #[doc = "PERFSEL3 (rw) register accessor: Bus fabric performance event select for PERFCTR3  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`perfsel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@perfsel3`]
 module"]
diff --git a/src/busctrl/bus_priority.rs b/src/busctrl/bus_priority.rs
index c338724e1..d18f16596 100644
--- a/src/busctrl/bus_priority.rs
+++ b/src/busctrl/bus_priority.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Set the priority of each master for bus arbitration.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`bus_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_PRIORITY_SPEC;
 impl crate::RegisterSpec for BUS_PRIORITY_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/bus_priority_ack.rs b/src/busctrl/bus_priority_ack.rs
index 6384115fb..85c830cc7 100644
--- a/src/busctrl/bus_priority_ack.rs
+++ b/src/busctrl/bus_priority_ack.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Bus priority acknowledge  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`bus_priority_ack::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_PRIORITY_ACK_SPEC;
 impl crate::RegisterSpec for BUS_PRIORITY_ACK_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs
index 24c7eef13..9d6040d03 100644
--- a/src/busctrl/perfctr0.rs
+++ b/src/busctrl/perfctr0.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Bus fabric performance counter 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfctr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFCTR0_SPEC;
 impl crate::RegisterSpec for PERFCTR0_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs
index 5d755ae07..678e16756 100644
--- a/src/busctrl/perfctr1.rs
+++ b/src/busctrl/perfctr1.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Bus fabric performance counter 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfctr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFCTR1_SPEC;
 impl crate::RegisterSpec for PERFCTR1_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs
index d93cd401b..53fd5200a 100644
--- a/src/busctrl/perfctr2.rs
+++ b/src/busctrl/perfctr2.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Bus fabric performance counter 2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfctr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFCTR2_SPEC;
 impl crate::RegisterSpec for PERFCTR2_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs
index 6946cf253..9d28c781a 100644
--- a/src/busctrl/perfctr3.rs
+++ b/src/busctrl/perfctr3.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Bus fabric performance counter 3  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfctr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfctr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfctr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFCTR3_SPEC;
 impl crate::RegisterSpec for PERFCTR3_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs
index ce44b8c5b..0cf532948 100644
--- a/src/busctrl/perfsel0.rs
+++ b/src/busctrl/perfsel0.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL0_A> for u8 {
 impl crate::FieldSpec for PERFSEL0_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL0_A {}
 #[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL0_R = crate::FieldReader<PERFSEL0_A>;
 impl PERFSEL0_R {
@@ -314,7 +315,7 @@ impl W {
 }
 #[doc = "Bus fabric performance event select for PERFCTR0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfsel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFSEL0_SPEC;
 impl crate::RegisterSpec for PERFSEL0_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs
index 01daabc0f..7cd77952a 100644
--- a/src/busctrl/perfsel1.rs
+++ b/src/busctrl/perfsel1.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL1_A> for u8 {
 impl crate::FieldSpec for PERFSEL1_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL1_A {}
 #[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
 impl PERFSEL1_R {
@@ -314,7 +315,7 @@ impl W {
 }
 #[doc = "Bus fabric performance event select for PERFCTR1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFSEL1_SPEC;
 impl crate::RegisterSpec for PERFSEL1_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs
index 1a39e60f0..8758b8448 100644
--- a/src/busctrl/perfsel2.rs
+++ b/src/busctrl/perfsel2.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL2_A> for u8 {
 impl crate::FieldSpec for PERFSEL2_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL2_A {}
 #[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL2_R = crate::FieldReader<PERFSEL2_A>;
 impl PERFSEL2_R {
@@ -314,7 +315,7 @@ impl W {
 }
 #[doc = "Bus fabric performance event select for PERFCTR2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfsel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFSEL2_SPEC;
 impl crate::RegisterSpec for PERFSEL2_SPEC {
     type Ux = u32;
diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs
index 2f34e1e83..b8ac77b1f 100644
--- a/src/busctrl/perfsel3.rs
+++ b/src/busctrl/perfsel3.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL3_A> for u8 {
 impl crate::FieldSpec for PERFSEL3_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL3_A {}
 #[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL3_R = crate::FieldReader<PERFSEL3_A>;
 impl PERFSEL3_R {
@@ -314,7 +315,7 @@ impl W {
 }
 #[doc = "Bus fabric performance event select for PERFCTR3  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`perfsel3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`perfsel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`perfsel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERFSEL3_SPEC;
 impl crate::RegisterSpec for PERFSEL3_SPEC {
     type Ux = u32;
diff --git a/src/clocks.rs b/src/clocks.rs
index 92a0dda46..8d1e6fbce 100644
--- a/src/clocks.rs
+++ b/src/clocks.rs
@@ -314,7 +314,7 @@ impl RegisterBlock {
 }
 #[doc = "CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout0_ctrl`]
 module"]
@@ -323,7 +323,7 @@ pub type CLK_GPOUT0_CTRL = crate::Reg<clk_gpout0_ctrl::CLK_GPOUT0_CTRL_SPEC>;
 pub mod clk_gpout0_ctrl;
 #[doc = "CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout0_div`]
 module"]
@@ -333,7 +333,7 @@ pub mod clk_gpout0_div;
 #[doc = "CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout0_selected`]
 module"]
@@ -343,7 +343,7 @@ pub type CLK_GPOUT0_SELECTED = crate::Reg<clk_gpout0_selected::CLK_GPOUT0_SELECT
 pub mod clk_gpout0_selected;
 #[doc = "CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout1_ctrl`]
 module"]
@@ -352,7 +352,7 @@ pub type CLK_GPOUT1_CTRL = crate::Reg<clk_gpout1_ctrl::CLK_GPOUT1_CTRL_SPEC>;
 pub mod clk_gpout1_ctrl;
 #[doc = "CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout1_div`]
 module"]
@@ -362,7 +362,7 @@ pub mod clk_gpout1_div;
 #[doc = "CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout1_selected`]
 module"]
@@ -372,7 +372,7 @@ pub type CLK_GPOUT1_SELECTED = crate::Reg<clk_gpout1_selected::CLK_GPOUT1_SELECT
 pub mod clk_gpout1_selected;
 #[doc = "CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout2_ctrl`]
 module"]
@@ -381,7 +381,7 @@ pub type CLK_GPOUT2_CTRL = crate::Reg<clk_gpout2_ctrl::CLK_GPOUT2_CTRL_SPEC>;
 pub mod clk_gpout2_ctrl;
 #[doc = "CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout2_div`]
 module"]
@@ -391,7 +391,7 @@ pub mod clk_gpout2_div;
 #[doc = "CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout2_selected`]
 module"]
@@ -401,7 +401,7 @@ pub type CLK_GPOUT2_SELECTED = crate::Reg<clk_gpout2_selected::CLK_GPOUT2_SELECT
 pub mod clk_gpout2_selected;
 #[doc = "CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout3_ctrl`]
 module"]
@@ -410,7 +410,7 @@ pub type CLK_GPOUT3_CTRL = crate::Reg<clk_gpout3_ctrl::CLK_GPOUT3_CTRL_SPEC>;
 pub mod clk_gpout3_ctrl;
 #[doc = "CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout3_div`]
 module"]
@@ -420,7 +420,7 @@ pub mod clk_gpout3_div;
 #[doc = "CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_gpout3_selected`]
 module"]
@@ -430,7 +430,7 @@ pub type CLK_GPOUT3_SELECTED = crate::Reg<clk_gpout3_selected::CLK_GPOUT3_SELECT
 pub mod clk_gpout3_selected;
 #[doc = "CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_ref_ctrl`]
 module"]
@@ -439,7 +439,7 @@ pub type CLK_REF_CTRL = crate::Reg<clk_ref_ctrl::CLK_REF_CTRL_SPEC>;
 pub mod clk_ref_ctrl;
 #[doc = "CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_ref_div`]
 module"]
@@ -449,7 +449,7 @@ pub mod clk_ref_div;
 #[doc = "CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_ref_selected`]
 module"]
@@ -459,7 +459,7 @@ pub type CLK_REF_SELECTED = crate::Reg<clk_ref_selected::CLK_REF_SELECTED_SPEC>;
 pub mod clk_ref_selected;
 #[doc = "CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_sys_ctrl`]
 module"]
@@ -468,7 +468,7 @@ pub type CLK_SYS_CTRL = crate::Reg<clk_sys_ctrl::CLK_SYS_CTRL_SPEC>;
 pub mod clk_sys_ctrl;
 #[doc = "CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_sys_div`]
 module"]
@@ -478,7 +478,7 @@ pub mod clk_sys_div;
 #[doc = "CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_sys_selected`]
 module"]
@@ -488,7 +488,7 @@ pub type CLK_SYS_SELECTED = crate::Reg<clk_sys_selected::CLK_SYS_SELECTED_SPEC>;
 pub mod clk_sys_selected;
 #[doc = "CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_peri_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_peri_ctrl`]
 module"]
@@ -498,7 +498,7 @@ pub mod clk_peri_ctrl;
 #[doc = "CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_peri_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_peri_selected`]
 module"]
@@ -508,7 +508,7 @@ pub type CLK_PERI_SELECTED = crate::Reg<clk_peri_selected::CLK_PERI_SELECTED_SPE
 pub mod clk_peri_selected;
 #[doc = "CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_usb_ctrl`]
 module"]
@@ -517,7 +517,7 @@ pub type CLK_USB_CTRL = crate::Reg<clk_usb_ctrl::CLK_USB_CTRL_SPEC>;
 pub mod clk_usb_ctrl;
 #[doc = "CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_usb_div`]
 module"]
@@ -527,7 +527,7 @@ pub mod clk_usb_div;
 #[doc = "CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_usb_selected`]
 module"]
@@ -537,7 +537,7 @@ pub type CLK_USB_SELECTED = crate::Reg<clk_usb_selected::CLK_USB_SELECTED_SPEC>;
 pub mod clk_usb_selected;
 #[doc = "CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_adc_ctrl`]
 module"]
@@ -546,7 +546,7 @@ pub type CLK_ADC_CTRL = crate::Reg<clk_adc_ctrl::CLK_ADC_CTRL_SPEC>;
 pub mod clk_adc_ctrl;
 #[doc = "CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_adc_div`]
 module"]
@@ -556,7 +556,7 @@ pub mod clk_adc_div;
 #[doc = "CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_adc_selected`]
 module"]
@@ -566,7 +566,7 @@ pub type CLK_ADC_SELECTED = crate::Reg<clk_adc_selected::CLK_ADC_SELECTED_SPEC>;
 pub mod clk_adc_selected;
 #[doc = "CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_rtc_ctrl`]
 module"]
@@ -575,7 +575,7 @@ pub type CLK_RTC_CTRL = crate::Reg<clk_rtc_ctrl::CLK_RTC_CTRL_SPEC>;
 pub mod clk_rtc_ctrl;
 #[doc = "CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rtc_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_rtc_div`]
 module"]
@@ -585,7 +585,7 @@ pub mod clk_rtc_div;
 #[doc = "CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_rtc_selected`]
 module"]
@@ -595,7 +595,7 @@ pub type CLK_RTC_SELECTED = crate::Reg<clk_rtc_selected::CLK_RTC_SELECTED_SPEC>;
 pub mod clk_rtc_selected;
 #[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor:   
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_sys_resus_ctrl`]
 module"]
@@ -604,7 +604,7 @@ pub type CLK_SYS_RESUS_CTRL = crate::Reg<clk_sys_resus_ctrl::CLK_SYS_RESUS_CTRL_
 pub mod clk_sys_resus_ctrl;
 #[doc = "CLK_SYS_RESUS_STATUS (r) register accessor:   
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clk_sys_resus_status`]
 module"]
@@ -613,7 +613,7 @@ pub type CLK_SYS_RESUS_STATUS = crate::Reg<clk_sys_resus_status::CLK_SYS_RESUS_S
 pub mod clk_sys_resus_status;
 #[doc = "FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_ref_khz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_ref_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_ref_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_ref_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_ref_khz`]
 module"]
@@ -622,7 +622,7 @@ pub type FC0_REF_KHZ = crate::Reg<fc0_ref_khz::FC0_REF_KHZ_SPEC>;
 pub mod fc0_ref_khz;
 #[doc = "FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_min_khz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_min_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_min_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_min_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_min_khz`]
 module"]
@@ -631,7 +631,7 @@ pub type FC0_MIN_KHZ = crate::Reg<fc0_min_khz::FC0_MIN_KHZ_SPEC>;
 pub mod fc0_min_khz;
 #[doc = "FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_max_khz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_max_khz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_max_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_max_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_max_khz`]
 module"]
@@ -641,7 +641,7 @@ pub mod fc0_max_khz;
 #[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle  
  Delay is measured in multiples of the reference clock period  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_delay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_delay`]
 module"]
@@ -652,7 +652,7 @@ pub mod fc0_delay;
 #[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval  
  The default gives a test interval of 250us  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_interval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_interval`]
 module"]
@@ -663,7 +663,7 @@ pub mod fc0_interval;
 #[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required  
  Writing to this register initiates the frequency count  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_src`]
 module"]
@@ -673,7 +673,7 @@ pub type FC0_SRC = crate::Reg<fc0_src::FC0_SRC_SPEC>;
 pub mod fc0_src;
 #[doc = "FC0_STATUS (r) register accessor: Frequency counter status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_status`]
 module"]
@@ -682,7 +682,7 @@ pub type FC0_STATUS = crate::Reg<fc0_status::FC0_STATUS_SPEC>;
 pub mod fc0_status;
 #[doc = "FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fc0_result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fc0_result`]
 module"]
@@ -691,7 +691,7 @@ pub type FC0_RESULT = crate::Reg<fc0_result::FC0_RESULT_SPEC>;
 pub mod fc0_result;
 #[doc = "WAKE_EN0 (rw) register accessor: enable clock in wake mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`wake_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@wake_en0`]
 module"]
@@ -700,7 +700,7 @@ pub type WAKE_EN0 = crate::Reg<wake_en0::WAKE_EN0_SPEC>;
 pub mod wake_en0;
 #[doc = "WAKE_EN1 (rw) register accessor: enable clock in wake mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`wake_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@wake_en1`]
 module"]
@@ -709,7 +709,7 @@ pub type WAKE_EN1 = crate::Reg<wake_en1::WAKE_EN1_SPEC>;
 pub mod wake_en1;
 #[doc = "SLEEP_EN0 (rw) register accessor: enable clock in sleep mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sleep_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sleep_en0`]
 module"]
@@ -718,7 +718,7 @@ pub type SLEEP_EN0 = crate::Reg<sleep_en0::SLEEP_EN0_SPEC>;
 pub mod sleep_en0;
 #[doc = "SLEEP_EN1 (rw) register accessor: enable clock in sleep mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sleep_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sleep_en1`]
 module"]
@@ -727,7 +727,7 @@ pub type SLEEP_EN1 = crate::Reg<sleep_en1::SLEEP_EN1_SPEC>;
 pub mod sleep_en1;
 #[doc = "ENABLED0 (r) register accessor: indicates the state of the clock enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`enabled0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@enabled0`]
 module"]
@@ -736,7 +736,7 @@ pub type ENABLED0 = crate::Reg<enabled0::ENABLED0_SPEC>;
 pub mod enabled0;
 #[doc = "ENABLED1 (r) register accessor: indicates the state of the clock enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`enabled1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@enabled1`]
 module"]
@@ -745,7 +745,7 @@ pub type ENABLED1 = crate::Reg<enabled1::ENABLED1_SPEC>;
 pub mod enabled1;
 #[doc = "INTR (r) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -754,7 +754,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -763,7 +763,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -772,7 +772,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs
index b22f652f0..dff8d2182 100644
--- a/src/clocks/clk_adc_ctrl.rs
+++ b/src/clocks/clk_adc_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -200,7 +201,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_ADC_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_ADC_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_adc_div.rs b/src/clocks/clk_adc_div.rs
index 3d257c5db..31cbfa450 100644
--- a/src/clocks/clk_adc_div.rs
+++ b/src/clocks/clk_adc_div.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_ADC_DIV_SPEC;
 impl crate::RegisterSpec for CLK_ADC_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_adc_selected.rs b/src/clocks/clk_adc_selected.rs
index d3b7133a4..9a65f30e5 100644
--- a/src/clocks/clk_adc_selected.rs
+++ b/src/clocks/clk_adc_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_ADC_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_adc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_ADC_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_ADC_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs
index 4edce962e..94f676cd7 100644
--- a/src/clocks/clk_gpout0_ctrl.rs
+++ b/src/clocks/clk_gpout0_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -280,7 +281,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT0_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT0_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout0_div.rs b/src/clocks/clk_gpout0_div.rs
index f96a67f2b..8bfe81479 100644
--- a/src/clocks/clk_gpout0_div.rs
+++ b/src/clocks/clk_gpout0_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT0_DIV_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT0_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout0_selected.rs b/src/clocks/clk_gpout0_selected.rs
index 461264479..0a173d811 100644
--- a/src/clocks/clk_gpout0_selected.rs
+++ b/src/clocks/clk_gpout0_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_GPOUT0_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT0_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT0_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs
index eab13e0a1..8a981d64b 100644
--- a/src/clocks/clk_gpout1_ctrl.rs
+++ b/src/clocks/clk_gpout1_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -280,7 +281,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT1_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT1_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout1_div.rs b/src/clocks/clk_gpout1_div.rs
index 3280a631c..d14ab2514 100644
--- a/src/clocks/clk_gpout1_div.rs
+++ b/src/clocks/clk_gpout1_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT1_DIV_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT1_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout1_selected.rs b/src/clocks/clk_gpout1_selected.rs
index 2735720a5..f3ec77982 100644
--- a/src/clocks/clk_gpout1_selected.rs
+++ b/src/clocks/clk_gpout1_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_GPOUT1_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT1_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT1_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs
index 25badf597..8f437198a 100644
--- a/src/clocks/clk_gpout2_ctrl.rs
+++ b/src/clocks/clk_gpout2_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -280,7 +281,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT2_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT2_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout2_div.rs b/src/clocks/clk_gpout2_div.rs
index 653b2e7fb..0d18029e3 100644
--- a/src/clocks/clk_gpout2_div.rs
+++ b/src/clocks/clk_gpout2_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT2_DIV_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT2_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout2_selected.rs b/src/clocks/clk_gpout2_selected.rs
index a479a11e8..1ad715251 100644
--- a/src/clocks/clk_gpout2_selected.rs
+++ b/src/clocks/clk_gpout2_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_GPOUT2_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT2_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT2_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs
index b5b5ed98d..45a00d83d 100644
--- a/src/clocks/clk_gpout3_ctrl.rs
+++ b/src/clocks/clk_gpout3_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -280,7 +281,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT3_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT3_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout3_div.rs b/src/clocks/clk_gpout3_div.rs
index 282846899..d26d60bc9 100644
--- a/src/clocks/clk_gpout3_div.rs
+++ b/src/clocks/clk_gpout3_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT3_DIV_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT3_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_gpout3_selected.rs b/src/clocks/clk_gpout3_selected.rs
index 7eddbc580..87d3c67c1 100644
--- a/src/clocks/clk_gpout3_selected.rs
+++ b/src/clocks/clk_gpout3_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_GPOUT3_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_GPOUT3_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_GPOUT3_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs
index 3e2ef59ee..eb1fd4d17 100644
--- a/src/clocks/clk_peri_ctrl.rs
+++ b/src/clocks/clk_peri_ctrl.rs
@@ -32,6 +32,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -175,7 +176,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_peri_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_PERI_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_PERI_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_peri_selected.rs b/src/clocks/clk_peri_selected.rs
index 414c9b912..8aca7e4af 100644
--- a/src/clocks/clk_peri_selected.rs
+++ b/src/clocks/clk_peri_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_PERI_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_peri_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_PERI_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_PERI_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs
index a81dc5705..0bef4533e 100644
--- a/src/clocks/clk_ref_ctrl.rs
+++ b/src/clocks/clk_ref_ctrl.rs
@@ -24,6 +24,7 @@ impl From<SRC_A> for u8 {
 impl crate::FieldSpec for SRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for SRC_A {}
 #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"]
 pub type SRC_R = crate::FieldReader<SRC_A>;
 impl SRC_R {
@@ -98,6 +99,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -178,7 +180,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_REF_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_REF_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_ref_div.rs b/src/clocks/clk_ref_div.rs
index 2cd4bbe79..b6aee0d81 100644
--- a/src/clocks/clk_ref_div.rs
+++ b/src/clocks/clk_ref_div.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_REF_DIV_SPEC;
 impl crate::RegisterSpec for CLK_REF_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_ref_selected.rs b/src/clocks/clk_ref_selected.rs
index e9f9a7ea6..d23ca09cc 100644
--- a/src/clocks/clk_ref_selected.rs
+++ b/src/clocks/clk_ref_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_REF_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_ref_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_REF_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_REF_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs
index 6adf1f9a7..52d12c912 100644
--- a/src/clocks/clk_rtc_ctrl.rs
+++ b/src/clocks/clk_rtc_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -200,7 +201,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rtc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_RTC_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_RTC_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_rtc_div.rs b/src/clocks/clk_rtc_div.rs
index e79f911f5..2467e1472 100644
--- a/src/clocks/clk_rtc_div.rs
+++ b/src/clocks/clk_rtc_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rtc_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_RTC_DIV_SPEC;
 impl crate::RegisterSpec for CLK_RTC_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_rtc_selected.rs b/src/clocks/clk_rtc_selected.rs
index b6d5dd9f0..3b92d899f 100644
--- a/src/clocks/clk_rtc_selected.rs
+++ b/src/clocks/clk_rtc_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_RTC_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_rtc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_RTC_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_RTC_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs
index 2a489cfbc..07a9211e4 100644
--- a/src/clocks/clk_sys_ctrl.rs
+++ b/src/clocks/clk_sys_ctrl.rs
@@ -85,6 +85,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -198,7 +199,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_SYS_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_SYS_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_sys_div.rs b/src/clocks/clk_sys_div.rs
index 0e32cc7a1..8a83e1f79 100644
--- a/src/clocks/clk_sys_div.rs
+++ b/src/clocks/clk_sys_div.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_SYS_DIV_SPEC;
 impl crate::RegisterSpec for CLK_SYS_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs
index b1551c978..4f726f708 100644
--- a/src/clocks/clk_sys_resus_ctrl.rs
+++ b/src/clocks/clk_sys_resus_ctrl.rs
@@ -72,7 +72,7 @@ impl W {
 }
 #[doc = "  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_SYS_RESUS_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_SYS_RESUS_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_sys_resus_status.rs b/src/clocks/clk_sys_resus_status.rs
index 90d4144e1..cb7be5304 100644
--- a/src/clocks/clk_sys_resus_status.rs
+++ b/src/clocks/clk_sys_resus_status.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_SYS_RESUS_STATUS_SPEC;
 impl crate::RegisterSpec for CLK_SYS_RESUS_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_sys_selected.rs b/src/clocks/clk_sys_selected.rs
index 8002b6a02..0b6c58a35 100644
--- a/src/clocks/clk_sys_selected.rs
+++ b/src/clocks/clk_sys_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_SYS_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_sys_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_SYS_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_SYS_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs
index b67c9bbb3..25e960c0d 100644
--- a/src/clocks/clk_usb_ctrl.rs
+++ b/src/clocks/clk_usb_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {
@@ -200,7 +201,7 @@ impl W {
 }
 #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_USB_CTRL_SPEC;
 impl crate::RegisterSpec for CLK_USB_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_usb_div.rs b/src/clocks/clk_usb_div.rs
index 5fec1d8e0..70bf4be74 100644
--- a/src/clocks/clk_usb_div.rs
+++ b/src/clocks/clk_usb_div.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Clock divisor, can be changed on-the-fly  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_USB_DIV_SPEC;
 impl crate::RegisterSpec for CLK_USB_DIV_SPEC {
     type Ux = u32;
diff --git a/src/clocks/clk_usb_selected.rs b/src/clocks/clk_usb_selected.rs
index ade608791..a51eaa0e9 100644
--- a/src/clocks/clk_usb_selected.rs
+++ b/src/clocks/clk_usb_selected.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CLK_USB_SELECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot).  
  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clk_usb_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_USB_SELECTED_SPEC;
 impl crate::RegisterSpec for CLK_USB_SELECTED_SPEC {
     type Ux = u32;
diff --git a/src/clocks/enabled0.rs b/src/clocks/enabled0.rs
index cb44fc420..f7e014150 100644
--- a/src/clocks/enabled0.rs
+++ b/src/clocks/enabled0.rs
@@ -228,7 +228,7 @@ impl R {
 }
 #[doc = "indicates the state of the clock enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`enabled0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ENABLED0_SPEC;
 impl crate::RegisterSpec for ENABLED0_SPEC {
     type Ux = u32;
diff --git a/src/clocks/enabled1.rs b/src/clocks/enabled1.rs
index 3db69c4a2..6574960c1 100644
--- a/src/clocks/enabled1.rs
+++ b/src/clocks/enabled1.rs
@@ -109,7 +109,7 @@ impl R {
 }
 #[doc = "indicates the state of the clock enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`enabled1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ENABLED1_SPEC;
 impl crate::RegisterSpec for ENABLED1_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs
index de0b8cf10..8eba16758 100644
--- a/src/clocks/fc0_delay.rs
+++ b/src/clocks/fc0_delay.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Delays the start of frequency counting to allow the mux to settle  
  Delay is measured in multiples of the reference clock period  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_delay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_DELAY_SPEC;
 impl crate::RegisterSpec for FC0_DELAY_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs
index 596f6a01b..f93d54bd2 100644
--- a/src/clocks/fc0_interval.rs
+++ b/src/clocks/fc0_interval.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval  
  The default gives a test interval of 250us  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_interval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_interval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_INTERVAL_SPEC;
 impl crate::RegisterSpec for FC0_INTERVAL_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_max_khz.rs b/src/clocks/fc0_max_khz.rs
index f52c4bf84..73cb959bb 100644
--- a/src/clocks/fc0_max_khz.rs
+++ b/src/clocks/fc0_max_khz.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_max_khz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_max_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_max_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_max_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_MAX_KHZ_SPEC;
 impl crate::RegisterSpec for FC0_MAX_KHZ_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_min_khz.rs b/src/clocks/fc0_min_khz.rs
index 93c5c41f6..55d4d4986 100644
--- a/src/clocks/fc0_min_khz.rs
+++ b/src/clocks/fc0_min_khz.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_min_khz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_min_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_min_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_min_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_MIN_KHZ_SPEC;
 impl crate::RegisterSpec for FC0_MIN_KHZ_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_ref_khz.rs b/src/clocks/fc0_ref_khz.rs
index 74a091f9b..2390238ce 100644
--- a/src/clocks/fc0_ref_khz.rs
+++ b/src/clocks/fc0_ref_khz.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Reference clock frequency in kHz  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_ref_khz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_ref_khz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_ref_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_ref_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_REF_KHZ_SPEC;
 impl crate::RegisterSpec for FC0_REF_KHZ_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_result.rs b/src/clocks/fc0_result.rs
index b135bee61..97a523e01 100644
--- a/src/clocks/fc0_result.rs
+++ b/src/clocks/fc0_result.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Result of frequency measurement, only valid when status_done=1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_RESULT_SPEC;
 impl crate::RegisterSpec for FC0_RESULT_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs
index bfcf72e23..aee2bbae3 100644
--- a/src/clocks/fc0_src.rs
+++ b/src/clocks/fc0_src.rs
@@ -46,6 +46,7 @@ impl From<FC0_SRC_A> for u8 {
 impl crate::FieldSpec for FC0_SRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FC0_SRC_A {}
 #[doc = "Field `FC0_SRC` reader - "]
 pub type FC0_SRC_R = crate::FieldReader<FC0_SRC_A>;
 impl FC0_SRC_R {
@@ -237,7 +238,7 @@ impl W {
 #[doc = "Clock sent to frequency counter, set to 0 when not required  
  Writing to this register initiates the frequency count  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_SRC_SPEC;
 impl crate::RegisterSpec for FC0_SRC_SPEC {
     type Ux = u32;
diff --git a/src/clocks/fc0_status.rs b/src/clocks/fc0_status.rs
index 6d65590f6..17d2f01a5 100644
--- a/src/clocks/fc0_status.rs
+++ b/src/clocks/fc0_status.rs
@@ -60,7 +60,7 @@ impl R {
 }
 #[doc = "Frequency counter status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fc0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FC0_STATUS_SPEC;
 impl crate::RegisterSpec for FC0_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/clocks/inte.rs b/src/clocks/inte.rs
index cf327c382..9338abd07 100644
--- a/src/clocks/inte.rs
+++ b/src/clocks/inte.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/clocks/intf.rs b/src/clocks/intf.rs
index 4737fa057..662ebd89c 100644
--- a/src/clocks/intf.rs
+++ b/src/clocks/intf.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/clocks/intr.rs b/src/clocks/intr.rs
index e277eca51..219a0cafc 100644
--- a/src/clocks/intr.rs
+++ b/src/clocks/intr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/clocks/ints.rs b/src/clocks/ints.rs
index 4b65451ca..7a2362bc3 100644
--- a/src/clocks/ints.rs
+++ b/src/clocks/ints.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs
index 5104a40f9..f2680595f 100644
--- a/src/clocks/sleep_en0.rs
+++ b/src/clocks/sleep_en0.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "enable clock in sleep mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sleep_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLEEP_EN0_SPEC;
 impl crate::RegisterSpec for SLEEP_EN0_SPEC {
     type Ux = u32;
diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs
index cd786cf31..5f92b9096 100644
--- a/src/clocks/sleep_en1.rs
+++ b/src/clocks/sleep_en1.rs
@@ -233,7 +233,7 @@ impl W {
 }
 #[doc = "enable clock in sleep mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sleep_en1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sleep_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLEEP_EN1_SPEC;
 impl crate::RegisterSpec for SLEEP_EN1_SPEC {
     type Ux = u32;
diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs
index b1c0edb48..84d35b10d 100644
--- a/src/clocks/wake_en0.rs
+++ b/src/clocks/wake_en0.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "enable clock in wake mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wake_en0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`wake_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WAKE_EN0_SPEC;
 impl crate::RegisterSpec for WAKE_EN0_SPEC {
     type Ux = u32;
diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs
index 9e4eca31a..f6e68bbfe 100644
--- a/src/clocks/wake_en1.rs
+++ b/src/clocks/wake_en1.rs
@@ -233,7 +233,7 @@ impl W {
 }
 #[doc = "enable clock in wake mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wake_en1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`wake_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WAKE_EN1_SPEC;
 impl crate::RegisterSpec for WAKE_EN1_SPEC {
     type Ux = u32;
diff --git a/src/dma.rs b/src/dma.rs
index 388108620..1bfc8cf11 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -289,7 +289,7 @@ pub use self::ch::CH;
 pub mod ch;
 #[doc = "INTR (rw) register accessor: Interrupt Status (raw)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -298,7 +298,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE0 (rw) register accessor: Interrupt Enables for IRQ 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte0`]
 module"]
@@ -307,7 +307,7 @@ pub type INTE0 = crate::Reg<inte0::INTE0_SPEC>;
 pub mod inte0;
 #[doc = "INTF0 (rw) register accessor: Force Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf0`]
 module"]
@@ -316,7 +316,7 @@ pub type INTF0 = crate::Reg<intf0::INTF0_SPEC>;
 pub mod intf0;
 #[doc = "INTS0 (rw) register accessor: Interrupt Status for IRQ 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints0`]
 module"]
@@ -325,7 +325,7 @@ pub type INTS0 = crate::Reg<ints0::INTS0_SPEC>;
 pub mod ints0;
 #[doc = "INTE1 (rw) register accessor: Interrupt Enables for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte1`]
 module"]
@@ -334,7 +334,7 @@ pub type INTE1 = crate::Reg<inte1::INTE1_SPEC>;
 pub mod inte1;
 #[doc = "INTF1 (rw) register accessor: Force Interrupts for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf1`]
 module"]
@@ -343,7 +343,7 @@ pub type INTF1 = crate::Reg<intf1::INTF1_SPEC>;
 pub mod intf1;
 #[doc = "INTS1 (rw) register accessor: Interrupt Status (masked) for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints1`]
 module"]
@@ -353,7 +353,7 @@ pub mod ints1;
 #[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timer0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timer0`]
 module"]
@@ -364,7 +364,7 @@ pub mod timer0;
 #[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timer1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timer1`]
 module"]
@@ -375,7 +375,7 @@ pub mod timer1;
 #[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timer2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timer2`]
 module"]
@@ -386,7 +386,7 @@ pub mod timer2;
 #[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timer3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timer3`]
 module"]
@@ -396,7 +396,7 @@ pub type TIMER3 = crate::Reg<timer3::TIMER3_SPEC>;
 pub mod timer3;
 #[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`multi_chan_trigger::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`multi_chan_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`multi_chan_trigger::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`multi_chan_trigger::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@multi_chan_trigger`]
 module"]
@@ -405,7 +405,7 @@ pub type MULTI_CHAN_TRIGGER = crate::Reg<multi_chan_trigger::MULTI_CHAN_TRIGGER_
 pub mod multi_chan_trigger;
 #[doc = "SNIFF_CTRL (rw) register accessor: Sniffer Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sniff_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sniff_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sniff_ctrl`]
 module"]
@@ -415,7 +415,7 @@ pub mod sniff_ctrl;
 #[doc = "SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware  
  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sniff_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sniff_data`]
 module"]
@@ -425,7 +425,7 @@ pub type SNIFF_DATA = crate::Reg<sniff_data::SNIFF_DATA_SPEC>;
 pub mod sniff_data;
 #[doc = "FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fifo_levels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo_levels`]
 module"]
@@ -434,7 +434,7 @@ pub type FIFO_LEVELS = crate::Reg<fifo_levels::FIFO_LEVELS_SPEC>;
 pub mod fifo_levels;
 #[doc = "CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chan_abort::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`chan_abort::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chan_abort::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@chan_abort`]
 module"]
@@ -443,7 +443,7 @@ pub type CHAN_ABORT = crate::Reg<chan_abort::CHAN_ABORT_SPEC>;
 pub mod chan_abort;
 #[doc = "N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`n_channels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@n_channels`]
 module"]
@@ -452,7 +452,7 @@ pub type N_CHANNELS = crate::Reg<n_channels::N_CHANNELS_SPEC>;
 pub mod n_channels;
 #[doc = "CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch0_dbg_ctdreq`]
 module"]
@@ -461,7 +461,7 @@ pub type CH0_DBG_CTDREQ = crate::Reg<ch0_dbg_ctdreq::CH0_DBG_CTDREQ_SPEC>;
 pub mod ch0_dbg_ctdreq;
 #[doc = "CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch0_dbg_tcr`]
 module"]
@@ -470,7 +470,7 @@ pub type CH0_DBG_TCR = crate::Reg<ch0_dbg_tcr::CH0_DBG_TCR_SPEC>;
 pub mod ch0_dbg_tcr;
 #[doc = "CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch1_dbg_ctdreq`]
 module"]
@@ -479,7 +479,7 @@ pub type CH1_DBG_CTDREQ = crate::Reg<ch1_dbg_ctdreq::CH1_DBG_CTDREQ_SPEC>;
 pub mod ch1_dbg_ctdreq;
 #[doc = "CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch1_dbg_tcr`]
 module"]
@@ -488,7 +488,7 @@ pub type CH1_DBG_TCR = crate::Reg<ch1_dbg_tcr::CH1_DBG_TCR_SPEC>;
 pub mod ch1_dbg_tcr;
 #[doc = "CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch2_dbg_ctdreq`]
 module"]
@@ -497,7 +497,7 @@ pub type CH2_DBG_CTDREQ = crate::Reg<ch2_dbg_ctdreq::CH2_DBG_CTDREQ_SPEC>;
 pub mod ch2_dbg_ctdreq;
 #[doc = "CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch2_dbg_tcr`]
 module"]
@@ -506,7 +506,7 @@ pub type CH2_DBG_TCR = crate::Reg<ch2_dbg_tcr::CH2_DBG_TCR_SPEC>;
 pub mod ch2_dbg_tcr;
 #[doc = "CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch3_dbg_ctdreq`]
 module"]
@@ -515,7 +515,7 @@ pub type CH3_DBG_CTDREQ = crate::Reg<ch3_dbg_ctdreq::CH3_DBG_CTDREQ_SPEC>;
 pub mod ch3_dbg_ctdreq;
 #[doc = "CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch3_dbg_tcr`]
 module"]
@@ -524,7 +524,7 @@ pub type CH3_DBG_TCR = crate::Reg<ch3_dbg_tcr::CH3_DBG_TCR_SPEC>;
 pub mod ch3_dbg_tcr;
 #[doc = "CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch4_dbg_ctdreq`]
 module"]
@@ -533,7 +533,7 @@ pub type CH4_DBG_CTDREQ = crate::Reg<ch4_dbg_ctdreq::CH4_DBG_CTDREQ_SPEC>;
 pub mod ch4_dbg_ctdreq;
 #[doc = "CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch4_dbg_tcr`]
 module"]
@@ -542,7 +542,7 @@ pub type CH4_DBG_TCR = crate::Reg<ch4_dbg_tcr::CH4_DBG_TCR_SPEC>;
 pub mod ch4_dbg_tcr;
 #[doc = "CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch5_dbg_ctdreq`]
 module"]
@@ -551,7 +551,7 @@ pub type CH5_DBG_CTDREQ = crate::Reg<ch5_dbg_ctdreq::CH5_DBG_CTDREQ_SPEC>;
 pub mod ch5_dbg_ctdreq;
 #[doc = "CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch5_dbg_tcr`]
 module"]
@@ -560,7 +560,7 @@ pub type CH5_DBG_TCR = crate::Reg<ch5_dbg_tcr::CH5_DBG_TCR_SPEC>;
 pub mod ch5_dbg_tcr;
 #[doc = "CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch6_dbg_ctdreq`]
 module"]
@@ -569,7 +569,7 @@ pub type CH6_DBG_CTDREQ = crate::Reg<ch6_dbg_ctdreq::CH6_DBG_CTDREQ_SPEC>;
 pub mod ch6_dbg_ctdreq;
 #[doc = "CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch6_dbg_tcr`]
 module"]
@@ -578,7 +578,7 @@ pub type CH6_DBG_TCR = crate::Reg<ch6_dbg_tcr::CH6_DBG_TCR_SPEC>;
 pub mod ch6_dbg_tcr;
 #[doc = "CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch7_dbg_ctdreq`]
 module"]
@@ -587,7 +587,7 @@ pub type CH7_DBG_CTDREQ = crate::Reg<ch7_dbg_ctdreq::CH7_DBG_CTDREQ_SPEC>;
 pub mod ch7_dbg_ctdreq;
 #[doc = "CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch7_dbg_tcr`]
 module"]
@@ -596,7 +596,7 @@ pub type CH7_DBG_TCR = crate::Reg<ch7_dbg_tcr::CH7_DBG_TCR_SPEC>;
 pub mod ch7_dbg_tcr;
 #[doc = "CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch8_dbg_ctdreq`]
 module"]
@@ -605,7 +605,7 @@ pub type CH8_DBG_CTDREQ = crate::Reg<ch8_dbg_ctdreq::CH8_DBG_CTDREQ_SPEC>;
 pub mod ch8_dbg_ctdreq;
 #[doc = "CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch8_dbg_tcr`]
 module"]
@@ -614,7 +614,7 @@ pub type CH8_DBG_TCR = crate::Reg<ch8_dbg_tcr::CH8_DBG_TCR_SPEC>;
 pub mod ch8_dbg_tcr;
 #[doc = "CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch9_dbg_ctdreq`]
 module"]
@@ -623,7 +623,7 @@ pub type CH9_DBG_CTDREQ = crate::Reg<ch9_dbg_ctdreq::CH9_DBG_CTDREQ_SPEC>;
 pub mod ch9_dbg_ctdreq;
 #[doc = "CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch9_dbg_tcr`]
 module"]
@@ -632,7 +632,7 @@ pub type CH9_DBG_TCR = crate::Reg<ch9_dbg_tcr::CH9_DBG_TCR_SPEC>;
 pub mod ch9_dbg_tcr;
 #[doc = "CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch10_dbg_ctdreq`]
 module"]
@@ -641,7 +641,7 @@ pub type CH10_DBG_CTDREQ = crate::Reg<ch10_dbg_ctdreq::CH10_DBG_CTDREQ_SPEC>;
 pub mod ch10_dbg_ctdreq;
 #[doc = "CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch10_dbg_tcr`]
 module"]
@@ -650,7 +650,7 @@ pub type CH10_DBG_TCR = crate::Reg<ch10_dbg_tcr::CH10_DBG_TCR_SPEC>;
 pub mod ch10_dbg_tcr;
 #[doc = "CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_ctdreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch11_dbg_ctdreq`]
 module"]
@@ -659,7 +659,7 @@ pub type CH11_DBG_CTDREQ = crate::Reg<ch11_dbg_ctdreq::CH11_DBG_CTDREQ_SPEC>;
 pub mod ch11_dbg_ctdreq;
 #[doc = "CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch11_dbg_tcr`]
 module"]
diff --git a/src/dma/ch.rs b/src/dma/ch.rs
index d00408bfd..ce1523eaf 100644
--- a/src/dma/ch.rs
+++ b/src/dma/ch.rs
@@ -118,7 +118,7 @@ impl CH {
 #[doc = "CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer  
  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_read_addr`]
 module"]
@@ -129,7 +129,7 @@ pub mod ch_read_addr;
 #[doc = "CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer  
  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_write_addr`]
 module"]
@@ -146,7 +146,7 @@ pub mod ch_write_addr;
 
  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_trans_count`]
 module"]
@@ -162,7 +162,7 @@ pub type CH_TRANS_COUNT = crate::Reg<ch_trans_count::CH_TRANS_COUNT_SPEC>;
 pub mod ch_trans_count;
 #[doc = "CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_ctrl_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_ctrl_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_ctrl_trig`]
 module"]
@@ -171,7 +171,7 @@ pub type CH_CTRL_TRIG = crate::Reg<ch_ctrl_trig::CH_CTRL_TRIG_SPEC>;
 pub mod ch_ctrl_trig;
 #[doc = "CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al1_ctrl`]
 module"]
@@ -180,7 +180,7 @@ pub type CH_AL1_CTRL = crate::Reg<ch_al1_ctrl::CH_AL1_CTRL_SPEC>;
 pub mod ch_al1_ctrl;
 #[doc = "CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al1_read_addr`]
 module"]
@@ -189,7 +189,7 @@ pub type CH_AL1_READ_ADDR = crate::Reg<ch_al1_read_addr::CH_AL1_READ_ADDR_SPEC>;
 pub mod ch_al1_read_addr;
 #[doc = "CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al1_write_addr`]
 module"]
@@ -200,7 +200,7 @@ pub mod ch_al1_write_addr;
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_trans_count_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al1_trans_count_trig`]
 module"]
@@ -212,7 +212,7 @@ pub type CH_AL1_TRANS_COUNT_TRIG =
 pub mod ch_al1_trans_count_trig;
 #[doc = "CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al2_ctrl`]
 module"]
@@ -221,7 +221,7 @@ pub type CH_AL2_CTRL = crate::Reg<ch_al2_ctrl::CH_AL2_CTRL_SPEC>;
 pub mod ch_al2_ctrl;
 #[doc = "CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al2_trans_count`]
 module"]
@@ -230,7 +230,7 @@ pub type CH_AL2_TRANS_COUNT = crate::Reg<ch_al2_trans_count::CH_AL2_TRANS_COUNT_
 pub mod ch_al2_trans_count;
 #[doc = "CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al2_read_addr`]
 module"]
@@ -241,7 +241,7 @@ pub mod ch_al2_read_addr;
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_write_addr_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al2_write_addr_trig`]
 module"]
@@ -252,7 +252,7 @@ pub type CH_AL2_WRITE_ADDR_TRIG = crate::Reg<ch_al2_write_addr_trig::CH_AL2_WRIT
 pub mod ch_al2_write_addr_trig;
 #[doc = "CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al3_ctrl`]
 module"]
@@ -261,7 +261,7 @@ pub type CH_AL3_CTRL = crate::Reg<ch_al3_ctrl::CH_AL3_CTRL_SPEC>;
 pub mod ch_al3_ctrl;
 #[doc = "CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al3_write_addr`]
 module"]
@@ -270,7 +270,7 @@ pub type CH_AL3_WRITE_ADDR = crate::Reg<ch_al3_write_addr::CH_AL3_WRITE_ADDR_SPE
 pub mod ch_al3_write_addr;
 #[doc = "CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al3_trans_count`]
 module"]
@@ -281,7 +281,7 @@ pub mod ch_al3_trans_count;
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_read_addr_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ch_al3_read_addr_trig`]
 module"]
diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs
index 36865c3d9..f0fff2134 100644
--- a/src/dma/ch/ch_al1_ctrl.rs
+++ b/src/dma/ch/ch_al1_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]
@@ -1050,7 +1053,7 @@ impl W {
 }
 #[doc = "DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL1_CTRL_SPEC;
 impl crate::RegisterSpec for CH_AL1_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/dma/ch/ch_al1_read_addr.rs
index 006c80538..6e9f8c3c0 100644
--- a/src/dma/ch/ch_al1_read_addr.rs
+++ b/src/dma/ch/ch_al1_read_addr.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL1_READ_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 READ_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL1_READ_ADDR_SPEC;
 impl crate::RegisterSpec for CH_AL1_READ_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/dma/ch/ch_al1_trans_count_trig.rs
index 37ed300d8..6e5ce17bf 100644
--- a/src/dma/ch/ch_al1_trans_count_trig.rs
+++ b/src/dma/ch/ch_al1_trans_count_trig.rs
@@ -7,17 +7,12 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL1_TRANS_COUNT_TRIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 TRANS_COUNT register  
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_trans_count_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL1_TRANS_COUNT_TRIG_SPEC;
 impl crate::RegisterSpec for CH_AL1_TRANS_COUNT_TRIG_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/dma/ch/ch_al1_write_addr.rs
index 749156fec..4de373bf0 100644
--- a/src/dma/ch/ch_al1_write_addr.rs
+++ b/src/dma/ch/ch_al1_write_addr.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL1_WRITE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 WRITE_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al1_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL1_WRITE_ADDR_SPEC;
 impl crate::RegisterSpec for CH_AL1_WRITE_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs
index dcf6e4082..d6d5fd59c 100644
--- a/src/dma/ch/ch_al2_ctrl.rs
+++ b/src/dma/ch/ch_al2_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]
@@ -1050,7 +1053,7 @@ impl W {
 }
 #[doc = "DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL2_CTRL_SPEC;
 impl crate::RegisterSpec for CH_AL2_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/dma/ch/ch_al2_read_addr.rs
index 0dd73092b..9b48fb391 100644
--- a/src/dma/ch/ch_al2_read_addr.rs
+++ b/src/dma/ch/ch_al2_read_addr.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL2_READ_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 READ_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL2_READ_ADDR_SPEC;
 impl crate::RegisterSpec for CH_AL2_READ_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/dma/ch/ch_al2_trans_count.rs
index 2053f2ddb..6ae8fb381 100644
--- a/src/dma/ch/ch_al2_trans_count.rs
+++ b/src/dma/ch/ch_al2_trans_count.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL2_TRANS_COUNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 TRANS_COUNT register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL2_TRANS_COUNT_SPEC;
 impl crate::RegisterSpec for CH_AL2_TRANS_COUNT_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/dma/ch/ch_al2_write_addr_trig.rs
index a3b75870c..44c70714e 100644
--- a/src/dma/ch/ch_al2_write_addr_trig.rs
+++ b/src/dma/ch/ch_al2_write_addr_trig.rs
@@ -7,17 +7,12 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL2_WRITE_ADDR_TRIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 WRITE_ADDR register  
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al2_write_addr_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL2_WRITE_ADDR_TRIG_SPEC;
 impl crate::RegisterSpec for CH_AL2_WRITE_ADDR_TRIG_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs
index f4ea5fd08..2c0dad843 100644
--- a/src/dma/ch/ch_al3_ctrl.rs
+++ b/src/dma/ch/ch_al3_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]
@@ -1050,7 +1053,7 @@ impl W {
 }
 #[doc = "DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL3_CTRL_SPEC;
 impl crate::RegisterSpec for CH_AL3_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/dma/ch/ch_al3_read_addr_trig.rs
index ce54935ae..f5f801350 100644
--- a/src/dma/ch/ch_al3_read_addr_trig.rs
+++ b/src/dma/ch/ch_al3_read_addr_trig.rs
@@ -7,17 +7,12 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL3_READ_ADDR_TRIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 READ_ADDR register  
  This is a trigger register (0xc). Writing a nonzero value will  
  reload the channel counter and start the channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_read_addr_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL3_READ_ADDR_TRIG_SPEC;
 impl crate::RegisterSpec for CH_AL3_READ_ADDR_TRIG_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/dma/ch/ch_al3_trans_count.rs
index 7cef663be..c72320eb1 100644
--- a/src/dma/ch/ch_al3_trans_count.rs
+++ b/src/dma/ch/ch_al3_trans_count.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL3_TRANS_COUNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 TRANS_COUNT register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL3_TRANS_COUNT_SPEC;
 impl crate::RegisterSpec for CH_AL3_TRANS_COUNT_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/dma/ch/ch_al3_write_addr.rs
index d69813fe0..9b24f4f25 100644
--- a/src/dma/ch/ch_al3_write_addr.rs
+++ b/src/dma/ch/ch_al3_write_addr.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_AL3_WRITE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Alias for channel 0 WRITE_ADDR register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_al3_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_AL3_WRITE_ADDR_SPEC;
 impl crate::RegisterSpec for CH_AL3_WRITE_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs
index af5e735ef..e1166ffc7 100644
--- a/src/dma/ch/ch_ctrl_trig.rs
+++ b/src/dma/ch/ch_ctrl_trig.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]
@@ -1050,7 +1053,7 @@ impl W {
 }
 #[doc = "DMA Channel 0 Control and Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_ctrl_trig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_ctrl_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_CTRL_TRIG_SPEC;
 impl crate::RegisterSpec for CH_CTRL_TRIG_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_read_addr.rs b/src/dma/ch/ch_read_addr.rs
index f40b0adec..1d6155c98 100644
--- a/src/dma/ch/ch_read_addr.rs
+++ b/src/dma/ch/ch_read_addr.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_READ_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "DMA Channel 0 Read Address pointer  
  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_READ_ADDR_SPEC;
 impl crate::RegisterSpec for CH_READ_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_trans_count.rs b/src/dma/ch/ch_trans_count.rs
index 0868b3baa..44ad3a75d 100644
--- a/src/dma/ch/ch_trans_count.rs
+++ b/src/dma/ch/ch_trans_count.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_TRANS_COUNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "DMA Channel 0 Transfer Count  
  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).  
@@ -22,7 +17,7 @@ impl W {}
 
  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_TRANS_COUNT_SPEC;
 impl crate::RegisterSpec for CH_TRANS_COUNT_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch/ch_write_addr.rs b/src/dma/ch/ch_write_addr.rs
index 2aef1f437..51c519b2e 100644
--- a/src/dma/ch/ch_write_addr.rs
+++ b/src/dma/ch/ch_write_addr.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH_WRITE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "DMA Channel 0 Write Address pointer  
  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_WRITE_ADDR_SPEC;
 impl crate::RegisterSpec for CH_WRITE_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/dma/ch0_dbg_ctdreq.rs
index 94a4c0e31..ec7ad62dd 100644
--- a/src/dma/ch0_dbg_ctdreq.rs
+++ b/src/dma/ch0_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH0_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH0_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch0_dbg_tcr.rs b/src/dma/ch0_dbg_tcr.rs
index 6678dbc78..a15ccdff9 100644
--- a/src/dma/ch0_dbg_tcr.rs
+++ b/src/dma/ch0_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH0_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH0_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH0_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/dma/ch10_dbg_ctdreq.rs
index 354170fe0..cbb3bda68 100644
--- a/src/dma/ch10_dbg_ctdreq.rs
+++ b/src/dma/ch10_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH10_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH10_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch10_dbg_tcr.rs b/src/dma/ch10_dbg_tcr.rs
index 446be4624..ce1ac116c 100644
--- a/src/dma/ch10_dbg_tcr.rs
+++ b/src/dma/ch10_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH10_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH10_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH10_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/dma/ch11_dbg_ctdreq.rs
index 4bc819302..c0ba0f22a 100644
--- a/src/dma/ch11_dbg_ctdreq.rs
+++ b/src/dma/ch11_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH11_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH11_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch11_dbg_tcr.rs b/src/dma/ch11_dbg_tcr.rs
index a69c787ff..18ae7a541 100644
--- a/src/dma/ch11_dbg_tcr.rs
+++ b/src/dma/ch11_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH11_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH11_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH11_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/dma/ch1_dbg_ctdreq.rs
index 4f4482b5f..76305bd54 100644
--- a/src/dma/ch1_dbg_ctdreq.rs
+++ b/src/dma/ch1_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH1_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH1_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch1_dbg_tcr.rs b/src/dma/ch1_dbg_tcr.rs
index f7646ddc9..67537ebe4 100644
--- a/src/dma/ch1_dbg_tcr.rs
+++ b/src/dma/ch1_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH1_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH1_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH1_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/dma/ch2_dbg_ctdreq.rs
index 8217bf82c..0f5bb657b 100644
--- a/src/dma/ch2_dbg_ctdreq.rs
+++ b/src/dma/ch2_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH2_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH2_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch2_dbg_tcr.rs b/src/dma/ch2_dbg_tcr.rs
index 3ba047943..7046db407 100644
--- a/src/dma/ch2_dbg_tcr.rs
+++ b/src/dma/ch2_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH2_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH2_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH2_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/dma/ch3_dbg_ctdreq.rs
index 3565fef13..3427fdeb5 100644
--- a/src/dma/ch3_dbg_ctdreq.rs
+++ b/src/dma/ch3_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH3_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH3_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch3_dbg_tcr.rs b/src/dma/ch3_dbg_tcr.rs
index 14336b066..e06628616 100644
--- a/src/dma/ch3_dbg_tcr.rs
+++ b/src/dma/ch3_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH3_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH3_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH3_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/dma/ch4_dbg_ctdreq.rs
index 670efba69..8adbc244c 100644
--- a/src/dma/ch4_dbg_ctdreq.rs
+++ b/src/dma/ch4_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH4_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH4_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch4_dbg_tcr.rs b/src/dma/ch4_dbg_tcr.rs
index d505fc107..e6ca66941 100644
--- a/src/dma/ch4_dbg_tcr.rs
+++ b/src/dma/ch4_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH4_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH4_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH4_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/dma/ch5_dbg_ctdreq.rs
index 60c56b0b9..e13044b47 100644
--- a/src/dma/ch5_dbg_ctdreq.rs
+++ b/src/dma/ch5_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH5_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH5_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch5_dbg_tcr.rs b/src/dma/ch5_dbg_tcr.rs
index e6c36ad63..d93c3e562 100644
--- a/src/dma/ch5_dbg_tcr.rs
+++ b/src/dma/ch5_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH5_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH5_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH5_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/dma/ch6_dbg_ctdreq.rs
index f97bfbd5b..ec820b385 100644
--- a/src/dma/ch6_dbg_ctdreq.rs
+++ b/src/dma/ch6_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH6_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH6_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch6_dbg_tcr.rs b/src/dma/ch6_dbg_tcr.rs
index a522ebdcf..c8e0bd654 100644
--- a/src/dma/ch6_dbg_tcr.rs
+++ b/src/dma/ch6_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH6_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH6_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH6_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/dma/ch7_dbg_ctdreq.rs
index 59b87fd7f..c83561aab 100644
--- a/src/dma/ch7_dbg_ctdreq.rs
+++ b/src/dma/ch7_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH7_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH7_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch7_dbg_tcr.rs b/src/dma/ch7_dbg_tcr.rs
index e85acab52..4ebcb96c1 100644
--- a/src/dma/ch7_dbg_tcr.rs
+++ b/src/dma/ch7_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH7_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH7_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH7_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/dma/ch8_dbg_ctdreq.rs
index 87d191d6c..8ba03d549 100644
--- a/src/dma/ch8_dbg_ctdreq.rs
+++ b/src/dma/ch8_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH8_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH8_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch8_dbg_tcr.rs b/src/dma/ch8_dbg_tcr.rs
index 74ee9a4c4..7e252c701 100644
--- a/src/dma/ch8_dbg_tcr.rs
+++ b/src/dma/ch8_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH8_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH8_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH8_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/dma/ch9_dbg_ctdreq.rs
index 8e1f5a499..8017e5ca4 100644
--- a/src/dma/ch9_dbg_ctdreq.rs
+++ b/src/dma/ch9_dbg_ctdreq.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_ctdreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH9_DBG_CTDREQ_SPEC;
 impl crate::RegisterSpec for CH9_DBG_CTDREQ_SPEC {
     type Ux = u32;
diff --git a/src/dma/ch9_dbg_tcr.rs b/src/dma/ch9_dbg_tcr.rs
index 02a6dd942..628324ed6 100644
--- a/src/dma/ch9_dbg_tcr.rs
+++ b/src/dma/ch9_dbg_tcr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CH9_DBG_TCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH9_DBG_TCR_SPEC;
 impl crate::RegisterSpec for CH9_DBG_TCR_SPEC {
     type Ux = u32;
diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs
index 82c47ba6b..f085682d7 100644
--- a/src/dma/chan_abort.rs
+++ b/src/dma/chan_abort.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Abort an in-progress transfer sequence on one or more channels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chan_abort::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_abort::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`chan_abort::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chan_abort::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHAN_ABORT_SPEC;
 impl crate::RegisterSpec for CHAN_ABORT_SPEC {
     type Ux = u32;
diff --git a/src/dma/fifo_levels.rs b/src/dma/fifo_levels.rs
index 19224ce00..7e5a75b83 100644
--- a/src/dma/fifo_levels.rs
+++ b/src/dma/fifo_levels.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "Debug RAF, WAF, TDF levels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fifo_levels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_LEVELS_SPEC;
 impl crate::RegisterSpec for FIFO_LEVELS_SPEC {
     type Ux = u32;
diff --git a/src/dma/inte0.rs b/src/dma/inte0.rs
index 0d431a47a..238632c88 100644
--- a/src/dma/inte0.rs
+++ b/src/dma/inte0.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Enables for IRQ 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE0_SPEC;
 impl crate::RegisterSpec for INTE0_SPEC {
     type Ux = u32;
diff --git a/src/dma/inte1.rs b/src/dma/inte1.rs
index b294bfcbf..49a8872e4 100644
--- a/src/dma/inte1.rs
+++ b/src/dma/inte1.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Enables for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE1_SPEC;
 impl crate::RegisterSpec for INTE1_SPEC {
     type Ux = u32;
diff --git a/src/dma/intf0.rs b/src/dma/intf0.rs
index 2a99c3050..b8fb45aa5 100644
--- a/src/dma/intf0.rs
+++ b/src/dma/intf0.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Force Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF0_SPEC;
 impl crate::RegisterSpec for INTF0_SPEC {
     type Ux = u32;
diff --git a/src/dma/intf1.rs b/src/dma/intf1.rs
index d79d3bac4..13fbc9281 100644
--- a/src/dma/intf1.rs
+++ b/src/dma/intf1.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Force Interrupts for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF1_SPEC;
 impl crate::RegisterSpec for INTF1_SPEC {
     type Ux = u32;
diff --git a/src/dma/intr.rs b/src/dma/intr.rs
index c84d7c909..9ad684ff9 100644
--- a/src/dma/intr.rs
+++ b/src/dma/intr.rs
@@ -47,7 +47,7 @@ impl W {
 }
 #[doc = "Interrupt Status (raw)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs
index 994a68e80..b80352563 100644
--- a/src/dma/ints0.rs
+++ b/src/dma/ints0.rs
@@ -27,7 +27,7 @@ impl W {
 }
 #[doc = "Interrupt Status for IRQ 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS0_SPEC;
 impl crate::RegisterSpec for INTS0_SPEC {
     type Ux = u32;
diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs
index 78beebea6..e7f3f9afd 100644
--- a/src/dma/ints1.rs
+++ b/src/dma/ints1.rs
@@ -27,7 +27,7 @@ impl W {
 }
 #[doc = "Interrupt Status (masked) for IRQ 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS1_SPEC;
 impl crate::RegisterSpec for INTS1_SPEC {
     type Ux = u32;
diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs
index 0eb8b0e67..32af7a2fc 100644
--- a/src/dma/multi_chan_trigger.rs
+++ b/src/dma/multi_chan_trigger.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Trigger one or more channels simultaneously  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`multi_chan_trigger::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`multi_chan_trigger::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`multi_chan_trigger::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`multi_chan_trigger::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULTI_CHAN_TRIGGER_SPEC;
 impl crate::RegisterSpec for MULTI_CHAN_TRIGGER_SPEC {
     type Ux = u32;
diff --git a/src/dma/n_channels.rs b/src/dma/n_channels.rs
index ae6c2bc5f..08bff5579 100644
--- a/src/dma/n_channels.rs
+++ b/src/dma/n_channels.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`n_channels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct N_CHANNELS_SPEC;
 impl crate::RegisterSpec for N_CHANNELS_SPEC {
     type Ux = u32;
diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs
index 1e4432c05..1d4472076 100644
--- a/src/dma/sniff_ctrl.rs
+++ b/src/dma/sniff_ctrl.rs
@@ -38,6 +38,7 @@ impl From<CALC_A> for u8 {
 impl crate::FieldSpec for CALC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for CALC_A {}
 #[doc = "Field `CALC` reader - "]
 pub type CALC_R = crate::FieldReader<CALC_A>;
 impl CALC_R {
@@ -215,7 +216,7 @@ impl W {
 }
 #[doc = "Sniffer Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sniff_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sniff_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SNIFF_CTRL_SPEC;
 impl crate::RegisterSpec for SNIFF_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/dma/sniff_data.rs b/src/dma/sniff_data.rs
index 298f49b3a..5b36a860e 100644
--- a/src/dma/sniff_data.rs
+++ b/src/dma/sniff_data.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SNIFF_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Data accumulator for sniff hardware  
  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sniff_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SNIFF_DATA_SPEC;
 impl crate::RegisterSpec for SNIFF_DATA_SPEC {
     type Ux = u32;
diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs
index b0c0d1395..599cb4c82 100644
--- a/src/dma/timer0.rs
+++ b/src/dma/timer0.rs
@@ -39,7 +39,7 @@ impl W {
 #[doc = "Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timer0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER0_SPEC;
 impl crate::RegisterSpec for TIMER0_SPEC {
     type Ux = u32;
diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs
index ddf44a745..33cce4820 100644
--- a/src/dma/timer1.rs
+++ b/src/dma/timer1.rs
@@ -39,7 +39,7 @@ impl W {
 #[doc = "Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER1_SPEC;
 impl crate::RegisterSpec for TIMER1_SPEC {
     type Ux = u32;
diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs
index b23b748cb..bc135b096 100644
--- a/src/dma/timer2.rs
+++ b/src/dma/timer2.rs
@@ -39,7 +39,7 @@ impl W {
 #[doc = "Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timer2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER2_SPEC;
 impl crate::RegisterSpec for TIMER2_SPEC {
     type Ux = u32;
diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs
index 0041ca097..e209adee6 100644
--- a/src/dma/timer3.rs
+++ b/src/dma/timer3.rs
@@ -39,7 +39,7 @@ impl W {
 #[doc = "Pacing (X/Y) Fractional Timer  
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timer3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER3_SPEC;
 impl crate::RegisterSpec for TIMER3_SPEC {
     type Ux = u32;
diff --git a/src/generic.rs b/src/generic.rs
index db0f701ae..d57106cb2 100644
--- a/src/generic.rs
+++ b/src/generic.rs
@@ -48,8 +48,10 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
 #[doc = " Trait implemented by readable registers to enable the `read` method."]
 #[doc = ""]
 #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
@@ -80,161 +82,6 @@ pub trait Resettable: RegisterSpec {
         Self::RESET_VALUE
     }
 }
-#[doc = " This structure provides volatile access to registers."]
-#[repr(transparent)]
-pub struct Reg<REG: RegisterSpec> {
-    register: vcell::VolatileCell<REG::Ux>,
-    _marker: marker::PhantomData<REG>,
-}
-unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
-impl<REG: RegisterSpec> Reg<REG> {
-    #[doc = " Returns the underlying memory address of register."]
-    #[doc = ""]
-    #[doc = " ```ignore"]
-    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn as_ptr(&self) -> *mut REG::Ux {
-        self.register.as_ptr()
-    }
-}
-impl<REG: Readable> Reg<REG> {
-    #[doc = " Reads the contents of a `Readable` register."]
-    #[doc = ""]
-    #[doc = " You can read the raw contents of a register by using `bits`:"]
-    #[doc = " ```ignore"]
-    #[doc = " let bits = periph.reg.read().bits();"]
-    #[doc = " ```"]
-    #[doc = " or get the content of a particular field of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " let reader = periph.reg.read();"]
-    #[doc = " let bits = reader.field1().bits();"]
-    #[doc = " let flag = reader.field2().bit_is_set();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn read(&self) -> R<REG> {
-        R {
-            bits: self.register.get(),
-            _reg: marker::PhantomData,
-        }
-    }
-}
-impl<REG: Resettable + Writable> Reg<REG> {
-    #[doc = " Writes the reset value to `Writable` register."]
-    #[doc = ""]
-    #[doc = " Resets the register to its initial state."]
-    #[inline(always)]
-    pub fn reset(&self) {
-        self.register.set(REG::RESET_VALUE)
-    }
-    #[doc = " Writes bits to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " You can write raw bits into a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
-    #[doc = " ```"]
-    #[doc = " or write only the fields you need:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " In the latter case, other fields will be set to their reset value."]
-    #[inline(always)]
-    pub fn write<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        self.register.set(
-            f(&mut W {
-                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
-    }
-}
-impl<REG: Writable> Reg<REG> {
-    #[doc = " Writes 0 to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " Similar to `write`, but unused bits will contain 0."]
-    #[doc = ""]
-    #[doc = " # Safety"]
-    #[doc = ""]
-    #[doc = " Unsafe to use with registers which don't allow to write 0."]
-    #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F)
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        self.register.set(
-            f(&mut W {
-                bits: REG::Ux::default(),
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
-    }
-}
-impl<REG: Readable + Writable> Reg<REG> {
-    #[doc = " Modifies the contents of the register by reading and then writing it."]
-    #[doc = ""]
-    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
-    #[doc = "    r.bits() | 3"]
-    #[doc = " ) });"]
-    #[doc = " ```"]
-    #[doc = " or"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " Other fields will have the value they had before the call to `modify`."]
-    #[inline(always)]
-    pub fn modify<F>(&self, f: F)
-    where
-        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
-    {
-        let bits = self.register.get();
-        self.register.set(
-            f(
-                &R {
-                    bits,
-                    _reg: marker::PhantomData,
-                },
-                &mut W {
-                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                    _reg: marker::PhantomData,
-                },
-            )
-            .bits,
-        );
-    }
-}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -300,6 +147,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -336,19 +188,28 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
-#[doc = " Write field Proxy with unsafe `bits`"]
-pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
-#[doc = " Write field Proxy with safe `bits`"]
-pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
-impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
 {
     #[doc = " Field width"]
     pub const WIDTH: u8 = WI;
@@ -362,6 +223,13 @@ where
     pub const fn offset(&self) -> u8 {
         self.o
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes raw bits to the field"]
     #[doc = ""]
     #[doc = " # Safety"]
@@ -373,41 +241,81 @@ where
         self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
         self.w
     }
-    #[doc = " Writes `variant` to the field"]
+}
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        unsafe { self.bits(FI::Ux::from(variant)) }
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
     }
 }
-impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
     REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
 {
-    #[doc = " Field width"]
-    pub const WIDTH: u8 = WI;
-    #[doc = " Field width"]
+    #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub const fn width(&self) -> u8 {
-        WI
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
     }
-    #[doc = " Field offset"]
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub const fn offset(&self) -> u8 {
-        self.o
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
     }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
     #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
-        self.w
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes `variant` to the field"]
     #[inline(always)]
     pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        self.bits(FI::Ux::from(variant))
+        unsafe { self.bits(FI::Ux::from(variant)) }
     }
 }
 macro_rules! bit_proxy {
@@ -545,3 +453,166 @@ where
         self.w
     }
 }
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> R<REG> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG> {
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &R {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+                &mut W {
+                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                    _reg: marker::PhantomData,
+                },
+            )
+            .bits,
+        );
+    }
+}
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
diff --git a/src/i2c0.rs b/src/i2c0.rs
index 5e09fdf84..5f31f3667 100644
--- a/src/i2c0.rs
+++ b/src/i2c0.rs
@@ -339,7 +339,7 @@ register being set to 0. Writes at other times have no effect.
 
  Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_con`]
 module"]
@@ -356,7 +356,7 @@ is set to 0.
 
  Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_tar`]
 module"]
@@ -370,7 +370,7 @@ is set to 0.
 pub mod ic_tar;
 #[doc = "IC_SAR (rw) register accessor: I2C Slave Address Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_sar`]
 module"]
@@ -383,7 +383,7 @@ pub mod ic_sar;
 
  Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_data_cmd`]
 module"]
@@ -396,7 +396,7 @@ pub type IC_DATA_CMD = crate::Reg<ic_data_cmd::IC_DATA_CMD_SPEC>;
 pub mod ic_data_cmd;
 #[doc = "IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_ss_scl_hcnt`]
 module"]
@@ -405,7 +405,7 @@ pub type IC_SS_SCL_HCNT = crate::Reg<ic_ss_scl_hcnt::IC_SS_SCL_HCNT_SPEC>;
 pub mod ic_ss_scl_hcnt;
 #[doc = "IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_ss_scl_lcnt`]
 module"]
@@ -414,7 +414,7 @@ pub type IC_SS_SCL_LCNT = crate::Reg<ic_ss_scl_lcnt::IC_SS_SCL_LCNT_SPEC>;
 pub mod ic_ss_scl_lcnt;
 #[doc = "IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_hcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_fs_scl_hcnt`]
 module"]
@@ -423,7 +423,7 @@ pub type IC_FS_SCL_HCNT = crate::Reg<ic_fs_scl_hcnt::IC_FS_SCL_HCNT_SPEC>;
 pub mod ic_fs_scl_hcnt;
 #[doc = "IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_fs_scl_lcnt`]
 module"]
@@ -434,7 +434,7 @@ pub mod ic_fs_scl_lcnt;
 
  Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_intr_stat`]
 module"]
@@ -447,7 +447,7 @@ pub mod ic_intr_stat;
 
  These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_intr_mask`]
 module"]
@@ -460,7 +460,7 @@ pub mod ic_intr_mask;
 
  Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_raw_intr_stat`]
 module"]
@@ -471,7 +471,7 @@ pub type IC_RAW_INTR_STAT = crate::Reg<ic_raw_intr_stat::IC_RAW_INTR_STAT_SPEC>;
 pub mod ic_raw_intr_stat;
 #[doc = "IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_rx_tl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_rx_tl`]
 module"]
@@ -480,7 +480,7 @@ pub type IC_RX_TL = crate::Reg<ic_rx_tl::IC_RX_TL_SPEC>;
 pub mod ic_rx_tl;
 #[doc = "IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_tl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_tx_tl`]
 module"]
@@ -489,7 +489,7 @@ pub type IC_TX_TL = crate::Reg<ic_tx_tl::IC_TX_TL_SPEC>;
 pub mod ic_tx_tl;
 #[doc = "IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_intr`]
 module"]
@@ -498,7 +498,7 @@ pub type IC_CLR_INTR = crate::Reg<ic_clr_intr::IC_CLR_INTR_SPEC>;
 pub mod ic_clr_intr;
 #[doc = "IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_under::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_rx_under`]
 module"]
@@ -507,7 +507,7 @@ pub type IC_CLR_RX_UNDER = crate::Reg<ic_clr_rx_under::IC_CLR_RX_UNDER_SPEC>;
 pub mod ic_clr_rx_under;
 #[doc = "IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_rx_over`]
 module"]
@@ -516,7 +516,7 @@ pub type IC_CLR_RX_OVER = crate::Reg<ic_clr_rx_over::IC_CLR_RX_OVER_SPEC>;
 pub mod ic_clr_rx_over;
 #[doc = "IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_tx_over`]
 module"]
@@ -525,7 +525,7 @@ pub type IC_CLR_TX_OVER = crate::Reg<ic_clr_tx_over::IC_CLR_TX_OVER_SPEC>;
 pub mod ic_clr_tx_over;
 #[doc = "IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rd_req::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_rd_req`]
 module"]
@@ -534,7 +534,7 @@ pub type IC_CLR_RD_REQ = crate::Reg<ic_clr_rd_req::IC_CLR_RD_REQ_SPEC>;
 pub mod ic_clr_rd_req;
 #[doc = "IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_tx_abrt`]
 module"]
@@ -543,7 +543,7 @@ pub type IC_CLR_TX_ABRT = crate::Reg<ic_clr_tx_abrt::IC_CLR_TX_ABRT_SPEC>;
 pub mod ic_clr_tx_abrt;
 #[doc = "IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_rx_done`]
 module"]
@@ -552,7 +552,7 @@ pub type IC_CLR_RX_DONE = crate::Reg<ic_clr_rx_done::IC_CLR_RX_DONE_SPEC>;
 pub mod ic_clr_rx_done;
 #[doc = "IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_activity::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_activity`]
 module"]
@@ -561,7 +561,7 @@ pub type IC_CLR_ACTIVITY = crate::Reg<ic_clr_activity::IC_CLR_ACTIVITY_SPEC>;
 pub mod ic_clr_activity;
 #[doc = "IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_stop_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_stop_det`]
 module"]
@@ -570,7 +570,7 @@ pub type IC_CLR_STOP_DET = crate::Reg<ic_clr_stop_det::IC_CLR_STOP_DET_SPEC>;
 pub mod ic_clr_stop_det;
 #[doc = "IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_start_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_start_det`]
 module"]
@@ -579,7 +579,7 @@ pub type IC_CLR_START_DET = crate::Reg<ic_clr_start_det::IC_CLR_START_DET_SPEC>;
 pub mod ic_clr_start_det;
 #[doc = "IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_gen_call::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_gen_call`]
 module"]
@@ -588,7 +588,7 @@ pub type IC_CLR_GEN_CALL = crate::Reg<ic_clr_gen_call::IC_CLR_GEN_CALL_SPEC>;
 pub mod ic_clr_gen_call;
 #[doc = "IC_ENABLE (rw) register accessor: I2C Enable Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_enable`]
 module"]
@@ -601,7 +601,7 @@ pub mod ic_enable;
 
  When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_status`]
 module"]
@@ -614,7 +614,7 @@ pub type IC_STATUS = crate::Reg<ic_status::IC_STATUS_SPEC>;
 pub mod ic_status;
 #[doc = "IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_txflr`]
 module"]
@@ -623,7 +623,7 @@ pub type IC_TXFLR = crate::Reg<ic_txflr::IC_TXFLR_SPEC>;
 pub mod ic_txflr;
 #[doc = "IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_rxflr`]
 module"]
@@ -644,7 +644,7 @@ of this register are used to extend the SDA transition (if any) whenever SCL is
 
  The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_sda_hold`]
 module"]
@@ -669,7 +669,7 @@ pub mod ic_sda_hold;
 
  Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_tx_abrt_source`]
 module"]
@@ -689,7 +689,7 @@ pub mod ic_tx_abrt_source;
 = 0) Note: The IC_STATUS\\[6\\]
 is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_slv_data_nack_only::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_slv_data_nack_only`]
 module"]
@@ -707,7 +707,7 @@ pub mod ic_slv_data_nack_only;
 
  The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_dma_cr`]
 module"]
@@ -718,7 +718,7 @@ pub type IC_DMA_CR = crate::Reg<ic_dma_cr::IC_DMA_CR_SPEC>;
 pub mod ic_dma_cr;
 #[doc = "IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_tdlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_dma_tdlr`]
 module"]
@@ -727,7 +727,7 @@ pub type IC_DMA_TDLR = crate::Reg<ic_dma_tdlr::IC_DMA_TDLR_SPEC>;
 pub mod ic_dma_tdlr;
 #[doc = "IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_dma_rdlr`]
 module"]
@@ -743,7 +743,7 @@ pub mod ic_dma_rdlr;
 
  Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_sda_setup`]
 module"]
@@ -763,7 +763,7 @@ pub mod ic_sda_setup;
 
  This register is applicable only when the DW_apb_i2c is in slave mode.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_ack_general_call`]
 module"]
@@ -788,7 +788,7 @@ has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
  Note: When IC_ENABLE\\[0\\]
 has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_enable_status`]
 module"]
@@ -811,7 +811,7 @@ pub mod ic_enable_status;
 
  This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_spklen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_fs_spklen`]
 module"]
@@ -822,7 +822,7 @@ pub type IC_FS_SPKLEN = crate::Reg<ic_fs_spklen::IC_FS_SPKLEN_SPEC>;
 pub mod ic_fs_spklen;
 #[doc = "IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_restart_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_clr_restart_det`]
 module"]
@@ -833,7 +833,7 @@ pub mod ic_clr_restart_det;
 
  Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_param_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_comp_param_1`]
 module"]
@@ -844,7 +844,7 @@ pub type IC_COMP_PARAM_1 = crate::Reg<ic_comp_param_1::IC_COMP_PARAM_1_SPEC>;
 pub mod ic_comp_param_1;
 #[doc = "IC_COMP_VERSION (r) register accessor: I2C Component Version Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_comp_version`]
 module"]
@@ -853,7 +853,7 @@ pub type IC_COMP_VERSION = crate::Reg<ic_comp_version::IC_COMP_VERSION_SPEC>;
 pub mod ic_comp_version;
 #[doc = "IC_COMP_TYPE (r) register accessor: I2C Component Type Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ic_comp_type`]
 module"]
diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs
index d012db2fe..b8a395679 100644
--- a/src/i2c0/ic_ack_general_call.rs
+++ b/src/i2c0/ic_ack_general_call.rs
@@ -78,7 +78,7 @@ impl W {
 
  This register is applicable only when the DW_apb_i2c is in slave mode.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_ACK_GENERAL_CALL_SPEC;
 impl crate::RegisterSpec for IC_ACK_GENERAL_CALL_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_activity.rs b/src/i2c0/ic_clr_activity.rs
index aa363a7e3..4f7475ad6 100644
--- a/src/i2c0/ic_clr_activity.rs
+++ b/src/i2c0/ic_clr_activity.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear ACTIVITY Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_activity::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_ACTIVITY_SPEC;
 impl crate::RegisterSpec for IC_CLR_ACTIVITY_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/i2c0/ic_clr_gen_call.rs
index fffd7c810..f2be48388 100644
--- a/src/i2c0/ic_clr_gen_call.rs
+++ b/src/i2c0/ic_clr_gen_call.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear GEN_CALL Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_gen_call::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_GEN_CALL_SPEC;
 impl crate::RegisterSpec for IC_CLR_GEN_CALL_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_intr.rs b/src/i2c0/ic_clr_intr.rs
index 0f5eb9146..87541c653 100644
--- a/src/i2c0/ic_clr_intr.rs
+++ b/src/i2c0/ic_clr_intr.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear Combined and Individual Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_INTR_SPEC;
 impl crate::RegisterSpec for IC_CLR_INTR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/i2c0/ic_clr_rd_req.rs
index 41a234ccd..39d9fea2b 100644
--- a/src/i2c0/ic_clr_rd_req.rs
+++ b/src/i2c0/ic_clr_rd_req.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear RD_REQ Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rd_req::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_RD_REQ_SPEC;
 impl crate::RegisterSpec for IC_CLR_RD_REQ_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/i2c0/ic_clr_restart_det.rs
index bc047b617..2ddcebdf6 100644
--- a/src/i2c0/ic_clr_restart_det.rs
+++ b/src/i2c0/ic_clr_restart_det.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear RESTART_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_restart_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_RESTART_DET_SPEC;
 impl crate::RegisterSpec for IC_CLR_RESTART_DET_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/i2c0/ic_clr_rx_done.rs
index c1e30fc5f..f9fea362e 100644
--- a/src/i2c0/ic_clr_rx_done.rs
+++ b/src/i2c0/ic_clr_rx_done.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear RX_DONE Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_RX_DONE_SPEC;
 impl crate::RegisterSpec for IC_CLR_RX_DONE_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/i2c0/ic_clr_rx_over.rs
index e971de22d..fddda577f 100644
--- a/src/i2c0/ic_clr_rx_over.rs
+++ b/src/i2c0/ic_clr_rx_over.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear RX_OVER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_RX_OVER_SPEC;
 impl crate::RegisterSpec for IC_CLR_RX_OVER_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/i2c0/ic_clr_rx_under.rs
index 1b213b86e..1c4f13fea 100644
--- a/src/i2c0/ic_clr_rx_under.rs
+++ b/src/i2c0/ic_clr_rx_under.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear RX_UNDER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_under::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_RX_UNDER_SPEC;
 impl crate::RegisterSpec for IC_CLR_RX_UNDER_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_start_det.rs b/src/i2c0/ic_clr_start_det.rs
index 6b023c604..cebbeee44 100644
--- a/src/i2c0/ic_clr_start_det.rs
+++ b/src/i2c0/ic_clr_start_det.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear START_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_start_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_START_DET_SPEC;
 impl crate::RegisterSpec for IC_CLR_START_DET_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/i2c0/ic_clr_stop_det.rs
index 21e987281..bdea17f21 100644
--- a/src/i2c0/ic_clr_stop_det.rs
+++ b/src/i2c0/ic_clr_stop_det.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear STOP_DET Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_stop_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_STOP_DET_SPEC;
 impl crate::RegisterSpec for IC_CLR_STOP_DET_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/i2c0/ic_clr_tx_abrt.rs
index 5e607c9d6..5b5493cde 100644
--- a/src/i2c0/ic_clr_tx_abrt.rs
+++ b/src/i2c0/ic_clr_tx_abrt.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear TX_ABRT Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_TX_ABRT_SPEC;
 impl crate::RegisterSpec for IC_CLR_TX_ABRT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/i2c0/ic_clr_tx_over.rs
index 47d8502ce..57b1c3db9 100644
--- a/src/i2c0/ic_clr_tx_over.rs
+++ b/src/i2c0/ic_clr_tx_over.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "Clear TX_OVER Interrupt Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CLR_TX_OVER_SPEC;
 impl crate::RegisterSpec for IC_CLR_TX_OVER_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_comp_param_1.rs b/src/i2c0/ic_comp_param_1.rs
index d059487c3..4d39e7807 100644
--- a/src/i2c0/ic_comp_param_1.rs
+++ b/src/i2c0/ic_comp_param_1.rs
@@ -62,7 +62,7 @@ impl R {
 
  Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_param_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_COMP_PARAM_1_SPEC;
 impl crate::RegisterSpec for IC_COMP_PARAM_1_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_comp_type.rs b/src/i2c0/ic_comp_type.rs
index 00fa9e0e4..f3d157d14 100644
--- a/src/i2c0/ic_comp_type.rs
+++ b/src/i2c0/ic_comp_type.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "I2C Component Type Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_COMP_TYPE_SPEC;
 impl crate::RegisterSpec for IC_COMP_TYPE_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_comp_version.rs b/src/i2c0/ic_comp_version.rs
index 488ce877e..a10213d10 100644
--- a/src/i2c0/ic_comp_version.rs
+++ b/src/i2c0/ic_comp_version.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "I2C Component Version Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_comp_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_COMP_VERSION_SPEC;
 impl crate::RegisterSpec for IC_COMP_VERSION_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs
index a210ffffa..6f2c2d167 100644
--- a/src/i2c0/ic_con.rs
+++ b/src/i2c0/ic_con.rs
@@ -95,6 +95,7 @@ impl From<SPEED_A> for u8 {
 impl crate::FieldSpec for SPEED_A {
     type Ux = u8;
 }
+impl crate::IsEnum for SPEED_A {}
 #[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
 
  This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.  
@@ -751,7 +752,7 @@ register being set to 0. Writes at other times have no effect.
 
  Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_CON_SPEC;
 impl crate::RegisterSpec for IC_CON_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs
index a0cd32bcb..11abc534f 100644
--- a/src/i2c0/ic_data_cmd.rs
+++ b/src/i2c0/ic_data_cmd.rs
@@ -385,7 +385,7 @@ impl W {
 
  Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_DATA_CMD_SPEC;
 impl crate::RegisterSpec for IC_DATA_CMD_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs
index 73ace2dd3..857323a3a 100644
--- a/src/i2c0/ic_dma_cr.rs
+++ b/src/i2c0/ic_dma_cr.rs
@@ -142,7 +142,7 @@ impl W {
 
  The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_DMA_CR_SPEC;
 impl crate::RegisterSpec for IC_DMA_CR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs
index 0acb62409..b367e205b 100644
--- a/src/i2c0/ic_dma_rdlr.rs
+++ b/src/i2c0/ic_dma_rdlr.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "I2C Receive Data Level Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_rdlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_DMA_RDLR_SPEC;
 impl crate::RegisterSpec for IC_DMA_RDLR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs
index 9afd98445..5aa1c4e8f 100644
--- a/src/i2c0/ic_dma_tdlr.rs
+++ b/src/i2c0/ic_dma_tdlr.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "DMA Transmit Data Level Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_tdlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_DMA_TDLR_SPEC;
 impl crate::RegisterSpec for IC_DMA_TDLR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs
index 960e02f5c..ac4703779 100644
--- a/src/i2c0/ic_enable.rs
+++ b/src/i2c0/ic_enable.rs
@@ -261,7 +261,7 @@ impl W {
 }
 #[doc = "I2C Enable Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_ENABLE_SPEC;
 impl crate::RegisterSpec for IC_ENABLE_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs
index b431554b3..423015e8d 100644
--- a/src/i2c0/ic_enable_status.rs
+++ b/src/i2c0/ic_enable_status.rs
@@ -229,7 +229,7 @@ has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
  Note: When IC_ENABLE\\[0\\]
 has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_ENABLE_STATUS_SPEC;
 impl crate::RegisterSpec for IC_ENABLE_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs
index 85d134b2d..b4a42c88f 100644
--- a/src/i2c0/ic_fs_scl_hcnt.rs
+++ b/src/i2c0/ic_fs_scl_hcnt.rs
@@ -43,7 +43,7 @@ register being set to 0. Writes at other times have no effect.
 }
 #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_FS_SCL_HCNT_SPEC;
 impl crate::RegisterSpec for IC_FS_SCL_HCNT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs
index 046f1eb3a..428ed75a2 100644
--- a/src/i2c0/ic_fs_scl_lcnt.rs
+++ b/src/i2c0/ic_fs_scl_lcnt.rs
@@ -51,7 +51,7 @@ register being set to 0. Writes at other times have no effect.
 }
 #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_FS_SCL_LCNT_SPEC;
 impl crate::RegisterSpec for IC_FS_SCL_LCNT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs
index 59d99b468..07700b0e7 100644
--- a/src/i2c0/ic_fs_spklen.rs
+++ b/src/i2c0/ic_fs_spklen.rs
@@ -29,7 +29,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid
 
  This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_fs_spklen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_spklen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_FS_SPKLEN_SPEC;
 impl crate::RegisterSpec for IC_FS_SPKLEN_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs
index f2512f11c..b0d499ff4 100644
--- a/src/i2c0/ic_intr_mask.rs
+++ b/src/i2c0/ic_intr_mask.rs
@@ -998,7 +998,7 @@ impl W {
 
  These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_INTR_MASK_SPEC;
 impl crate::RegisterSpec for IC_INTR_MASK_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs
index c8aea206a..f94afd6f6 100644
--- a/src/i2c0/ic_intr_stat.rs
+++ b/src/i2c0/ic_intr_stat.rs
@@ -643,7 +643,7 @@ impl R {
 
  Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_INTR_STAT_SPEC;
 impl crate::RegisterSpec for IC_INTR_STAT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs
index 527538c31..ef9132cfa 100644
--- a/src/i2c0/ic_raw_intr_stat.rs
+++ b/src/i2c0/ic_raw_intr_stat.rs
@@ -664,7 +664,7 @@ is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks l
 
  Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_RAW_INTR_STAT_SPEC;
 impl crate::RegisterSpec for IC_RAW_INTR_STAT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs
index bc573d9c7..40cd3a680 100644
--- a/src/i2c0/ic_rx_tl.rs
+++ b/src/i2c0/ic_rx_tl.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "I2C Receive FIFO Threshold Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_rx_tl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_RX_TL_SPEC;
 impl crate::RegisterSpec for IC_RX_TL_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_rxflr.rs b/src/i2c0/ic_rxflr.rs
index 93f75cb4f..7cdff9285 100644
--- a/src/i2c0/ic_rxflr.rs
+++ b/src/i2c0/ic_rxflr.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_RXFLR_SPEC;
 impl crate::RegisterSpec for IC_RXFLR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs
index ea3e58ee4..5c01360ad 100644
--- a/src/i2c0/ic_sar.rs
+++ b/src/i2c0/ic_sar.rs
@@ -47,7 +47,7 @@ register being set to 0. Writes at other times have no effect.
 }
 #[doc = "I2C Slave Address Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SAR_SPEC;
 impl crate::RegisterSpec for IC_SAR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs
index 60f8bddc2..cfa6683a8 100644
--- a/src/i2c0/ic_sda_hold.rs
+++ b/src/i2c0/ic_sda_hold.rs
@@ -66,7 +66,7 @@ of this register are used to extend the SDA transition (if any) whenever SCL is
 
  The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SDA_HOLD_SPEC;
 impl crate::RegisterSpec for IC_SDA_HOLD_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs
index d6d02c3ba..acbe7cea0 100644
--- a/src/i2c0/ic_sda_setup.rs
+++ b/src/i2c0/ic_sda_setup.rs
@@ -30,7 +30,7 @@ impl W {
 
  Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SDA_SETUP_SPEC;
 impl crate::RegisterSpec for IC_SDA_SETUP_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs
index beb7e06bb..7d7296899 100644
--- a/src/i2c0/ic_slv_data_nack_only.rs
+++ b/src/i2c0/ic_slv_data_nack_only.rs
@@ -91,7 +91,7 @@ impl W {
 = 0) Note: The IC_STATUS\\[6\\]
 is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SLV_DATA_NACK_ONLY_SPEC;
 impl crate::RegisterSpec for IC_SLV_DATA_NACK_ONLY_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs
index f6272e5c5..4e492c58a 100644
--- a/src/i2c0/ic_ss_scl_hcnt.rs
+++ b/src/i2c0/ic_ss_scl_hcnt.rs
@@ -51,7 +51,7 @@ register being set to 0. Writes at other times have no effect.
 }
 #[doc = "Standard Speed I2C Clock SCL High Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SS_SCL_HCNT_SPEC;
 impl crate::RegisterSpec for IC_SS_SCL_HCNT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs
index 99940d30a..dbd6fee43 100644
--- a/src/i2c0/ic_ss_scl_lcnt.rs
+++ b/src/i2c0/ic_ss_scl_lcnt.rs
@@ -43,7 +43,7 @@ register being set to 0. Writes at other times have no effect.
 }
 #[doc = "Standard Speed I2C Clock SCL Low Count Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_SS_SCL_LCNT_SPEC;
 impl crate::RegisterSpec for IC_SS_SCL_LCNT_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs
index a449a0b2e..29ec4330b 100644
--- a/src/i2c0/ic_status.rs
+++ b/src/i2c0/ic_status.rs
@@ -315,7 +315,7 @@ impl R {
 
  When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_STATUS_SPEC;
 impl crate::RegisterSpec for IC_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs
index 4cf0e1e35..601e7ae8a 100644
--- a/src/i2c0/ic_tar.rs
+++ b/src/i2c0/ic_tar.rs
@@ -168,7 +168,7 @@ is set to 0.
 
  Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_TAR_SPEC;
 impl crate::RegisterSpec for IC_TAR_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs
index 7fbde9336..262245079 100644
--- a/src/i2c0/ic_tx_abrt_source.rs
+++ b/src/i2c0/ic_tx_abrt_source.rs
@@ -967,7 +967,7 @@ is set at the same time. Note: Even though the slave never 'owns' the bus, somet
 
  Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_TX_ABRT_SOURCE_SPEC;
 impl crate::RegisterSpec for IC_TX_ABRT_SOURCE_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs
index 32fa42d7e..5000b14fb 100644
--- a/src/i2c0/ic_tx_tl.rs
+++ b/src/i2c0/ic_tx_tl.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "I2C Transmit FIFO Threshold Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_tl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_TX_TL_SPEC;
 impl crate::RegisterSpec for IC_TX_TL_SPEC {
     type Ux = u32;
diff --git a/src/i2c0/ic_txflr.rs b/src/i2c0/ic_txflr.rs
index 66e5c8cc3..32661087c 100644
--- a/src/i2c0/ic_txflr.rs
+++ b/src/i2c0/ic_txflr.rs
@@ -15,7 +15,7 @@ impl R {
 }
 #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_TXFLR_SPEC;
 impl crate::RegisterSpec for IC_TXFLR_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0.rs b/src/io_bank0.rs
index 728289fcf..703f040cb 100644
--- a/src/io_bank0.rs
+++ b/src/io_bank0.rs
@@ -143,7 +143,7 @@ pub use self::gpio::GPIO;
 pub mod gpio;
 #[doc = "INTR (rw) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -152,7 +152,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_inte`]
 module"]
@@ -161,7 +161,7 @@ pub type PROC0_INTE = crate::Reg<proc0_inte::PROC0_INTE_SPEC>;
 pub mod proc0_inte;
 #[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_intf`]
 module"]
@@ -170,7 +170,7 @@ pub type PROC0_INTF = crate::Reg<proc0_intf::PROC0_INTF_SPEC>;
 pub mod proc0_intf;
 #[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking &amp; forcing for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_ints`]
 module"]
@@ -179,7 +179,7 @@ pub type PROC0_INTS = crate::Reg<proc0_ints::PROC0_INTS_SPEC>;
 pub mod proc0_ints;
 #[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_inte`]
 module"]
@@ -188,7 +188,7 @@ pub type PROC1_INTE = crate::Reg<proc1_inte::PROC1_INTE_SPEC>;
 pub mod proc1_inte;
 #[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_intf`]
 module"]
@@ -197,7 +197,7 @@ pub type PROC1_INTF = crate::Reg<proc1_intf::PROC1_INTF_SPEC>;
 pub mod proc1_intf;
 #[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking &amp; forcing for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_ints`]
 module"]
@@ -206,7 +206,7 @@ pub type PROC1_INTS = crate::Reg<proc1_ints::PROC1_INTS_SPEC>;
 pub mod proc1_ints;
 #[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_inte`]
 module"]
@@ -215,7 +215,7 @@ pub type DORMANT_WAKE_INTE = crate::Reg<dormant_wake_inte::DORMANT_WAKE_INTE_SPE
 pub mod dormant_wake_inte;
 #[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_intf`]
 module"]
@@ -224,7 +224,7 @@ pub type DORMANT_WAKE_INTF = crate::Reg<dormant_wake_intf::DORMANT_WAKE_INTF_SPE
 pub mod dormant_wake_intf;
 #[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking &amp; forcing for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_ints`]
 module"]
diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/io_bank0/dormant_wake_inte.rs
index 2375a5ef8..e45d87a4e 100644
--- a/src/io_bank0/dormant_wake_inte.rs
+++ b/src/io_bank0/dormant_wake_inte.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTE_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/io_bank0/dormant_wake_intf.rs
index 9099fcaa9..5a61c1645 100644
--- a/src/io_bank0/dormant_wake_intf.rs
+++ b/src/io_bank0/dormant_wake_intf.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Force for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTF_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/io_bank0/dormant_wake_ints.rs
index 7e5165f17..eab41b1ec 100644
--- a/src/io_bank0/dormant_wake_ints.rs
+++ b/src/io_bank0/dormant_wake_ints.rs
@@ -228,7 +228,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTS_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/gpio.rs b/src/io_bank0/gpio.rs
index 77023bc7d..ee29ce97a 100644
--- a/src/io_bank0/gpio.rs
+++ b/src/io_bank0/gpio.rs
@@ -18,7 +18,7 @@ impl GPIO {
 }
 #[doc = "GPIO_STATUS (r) register accessor: GPIO status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_status`]
 module"]
@@ -27,7 +27,7 @@ pub type GPIO_STATUS = crate::Reg<gpio_status::GPIO_STATUS_SPEC>;
 pub mod gpio_status;
 #[doc = "GPIO_CTRL (rw) register accessor: GPIO control including function select and overrides.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_ctrl`]
 module"]
diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs
index f0b9aee22..7c1f7ff1d 100644
--- a/src/io_bank0/gpio/gpio_ctrl.rs
+++ b/src/io_bank0/gpio/gpio_ctrl.rs
@@ -40,6 +40,7 @@ impl From<FUNCSEL_A> for u8 {
 impl crate::FieldSpec for FUNCSEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FUNCSEL_A {}
 #[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
 pub type FUNCSEL_R = crate::FieldReader<FUNCSEL_A>;
 impl FUNCSEL_R {
@@ -204,6 +205,7 @@ impl From<OUTOVER_A> for u8 {
 impl crate::FieldSpec for OUTOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for OUTOVER_A {}
 #[doc = "Field `OUTOVER` reader - "]
 pub type OUTOVER_R = crate::FieldReader<OUTOVER_A>;
 impl OUTOVER_R {
@@ -240,7 +242,7 @@ impl OUTOVER_R {
     }
 }
 #[doc = "Field `OUTOVER` writer - "]
-pub type OUTOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OUTOVER_A>;
+pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>;
 impl<'a, REG> OUTOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -291,6 +293,7 @@ impl From<OEOVER_A> for u8 {
 impl crate::FieldSpec for OEOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for OEOVER_A {}
 #[doc = "Field `OEOVER` reader - "]
 pub type OEOVER_R = crate::FieldReader<OEOVER_A>;
 impl OEOVER_R {
@@ -327,7 +330,7 @@ impl OEOVER_R {
     }
 }
 #[doc = "Field `OEOVER` writer - "]
-pub type OEOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OEOVER_A>;
+pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>;
 impl<'a, REG> OEOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -378,6 +381,7 @@ impl From<INOVER_A> for u8 {
 impl crate::FieldSpec for INOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for INOVER_A {}
 #[doc = "Field `INOVER` reader - "]
 pub type INOVER_R = crate::FieldReader<INOVER_A>;
 impl INOVER_R {
@@ -414,7 +418,7 @@ impl INOVER_R {
     }
 }
 #[doc = "Field `INOVER` writer - "]
-pub type INOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INOVER_A>;
+pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>;
 impl<'a, REG> INOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -465,6 +469,7 @@ impl From<IRQOVER_A> for u8 {
 impl crate::FieldSpec for IRQOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for IRQOVER_A {}
 #[doc = "Field `IRQOVER` reader - "]
 pub type IRQOVER_R = crate::FieldReader<IRQOVER_A>;
 impl IRQOVER_R {
@@ -501,7 +506,7 @@ impl IRQOVER_R {
     }
 }
 #[doc = "Field `IRQOVER` writer - "]
-pub type IRQOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IRQOVER_A>;
+pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>;
 impl<'a, REG> IRQOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -589,7 +594,7 @@ impl W {
 }
 #[doc = "GPIO control including function select and overrides.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_CTRL_SPEC;
 impl crate::RegisterSpec for GPIO_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/io_bank0/gpio/gpio_status.rs
index 801488279..940288f5b 100644
--- a/src/io_bank0/gpio/gpio_status.rs
+++ b/src/io_bank0/gpio/gpio_status.rs
@@ -60,7 +60,7 @@ impl R {
 }
 #[doc = "GPIO status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_STATUS_SPEC;
 impl crate::RegisterSpec for GPIO_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/intr.rs b/src/io_bank0/intr.rs
index 4cae9a89f..2f2f3f570 100644
--- a/src/io_bank0/intr.rs
+++ b/src/io_bank0/intr.rs
@@ -360,7 +360,7 @@ impl W {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc0_inte.rs b/src/io_bank0/proc0_inte.rs
index 931d527da..39ba86d68 100644
--- a/src/io_bank0/proc0_inte.rs
+++ b/src/io_bank0/proc0_inte.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTE_SPEC;
 impl crate::RegisterSpec for PROC0_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc0_intf.rs b/src/io_bank0/proc0_intf.rs
index a676b4300..0ef08c9be 100644
--- a/src/io_bank0/proc0_intf.rs
+++ b/src/io_bank0/proc0_intf.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Force for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTF_SPEC;
 impl crate::RegisterSpec for PROC0_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc0_ints.rs b/src/io_bank0/proc0_ints.rs
index 730b0f968..79a1e96ed 100644
--- a/src/io_bank0/proc0_ints.rs
+++ b/src/io_bank0/proc0_ints.rs
@@ -228,7 +228,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTS_SPEC;
 impl crate::RegisterSpec for PROC0_INTS_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc1_inte.rs b/src/io_bank0/proc1_inte.rs
index d92cb269f..856a70abe 100644
--- a/src/io_bank0/proc1_inte.rs
+++ b/src/io_bank0/proc1_inte.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTE_SPEC;
 impl crate::RegisterSpec for PROC1_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc1_intf.rs b/src/io_bank0/proc1_intf.rs
index 9085b9c12..5f8ba20d2 100644
--- a/src/io_bank0/proc1_intf.rs
+++ b/src/io_bank0/proc1_intf.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Interrupt Force for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTF_SPEC;
 impl crate::RegisterSpec for PROC1_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_bank0/proc1_ints.rs b/src/io_bank0/proc1_ints.rs
index 24303f139..1bf6ad61a 100644
--- a/src/io_bank0/proc1_ints.rs
+++ b/src/io_bank0/proc1_ints.rs
@@ -228,7 +228,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTS_SPEC;
 impl crate::RegisterSpec for PROC1_INTS_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi.rs b/src/io_qspi.rs
index aeaf4ad26..5d13b0a2f 100644
--- a/src/io_qspi.rs
+++ b/src/io_qspi.rs
@@ -113,7 +113,7 @@ pub use self::gpio_qspi::GPIO_QSPI;
 pub mod gpio_qspi;
 #[doc = "INTR (rw) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -122,7 +122,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_inte`]
 module"]
@@ -131,7 +131,7 @@ pub type PROC0_INTE = crate::Reg<proc0_inte::PROC0_INTE_SPEC>;
 pub mod proc0_inte;
 #[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_intf`]
 module"]
@@ -140,7 +140,7 @@ pub type PROC0_INTF = crate::Reg<proc0_intf::PROC0_INTF_SPEC>;
 pub mod proc0_intf;
 #[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking &amp; forcing for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_ints`]
 module"]
@@ -149,7 +149,7 @@ pub type PROC0_INTS = crate::Reg<proc0_ints::PROC0_INTS_SPEC>;
 pub mod proc0_ints;
 #[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_inte`]
 module"]
@@ -158,7 +158,7 @@ pub type PROC1_INTE = crate::Reg<proc1_inte::PROC1_INTE_SPEC>;
 pub mod proc1_inte;
 #[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_intf`]
 module"]
@@ -167,7 +167,7 @@ pub type PROC1_INTF = crate::Reg<proc1_intf::PROC1_INTF_SPEC>;
 pub mod proc1_intf;
 #[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking &amp; forcing for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_ints`]
 module"]
@@ -176,7 +176,7 @@ pub type PROC1_INTS = crate::Reg<proc1_ints::PROC1_INTS_SPEC>;
 pub mod proc1_ints;
 #[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_inte`]
 module"]
@@ -185,7 +185,7 @@ pub type DORMANT_WAKE_INTE = crate::Reg<dormant_wake_inte::DORMANT_WAKE_INTE_SPE
 pub mod dormant_wake_inte;
 #[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_intf`]
 module"]
@@ -194,7 +194,7 @@ pub type DORMANT_WAKE_INTF = crate::Reg<dormant_wake_intf::DORMANT_WAKE_INTF_SPE
 pub mod dormant_wake_intf;
 #[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking &amp; forcing for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_ints`]
 module"]
diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/io_qspi/dormant_wake_inte.rs
index 491c009cb..90649d2d6 100644
--- a/src/io_qspi/dormant_wake_inte.rs
+++ b/src/io_qspi/dormant_wake_inte.rs
@@ -382,7 +382,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTE_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/io_qspi/dormant_wake_intf.rs
index 91e15fc0e..89719e9fb 100644
--- a/src/io_qspi/dormant_wake_intf.rs
+++ b/src/io_qspi/dormant_wake_intf.rs
@@ -382,7 +382,7 @@ impl W {
 }
 #[doc = "Interrupt Force for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTF_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/io_qspi/dormant_wake_ints.rs
index 732122cd2..864981269 100644
--- a/src/io_qspi/dormant_wake_ints.rs
+++ b/src/io_qspi/dormant_wake_ints.rs
@@ -172,7 +172,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for dormant_wake  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTS_SPEC;
 impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/gpio_qspi.rs b/src/io_qspi/gpio_qspi.rs
index 8b60a9ad1..fffaec7cf 100644
--- a/src/io_qspi/gpio_qspi.rs
+++ b/src/io_qspi/gpio_qspi.rs
@@ -18,7 +18,7 @@ impl GPIO_QSPI {
 }
 #[doc = "GPIO_STATUS (r) register accessor: GPIO status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_status`]
 module"]
@@ -27,7 +27,7 @@ pub type GPIO_STATUS = crate::Reg<gpio_status::GPIO_STATUS_SPEC>;
 pub mod gpio_status;
 #[doc = "GPIO_CTRL (rw) register accessor: GPIO control including function select and overrides.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_ctrl`]
 module"]
diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs
index c91a7f94c..61b5f6c41 100644
--- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs
+++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs
@@ -25,6 +25,7 @@ impl From<FUNCSEL_A> for u8 {
 impl crate::FieldSpec for FUNCSEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FUNCSEL_A {}
 #[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table  
  31 == NULL"]
 pub type FUNCSEL_R = crate::FieldReader<FUNCSEL_A>;
@@ -103,6 +104,7 @@ impl From<OUTOVER_A> for u8 {
 impl crate::FieldSpec for OUTOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for OUTOVER_A {}
 #[doc = "Field `OUTOVER` reader - "]
 pub type OUTOVER_R = crate::FieldReader<OUTOVER_A>;
 impl OUTOVER_R {
@@ -139,7 +141,7 @@ impl OUTOVER_R {
     }
 }
 #[doc = "Field `OUTOVER` writer - "]
-pub type OUTOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OUTOVER_A>;
+pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>;
 impl<'a, REG> OUTOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -190,6 +192,7 @@ impl From<OEOVER_A> for u8 {
 impl crate::FieldSpec for OEOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for OEOVER_A {}
 #[doc = "Field `OEOVER` reader - "]
 pub type OEOVER_R = crate::FieldReader<OEOVER_A>;
 impl OEOVER_R {
@@ -226,7 +229,7 @@ impl OEOVER_R {
     }
 }
 #[doc = "Field `OEOVER` writer - "]
-pub type OEOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OEOVER_A>;
+pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>;
 impl<'a, REG> OEOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -277,6 +280,7 @@ impl From<INOVER_A> for u8 {
 impl crate::FieldSpec for INOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for INOVER_A {}
 #[doc = "Field `INOVER` reader - "]
 pub type INOVER_R = crate::FieldReader<INOVER_A>;
 impl INOVER_R {
@@ -313,7 +317,7 @@ impl INOVER_R {
     }
 }
 #[doc = "Field `INOVER` writer - "]
-pub type INOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INOVER_A>;
+pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>;
 impl<'a, REG> INOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -364,6 +368,7 @@ impl From<IRQOVER_A> for u8 {
 impl crate::FieldSpec for IRQOVER_A {
     type Ux = u8;
 }
+impl crate::IsEnum for IRQOVER_A {}
 #[doc = "Field `IRQOVER` reader - "]
 pub type IRQOVER_R = crate::FieldReader<IRQOVER_A>;
 impl IRQOVER_R {
@@ -400,7 +405,7 @@ impl IRQOVER_R {
     }
 }
 #[doc = "Field `IRQOVER` writer - "]
-pub type IRQOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IRQOVER_A>;
+pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>;
 impl<'a, REG> IRQOVER_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -490,7 +495,7 @@ impl W {
 }
 #[doc = "GPIO control including function select and overrides.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_CTRL_SPEC;
 impl crate::RegisterSpec for GPIO_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/io_qspi/gpio_qspi/gpio_status.rs
index 801488279..940288f5b 100644
--- a/src/io_qspi/gpio_qspi/gpio_status.rs
+++ b/src/io_qspi/gpio_qspi/gpio_status.rs
@@ -60,7 +60,7 @@ impl R {
 }
 #[doc = "GPIO status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_STATUS_SPEC;
 impl crate::RegisterSpec for GPIO_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/intr.rs b/src/io_qspi/intr.rs
index 9329d4c32..dedbe30a2 100644
--- a/src/io_qspi/intr.rs
+++ b/src/io_qspi/intr.rs
@@ -272,7 +272,7 @@ impl W {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc0_inte.rs b/src/io_qspi/proc0_inte.rs
index 8d194d6c0..94d8a757b 100644
--- a/src/io_qspi/proc0_inte.rs
+++ b/src/io_qspi/proc0_inte.rs
@@ -368,7 +368,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTE_SPEC;
 impl crate::RegisterSpec for PROC0_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc0_intf.rs b/src/io_qspi/proc0_intf.rs
index 7c3d6b1a4..b67f75f14 100644
--- a/src/io_qspi/proc0_intf.rs
+++ b/src/io_qspi/proc0_intf.rs
@@ -368,7 +368,7 @@ impl W {
 }
 #[doc = "Interrupt Force for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTF_SPEC;
 impl crate::RegisterSpec for PROC0_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc0_ints.rs b/src/io_qspi/proc0_ints.rs
index b59526569..5a70575b3 100644
--- a/src/io_qspi/proc0_ints.rs
+++ b/src/io_qspi/proc0_ints.rs
@@ -172,7 +172,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for proc0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTS_SPEC;
 impl crate::RegisterSpec for PROC0_INTS_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc1_inte.rs b/src/io_qspi/proc1_inte.rs
index 923279580..653c0ffdc 100644
--- a/src/io_qspi/proc1_inte.rs
+++ b/src/io_qspi/proc1_inte.rs
@@ -368,7 +368,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTE_SPEC;
 impl crate::RegisterSpec for PROC1_INTE_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc1_intf.rs b/src/io_qspi/proc1_intf.rs
index a845d3315..4c1b8d6fb 100644
--- a/src/io_qspi/proc1_intf.rs
+++ b/src/io_qspi/proc1_intf.rs
@@ -368,7 +368,7 @@ impl W {
 }
 #[doc = "Interrupt Force for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTF_SPEC;
 impl crate::RegisterSpec for PROC1_INTF_SPEC {
     type Ux = u32;
diff --git a/src/io_qspi/proc1_ints.rs b/src/io_qspi/proc1_ints.rs
index a31d11608..f6c8b6dc2 100644
--- a/src/io_qspi/proc1_ints.rs
+++ b/src/io_qspi/proc1_ints.rs
@@ -172,7 +172,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for proc1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTS_SPEC;
 impl crate::RegisterSpec for PROC1_INTS_SPEC {
     type Ux = u32;
diff --git a/src/lib.rs b/src/lib.rs
index 094585a0a..7a8bae23f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,11 +1,11 @@
-#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.32.0 ( ))  
+#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.33.5 ( ))  
 
 You can find an overview of the generated API [here].  
 
 API features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.  
 
-[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api  
+[here]: https://docs.rs/svd2rust/0.33.5/svd2rust/#peripheral-api  
 [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased  
 [repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
@@ -2328,114 +2328,42 @@ impl Peripherals {
     pub unsafe fn steal() -> Self {
         DEVICE_PERIPHERALS = true;
         Peripherals {
-            XIP_CTRL: XIP_CTRL {
-                _marker: PhantomData,
-            },
-            XIP_SSI: XIP_SSI {
-                _marker: PhantomData,
-            },
-            SYSINFO: SYSINFO {
-                _marker: PhantomData,
-            },
-            SYSCFG: SYSCFG {
-                _marker: PhantomData,
-            },
-            CLOCKS: CLOCKS {
-                _marker: PhantomData,
-            },
-            RESETS: RESETS {
-                _marker: PhantomData,
-            },
-            PSM: PSM {
-                _marker: PhantomData,
-            },
-            IO_BANK0: IO_BANK0 {
-                _marker: PhantomData,
-            },
-            IO_QSPI: IO_QSPI {
-                _marker: PhantomData,
-            },
-            PADS_BANK0: PADS_BANK0 {
-                _marker: PhantomData,
-            },
-            PADS_QSPI: PADS_QSPI {
-                _marker: PhantomData,
-            },
-            XOSC: XOSC {
-                _marker: PhantomData,
-            },
-            PLL_SYS: PLL_SYS {
-                _marker: PhantomData,
-            },
-            PLL_USB: PLL_USB {
-                _marker: PhantomData,
-            },
-            BUSCTRL: BUSCTRL {
-                _marker: PhantomData,
-            },
-            UART0: UART0 {
-                _marker: PhantomData,
-            },
-            UART1: UART1 {
-                _marker: PhantomData,
-            },
-            SPI0: SPI0 {
-                _marker: PhantomData,
-            },
-            SPI1: SPI1 {
-                _marker: PhantomData,
-            },
-            I2C0: I2C0 {
-                _marker: PhantomData,
-            },
-            I2C1: I2C1 {
-                _marker: PhantomData,
-            },
-            ADC: ADC {
-                _marker: PhantomData,
-            },
-            PWM: PWM {
-                _marker: PhantomData,
-            },
-            TIMER: TIMER {
-                _marker: PhantomData,
-            },
-            WATCHDOG: WATCHDOG {
-                _marker: PhantomData,
-            },
-            RTC: RTC {
-                _marker: PhantomData,
-            },
-            ROSC: ROSC {
-                _marker: PhantomData,
-            },
-            VREG_AND_CHIP_RESET: VREG_AND_CHIP_RESET {
-                _marker: PhantomData,
-            },
-            TBMAN: TBMAN {
-                _marker: PhantomData,
-            },
-            DMA: DMA {
-                _marker: PhantomData,
-            },
-            USBCTRL_DPRAM: USBCTRL_DPRAM {
-                _marker: PhantomData,
-            },
-            USBCTRL_REGS: USBCTRL_REGS {
-                _marker: PhantomData,
-            },
-            PIO0: PIO0 {
-                _marker: PhantomData,
-            },
-            PIO1: PIO1 {
-                _marker: PhantomData,
-            },
-            SIO: SIO {
-                _marker: PhantomData,
-            },
-            PPB: PPB {
-                _marker: PhantomData,
-            },
+            XIP_CTRL: XIP_CTRL::steal(),
+            XIP_SSI: XIP_SSI::steal(),
+            SYSINFO: SYSINFO::steal(),
+            SYSCFG: SYSCFG::steal(),
+            CLOCKS: CLOCKS::steal(),
+            RESETS: RESETS::steal(),
+            PSM: PSM::steal(),
+            IO_BANK0: IO_BANK0::steal(),
+            IO_QSPI: IO_QSPI::steal(),
+            PADS_BANK0: PADS_BANK0::steal(),
+            PADS_QSPI: PADS_QSPI::steal(),
+            XOSC: XOSC::steal(),
+            PLL_SYS: PLL_SYS::steal(),
+            PLL_USB: PLL_USB::steal(),
+            BUSCTRL: BUSCTRL::steal(),
+            UART0: UART0::steal(),
+            UART1: UART1::steal(),
+            SPI0: SPI0::steal(),
+            SPI1: SPI1::steal(),
+            I2C0: I2C0::steal(),
+            I2C1: I2C1::steal(),
+            ADC: ADC::steal(),
+            PWM: PWM::steal(),
+            TIMER: TIMER::steal(),
+            WATCHDOG: WATCHDOG::steal(),
+            RTC: RTC::steal(),
+            ROSC: ROSC::steal(),
+            VREG_AND_CHIP_RESET: VREG_AND_CHIP_RESET::steal(),
+            TBMAN: TBMAN::steal(),
+            DMA: DMA::steal(),
+            USBCTRL_DPRAM: USBCTRL_DPRAM::steal(),
+            USBCTRL_REGS: USBCTRL_REGS::steal(),
+            PIO0: PIO0::steal(),
+            PIO1: PIO1::steal(),
+            SIO: SIO::steal(),
+            PPB: PPB::steal(),
         }
     }
 }
diff --git a/src/pads_bank0.rs b/src/pads_bank0.rs
index fdbed2a54..1e3374e7c 100644
--- a/src/pads_bank0.rs
+++ b/src/pads_bank0.rs
@@ -36,7 +36,7 @@ impl RegisterBlock {
 }
 #[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@voltage_select`]
 module"]
@@ -45,7 +45,7 @@ pub type VOLTAGE_SELECT = crate::Reg<voltage_select::VOLTAGE_SELECT_SPEC>;
 pub mod voltage_select;
 #[doc = "GPIO (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio`]
 module"]
@@ -54,7 +54,7 @@ pub type GPIO = crate::Reg<gpio::GPIO_SPEC>;
 pub mod gpio;
 #[doc = "SWCLK (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`swclk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`swclk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swclk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@swclk`]
 module"]
@@ -63,7 +63,7 @@ pub type SWCLK = crate::Reg<swclk::SWCLK_SPEC>;
 pub mod swclk;
 #[doc = "SWD (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`swd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`swd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@swd`]
 module"]
diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs
index 98bfa5b24..b848b9c19 100644
--- a/src/pads_bank0/gpio.rs
+++ b/src/pads_bank0/gpio.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_SPEC;
 impl crate::RegisterSpec for GPIO_SPEC {
     type Ux = u32;
diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs
index 7b909ce86..e8a6f3fd6 100644
--- a/src/pads_bank0/swclk.rs
+++ b/src/pads_bank0/swclk.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`swclk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`swclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SWCLK_SPEC;
 impl crate::RegisterSpec for SWCLK_SPEC {
     type Ux = u32;
diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs
index 4df05995e..5cdbb6789 100644
--- a/src/pads_bank0/swd.rs
+++ b/src/pads_bank0/swd.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`swd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`swd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SWD_SPEC;
 impl crate::RegisterSpec for SWD_SPEC {
     type Ux = u32;
diff --git a/src/pads_bank0/voltage_select.rs b/src/pads_bank0/voltage_select.rs
index e1ca5ea9a..f9c428efb 100644
--- a/src/pads_bank0/voltage_select.rs
+++ b/src/pads_bank0/voltage_select.rs
@@ -74,7 +74,7 @@ impl W {
 }
 #[doc = "Voltage select. Per bank control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VOLTAGE_SELECT_SPEC;
 impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi.rs b/src/pads_qspi.rs
index 27cf3bde9..4fabc6800 100644
--- a/src/pads_qspi.rs
+++ b/src/pads_qspi.rs
@@ -48,7 +48,7 @@ impl RegisterBlock {
 }
 #[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@voltage_select`]
 module"]
@@ -57,7 +57,7 @@ pub type VOLTAGE_SELECT = crate::Reg<voltage_select::VOLTAGE_SELECT_SPEC>;
 pub mod voltage_select;
 #[doc = "GPIO_QSPI_SCLK (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sclk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sclk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_sclk`]
 module"]
@@ -66,7 +66,7 @@ pub type GPIO_QSPI_SCLK = crate::Reg<gpio_qspi_sclk::GPIO_QSPI_SCLK_SPEC>;
 pub mod gpio_qspi_sclk;
 #[doc = "GPIO_QSPI_SD0 (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_sd0`]
 module"]
@@ -75,7 +75,7 @@ pub type GPIO_QSPI_SD0 = crate::Reg<gpio_qspi_sd0::GPIO_QSPI_SD0_SPEC>;
 pub mod gpio_qspi_sd0;
 #[doc = "GPIO_QSPI_SD1 (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_sd1`]
 module"]
@@ -84,7 +84,7 @@ pub type GPIO_QSPI_SD1 = crate::Reg<gpio_qspi_sd1::GPIO_QSPI_SD1_SPEC>;
 pub mod gpio_qspi_sd1;
 #[doc = "GPIO_QSPI_SD2 (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_sd2`]
 module"]
@@ -93,7 +93,7 @@ pub type GPIO_QSPI_SD2 = crate::Reg<gpio_qspi_sd2::GPIO_QSPI_SD2_SPEC>;
 pub mod gpio_qspi_sd2;
 #[doc = "GPIO_QSPI_SD3 (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_sd3`]
 module"]
@@ -102,7 +102,7 @@ pub type GPIO_QSPI_SD3 = crate::Reg<gpio_qspi_sd3::GPIO_QSPI_SD3_SPEC>;
 pub mod gpio_qspi_sd3;
 #[doc = "GPIO_QSPI_SS (rw) register accessor: Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_ss::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_ss::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_qspi_ss`]
 module"]
diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs
index 96d9229fc..5f2288d30 100644
--- a/src/pads_qspi/gpio_qspi_sclk.rs
+++ b/src/pads_qspi/gpio_qspi_sclk.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sclk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SCLK_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SCLK_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs
index cd34d33d7..218038626 100644
--- a/src/pads_qspi/gpio_qspi_sd0.rs
+++ b/src/pads_qspi/gpio_qspi_sd0.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SD0_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SD0_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs
index 073b9f561..e562f52e8 100644
--- a/src/pads_qspi/gpio_qspi_sd1.rs
+++ b/src/pads_qspi/gpio_qspi_sd1.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SD1_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SD1_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs
index 738b7ef2b..5dbf05d53 100644
--- a/src/pads_qspi/gpio_qspi_sd2.rs
+++ b/src/pads_qspi/gpio_qspi_sd2.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SD2_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SD2_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs
index da18ad2c0..6bdf02888 100644
--- a/src/pads_qspi/gpio_qspi_sd3.rs
+++ b/src/pads_qspi/gpio_qspi_sd3.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_sd3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SD3_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SD3_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs
index de88f61b0..9f6016d99 100644
--- a/src/pads_qspi/gpio_qspi_ss.rs
+++ b/src/pads_qspi/gpio_qspi_ss.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
 impl crate::FieldSpec for DRIVE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DRIVE_A {}
 #[doc = "Field `DRIVE` reader - Drive strength."]
 pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
 impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
     }
 }
 #[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
 impl<'a, REG> DRIVE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -196,7 +197,7 @@ impl W {
 }
 #[doc = "Pad control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_qspi_ss::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_ss::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_QSPI_SS_SPEC;
 impl crate::RegisterSpec for GPIO_QSPI_SS_SPEC {
     type Ux = u32;
diff --git a/src/pads_qspi/voltage_select.rs b/src/pads_qspi/voltage_select.rs
index e1ca5ea9a..f9c428efb 100644
--- a/src/pads_qspi/voltage_select.rs
+++ b/src/pads_qspi/voltage_select.rs
@@ -74,7 +74,7 @@ impl W {
 }
 #[doc = "Voltage select. Per bank control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`voltage_select::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VOLTAGE_SELECT_SPEC;
 impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC {
     type Ux = u32;
diff --git a/src/pio0.rs b/src/pio0.rs
index d13478492..299b5b0bf 100644
--- a/src/pio0.rs
+++ b/src/pio0.rs
@@ -138,7 +138,7 @@ impl RegisterBlock {
 }
 #[doc = "CTRL (rw) register accessor: PIO control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -147,7 +147,7 @@ pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 pub mod ctrl;
 #[doc = "FSTAT (r) register accessor: FIFO status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fstat`]
 module"]
@@ -156,7 +156,7 @@ pub type FSTAT = crate::Reg<fstat::FSTAT_SPEC>;
 pub mod fstat;
 #[doc = "FDEBUG (rw) register accessor: FIFO debug register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fdebug::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdebug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fdebug::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdebug::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fdebug`]
 module"]
@@ -165,7 +165,7 @@ pub type FDEBUG = crate::Reg<fdebug::FDEBUG_SPEC>;
 pub mod fdebug;
 #[doc = "FLEVEL (r) register accessor: FIFO levels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`flevel::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@flevel`]
 module"]
@@ -174,7 +174,7 @@ pub type FLEVEL = crate::Reg<flevel::FLEVEL_SPEC>;
 pub mod flevel;
 #[doc = "TXF (w) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@txf`]
 module"]
@@ -183,7 +183,7 @@ pub type TXF = crate::Reg<txf::TXF_SPEC>;
 pub mod txf;
 #[doc = "RXF (r) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rxf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rxf`]
 module"]
@@ -194,7 +194,7 @@ pub mod rxf;
 
  Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq`]
 module"]
@@ -205,7 +205,7 @@ pub type IRQ = crate::Reg<irq::IRQ_SPEC>;
 pub mod irq;
 #[doc = "IRQ_FORCE (w) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_force::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_force`]
 module"]
@@ -217,7 +217,7 @@ pub mod irq_force;
  1 -> synchronizer is bypassed  
  If in doubt, leave this register as all zeroes.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`input_sync_bypass::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`input_sync_bypass::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@input_sync_bypass`]
 module"]
@@ -229,7 +229,7 @@ pub type INPUT_SYNC_BYPASS = crate::Reg<input_sync_bypass::INPUT_SYNC_BYPASS_SPE
 pub mod input_sync_bypass;
 #[doc = "DBG_PADOUT (r) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dbg_padout::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dbg_padout`]
 module"]
@@ -238,7 +238,7 @@ pub type DBG_PADOUT = crate::Reg<dbg_padout::DBG_PADOUT_SPEC>;
 pub mod dbg_padout;
 #[doc = "DBG_PADOE (r) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dbg_padoe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dbg_padoe`]
 module"]
@@ -248,7 +248,7 @@ pub mod dbg_padoe;
 #[doc = "DBG_CFGINFO (r) register accessor: The PIO hardware has some free parameters that may vary between chip products.  
  These should be provided in the chip datasheet, but are also exposed here.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dbg_cfginfo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dbg_cfginfo`]
 module"]
@@ -258,7 +258,7 @@ pub type DBG_CFGINFO = crate::Reg<dbg_cfginfo::DBG_CFGINFO_SPEC>;
 pub mod dbg_cfginfo;
 #[doc = "INSTR_MEM (w) register accessor: Write-only access to instruction memory location %s  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`instr_mem::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@instr_mem`]
 module"]
@@ -272,7 +272,7 @@ pub use self::sm::SM;
 pub mod sm;
 #[doc = "INTR (r) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs
index a3638640d..ad51e5d86 100644
--- a/src/pio0/ctrl.rs
+++ b/src/pio0/ctrl.rs
@@ -85,7 +85,7 @@ impl W {
 }
 #[doc = "PIO control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/pio0/dbg_cfginfo.rs b/src/pio0/dbg_cfginfo.rs
index cb8479c69..f1c3ffed7 100644
--- a/src/pio0/dbg_cfginfo.rs
+++ b/src/pio0/dbg_cfginfo.rs
@@ -30,7 +30,7 @@ impl R {
 #[doc = "The PIO hardware has some free parameters that may vary between chip products.  
  These should be provided in the chip datasheet, but are also exposed here.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dbg_cfginfo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBG_CFGINFO_SPEC;
 impl crate::RegisterSpec for DBG_CFGINFO_SPEC {
     type Ux = u32;
diff --git a/src/pio0/dbg_padoe.rs b/src/pio0/dbg_padoe.rs
index 259791d8c..f4014bf32 100644
--- a/src/pio0/dbg_padoe.rs
+++ b/src/pio0/dbg_padoe.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DBG_PADOE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dbg_padoe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBG_PADOE_SPEC;
 impl crate::RegisterSpec for DBG_PADOE_SPEC {
     type Ux = u32;
diff --git a/src/pio0/dbg_padout.rs b/src/pio0/dbg_padout.rs
index 793c02697..44a44df04 100644
--- a/src/pio0/dbg_padout.rs
+++ b/src/pio0/dbg_padout.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DBG_PADOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dbg_padout::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBG_PADOUT_SPEC;
 impl crate::RegisterSpec for DBG_PADOUT_SPEC {
     type Ux = u32;
diff --git a/src/pio0/fdebug.rs b/src/pio0/fdebug.rs
index fd533d10f..cd1ea5664 100644
--- a/src/pio0/fdebug.rs
+++ b/src/pio0/fdebug.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "FIFO debug register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fdebug::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdebug::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fdebug::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdebug::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FDEBUG_SPEC;
 impl crate::RegisterSpec for FDEBUG_SPEC {
     type Ux = u32;
diff --git a/src/pio0/flevel.rs b/src/pio0/flevel.rs
index baf39f5ec..d6bddc695 100644
--- a/src/pio0/flevel.rs
+++ b/src/pio0/flevel.rs
@@ -60,7 +60,7 @@ impl R {
 }
 #[doc = "FIFO levels  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`flevel::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FLEVEL_SPEC;
 impl crate::RegisterSpec for FLEVEL_SPEC {
     type Ux = u32;
diff --git a/src/pio0/fstat.rs b/src/pio0/fstat.rs
index 8c22f835a..1cd80098d 100644
--- a/src/pio0/fstat.rs
+++ b/src/pio0/fstat.rs
@@ -32,7 +32,7 @@ impl R {
 }
 #[doc = "FIFO status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSTAT_SPEC;
 impl crate::RegisterSpec for FSTAT_SPEC {
     type Ux = u32;
diff --git a/src/pio0/input_sync_bypass.rs b/src/pio0/input_sync_bypass.rs
index 0b355db58..7c6674e9c 100644
--- a/src/pio0/input_sync_bypass.rs
+++ b/src/pio0/input_sync_bypass.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INPUT_SYNC_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.  
  0 -> input is synchronized (default)  
  1 -> synchronizer is bypassed  
  If in doubt, leave this register as all zeroes.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`input_sync_bypass::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INPUT_SYNC_BYPASS_SPEC;
 impl crate::RegisterSpec for INPUT_SYNC_BYPASS_SPEC {
     type Ux = u32;
diff --git a/src/pio0/instr_mem.rs b/src/pio0/instr_mem.rs
index 1b69c4ef9..2f16e2c05 100644
--- a/src/pio0/instr_mem.rs
+++ b/src/pio0/instr_mem.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "Write-only access to instruction memory location %s  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`instr_mem::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INSTR_MEM_SPEC;
 impl crate::RegisterSpec for INSTR_MEM_SPEC {
     type Ux = u32;
diff --git a/src/pio0/intr.rs b/src/pio0/intr.rs
index 49bb86e21..7fe6463bf 100644
--- a/src/pio0/intr.rs
+++ b/src/pio0/intr.rs
@@ -88,7 +88,7 @@ impl R {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs
index 587f8f05e..b6e024bc3 100644
--- a/src/pio0/irq.rs
+++ b/src/pio0/irq.rs
@@ -25,7 +25,7 @@ impl W {
 
  Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_SPEC;
 impl crate::RegisterSpec for IRQ_SPEC {
     type Ux = u32;
diff --git a/src/pio0/irq_force.rs b/src/pio0/irq_force.rs
index 46e8b95fd..4d53c7932 100644
--- a/src/pio0/irq_force.rs
+++ b/src/pio0/irq_force.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_force::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_FORCE_SPEC;
 impl crate::RegisterSpec for IRQ_FORCE_SPEC {
     type Ux = u32;
diff --git a/src/pio0/rxf.rs b/src/pio0/rxf.rs
index 30cbc12b6..70893ece6 100644
--- a/src/pio0/rxf.rs
+++ b/src/pio0/rxf.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<RXF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rxf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXF_SPEC;
 impl crate::RegisterSpec for RXF_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm.rs b/src/pio0/sm.rs
index 05686cd36..eebeddaff 100644
--- a/src/pio0/sm.rs
+++ b/src/pio0/sm.rs
@@ -45,7 +45,7 @@ impl SM {
 #[doc = "SM_CLKDIV (rw) register accessor: Clock divisor register for state machine 0  
  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_clkdiv`]
 module"]
@@ -55,7 +55,7 @@ pub type SM_CLKDIV = crate::Reg<sm_clkdiv::SM_CLKDIV_SPEC>;
 pub mod sm_clkdiv;
 #[doc = "SM_EXECCTRL (rw) register accessor: Execution/behavioural settings for state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_execctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_execctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_execctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_execctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_execctrl`]
 module"]
@@ -64,7 +64,7 @@ pub type SM_EXECCTRL = crate::Reg<sm_execctrl::SM_EXECCTRL_SPEC>;
 pub mod sm_execctrl;
 #[doc = "SM_SHIFTCTRL (rw) register accessor: Control behaviour of the input/output shift registers for state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_shiftctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_shiftctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_shiftctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_shiftctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_shiftctrl`]
 module"]
@@ -73,7 +73,7 @@ pub type SM_SHIFTCTRL = crate::Reg<sm_shiftctrl::SM_SHIFTCTRL_SPEC>;
 pub mod sm_shiftctrl;
 #[doc = "SM_ADDR (r) register accessor: Current instruction address of state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_addr`]
 module"]
@@ -83,7 +83,7 @@ pub mod sm_addr;
 #[doc = "SM_INSTR (rw) register accessor: Read to see the instruction currently addressed by state machine 0's program counter  
  Write to execute an instruction immediately (including jumps) and then resume execution.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_instr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_instr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_instr`]
 module"]
@@ -93,7 +93,7 @@ pub type SM_INSTR = crate::Reg<sm_instr::SM_INSTR_SPEC>;
 pub mod sm_instr;
 #[doc = "SM_PINCTRL (rw) register accessor: State machine pin control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_pinctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_pinctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sm_pinctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_pinctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sm_pinctrl`]
 module"]
diff --git a/src/pio0/sm/sm_addr.rs b/src/pio0/sm/sm_addr.rs
index 56a6ac71d..3d658db4e 100644
--- a/src/pio0/sm/sm_addr.rs
+++ b/src/pio0/sm/sm_addr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Current instruction address of state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_ADDR_SPEC;
 impl crate::RegisterSpec for SM_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs
index e65fbf594..7b7ca8a18 100644
--- a/src/pio0/sm/sm_clkdiv.rs
+++ b/src/pio0/sm/sm_clkdiv.rs
@@ -43,7 +43,7 @@ impl W {
 #[doc = "Clock divisor register for state machine 0  
  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_CLKDIV_SPEC;
 impl crate::RegisterSpec for SM_CLKDIV_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs
index 419ecc091..5d7307593 100644
--- a/src/pio0/sm/sm_execctrl.rs
+++ b/src/pio0/sm/sm_execctrl.rs
@@ -232,7 +232,7 @@ impl W {
 }
 #[doc = "Execution/behavioural settings for state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_execctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_execctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_execctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_execctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_EXECCTRL_SPEC;
 impl crate::RegisterSpec for SM_EXECCTRL_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs
index 795552995..84bbd99a2 100644
--- a/src/pio0/sm/sm_instr.rs
+++ b/src/pio0/sm/sm_instr.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Read to see the instruction currently addressed by state machine 0's program counter  
  Write to execute an instruction immediately (including jumps) and then resume execution.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_instr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_instr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_INSTR_SPEC;
 impl crate::RegisterSpec for SM_INSTR_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/pio0/sm/sm_pinctrl.rs
index 29072b12d..23664f15d 100644
--- a/src/pio0/sm/sm_pinctrl.rs
+++ b/src/pio0/sm/sm_pinctrl.rs
@@ -113,7 +113,7 @@ impl W {
 }
 #[doc = "State machine pin control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_pinctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_pinctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_pinctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_pinctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_PINCTRL_SPEC;
 impl crate::RegisterSpec for SM_PINCTRL_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs
index bcb7872b2..c5b85c7d7 100644
--- a/src/pio0/sm/sm_shiftctrl.rs
+++ b/src/pio0/sm/sm_shiftctrl.rs
@@ -152,7 +152,7 @@ impl W {
 }
 #[doc = "Control behaviour of the input/output shift registers for state machine 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sm_shiftctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_shiftctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sm_shiftctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_shiftctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SM_SHIFTCTRL_SPEC;
 impl crate::RegisterSpec for SM_SHIFTCTRL_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm_irq.rs b/src/pio0/sm_irq.rs
index b059f6698..eb3f7edf7 100644
--- a/src/pio0/sm_irq.rs
+++ b/src/pio0/sm_irq.rs
@@ -24,7 +24,7 @@ impl SM_IRQ {
 }
 #[doc = "IRQ_INTE (rw) register accessor: Interrupt Enable for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_inte`]
 module"]
@@ -33,7 +33,7 @@ pub type IRQ_INTE = crate::Reg<irq_inte::IRQ_INTE_SPEC>;
 pub mod irq_inte;
 #[doc = "IRQ_INTF (rw) register accessor: Interrupt Force for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_intf`]
 module"]
@@ -42,7 +42,7 @@ pub type IRQ_INTF = crate::Reg<irq_intf::IRQ_INTF_SPEC>;
 pub mod irq_intf;
 #[doc = "IRQ_INTS (r) register accessor: Interrupt status after masking &amp; forcing for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_ints`]
 module"]
diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/pio0/sm_irq/irq_inte.rs
index 9ea0a5af4..0de87ac69 100644
--- a/src/pio0/sm_irq/irq_inte.rs
+++ b/src/pio0/sm_irq/irq_inte.rs
@@ -188,7 +188,7 @@ impl W {
 }
 #[doc = "Interrupt Enable for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_INTE_SPEC;
 impl crate::RegisterSpec for IRQ_INTE_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/pio0/sm_irq/irq_intf.rs
index b6a056989..d5ae2f9a7 100644
--- a/src/pio0/sm_irq/irq_intf.rs
+++ b/src/pio0/sm_irq/irq_intf.rs
@@ -188,7 +188,7 @@ impl W {
 }
 #[doc = "Interrupt Force for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_INTF_SPEC;
 impl crate::RegisterSpec for IRQ_INTF_SPEC {
     type Ux = u32;
diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/pio0/sm_irq/irq_ints.rs
index a4cdd2a7b..1c67db63e 100644
--- a/src/pio0/sm_irq/irq_ints.rs
+++ b/src/pio0/sm_irq/irq_ints.rs
@@ -88,7 +88,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing for irq0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_INTS_SPEC;
 impl crate::RegisterSpec for IRQ_INTS_SPEC {
     type Ux = u32;
diff --git a/src/pio0/txf.rs b/src/pio0/txf.rs
index 45803a49c..bca19ea61 100644
--- a/src/pio0/txf.rs
+++ b/src/pio0/txf.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for crate::generic::Reg<TXF_SPEC> {
 impl W {}
 #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXF_SPEC;
 impl crate::RegisterSpec for TXF_SPEC {
     type Ux = u32;
diff --git a/src/pll_sys.rs b/src/pll_sys.rs
index e0c16b1ec..db04a11f0 100644
--- a/src/pll_sys.rs
+++ b/src/pll_sys.rs
@@ -41,7 +41,7 @@ impl RegisterBlock {
  Feedback divider min=16, max=320  
  VCO frequency min=750MHz, max=1600MHz  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@cs`]
 module"]
@@ -54,7 +54,7 @@ pub type CS = crate::Reg<cs::CS_SPEC>;
 pub mod cs;
 #[doc = "PWR (rw) register accessor: Controls the PLL power modes.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`pwr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`pwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@pwr`]
 module"]
@@ -64,7 +64,7 @@ pub mod pwr;
 #[doc = "FBDIV_INT (rw) register accessor: Feedback divisor  
  (note: this PLL does not support fractional division)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fbdiv_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fbdiv_int`]
 module"]
@@ -76,7 +76,7 @@ pub mod fbdiv_int;
  (note: this PLL does not have a secondary output)  
  the primary output is driven from VCO divided by postdiv1*postdiv2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`prim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@prim`]
 module"]
diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs
index a24311e4a..124a0bb42 100644
--- a/src/pll_sys/cs.rs
+++ b/src/pll_sys/cs.rs
@@ -57,7 +57,7 @@ impl W {
  Feedback divider min=16, max=320  
  VCO frequency min=750MHz, max=1600MHz  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CS_SPEC;
 impl crate::RegisterSpec for CS_SPEC {
     type Ux = u32;
diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs
index 8295a2c89..758a610cc 100644
--- a/src/pll_sys/fbdiv_int.rs
+++ b/src/pll_sys/fbdiv_int.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Feedback divisor  
  (note: this PLL does not support fractional division)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fbdiv_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbdiv_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FBDIV_INT_SPEC;
 impl crate::RegisterSpec for FBDIV_INT_SPEC {
     type Ux = u32;
diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs
index 893d1d041..ad74ec197 100644
--- a/src/pll_sys/prim.rs
+++ b/src/pll_sys/prim.rs
@@ -40,7 +40,7 @@ impl W {
  (note: this PLL does not have a secondary output)  
  the primary output is driven from VCO divided by postdiv1*postdiv2  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`prim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRIM_SPEC;
 impl crate::RegisterSpec for PRIM_SPEC {
     type Ux = u32;
diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs
index de28e0723..bc3877efb 100644
--- a/src/pll_sys/pwr.rs
+++ b/src/pll_sys/pwr.rs
@@ -84,7 +84,7 @@ impl W {
 }
 #[doc = "Controls the PLL power modes.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`pwr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`pwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PWR_SPEC;
 impl crate::RegisterSpec for PWR_SPEC {
     type Ux = u32;
diff --git a/src/ppb.rs b/src/ppb.rs
index e8dee8f35..c853f9bf4 100644
--- a/src/ppb.rs
+++ b/src/ppb.rs
@@ -199,7 +199,7 @@ impl RegisterBlock {
 }
 #[doc = "SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_csr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`syst_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@syst_csr`]
 module"]
@@ -209,7 +209,7 @@ pub mod syst_csr;
 #[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.  
  To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`syst_rvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@syst_rvr`]
 module"]
@@ -219,7 +219,7 @@ pub type SYST_RVR = crate::Reg<syst_rvr::SYST_RVR_SPEC>;
 pub mod syst_rvr;
 #[doc = "SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`syst_cvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_cvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@syst_cvr`]
 module"]
@@ -228,7 +228,7 @@ pub type SYST_CVR = crate::Reg<syst_cvr::SYST_CVR_SPEC>;
 pub mod syst_cvr;
 #[doc = "SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`syst_calib::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@syst_calib`]
 module"]
@@ -238,7 +238,7 @@ pub mod syst_calib;
 #[doc = "NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.  
  If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_iser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_iser`]
 module"]
@@ -248,7 +248,7 @@ pub type NVIC_ISER = crate::Reg<nvic_iser::NVIC_ISER_SPEC>;
 pub mod nvic_iser;
 #[doc = "NVIC_ICER (rw) register accessor: Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_icer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_icer`]
 module"]
@@ -257,7 +257,7 @@ pub type NVIC_ICER = crate::Reg<nvic_icer::NVIC_ICER_SPEC>;
 pub mod nvic_icer;
 #[doc = "NVIC_ISPR (rw) register accessor: The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ispr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ispr`]
 module"]
@@ -266,7 +266,7 @@ pub type NVIC_ISPR = crate::Reg<nvic_ispr::NVIC_ISPR_SPEC>;
 pub mod nvic_ispr;
 #[doc = "NVIC_ICPR (rw) register accessor: Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_icpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_icpr`]
 module"]
@@ -277,7 +277,7 @@ pub mod nvic_icpr;
  Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.  
  These registers are only word-accessible  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr0`]
 module"]
@@ -288,7 +288,7 @@ pub type NVIC_IPR0 = crate::Reg<nvic_ipr0::NVIC_IPR0_SPEC>;
 pub mod nvic_ipr0;
 #[doc = "NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr1`]
 module"]
@@ -297,7 +297,7 @@ pub type NVIC_IPR1 = crate::Reg<nvic_ipr1::NVIC_IPR1_SPEC>;
 pub mod nvic_ipr1;
 #[doc = "NVIC_IPR2 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr2`]
 module"]
@@ -306,7 +306,7 @@ pub type NVIC_IPR2 = crate::Reg<nvic_ipr2::NVIC_IPR2_SPEC>;
 pub mod nvic_ipr2;
 #[doc = "NVIC_IPR3 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr3`]
 module"]
@@ -315,7 +315,7 @@ pub type NVIC_IPR3 = crate::Reg<nvic_ipr3::NVIC_IPR3_SPEC>;
 pub mod nvic_ipr3;
 #[doc = "NVIC_IPR4 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr4`]
 module"]
@@ -324,7 +324,7 @@ pub type NVIC_IPR4 = crate::Reg<nvic_ipr4::NVIC_IPR4_SPEC>;
 pub mod nvic_ipr4;
 #[doc = "NVIC_IPR5 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr5`]
 module"]
@@ -333,7 +333,7 @@ pub type NVIC_IPR5 = crate::Reg<nvic_ipr5::NVIC_IPR5_SPEC>;
 pub mod nvic_ipr5;
 #[doc = "NVIC_IPR6 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr6`]
 module"]
@@ -342,7 +342,7 @@ pub type NVIC_IPR6 = crate::Reg<nvic_ipr6::NVIC_IPR6_SPEC>;
 pub mod nvic_ipr6;
 #[doc = "NVIC_IPR7 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nvic_ipr7`]
 module"]
@@ -351,7 +351,7 @@ pub type NVIC_IPR7 = crate::Reg<nvic_ipr7::NVIC_IPR7_SPEC>;
 pub mod nvic_ipr7;
 #[doc = "CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@cpuid`]
 module"]
@@ -360,7 +360,7 @@ pub type CPUID = crate::Reg<cpuid::CPUID_SPEC>;
 pub mod cpuid;
 #[doc = "ICSR (rw) register accessor: Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@icsr`]
 module"]
@@ -369,7 +369,7 @@ pub type ICSR = crate::Reg<icsr::ICSR_SPEC>;
 pub mod icsr;
 #[doc = "VTOR (rw) register accessor: The VTOR holds the vector table offset address.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`vtor::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`vtor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vtor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@vtor`]
 module"]
@@ -378,7 +378,7 @@ pub type VTOR = crate::Reg<vtor::VTOR_SPEC>;
 pub mod vtor;
 #[doc = "AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`aircr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aircr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@aircr`]
 module"]
@@ -387,7 +387,7 @@ pub type AIRCR = crate::Reg<aircr::AIRCR_SPEC>;
 pub mod aircr;
 #[doc = "SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scr`]
 module"]
@@ -396,7 +396,7 @@ pub type SCR = crate::Reg<scr::SCR_SPEC>;
 pub mod scr;
 #[doc = "CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ccr`]
 module"]
@@ -405,7 +405,7 @@ pub type CCR = crate::Reg<ccr::CCR_SPEC>;
 pub mod ccr;
 #[doc = "SHPR2 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shpr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`shpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@shpr2`]
 module"]
@@ -414,7 +414,7 @@ pub type SHPR2 = crate::Reg<shpr2::SHPR2_SPEC>;
 pub mod shpr2;
 #[doc = "SHPR3 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shpr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`shpr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@shpr3`]
 module"]
@@ -423,7 +423,7 @@ pub type SHPR3 = crate::Reg<shpr3::SHPR3_SPEC>;
 pub mod shpr3;
 #[doc = "SHCSR (rw) register accessor: Use the System Handler Control and State Register to determine or clear the pending status of SVCall.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shcsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`shcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@shcsr`]
 module"]
@@ -432,7 +432,7 @@ pub type SHCSR = crate::Reg<shcsr::SHCSR_SPEC>;
 pub mod shcsr;
 #[doc = "MPU_TYPE (r) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mpu_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mpu_type`]
 module"]
@@ -441,7 +441,7 @@ pub type MPU_TYPE = crate::Reg<mpu_type::MPU_TYPE_SPEC>;
 pub mod mpu_type;
 #[doc = "MPU_CTRL (rw) register accessor: Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mpu_ctrl`]
 module"]
@@ -450,7 +450,7 @@ pub type MPU_CTRL = crate::Reg<mpu_ctrl::MPU_CTRL_SPEC>;
 pub mod mpu_ctrl;
 #[doc = "MPU_RNR (rw) register accessor: Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rnr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mpu_rnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mpu_rnr`]
 module"]
@@ -459,7 +459,7 @@ pub type MPU_RNR = crate::Reg<mpu_rnr::MPU_RNR_SPEC>;
 pub mod mpu_rnr;
 #[doc = "MPU_RBAR (rw) register accessor: Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rbar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rbar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mpu_rbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mpu_rbar`]
 module"]
@@ -468,7 +468,7 @@ pub type MPU_RBAR = crate::Reg<mpu_rbar::MPU_RBAR_SPEC>;
 pub mod mpu_rbar;
 #[doc = "MPU_RASR (rw) register accessor: Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mpu_rasr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rasr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mpu_rasr`]
 module"]
diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs
index 6421fe7b0..8ab7b436d 100644
--- a/src/ppb/aircr.rs
+++ b/src/ppb/aircr.rs
@@ -70,7 +70,7 @@ impl W {
 }
 #[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`aircr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`aircr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AIRCR_SPEC;
 impl crate::RegisterSpec for AIRCR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/ccr.rs b/src/ppb/ccr.rs
index cc9c77813..83f333d22 100644
--- a/src/ppb/ccr.rs
+++ b/src/ppb/ccr.rs
@@ -20,7 +20,7 @@ of the stacked PSR to indicate the stack alignment. On return from the exception
 }
 #[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CCR_SPEC;
 impl crate::RegisterSpec for CCR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/cpuid.rs b/src/ppb/cpuid.rs
index 639381b05..7e49dd649 100644
--- a/src/ppb/cpuid.rs
+++ b/src/ppb/cpuid.rs
@@ -45,7 +45,7 @@ impl R {
 }
 #[doc = "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUID_SPEC;
 impl crate::RegisterSpec for CPUID_SPEC {
     type Ux = u32;
diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs
index 962b96baa..bcfaf2966 100644
--- a/src/ppb/icsr.rs
+++ b/src/ppb/icsr.rs
@@ -235,7 +235,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`icsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ICSR_SPEC;
 impl crate::RegisterSpec for ICSR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs
index cf7f7d414..f27d1dbe1 100644
--- a/src/ppb/mpu_ctrl.rs
+++ b/src/ppb/mpu_ctrl.rs
@@ -89,7 +89,7 @@ impl W {
 }
 #[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MPU_CTRL_SPEC;
 impl crate::RegisterSpec for MPU_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/ppb/mpu_rasr.rs b/src/ppb/mpu_rasr.rs
index 0147611b6..d41f8d0f2 100644
--- a/src/ppb/mpu_rasr.rs
+++ b/src/ppb/mpu_rasr.rs
@@ -96,7 +96,7 @@ impl W {
 }
 #[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rasr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rasr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mpu_rasr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rasr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MPU_RASR_SPEC;
 impl crate::RegisterSpec for MPU_RASR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs
index b59f5b3ac..c484fd826 100644
--- a/src/ppb/mpu_rbar.rs
+++ b/src/ppb/mpu_rbar.rs
@@ -89,7 +89,7 @@ of MPU_RNR."]
 }
 #[doc = "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rbar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rbar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mpu_rbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MPU_RBAR_SPEC;
 impl crate::RegisterSpec for MPU_RBAR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs
index d1e57574f..96e28062c 100644
--- a/src/ppb/mpu_rnr.rs
+++ b/src/ppb/mpu_rnr.rs
@@ -27,7 +27,7 @@ impl W {
 }
 #[doc = "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_rnr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_rnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mpu_rnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MPU_RNR_SPEC;
 impl crate::RegisterSpec for MPU_RNR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/mpu_type.rs b/src/ppb/mpu_type.rs
index ff303fbca..6437ed08a 100644
--- a/src/ppb/mpu_type.rs
+++ b/src/ppb/mpu_type.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mpu_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MPU_TYPE_SPEC;
 impl crate::RegisterSpec for MPU_TYPE_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_icer.rs b/src/ppb/nvic_icer.rs
index 492c9a4f2..2afee3a6a 100644
--- a/src/ppb/nvic_icer.rs
+++ b/src/ppb/nvic_icer.rs
@@ -47,7 +47,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_icer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_ICER_SPEC;
 impl crate::RegisterSpec for NVIC_ICER_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_icpr.rs b/src/ppb/nvic_icpr.rs
index d1266559f..9275960a2 100644
--- a/src/ppb/nvic_icpr.rs
+++ b/src/ppb/nvic_icpr.rs
@@ -47,7 +47,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_icpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_ICPR_SPEC;
 impl crate::RegisterSpec for NVIC_ICPR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs
index 829f9209c..85c82db9d 100644
--- a/src/ppb/nvic_ipr0.rs
+++ b/src/ppb/nvic_ipr0.rs
@@ -70,7 +70,7 @@ impl W {
  Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.  
  These registers are only word-accessible  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR0_SPEC;
 impl crate::RegisterSpec for NVIC_IPR0_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr1.rs b/src/ppb/nvic_ipr1.rs
index 0dd33bc6c..bf5c77b1f 100644
--- a/src/ppb/nvic_ipr1.rs
+++ b/src/ppb/nvic_ipr1.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR1_SPEC;
 impl crate::RegisterSpec for NVIC_IPR1_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr2.rs b/src/ppb/nvic_ipr2.rs
index 6e7e90f7f..3a0f9f952 100644
--- a/src/ppb/nvic_ipr2.rs
+++ b/src/ppb/nvic_ipr2.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR2_SPEC;
 impl crate::RegisterSpec for NVIC_IPR2_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr3.rs b/src/ppb/nvic_ipr3.rs
index dc0f6aa80..7bb480439 100644
--- a/src/ppb/nvic_ipr3.rs
+++ b/src/ppb/nvic_ipr3.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR3_SPEC;
 impl crate::RegisterSpec for NVIC_IPR3_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr4.rs b/src/ppb/nvic_ipr4.rs
index 3dd6d0193..163f056e8 100644
--- a/src/ppb/nvic_ipr4.rs
+++ b/src/ppb/nvic_ipr4.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR4_SPEC;
 impl crate::RegisterSpec for NVIC_IPR4_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr5.rs b/src/ppb/nvic_ipr5.rs
index 381f61c8d..dbbb60fd7 100644
--- a/src/ppb/nvic_ipr5.rs
+++ b/src/ppb/nvic_ipr5.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR5_SPEC;
 impl crate::RegisterSpec for NVIC_IPR5_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr6.rs b/src/ppb/nvic_ipr6.rs
index dc6e71849..56a2ebd3a 100644
--- a/src/ppb/nvic_ipr6.rs
+++ b/src/ppb/nvic_ipr6.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR6_SPEC;
 impl crate::RegisterSpec for NVIC_IPR6_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ipr7.rs b/src/ppb/nvic_ipr7.rs
index 6a8735518..5bc29b9a0 100644
--- a/src/ppb/nvic_ipr7.rs
+++ b/src/ppb/nvic_ipr7.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ipr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_IPR7_SPEC;
 impl crate::RegisterSpec for NVIC_IPR7_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_iser.rs b/src/ppb/nvic_iser.rs
index 314c4d7f3..258a2214d 100644
--- a/src/ppb/nvic_iser.rs
+++ b/src/ppb/nvic_iser.rs
@@ -48,7 +48,7 @@ impl W {
 #[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.  
  If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_iser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_ISER_SPEC;
 impl crate::RegisterSpec for NVIC_ISER_SPEC {
     type Ux = u32;
diff --git a/src/ppb/nvic_ispr.rs b/src/ppb/nvic_ispr.rs
index e3462d616..d5805443d 100644
--- a/src/ppb/nvic_ispr.rs
+++ b/src/ppb/nvic_ispr.rs
@@ -59,7 +59,7 @@ impl W {
 }
 #[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ispr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ispr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nvic_ispr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NVIC_ISPR_SPEC;
 impl crate::RegisterSpec for NVIC_ISPR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs
index e21e417a4..506cf6d08 100644
--- a/src/ppb/scr.rs
+++ b/src/ppb/scr.rs
@@ -93,7 +93,7 @@ impl W {
 }
 #[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCR_SPEC;
 impl crate::RegisterSpec for SCR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/shcsr.rs b/src/ppb/shcsr.rs
index c3f2a47cf..95314c621 100644
--- a/src/ppb/shcsr.rs
+++ b/src/ppb/shcsr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shcsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`shcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHCSR_SPEC;
 impl crate::RegisterSpec for SHCSR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/shpr2.rs b/src/ppb/shpr2.rs
index f3a64b296..59986ba8c 100644
--- a/src/ppb/shpr2.rs
+++ b/src/ppb/shpr2.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shpr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`shpr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHPR2_SPEC;
 impl crate::RegisterSpec for SHPR2_SPEC {
     type Ux = u32;
diff --git a/src/ppb/shpr3.rs b/src/ppb/shpr3.rs
index cb51288d4..5e5e5844c 100644
--- a/src/ppb/shpr3.rs
+++ b/src/ppb/shpr3.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`shpr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shpr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`shpr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHPR3_SPEC;
 impl crate::RegisterSpec for SHPR3_SPEC {
     type Ux = u32;
diff --git a/src/ppb/syst_calib.rs b/src/ppb/syst_calib.rs
index b8dee019d..8c837347d 100644
--- a/src/ppb/syst_calib.rs
+++ b/src/ppb/syst_calib.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`syst_calib::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYST_CALIB_SPEC;
 impl crate::RegisterSpec for SYST_CALIB_SPEC {
     type Ux = u32;
diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs
index 40c993501..cddf4fb50 100644
--- a/src/ppb/syst_csr.rs
+++ b/src/ppb/syst_csr.rs
@@ -88,7 +88,7 @@ impl W {
 }
 #[doc = "Use the SysTick Control and Status Register to enable the SysTick features.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_csr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`syst_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYST_CSR_SPEC;
 impl crate::RegisterSpec for SYST_CSR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/syst_cvr.rs b/src/ppb/syst_cvr.rs
index 8d9bca983..43cdb568b 100644
--- a/src/ppb/syst_cvr.rs
+++ b/src/ppb/syst_cvr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`syst_cvr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_cvr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYST_CVR_SPEC;
 impl crate::RegisterSpec for SYST_CVR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs
index 4e8f0451e..885461807 100644
--- a/src/ppb/syst_rvr.rs
+++ b/src/ppb/syst_rvr.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.  
  To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`syst_rvr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_rvr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYST_RVR_SPEC;
 impl crate::RegisterSpec for SYST_RVR_SPEC {
     type Ux = u32;
diff --git a/src/ppb/vtor.rs b/src/ppb/vtor.rs
index bf4d3877e..55e35059d 100644
--- a/src/ppb/vtor.rs
+++ b/src/ppb/vtor.rs
@@ -27,7 +27,7 @@ of the indicate the vector table offset address."]
 }
 #[doc = "The VTOR holds the vector table offset address.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`vtor::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`vtor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vtor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VTOR_SPEC;
 impl crate::RegisterSpec for VTOR_SPEC {
     type Ux = u32;
diff --git a/src/psm.rs b/src/psm.rs
index c31b8c163..62eefbba3 100644
--- a/src/psm.rs
+++ b/src/psm.rs
@@ -30,7 +30,7 @@ impl RegisterBlock {
 }
 #[doc = "FRCE_ON (rw) register accessor: Force block out of reset (i.e. power it on)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`frce_on::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_on::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`frce_on::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_on::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@frce_on`]
 module"]
@@ -39,7 +39,7 @@ pub type FRCE_ON = crate::Reg<frce_on::FRCE_ON_SPEC>;
 pub mod frce_on;
 #[doc = "FRCE_OFF (rw) register accessor: Force into reset (i.e. power it off)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`frce_off::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_off::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`frce_off::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_off::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@frce_off`]
 module"]
@@ -48,7 +48,7 @@ pub type FRCE_OFF = crate::Reg<frce_off::FRCE_OFF_SPEC>;
 pub mod frce_off;
 #[doc = "WDSEL (rw) register accessor: Set to 1 if this peripheral should be reset when the watchdog fires.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@wdsel`]
 module"]
@@ -57,7 +57,7 @@ pub type WDSEL = crate::Reg<wdsel::WDSEL_SPEC>;
 pub mod wdsel;
 #[doc = "DONE (r) register accessor: Indicates the peripheral's registers are ready to access.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`done::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@done`]
 module"]
diff --git a/src/psm/done.rs b/src/psm/done.rs
index f8a86abc5..78e8ad990 100644
--- a/src/psm/done.rs
+++ b/src/psm/done.rs
@@ -123,7 +123,7 @@ impl R {
 }
 #[doc = "Indicates the peripheral's registers are ready to access.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`done::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DONE_SPEC;
 impl crate::RegisterSpec for DONE_SPEC {
     type Ux = u32;
diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs
index 762808564..246cacb6c 100644
--- a/src/psm/frce_off.rs
+++ b/src/psm/frce_off.rs
@@ -263,7 +263,7 @@ impl W {
 }
 #[doc = "Force into reset (i.e. power it off)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`frce_off::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_off::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`frce_off::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_off::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRCE_OFF_SPEC;
 impl crate::RegisterSpec for FRCE_OFF_SPEC {
     type Ux = u32;
diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs
index b13ba24ae..a50912318 100644
--- a/src/psm/frce_on.rs
+++ b/src/psm/frce_on.rs
@@ -263,7 +263,7 @@ impl W {
 }
 #[doc = "Force block out of reset (i.e. power it on)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`frce_on::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frce_on::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`frce_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRCE_ON_SPEC;
 impl crate::RegisterSpec for FRCE_ON_SPEC {
     type Ux = u32;
diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs
index 9a5c5d30a..24c511e40 100644
--- a/src/psm/wdsel.rs
+++ b/src/psm/wdsel.rs
@@ -263,7 +263,7 @@ impl W {
 }
 #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WDSEL_SPEC;
 impl crate::RegisterSpec for WDSEL_SPEC {
     type Ux = u32;
diff --git a/src/pwm.rs b/src/pwm.rs
index cfe10ce1c..94fad84ad 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -61,7 +61,7 @@ pub mod ch;
  For each channel, there is only one physical EN register bit,  
  which can be accessed through here or CHx_CSR.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@en`]
 module"]
@@ -74,7 +74,7 @@ pub type EN = crate::Reg<en::EN_SPEC>;
 pub mod en;
 #[doc = "INTR (rw) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -83,7 +83,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -92,7 +92,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -101,7 +101,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/pwm/ch.rs b/src/pwm/ch.rs
index e5b3a229b..b2acbe6e1 100644
--- a/src/pwm/ch.rs
+++ b/src/pwm/ch.rs
@@ -38,7 +38,7 @@ impl CH {
 }
 #[doc = "CC (rw) register accessor: Counter compare values  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`cc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@cc`]
 module"]
@@ -47,7 +47,7 @@ pub type CC = crate::Reg<cc::CC_SPEC>;
 pub mod cc;
 #[doc = "CSR (rw) register accessor: Control and status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`csr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@csr`]
 module"]
@@ -56,7 +56,7 @@ pub type CSR = crate::Reg<csr::CSR_SPEC>;
 pub mod csr;
 #[doc = "CTR (rw) register accessor: Direct access to the PWM counter  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctr`]
 module"]
@@ -67,7 +67,7 @@ pub mod ctr;
  Counting rate is system clock frequency divided by this number.  
  Fractional division uses simple 1st-order sigma-delta.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div`]
 module"]
@@ -78,7 +78,7 @@ pub type DIV = crate::Reg<div::DIV_SPEC>;
 pub mod div;
 #[doc = "TOP (rw) register accessor: Counter wrap value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`top::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`top::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@top`]
 module"]
diff --git a/src/pwm/ch/cc.rs b/src/pwm/ch/cc.rs
index 2e5f9c4c5..9239b42cb 100644
--- a/src/pwm/ch/cc.rs
+++ b/src/pwm/ch/cc.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Counter compare values  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`cc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CC_SPEC;
 impl crate::RegisterSpec for CC_SPEC {
     type Ux = u32;
diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs
index 991645642..889b61fea 100644
--- a/src/pwm/ch/csr.rs
+++ b/src/pwm/ch/csr.rs
@@ -42,6 +42,7 @@ impl From<DIVMODE_A> for u8 {
 impl crate::FieldSpec for DIVMODE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DIVMODE_A {}
 #[doc = "Field `DIVMODE` reader - "]
 pub type DIVMODE_R = crate::FieldReader<DIVMODE_A>;
 impl DIVMODE_R {
@@ -78,7 +79,7 @@ impl DIVMODE_R {
     }
 }
 #[doc = "Field `DIVMODE` writer - "]
-pub type DIVMODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DIVMODE_A>;
+pub type DIVMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DIVMODE_A, crate::Safe>;
 impl<'a, REG> DIVMODE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -208,7 +209,7 @@ impl W {
 }
 #[doc = "Control and status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CSR_SPEC;
 impl crate::RegisterSpec for CSR_SPEC {
     type Ux = u32;
diff --git a/src/pwm/ch/ctr.rs b/src/pwm/ch/ctr.rs
index b16809b46..a470facfc 100644
--- a/src/pwm/ch/ctr.rs
+++ b/src/pwm/ch/ctr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Direct access to the PWM counter  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTR_SPEC;
 impl crate::RegisterSpec for CTR_SPEC {
     type Ux = u32;
diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs
index 6c0ea55e2..11c2eaea3 100644
--- a/src/pwm/ch/div.rs
+++ b/src/pwm/ch/div.rs
@@ -40,7 +40,7 @@ impl W {
  Counting rate is system clock frequency divided by this number.  
  Fractional division uses simple 1st-order sigma-delta.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SPEC;
 impl crate::RegisterSpec for DIV_SPEC {
     type Ux = u32;
diff --git a/src/pwm/ch/top.rs b/src/pwm/ch/top.rs
index 6cd87eb82..7cede6171 100644
--- a/src/pwm/ch/top.rs
+++ b/src/pwm/ch/top.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Counter wrap value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`top::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`top::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TOP_SPEC;
 impl crate::RegisterSpec for TOP_SPEC {
     type Ux = u32;
diff --git a/src/pwm/en.rs b/src/pwm/en.rs
index 1e28b4742..521d1e8dc 100644
--- a/src/pwm/en.rs
+++ b/src/pwm/en.rs
@@ -132,7 +132,7 @@ impl W {
  For each channel, there is only one physical EN register bit,  
  which can be accessed through here or CHx_CSR.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EN_SPEC;
 impl crate::RegisterSpec for EN_SPEC {
     type Ux = u32;
diff --git a/src/pwm/inte.rs b/src/pwm/inte.rs
index 6da30341b..9438709af 100644
--- a/src/pwm/inte.rs
+++ b/src/pwm/inte.rs
@@ -128,7 +128,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/pwm/intf.rs b/src/pwm/intf.rs
index d4da1df39..b70176cff 100644
--- a/src/pwm/intf.rs
+++ b/src/pwm/intf.rs
@@ -128,7 +128,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/pwm/intr.rs b/src/pwm/intr.rs
index 0f14da7e1..15775e7a6 100644
--- a/src/pwm/intr.rs
+++ b/src/pwm/intr.rs
@@ -128,7 +128,7 @@ impl W {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/pwm/ints.rs b/src/pwm/ints.rs
index ee47535e3..0504c0b6a 100644
--- a/src/pwm/ints.rs
+++ b/src/pwm/ints.rs
@@ -60,7 +60,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/resets.rs b/src/resets.rs
index 01d9db6d4..9abe13d14 100644
--- a/src/resets.rs
+++ b/src/resets.rs
@@ -24,7 +24,7 @@ impl RegisterBlock {
 }
 #[doc = "RESET (rw) register accessor: Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@reset`]
 module"]
@@ -33,7 +33,7 @@ pub type RESET = crate::Reg<reset::RESET_SPEC>;
 pub mod reset;
 #[doc = "WDSEL (rw) register accessor: Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@wdsel`]
 module"]
@@ -42,7 +42,7 @@ pub type WDSEL = crate::Reg<wdsel::WDSEL_SPEC>;
 pub mod wdsel;
 #[doc = "RESET_DONE (r) register accessor: Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`reset_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@reset_done`]
 module"]
diff --git a/src/resets/reset.rs b/src/resets/reset.rs
index 7920fb593..9528aa198 100644
--- a/src/resets/reset.rs
+++ b/src/resets/reset.rs
@@ -383,7 +383,7 @@ impl W {
 }
 #[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESET_SPEC;
 impl crate::RegisterSpec for RESET_SPEC {
     type Ux = u32;
diff --git a/src/resets/reset_done.rs b/src/resets/reset_done.rs
index 0d9d16f76..39b0284f6 100644
--- a/src/resets/reset_done.rs
+++ b/src/resets/reset_done.rs
@@ -179,7 +179,7 @@ impl R {
 }
 #[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`reset_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESET_DONE_SPEC;
 impl crate::RegisterSpec for RESET_DONE_SPEC {
     type Ux = u32;
diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs
index 325379277..81953a187 100644
--- a/src/resets/wdsel.rs
+++ b/src/resets/wdsel.rs
@@ -383,7 +383,7 @@ impl W {
 }
 #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`wdsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WDSEL_SPEC;
 impl crate::RegisterSpec for WDSEL_SPEC {
     type Ux = u32;
diff --git a/src/rosc.rs b/src/rosc.rs
index 35c81fc3e..78135ad18 100644
--- a/src/rosc.rs
+++ b/src/rosc.rs
@@ -64,7 +64,7 @@ impl RegisterBlock {
 }
 #[doc = "CTRL (rw) register accessor: Ring Oscillator control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -79,7 +79,7 @@ pub mod ctrl;
  2 bits set triples drive strength  
  3 bits set quadruples drive strength  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`freqa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@freqa`]
 module"]
@@ -94,7 +94,7 @@ pub type FREQA = crate::Reg<freqa::FREQA_SPEC>;
 pub mod freqa;
 #[doc = "FREQB (rw) register accessor: For a detailed description see freqa register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`freqb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`freqb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@freqb`]
 module"]
@@ -107,7 +107,7 @@ pub mod freqb;
  An invalid write will also select WAKE  
  Warning: setup the irq before selecting dormant mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant`]
 module"]
@@ -120,7 +120,7 @@ pub type DORMANT = crate::Reg<dormant::DORMANT_SPEC>;
 pub mod dormant;
 #[doc = "DIV (rw) register accessor: Controls the output divider  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div`]
 module"]
@@ -129,7 +129,7 @@ pub type DIV = crate::Reg<div::DIV_SPEC>;
 pub mod div;
 #[doc = "PHASE (rw) register accessor: Controls the phase shifted output  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`phase::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`phase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@phase`]
 module"]
@@ -138,7 +138,7 @@ pub type PHASE = crate::Reg<phase::PHASE_SPEC>;
 pub mod phase;
 #[doc = "RANDOMBIT (r) register accessor: This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`randombit::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@randombit`]
 module"]
@@ -147,7 +147,7 @@ pub type RANDOMBIT = crate::Reg<randombit::RANDOMBIT_SPEC>;
 pub mod randombit;
 #[doc = "STATUS (r) register accessor: Ring Oscillator Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@status`]
 module"]
diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs
index 66bbef5e0..d62e5b988 100644
--- a/src/rosc/ctrl.rs
+++ b/src/rosc/ctrl.rs
@@ -33,6 +33,7 @@ impl From<FREQ_RANGE_A> for u16 {
 impl crate::FieldSpec for FREQ_RANGE_A {
     type Ux = u16;
 }
+impl crate::IsEnum for FREQ_RANGE_A {}
 #[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring  
  LOW uses stages 0 to 7  
  MEDIUM uses stages 0 to 5  
@@ -132,6 +133,7 @@ impl From<ENABLE_A> for u16 {
 impl crate::FieldSpec for ENABLE_A {
     type Ux = u16;
 }
+impl crate::IsEnum for ENABLE_A {}
 #[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE  
  The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up  
  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
@@ -223,7 +225,7 @@ impl W {
 }
 #[doc = "Ring Oscillator control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/rosc/div.rs b/src/rosc/div.rs
index d79cf2155..46ae3268c 100644
--- a/src/rosc/div.rs
+++ b/src/rosc/div.rs
@@ -24,6 +24,7 @@ impl From<DIV_A> for u16 {
 impl crate::FieldSpec for DIV_A {
     type Ux = u16;
 }
+impl crate::IsEnum for DIV_A {}
 #[doc = "Field `DIV` reader - set to 0xaa0 + div where  
  div = 0 divides by 32  
  div = 1-31 divides by div  
@@ -87,7 +88,7 @@ impl W {
 }
 #[doc = "Controls the output divider  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SPEC;
 impl crate::RegisterSpec for DIV_SPEC {
     type Ux = u32;
diff --git a/src/rosc/dormant.rs b/src/rosc/dormant.rs
index 1697d4d00..64b601abd 100644
--- a/src/rosc/dormant.rs
+++ b/src/rosc/dormant.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DORMANT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Ring Oscillator pause control  
  This is used to save power by pausing the ROSC  
@@ -19,7 +14,7 @@ impl W {}
  An invalid write will also select WAKE  
  Warning: setup the irq before selecting dormant mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_SPEC;
 impl crate::RegisterSpec for DORMANT_SPEC {
     type Ux = u32;
diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs
index d7c9b6476..698b039a8 100644
--- a/src/rosc/freqa.rs
+++ b/src/rosc/freqa.rs
@@ -37,6 +37,7 @@ impl From<PASSWD_A> for u16 {
 impl crate::FieldSpec for PASSWD_A {
     type Ux = u16;
 }
+impl crate::IsEnum for PASSWD_A {}
 #[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings  
  Any other value in this field will set all drive strengths to 0"]
 pub type PASSWD_R = crate::FieldReader<PASSWD_A>;
@@ -138,7 +139,7 @@ impl W {
  2 bits set triples drive strength  
  3 bits set quadruples drive strength  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`freqa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FREQA_SPEC;
 impl crate::RegisterSpec for FREQA_SPEC {
     type Ux = u32;
diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs
index c87b40ad0..d1d115f57 100644
--- a/src/rosc/freqb.rs
+++ b/src/rosc/freqb.rs
@@ -37,6 +37,7 @@ impl From<PASSWD_A> for u16 {
 impl crate::FieldSpec for PASSWD_A {
     type Ux = u16;
 }
+impl crate::IsEnum for PASSWD_A {}
 #[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings  
  Any other value in this field will set all drive strengths to 0"]
 pub type PASSWD_R = crate::FieldReader<PASSWD_A>;
@@ -132,7 +133,7 @@ impl W {
 }
 #[doc = "For a detailed description see freqa register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`freqb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`freqb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FREQB_SPEC;
 impl crate::RegisterSpec for FREQB_SPEC {
     type Ux = u32;
diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs
index 7275ec351..9f5a9feca 100644
--- a/src/rosc/phase.rs
+++ b/src/rosc/phase.rs
@@ -88,7 +88,7 @@ impl W {
 }
 #[doc = "Controls the phase shifted output  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`phase::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`phase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PHASE_SPEC;
 impl crate::RegisterSpec for PHASE_SPEC {
     type Ux = u32;
diff --git a/src/rosc/randombit.rs b/src/rosc/randombit.rs
index 1dde53a26..cbcd3b461 100644
--- a/src/rosc/randombit.rs
+++ b/src/rosc/randombit.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`randombit::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RANDOMBIT_SPEC;
 impl crate::RegisterSpec for RANDOMBIT_SPEC {
     type Ux = u32;
diff --git a/src/rosc/status.rs b/src/rosc/status.rs
index 43f66c678..6e9588c19 100644
--- a/src/rosc/status.rs
+++ b/src/rosc/status.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "Ring Oscillator Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
     type Ux = u32;
diff --git a/src/rtc.rs b/src/rtc.rs
index 3cac0834b..7e454681e 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -79,7 +79,7 @@ impl RegisterBlock {
 }
 #[doc = "CLKDIV_M1 (rw) register accessor: Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_m1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_m1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`clkdiv_m1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv_m1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@clkdiv_m1`]
 module"]
@@ -88,7 +88,7 @@ pub type CLKDIV_M1 = crate::Reg<clkdiv_m1::CLKDIV_M1_SPEC>;
 pub mod clkdiv_m1;
 #[doc = "SETUP_0 (rw) register accessor: RTC setup register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`setup_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@setup_0`]
 module"]
@@ -97,7 +97,7 @@ pub type SETUP_0 = crate::Reg<setup_0::SETUP_0_SPEC>;
 pub mod setup_0;
 #[doc = "SETUP_1 (rw) register accessor: RTC setup register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`setup_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@setup_1`]
 module"]
@@ -106,7 +106,7 @@ pub type SETUP_1 = crate::Reg<setup_1::SETUP_1_SPEC>;
 pub mod setup_1;
 #[doc = "CTRL (rw) register accessor: RTC Control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -115,7 +115,7 @@ pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 pub mod ctrl;
 #[doc = "IRQ_SETUP_0 (rw) register accessor: Interrupt setup register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq_setup_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_setup_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_setup_0`]
 module"]
@@ -124,7 +124,7 @@ pub type IRQ_SETUP_0 = crate::Reg<irq_setup_0::IRQ_SETUP_0_SPEC>;
 pub mod irq_setup_0;
 #[doc = "IRQ_SETUP_1 (rw) register accessor: Interrupt setup register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`irq_setup_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_setup_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_setup_1`]
 module"]
@@ -133,7 +133,7 @@ pub type IRQ_SETUP_1 = crate::Reg<irq_setup_1::IRQ_SETUP_1_SPEC>;
 pub mod irq_setup_1;
 #[doc = "RTC_1 (r) register accessor: RTC register 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rtc_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rtc_1`]
 module"]
@@ -143,7 +143,7 @@ pub mod rtc_1;
 #[doc = "RTC_0 (r) register accessor: RTC register 0  
  Read this before RTC 1!  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rtc_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rtc_0`]
 module"]
@@ -153,7 +153,7 @@ pub type RTC_0 = crate::Reg<rtc_0::RTC_0_SPEC>;
 pub mod rtc_0;
 #[doc = "INTR (r) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -162,7 +162,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -171,7 +171,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -180,7 +180,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/rtc/clkdiv_m1.rs b/src/rtc/clkdiv_m1.rs
index 0ba545123..7b7a41238 100644
--- a/src/rtc/clkdiv_m1.rs
+++ b/src/rtc/clkdiv_m1.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_m1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_m1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`clkdiv_m1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv_m1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLKDIV_M1_SPEC;
 impl crate::RegisterSpec for CLKDIV_M1_SPEC {
     type Ux = u32;
diff --git a/src/rtc/ctrl.rs b/src/rtc/ctrl.rs
index c4a46dc86..746691f91 100644
--- a/src/rtc/ctrl.rs
+++ b/src/rtc/ctrl.rs
@@ -64,7 +64,7 @@ impl W {
 }
 #[doc = "RTC Control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/rtc/inte.rs b/src/rtc/inte.rs
index c280da2d3..d89ac42d9 100644
--- a/src/rtc/inte.rs
+++ b/src/rtc/inte.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/rtc/intf.rs b/src/rtc/intf.rs
index 014bdf87c..960bc11cb 100644
--- a/src/rtc/intf.rs
+++ b/src/rtc/intf.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/rtc/intr.rs b/src/rtc/intr.rs
index a07f8b7cb..0b9d5f1be 100644
--- a/src/rtc/intr.rs
+++ b/src/rtc/intr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/rtc/ints.rs b/src/rtc/ints.rs
index 3918c0e92..6f9a71fe4 100644
--- a/src/rtc/ints.rs
+++ b/src/rtc/ints.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/rtc/irq_setup_0.rs b/src/rtc/irq_setup_0.rs
index b1791574c..c05ff34c4 100644
--- a/src/rtc/irq_setup_0.rs
+++ b/src/rtc/irq_setup_0.rs
@@ -120,7 +120,7 @@ impl W {
 }
 #[doc = "Interrupt setup register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq_setup_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_setup_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_SETUP_0_SPEC;
 impl crate::RegisterSpec for IRQ_SETUP_0_SPEC {
     type Ux = u32;
diff --git a/src/rtc/irq_setup_1.rs b/src/rtc/irq_setup_1.rs
index 4525a710a..75a2e6b83 100644
--- a/src/rtc/irq_setup_1.rs
+++ b/src/rtc/irq_setup_1.rs
@@ -128,7 +128,7 @@ impl W {
 }
 #[doc = "Interrupt setup register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`irq_setup_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_setup_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`irq_setup_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_setup_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_SETUP_1_SPEC;
 impl crate::RegisterSpec for IRQ_SETUP_1_SPEC {
     type Ux = u32;
diff --git a/src/rtc/rtc_0.rs b/src/rtc/rtc_0.rs
index 19581fee7..02e025034 100644
--- a/src/rtc/rtc_0.rs
+++ b/src/rtc/rtc_0.rs
@@ -33,7 +33,7 @@ impl R {
 #[doc = "RTC register 0  
  Read this before RTC 1!  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rtc_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_0_SPEC;
 impl crate::RegisterSpec for RTC_0_SPEC {
     type Ux = u32;
diff --git a/src/rtc/rtc_1.rs b/src/rtc/rtc_1.rs
index 78794efc6..b01ce4ba8 100644
--- a/src/rtc/rtc_1.rs
+++ b/src/rtc/rtc_1.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "RTC register 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rtc_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_1_SPEC;
 impl crate::RegisterSpec for RTC_1_SPEC {
     type Ux = u32;
diff --git a/src/rtc/setup_0.rs b/src/rtc/setup_0.rs
index 1bd9864d0..ff1c9275e 100644
--- a/src/rtc/setup_0.rs
+++ b/src/rtc/setup_0.rs
@@ -53,7 +53,7 @@ impl W {
 }
 #[doc = "RTC setup register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`setup_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SETUP_0_SPEC;
 impl crate::RegisterSpec for SETUP_0_SPEC {
     type Ux = u32;
diff --git a/src/rtc/setup_1.rs b/src/rtc/setup_1.rs
index 05b1bdff6..d1e449828 100644
--- a/src/rtc/setup_1.rs
+++ b/src/rtc/setup_1.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "RTC setup register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`setup_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SETUP_1_SPEC;
 impl crate::RegisterSpec for SETUP_1_SPEC {
     type Ux = u32;
diff --git a/src/sio.rs b/src/sio.rs
index 2b5353da9..beb6f4fa7 100644
--- a/src/sio.rs
+++ b/src/sio.rs
@@ -438,7 +438,7 @@ impl RegisterBlock {
 #[doc = "CPUID (r) register accessor: Processor core identifier  
  Value is 0 when read from processor core 0, and 1 when read from processor core 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@cpuid`]
 module"]
@@ -448,7 +448,7 @@ pub type CPUID = crate::Reg<cpuid::CPUID_SPEC>;
 pub mod cpuid;
 #[doc = "GPIO_IN (r) register accessor: Input value for GPIO pins  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_in`]
 module"]
@@ -457,7 +457,7 @@ pub type GPIO_IN = crate::Reg<gpio_in::GPIO_IN_SPEC>;
 pub mod gpio_in;
 #[doc = "GPIO_HI_IN (r) register accessor: Input value for QSPI pins  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_in`]
 module"]
@@ -466,7 +466,7 @@ pub type GPIO_HI_IN = crate::Reg<gpio_hi_in::GPIO_HI_IN_SPEC>;
 pub mod gpio_hi_in;
 #[doc = "GPIO_OUT (rw) register accessor: GPIO output value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_out`]
 module"]
@@ -475,7 +475,7 @@ pub type GPIO_OUT = crate::Reg<gpio_out::GPIO_OUT_SPEC>;
 pub mod gpio_out;
 #[doc = "GPIO_OUT_SET (w) register accessor: GPIO output value set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_out_set`]
 module"]
@@ -484,7 +484,7 @@ pub type GPIO_OUT_SET = crate::Reg<gpio_out_set::GPIO_OUT_SET_SPEC>;
 pub mod gpio_out_set;
 #[doc = "GPIO_OUT_CLR (w) register accessor: GPIO output value clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_out_clr`]
 module"]
@@ -493,7 +493,7 @@ pub type GPIO_OUT_CLR = crate::Reg<gpio_out_clr::GPIO_OUT_CLR_SPEC>;
 pub mod gpio_out_clr;
 #[doc = "GPIO_OUT_XOR (w) register accessor: GPIO output value XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_out_xor`]
 module"]
@@ -502,7 +502,7 @@ pub type GPIO_OUT_XOR = crate::Reg<gpio_out_xor::GPIO_OUT_XOR_SPEC>;
 pub mod gpio_out_xor;
 #[doc = "GPIO_OE (rw) register accessor: GPIO output enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_oe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_oe`]
 module"]
@@ -511,7 +511,7 @@ pub type GPIO_OE = crate::Reg<gpio_oe::GPIO_OE_SPEC>;
 pub mod gpio_oe;
 #[doc = "GPIO_OE_SET (w) register accessor: GPIO output enable set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_oe_set`]
 module"]
@@ -520,7 +520,7 @@ pub type GPIO_OE_SET = crate::Reg<gpio_oe_set::GPIO_OE_SET_SPEC>;
 pub mod gpio_oe_set;
 #[doc = "GPIO_OE_CLR (w) register accessor: GPIO output enable clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_oe_clr`]
 module"]
@@ -529,7 +529,7 @@ pub type GPIO_OE_CLR = crate::Reg<gpio_oe_clr::GPIO_OE_CLR_SPEC>;
 pub mod gpio_oe_clr;
 #[doc = "GPIO_OE_XOR (w) register accessor: GPIO output enable XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_oe_xor`]
 module"]
@@ -538,7 +538,7 @@ pub type GPIO_OE_XOR = crate::Reg<gpio_oe_xor::GPIO_OE_XOR_SPEC>;
 pub mod gpio_oe_xor;
 #[doc = "GPIO_HI_OUT (rw) register accessor: QSPI output value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_out`]
 module"]
@@ -547,7 +547,7 @@ pub type GPIO_HI_OUT = crate::Reg<gpio_hi_out::GPIO_HI_OUT_SPEC>;
 pub mod gpio_hi_out;
 #[doc = "GPIO_HI_OUT_SET (w) register accessor: QSPI output value set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_out_set`]
 module"]
@@ -556,7 +556,7 @@ pub type GPIO_HI_OUT_SET = crate::Reg<gpio_hi_out_set::GPIO_HI_OUT_SET_SPEC>;
 pub mod gpio_hi_out_set;
 #[doc = "GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_out_clr`]
 module"]
@@ -565,7 +565,7 @@ pub type GPIO_HI_OUT_CLR = crate::Reg<gpio_hi_out_clr::GPIO_HI_OUT_CLR_SPEC>;
 pub mod gpio_hi_out_clr;
 #[doc = "GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_out_xor`]
 module"]
@@ -574,7 +574,7 @@ pub type GPIO_HI_OUT_XOR = crate::Reg<gpio_hi_out_xor::GPIO_HI_OUT_XOR_SPEC>;
 pub mod gpio_hi_out_xor;
 #[doc = "GPIO_HI_OE (rw) register accessor: QSPI output enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_oe`]
 module"]
@@ -583,7 +583,7 @@ pub type GPIO_HI_OE = crate::Reg<gpio_hi_oe::GPIO_HI_OE_SPEC>;
 pub mod gpio_hi_oe;
 #[doc = "GPIO_HI_OE_SET (w) register accessor: QSPI output enable set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_oe_set`]
 module"]
@@ -592,7 +592,7 @@ pub type GPIO_HI_OE_SET = crate::Reg<gpio_hi_oe_set::GPIO_HI_OE_SET_SPEC>;
 pub mod gpio_hi_oe_set;
 #[doc = "GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_oe_clr`]
 module"]
@@ -601,7 +601,7 @@ pub type GPIO_HI_OE_CLR = crate::Reg<gpio_hi_oe_clr::GPIO_HI_OE_CLR_SPEC>;
 pub mod gpio_hi_oe_clr;
 #[doc = "GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_oe_xor`]
 module"]
@@ -614,7 +614,7 @@ pub mod gpio_hi_oe_xor;
  Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).  
  The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo_st`]
 module"]
@@ -627,7 +627,7 @@ pub type FIFO_ST = crate::Reg<fifo_st::FIFO_ST_SPEC>;
 pub mod fifo_st;
 #[doc = "FIFO_WR (w) register accessor: Write access to this core's TX FIFO  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo_wr`]
 module"]
@@ -636,7 +636,7 @@ pub type FIFO_WR = crate::Reg<fifo_wr::FIFO_WR_SPEC>;
 pub mod fifo_wr;
 #[doc = "FIFO_RD (r) register accessor: Read access to this core's RX FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`fifo_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@fifo_rd`]
 module"]
@@ -647,7 +647,7 @@ pub mod fifo_rd;
  A bitmap containing the state of all 32 spinlocks (1=locked).  
  Mainly intended for debugging.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`spinlock_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@spinlock_st`]
 module"]
@@ -662,7 +662,7 @@ pub mod spinlock_st;
  UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an  
  unsigned calculation, and the S alias starts a signed calculation.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_udividend::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_udividend::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_udividend`]
 module"]
@@ -679,7 +679,7 @@ pub mod div_udividend;
  UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an  
  unsigned calculation, and the S alias starts a signed calculation.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_udivisor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_udivisor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_udivisor`]
 module"]
@@ -693,7 +693,7 @@ pub mod div_udivisor;
 #[doc = "DIV_SDIVIDEND (rw) register accessor: Divider signed dividend  
  The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_sdividend::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_sdividend::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_sdividend`]
 module"]
@@ -704,7 +704,7 @@ pub mod div_sdividend;
 #[doc = "DIV_SDIVISOR (rw) register accessor: Divider signed divisor  
  The same as UDIVISOR, but starts a signed calculation, rather than unsigned.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_sdivisor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_sdivisor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_sdivisor`]
 module"]
@@ -720,7 +720,7 @@ pub mod div_sdivisor;
  Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order  
  REMAINDER, QUOTIENT if CSR_DIRTY is used.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_quotient::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_quotient::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_quotient`]
 module"]
@@ -739,7 +739,7 @@ pub mod div_quotient;
  This register can be written to directly, for context save/restore purposes. This halts any  
  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_remainder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_remainder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_remainder`]
 module"]
@@ -752,7 +752,7 @@ pub type DIV_REMAINDER = crate::Reg<div_remainder::DIV_REMAINDER_SPEC>;
 pub mod div_remainder;
 #[doc = "DIV_CSR (r) register accessor: Control and status register for divider.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`div_csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@div_csr`]
 module"]
@@ -761,7 +761,7 @@ pub type DIV_CSR = crate::Reg<div_csr::DIV_CSR_SPEC>;
 pub mod div_csr;
 #[doc = "INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_accum0`]
 module"]
@@ -770,7 +770,7 @@ pub type INTERP0_ACCUM0 = crate::Reg<interp0_accum0::INTERP0_ACCUM0_SPEC>;
 pub mod interp0_accum0;
 #[doc = "INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_accum1`]
 module"]
@@ -779,7 +779,7 @@ pub type INTERP0_ACCUM1 = crate::Reg<interp0_accum1::INTERP0_ACCUM1_SPEC>;
 pub mod interp0_accum1;
 #[doc = "INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_base0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_base0`]
 module"]
@@ -788,7 +788,7 @@ pub type INTERP0_BASE0 = crate::Reg<interp0_base0::INTERP0_BASE0_SPEC>;
 pub mod interp0_base0;
 #[doc = "INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_base1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_base1`]
 module"]
@@ -797,7 +797,7 @@ pub type INTERP0_BASE1 = crate::Reg<interp0_base1::INTERP0_BASE1_SPEC>;
 pub mod interp0_base1;
 #[doc = "INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_base2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_base2`]
 module"]
@@ -806,7 +806,7 @@ pub type INTERP0_BASE2 = crate::Reg<interp0_base2::INTERP0_BASE2_SPEC>;
 pub mod interp0_base2;
 #[doc = "INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_pop_lane0`]
 module"]
@@ -815,7 +815,7 @@ pub type INTERP0_POP_LANE0 = crate::Reg<interp0_pop_lane0::INTERP0_POP_LANE0_SPE
 pub mod interp0_pop_lane0;
 #[doc = "INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_pop_lane1`]
 module"]
@@ -824,7 +824,7 @@ pub type INTERP0_POP_LANE1 = crate::Reg<interp0_pop_lane1::INTERP0_POP_LANE1_SPE
 pub mod interp0_pop_lane1;
 #[doc = "INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_pop_full`]
 module"]
@@ -833,7 +833,7 @@ pub type INTERP0_POP_FULL = crate::Reg<interp0_pop_full::INTERP0_POP_FULL_SPEC>;
 pub mod interp0_pop_full;
 #[doc = "INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_peek_lane0`]
 module"]
@@ -842,7 +842,7 @@ pub type INTERP0_PEEK_LANE0 = crate::Reg<interp0_peek_lane0::INTERP0_PEEK_LANE0_
 pub mod interp0_peek_lane0;
 #[doc = "INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_peek_lane1`]
 module"]
@@ -851,7 +851,7 @@ pub type INTERP0_PEEK_LANE1 = crate::Reg<interp0_peek_lane1::INTERP0_PEEK_LANE1_
 pub mod interp0_peek_lane1;
 #[doc = "INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_peek_full`]
 module"]
@@ -860,7 +860,7 @@ pub type INTERP0_PEEK_FULL = crate::Reg<interp0_peek_full::INTERP0_PEEK_FULL_SPE
 pub mod interp0_peek_full;
 #[doc = "INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_ctrl_lane0`]
 module"]
@@ -869,7 +869,7 @@ pub type INTERP0_CTRL_LANE0 = crate::Reg<interp0_ctrl_lane0::INTERP0_CTRL_LANE0_
 pub mod interp0_ctrl_lane0;
 #[doc = "INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_ctrl_lane1`]
 module"]
@@ -879,7 +879,7 @@ pub mod interp0_ctrl_lane1;
 #[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0  
  Reading yields lane 0's raw shift and mask value (BASE0 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum0_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_accum0_add`]
 module"]
@@ -890,7 +890,7 @@ pub mod interp0_accum0_add;
 #[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1  
  Reading yields lane 1's raw shift and mask value (BASE1 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum1_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_accum1_add`]
 module"]
@@ -901,7 +901,7 @@ pub mod interp0_accum1_add;
 #[doc = "INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.  
  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp0_base_1and0`]
 module"]
@@ -911,7 +911,7 @@ pub type INTERP0_BASE_1AND0 = crate::Reg<interp0_base_1and0::INTERP0_BASE_1AND0_
 pub mod interp0_base_1and0;
 #[doc = "INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_accum0`]
 module"]
@@ -920,7 +920,7 @@ pub type INTERP1_ACCUM0 = crate::Reg<interp1_accum0::INTERP1_ACCUM0_SPEC>;
 pub mod interp1_accum0;
 #[doc = "INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_accum1`]
 module"]
@@ -929,7 +929,7 @@ pub type INTERP1_ACCUM1 = crate::Reg<interp1_accum1::INTERP1_ACCUM1_SPEC>;
 pub mod interp1_accum1;
 #[doc = "INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_base0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_base0`]
 module"]
@@ -938,7 +938,7 @@ pub type INTERP1_BASE0 = crate::Reg<interp1_base0::INTERP1_BASE0_SPEC>;
 pub mod interp1_base0;
 #[doc = "INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_base1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_base1`]
 module"]
@@ -947,7 +947,7 @@ pub type INTERP1_BASE1 = crate::Reg<interp1_base1::INTERP1_BASE1_SPEC>;
 pub mod interp1_base1;
 #[doc = "INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_base2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_base2`]
 module"]
@@ -956,7 +956,7 @@ pub type INTERP1_BASE2 = crate::Reg<interp1_base2::INTERP1_BASE2_SPEC>;
 pub mod interp1_base2;
 #[doc = "INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_pop_lane0`]
 module"]
@@ -965,7 +965,7 @@ pub type INTERP1_POP_LANE0 = crate::Reg<interp1_pop_lane0::INTERP1_POP_LANE0_SPE
 pub mod interp1_pop_lane0;
 #[doc = "INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_pop_lane1`]
 module"]
@@ -974,7 +974,7 @@ pub type INTERP1_POP_LANE1 = crate::Reg<interp1_pop_lane1::INTERP1_POP_LANE1_SPE
 pub mod interp1_pop_lane1;
 #[doc = "INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_pop_full`]
 module"]
@@ -983,7 +983,7 @@ pub type INTERP1_POP_FULL = crate::Reg<interp1_pop_full::INTERP1_POP_FULL_SPEC>;
 pub mod interp1_pop_full;
 #[doc = "INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_peek_lane0`]
 module"]
@@ -992,7 +992,7 @@ pub type INTERP1_PEEK_LANE0 = crate::Reg<interp1_peek_lane0::INTERP1_PEEK_LANE0_
 pub mod interp1_peek_lane0;
 #[doc = "INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_peek_lane1`]
 module"]
@@ -1001,7 +1001,7 @@ pub type INTERP1_PEEK_LANE1 = crate::Reg<interp1_peek_lane1::INTERP1_PEEK_LANE1_
 pub mod interp1_peek_lane1;
 #[doc = "INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_peek_full`]
 module"]
@@ -1010,7 +1010,7 @@ pub type INTERP1_PEEK_FULL = crate::Reg<interp1_peek_full::INTERP1_PEEK_FULL_SPE
 pub mod interp1_peek_full;
 #[doc = "INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_ctrl_lane0`]
 module"]
@@ -1019,7 +1019,7 @@ pub type INTERP1_CTRL_LANE0 = crate::Reg<interp1_ctrl_lane0::INTERP1_CTRL_LANE0_
 pub mod interp1_ctrl_lane0;
 #[doc = "INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_ctrl_lane1`]
 module"]
@@ -1029,7 +1029,7 @@ pub mod interp1_ctrl_lane1;
 #[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0  
  Reading yields lane 0's raw shift and mask value (BASE0 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum0_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_accum0_add`]
 module"]
@@ -1040,7 +1040,7 @@ pub mod interp1_accum0_add;
 #[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1  
  Reading yields lane 1's raw shift and mask value (BASE1 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum1_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_accum1_add`]
 module"]
@@ -1051,7 +1051,7 @@ pub mod interp1_accum1_add;
 #[doc = "INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.  
  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@interp1_base_1and0`]
 module"]
@@ -1067,7 +1067,7 @@ pub mod interp1_base_1and0;
  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.  
  The value returned on success is 0x1 &lt;&lt; lock number.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@spinlock`]
 module"]
diff --git a/src/sio/cpuid.rs b/src/sio/cpuid.rs
index f9cfebe71..ade436157 100644
--- a/src/sio/cpuid.rs
+++ b/src/sio/cpuid.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CPUID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Processor core identifier  
  Value is 0 when read from processor core 0, and 1 when read from processor core 1.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUID_SPEC;
 impl crate::RegisterSpec for CPUID_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_csr.rs b/src/sio/div_csr.rs
index a4d4ca012..48ad24b97 100644
--- a/src/sio/div_csr.rs
+++ b/src/sio/div_csr.rs
@@ -32,7 +32,7 @@ impl R {
 }
 #[doc = "Control and status register for divider.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_CSR_SPEC;
 impl crate::RegisterSpec for DIV_CSR_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_quotient.rs b/src/sio/div_quotient.rs
index d16a6cda5..91b6ff375 100644
--- a/src/sio/div_quotient.rs
+++ b/src/sio/div_quotient.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_QUOTIENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider result quotient  
  The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.  
@@ -21,7 +16,7 @@ impl W {}
  Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order  
  REMAINDER, QUOTIENT if CSR_DIRTY is used.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_quotient::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_quotient::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_QUOTIENT_SPEC;
 impl crate::RegisterSpec for DIV_QUOTIENT_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_remainder.rs b/src/sio/div_remainder.rs
index 12e963907..73b527aac 100644
--- a/src/sio/div_remainder.rs
+++ b/src/sio/div_remainder.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_REMAINDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider result remainder  
  The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.  
@@ -19,7 +14,7 @@ impl W {}
  This register can be written to directly, for context save/restore purposes. This halts any  
  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_remainder::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_remainder::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_REMAINDER_SPEC;
 impl crate::RegisterSpec for DIV_REMAINDER_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_sdividend.rs b/src/sio/div_sdividend.rs
index f94dfeefd..7cdabf897 100644
--- a/src/sio/div_sdividend.rs
+++ b/src/sio/div_sdividend.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_SDIVIDEND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider signed dividend  
  The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_sdividend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_sdividend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SDIVIDEND_SPEC;
 impl crate::RegisterSpec for DIV_SDIVIDEND_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_sdivisor.rs b/src/sio/div_sdivisor.rs
index b6a93d79d..fbd8f867d 100644
--- a/src/sio/div_sdivisor.rs
+++ b/src/sio/div_sdivisor.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_SDIVISOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider signed divisor  
  The same as UDIVISOR, but starts a signed calculation, rather than unsigned.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_sdivisor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_sdivisor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SDIVISOR_SPEC;
 impl crate::RegisterSpec for DIV_SDIVISOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_udividend.rs b/src/sio/div_udividend.rs
index 7dce964b5..5dc2ed883 100644
--- a/src/sio/div_udividend.rs
+++ b/src/sio/div_udividend.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_UDIVIDEND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider unsigned dividend  
  Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.  
@@ -19,7 +14,7 @@ impl W {}
  UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an  
  unsigned calculation, and the S alias starts a signed calculation.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_udividend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_udividend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_UDIVIDEND_SPEC;
 impl crate::RegisterSpec for DIV_UDIVIDEND_SPEC {
     type Ux = u32;
diff --git a/src/sio/div_udivisor.rs b/src/sio/div_udivisor.rs
index 835a5d191..eac6e0db3 100644
--- a/src/sio/div_udivisor.rs
+++ b/src/sio/div_udivisor.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DIV_UDIVISOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Divider unsigned divisor  
  Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.  
@@ -19,7 +14,7 @@ impl W {}
  UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an  
  unsigned calculation, and the S alias starts a signed calculation.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`div_udivisor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_udivisor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_UDIVISOR_SPEC;
 impl crate::RegisterSpec for DIV_UDIVISOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/fifo_rd.rs b/src/sio/fifo_rd.rs
index d087d0867..efb5c84d6 100644
--- a/src/sio/fifo_rd.rs
+++ b/src/sio/fifo_rd.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<FIFO_RD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read access to this core's RX FIFO  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fifo_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_RD_SPEC;
 impl crate::RegisterSpec for FIFO_RD_SPEC {
     type Ux = u32;
diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs
index 4429b09fd..60e23a94a 100644
--- a/src/sio/fifo_st.rs
+++ b/src/sio/fifo_st.rs
@@ -56,7 +56,7 @@ impl W {
  Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).  
  The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`fifo_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
     type Ux = u32;
diff --git a/src/sio/fifo_wr.rs b/src/sio/fifo_wr.rs
index b36d923d6..2ba228efc 100644
--- a/src/sio/fifo_wr.rs
+++ b/src/sio/fifo_wr.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for crate::generic::Reg<FIFO_WR_SPEC> {
 impl W {}
 #[doc = "Write access to this core's TX FIFO  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_WR_SPEC;
 impl crate::RegisterSpec for FIFO_WR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_in.rs b/src/sio/gpio_hi_in.rs
index 5a3b133ad..aee666321 100644
--- a/src/sio/gpio_hi_in.rs
+++ b/src/sio/gpio_hi_in.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Input value for QSPI pins  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_IN_SPEC;
 impl crate::RegisterSpec for GPIO_HI_IN_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs
index d5dfa20da..09142c0d9 100644
--- a/src/sio/gpio_hi_oe.rs
+++ b/src/sio/gpio_hi_oe.rs
@@ -39,7 +39,7 @@ impl W {
 }
 #[doc = "QSPI output enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OE_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OE_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/sio/gpio_hi_oe_clr.rs
index 748742b54..e9374a14f 100644
--- a/src/sio/gpio_hi_oe_clr.rs
+++ b/src/sio/gpio_hi_oe_clr.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output enable clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OE_CLR_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OE_CLR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_oe_set.rs b/src/sio/gpio_hi_oe_set.rs
index 094595426..3e72bf0a7 100644
--- a/src/sio/gpio_hi_oe_set.rs
+++ b/src/sio/gpio_hi_oe_set.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output enable set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OE_SET_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OE_SET_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/sio/gpio_hi_oe_xor.rs
index 76a630857..fad56b36a 100644
--- a/src/sio/gpio_hi_oe_xor.rs
+++ b/src/sio/gpio_hi_oe_xor.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output enable XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OE_XOR_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OE_XOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs
index 4bbc32ede..66683f34c 100644
--- a/src/sio/gpio_hi_out.rs
+++ b/src/sio/gpio_hi_out.rs
@@ -39,7 +39,7 @@ impl W {
 }
 #[doc = "QSPI output value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OUT_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OUT_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_out_clr.rs b/src/sio/gpio_hi_out_clr.rs
index 83f98f24f..d26409e73 100644
--- a/src/sio/gpio_hi_out_clr.rs
+++ b/src/sio/gpio_hi_out_clr.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output value clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OUT_CLR_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OUT_CLR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_out_set.rs b/src/sio/gpio_hi_out_set.rs
index f9b7d8e8d..daee0e39f 100644
--- a/src/sio/gpio_hi_out_set.rs
+++ b/src/sio/gpio_hi_out_set.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output value set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OUT_SET_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OUT_SET_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_hi_out_xor.rs b/src/sio/gpio_hi_out_xor.rs
index 791a410bd..3afab566c 100644
--- a/src/sio/gpio_hi_out_xor.rs
+++ b/src/sio/gpio_hi_out_xor.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "QSPI output value XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OUT_XOR_SPEC;
 impl crate::RegisterSpec for GPIO_HI_OUT_XOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_in.rs b/src/sio/gpio_in.rs
index 618b234ea..bd154f345 100644
--- a/src/sio/gpio_in.rs
+++ b/src/sio/gpio_in.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Input value for GPIO pins  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_IN_SPEC;
 impl crate::RegisterSpec for GPIO_IN_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs
index 0856f430d..01862888b 100644
--- a/src/sio/gpio_oe.rs
+++ b/src/sio/gpio_oe.rs
@@ -39,7 +39,7 @@ impl W {
 }
 #[doc = "GPIO output enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_oe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OE_SPEC;
 impl crate::RegisterSpec for GPIO_OE_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_oe_clr.rs b/src/sio/gpio_oe_clr.rs
index 9fe86e678..fc52a7ec9 100644
--- a/src/sio/gpio_oe_clr.rs
+++ b/src/sio/gpio_oe_clr.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output enable clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OE_CLR_SPEC;
 impl crate::RegisterSpec for GPIO_OE_CLR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_oe_set.rs b/src/sio/gpio_oe_set.rs
index f2adb3c2f..5314faa88 100644
--- a/src/sio/gpio_oe_set.rs
+++ b/src/sio/gpio_oe_set.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output enable set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OE_SET_SPEC;
 impl crate::RegisterSpec for GPIO_OE_SET_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_oe_xor.rs b/src/sio/gpio_oe_xor.rs
index c45870cf6..b6335b949 100644
--- a/src/sio/gpio_oe_xor.rs
+++ b/src/sio/gpio_oe_xor.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output enable XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OE_XOR_SPEC;
 impl crate::RegisterSpec for GPIO_OE_XOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs
index 77b14ae53..ff3431996 100644
--- a/src/sio/gpio_out.rs
+++ b/src/sio/gpio_out.rs
@@ -39,7 +39,7 @@ impl W {
 }
 #[doc = "GPIO output value  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gpio_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OUT_SPEC;
 impl crate::RegisterSpec for GPIO_OUT_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_out_clr.rs b/src/sio/gpio_out_clr.rs
index d854fc1a0..b5cf4ef68 100644
--- a/src/sio/gpio_out_clr.rs
+++ b/src/sio/gpio_out_clr.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output value clear  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OUT_CLR_SPEC;
 impl crate::RegisterSpec for GPIO_OUT_CLR_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_out_set.rs b/src/sio/gpio_out_set.rs
index 11b64976f..c3517b908 100644
--- a/src/sio/gpio_out_set.rs
+++ b/src/sio/gpio_out_set.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output value set  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OUT_SET_SPEC;
 impl crate::RegisterSpec for GPIO_OUT_SET_SPEC {
     type Ux = u32;
diff --git a/src/sio/gpio_out_xor.rs b/src/sio/gpio_out_xor.rs
index 1e51f0029..06d9b3fdd 100644
--- a/src/sio/gpio_out_xor.rs
+++ b/src/sio/gpio_out_xor.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "GPIO output value XOR  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_OUT_XOR_SPEC;
 impl crate::RegisterSpec for GPIO_OUT_XOR_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_accum0.rs b/src/sio/interp0_accum0.rs
index ed7c47463..c359827d1 100644
--- a/src/sio/interp0_accum0.rs
+++ b/src/sio/interp0_accum0.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_ACCUM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to accumulator 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_ACCUM0_SPEC;
 impl crate::RegisterSpec for INTERP0_ACCUM0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs
index 1addd12d8..5064365d5 100644
--- a/src/sio/interp0_accum0_add.rs
+++ b/src/sio/interp0_accum0_add.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Values written here are atomically added to ACCUM0  
  Reading yields lane 0's raw shift and mask value (BASE0 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum0_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_ACCUM0_ADD_SPEC;
 impl crate::RegisterSpec for INTERP0_ACCUM0_ADD_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_accum1.rs b/src/sio/interp0_accum1.rs
index 787d98c73..661d5ee15 100644
--- a/src/sio/interp0_accum1.rs
+++ b/src/sio/interp0_accum1.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_ACCUM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to accumulator 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_ACCUM1_SPEC;
 impl crate::RegisterSpec for INTERP0_ACCUM1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs
index 86ec6c6f5..9216d7707 100644
--- a/src/sio/interp0_accum1_add.rs
+++ b/src/sio/interp0_accum1_add.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Values written here are atomically added to ACCUM1  
  Reading yields lane 1's raw shift and mask value (BASE1 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_accum1_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_ACCUM1_ADD_SPEC;
 impl crate::RegisterSpec for INTERP0_ACCUM1_ADD_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_base0.rs b/src/sio/interp0_base0.rs
index adb318c1d..0961040ae 100644
--- a/src/sio/interp0_base0.rs
+++ b/src/sio/interp0_base0.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_BASE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE0 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_base0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_BASE0_SPEC;
 impl crate::RegisterSpec for INTERP0_BASE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_base1.rs b/src/sio/interp0_base1.rs
index d22741585..8e157e004 100644
--- a/src/sio/interp0_base1.rs
+++ b/src/sio/interp0_base1.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_BASE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE1 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_base1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_BASE1_SPEC;
 impl crate::RegisterSpec for INTERP0_BASE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_base2.rs b/src/sio/interp0_base2.rs
index 93931169f..b9b86974e 100644
--- a/src/sio/interp0_base2.rs
+++ b/src/sio/interp0_base2.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_BASE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE2 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_base2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_BASE2_SPEC;
 impl crate::RegisterSpec for INTERP0_BASE2_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_base_1and0.rs b/src/sio/interp0_base_1and0.rs
index 8f705a5da..019cb94a6 100644
--- a/src/sio/interp0_base_1and0.rs
+++ b/src/sio/interp0_base_1and0.rs
@@ -9,7 +9,7 @@ impl W {}
 #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.  
  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_BASE_1AND0_SPEC;
 impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs
index e5d70135f..3ea461eb8 100644
--- a/src/sio/interp0_ctrl_lane0.rs
+++ b/src/sio/interp0_ctrl_lane0.rs
@@ -208,7 +208,7 @@ impl W {
 }
 #[doc = "Control register for lane 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_CTRL_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP0_CTRL_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs
index 3f27fbab6..d430579f7 100644
--- a/src/sio/interp0_ctrl_lane1.rs
+++ b/src/sio/interp0_ctrl_lane1.rs
@@ -148,7 +148,7 @@ impl W {
 }
 #[doc = "Control register for lane 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_ctrl_lane1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_CTRL_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP0_CTRL_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_peek_full.rs b/src/sio/interp0_peek_full.rs
index 0098698b8..9621fe7e2 100644
--- a/src/sio/interp0_peek_full.rs
+++ b/src/sio/interp0_peek_full.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_PEEK_FULL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read FULL result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_PEEK_FULL_SPEC;
 impl crate::RegisterSpec for INTERP0_PEEK_FULL_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_peek_lane0.rs b/src/sio/interp0_peek_lane0.rs
index 12dd8e331..8cdd5804e 100644
--- a/src/sio/interp0_peek_lane0.rs
+++ b/src/sio/interp0_peek_lane0.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_PEEK_LANE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE0 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_PEEK_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP0_PEEK_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_peek_lane1.rs b/src/sio/interp0_peek_lane1.rs
index 16de12b8b..d2e37197c 100644
--- a/src/sio/interp0_peek_lane1.rs
+++ b/src/sio/interp0_peek_lane1.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_PEEK_LANE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE1 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_PEEK_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP0_PEEK_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_pop_full.rs b/src/sio/interp0_pop_full.rs
index 85d27ade5..3048d7093 100644
--- a/src/sio/interp0_pop_full.rs
+++ b/src/sio/interp0_pop_full.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_POP_FULL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_POP_FULL_SPEC;
 impl crate::RegisterSpec for INTERP0_POP_FULL_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_pop_lane0.rs b/src/sio/interp0_pop_lane0.rs
index 084d3f958..492ee2826 100644
--- a/src/sio/interp0_pop_lane0.rs
+++ b/src/sio/interp0_pop_lane0.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_POP_LANE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_POP_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP0_POP_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp0_pop_lane1.rs b/src/sio/interp0_pop_lane1.rs
index 654bc12b6..b2ab1ba8f 100644
--- a/src/sio/interp0_pop_lane1.rs
+++ b/src/sio/interp0_pop_lane1.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP0_POP_LANE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP0_POP_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP0_POP_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_accum0.rs b/src/sio/interp1_accum0.rs
index fb71f4bbc..13e3c795b 100644
--- a/src/sio/interp1_accum0.rs
+++ b/src/sio/interp1_accum0.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_ACCUM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to accumulator 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_ACCUM0_SPEC;
 impl crate::RegisterSpec for INTERP1_ACCUM0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs
index 98b58b1a9..3d7bfef9c 100644
--- a/src/sio/interp1_accum0_add.rs
+++ b/src/sio/interp1_accum0_add.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Values written here are atomically added to ACCUM0  
  Reading yields lane 0's raw shift and mask value (BASE0 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum0_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_ACCUM0_ADD_SPEC;
 impl crate::RegisterSpec for INTERP1_ACCUM0_ADD_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_accum1.rs b/src/sio/interp1_accum1.rs
index cb4174a1c..c9b84cf82 100644
--- a/src/sio/interp1_accum1.rs
+++ b/src/sio/interp1_accum1.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_ACCUM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to accumulator 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_ACCUM1_SPEC;
 impl crate::RegisterSpec for INTERP1_ACCUM1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs
index 7d4194fb6..89bd9b2c7 100644
--- a/src/sio/interp1_accum1_add.rs
+++ b/src/sio/interp1_accum1_add.rs
@@ -24,7 +24,7 @@ impl W {
 #[doc = "Values written here are atomically added to ACCUM1  
  Reading yields lane 1's raw shift and mask value (BASE1 not added).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_accum1_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_ACCUM1_ADD_SPEC;
 impl crate::RegisterSpec for INTERP1_ACCUM1_ADD_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_base0.rs b/src/sio/interp1_base0.rs
index 91dc452e4..9f6c02dcc 100644
--- a/src/sio/interp1_base0.rs
+++ b/src/sio/interp1_base0.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_BASE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE0 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_base0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_BASE0_SPEC;
 impl crate::RegisterSpec for INTERP1_BASE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_base1.rs b/src/sio/interp1_base1.rs
index 35c0e3e46..bf0359050 100644
--- a/src/sio/interp1_base1.rs
+++ b/src/sio/interp1_base1.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_BASE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE1 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_base1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_BASE1_SPEC;
 impl crate::RegisterSpec for INTERP1_BASE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_base2.rs b/src/sio/interp1_base2.rs
index 38a7dc662..47f75ac48 100644
--- a/src/sio/interp1_base2.rs
+++ b/src/sio/interp1_base2.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_BASE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Read/write access to BASE2 register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_base2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_BASE2_SPEC;
 impl crate::RegisterSpec for INTERP1_BASE2_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_base_1and0.rs b/src/sio/interp1_base_1and0.rs
index 962e327e2..3e3796309 100644
--- a/src/sio/interp1_base_1and0.rs
+++ b/src/sio/interp1_base_1and0.rs
@@ -9,7 +9,7 @@ impl W {}
 #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.  
  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_BASE_1AND0_SPEC;
 impl crate::RegisterSpec for INTERP1_BASE_1AND0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs
index f43f516e4..f8a6d73f1 100644
--- a/src/sio/interp1_ctrl_lane0.rs
+++ b/src/sio/interp1_ctrl_lane0.rs
@@ -196,7 +196,7 @@ impl W {
 }
 #[doc = "Control register for lane 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_CTRL_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP1_CTRL_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs
index 288187fb8..095071e69 100644
--- a/src/sio/interp1_ctrl_lane1.rs
+++ b/src/sio/interp1_ctrl_lane1.rs
@@ -148,7 +148,7 @@ impl W {
 }
 #[doc = "Control register for lane 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_ctrl_lane1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_CTRL_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP1_CTRL_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_peek_full.rs b/src/sio/interp1_peek_full.rs
index 715edb49a..df0de77fb 100644
--- a/src/sio/interp1_peek_full.rs
+++ b/src/sio/interp1_peek_full.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_PEEK_FULL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read FULL result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_PEEK_FULL_SPEC;
 impl crate::RegisterSpec for INTERP1_PEEK_FULL_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_peek_lane0.rs b/src/sio/interp1_peek_lane0.rs
index a1f693a21..cd6d6d1fd 100644
--- a/src/sio/interp1_peek_lane0.rs
+++ b/src/sio/interp1_peek_lane0.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_PEEK_LANE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE0 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_PEEK_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP1_PEEK_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_peek_lane1.rs b/src/sio/interp1_peek_lane1.rs
index f026c4e94..36901f519 100644
--- a/src/sio/interp1_peek_lane1.rs
+++ b/src/sio/interp1_peek_lane1.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_PEEK_LANE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE1 result, without altering any internal state (PEEK).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_PEEK_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP1_PEEK_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_pop_full.rs b/src/sio/interp1_pop_full.rs
index 9dd9ddc99..ad7212808 100644
--- a/src/sio/interp1_pop_full.rs
+++ b/src/sio/interp1_pop_full.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_POP_FULL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_POP_FULL_SPEC;
 impl crate::RegisterSpec for INTERP1_POP_FULL_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_pop_lane0.rs b/src/sio/interp1_pop_lane0.rs
index c02444534..d33638ba1 100644
--- a/src/sio/interp1_pop_lane0.rs
+++ b/src/sio/interp1_pop_lane0.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_POP_LANE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_POP_LANE0_SPEC;
 impl crate::RegisterSpec for INTERP1_POP_LANE0_SPEC {
     type Ux = u32;
diff --git a/src/sio/interp1_pop_lane1.rs b/src/sio/interp1_pop_lane1.rs
index 4a174b396..272f100f0 100644
--- a/src/sio/interp1_pop_lane1.rs
+++ b/src/sio/interp1_pop_lane1.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<INTERP1_POP_LANE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERP1_POP_LANE1_SPEC;
 impl crate::RegisterSpec for INTERP1_POP_LANE1_SPEC {
     type Ux = u32;
diff --git a/src/sio/spinlock.rs b/src/sio/spinlock.rs
index f1d37fb24..de6f0397e 100644
--- a/src/sio/spinlock.rs
+++ b/src/sio/spinlock.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SPINLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Reading from a spinlock address will:  
  - Return 0 if lock is already locked  
@@ -21,7 +16,7 @@ impl W {}
  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.  
  The value returned on success is 0x1 &lt;&lt; lock number.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`spinlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPINLOCK_SPEC;
 impl crate::RegisterSpec for SPINLOCK_SPEC {
     type Ux = u32;
diff --git a/src/sio/spinlock_st.rs b/src/sio/spinlock_st.rs
index da83deab1..fdd670aed 100644
--- a/src/sio/spinlock_st.rs
+++ b/src/sio/spinlock_st.rs
@@ -5,16 +5,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SPINLOCK_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Spinlock state  
  A bitmap containing the state of all 32 spinlocks (1=locked).  
  Mainly intended for debugging.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`spinlock_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPINLOCK_ST_SPEC;
 impl crate::RegisterSpec for SPINLOCK_ST_SPEC {
     type Ux = u32;
diff --git a/src/spi0.rs b/src/spi0.rs
index 50c0c5629..8dab6debb 100644
--- a/src/spi0.rs
+++ b/src/spi0.rs
@@ -115,7 +115,7 @@ impl RegisterBlock {
 }
 #[doc = "SSPCR0 (rw) register accessor: Control register 0, SSPCR0 on page 3-4  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspcr0`]
 module"]
@@ -124,7 +124,7 @@ pub type SSPCR0 = crate::Reg<sspcr0::SSPCR0_SPEC>;
 pub mod sspcr0;
 #[doc = "SSPCR1 (rw) register accessor: Control register 1, SSPCR1 on page 3-5  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspcr1`]
 module"]
@@ -133,7 +133,7 @@ pub type SSPCR1 = crate::Reg<sspcr1::SSPCR1_SPEC>;
 pub mod sspcr1;
 #[doc = "SSPDR (rw) register accessor: Data register, SSPDR on page 3-6  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspdr`]
 module"]
@@ -142,7 +142,7 @@ pub type SSPDR = crate::Reg<sspdr::SSPDR_SPEC>;
 pub mod sspdr;
 #[doc = "SSPSR (r) register accessor: Status register, SSPSR on page 3-7  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspsr`]
 module"]
@@ -151,7 +151,7 @@ pub type SSPSR = crate::Reg<sspsr::SSPSR_SPEC>;
 pub mod sspsr;
 #[doc = "SSPCPSR (rw) register accessor: Clock prescale register, SSPCPSR on page 3-8  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcpsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspcpsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcpsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspcpsr`]
 module"]
@@ -160,7 +160,7 @@ pub type SSPCPSR = crate::Reg<sspcpsr::SSPCPSR_SPEC>;
 pub mod sspcpsr;
 #[doc = "SSPIMSC (rw) register accessor: Interrupt mask set or clear register, SSPIMSC on page 3-9  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspimsc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspimsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspimsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspimsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspimsc`]
 module"]
@@ -169,7 +169,7 @@ pub type SSPIMSC = crate::Reg<sspimsc::SSPIMSC_SPEC>;
 pub mod sspimsc;
 #[doc = "SSPRIS (r) register accessor: Raw interrupt status register, SSPRIS on page 3-10  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspris`]
 module"]
@@ -178,7 +178,7 @@ pub type SSPRIS = crate::Reg<sspris::SSPRIS_SPEC>;
 pub mod sspris;
 #[doc = "SSPMIS (r) register accessor: Masked interrupt status register, SSPMIS on page 3-11  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspmis`]
 module"]
@@ -187,7 +187,7 @@ pub type SSPMIS = crate::Reg<sspmis::SSPMIS_SPEC>;
 pub mod sspmis;
 #[doc = "SSPICR (rw) register accessor: Interrupt clear register, SSPICR on page 3-11  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspicr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspicr`]
 module"]
@@ -196,7 +196,7 @@ pub type SSPICR = crate::Reg<sspicr::SSPICR_SPEC>;
 pub mod sspicr;
 #[doc = "SSPDMACR (rw) register accessor: DMA control register, SSPDMACR on page 3-12  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspdmacr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspdmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspdmacr`]
 module"]
@@ -205,7 +205,7 @@ pub type SSPDMACR = crate::Reg<sspdmacr::SSPDMACR_SPEC>;
 pub mod sspdmacr;
 #[doc = "SSPPERIPHID0 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspperiphid0`]
 module"]
@@ -214,7 +214,7 @@ pub type SSPPERIPHID0 = crate::Reg<sspperiphid0::SSPPERIPHID0_SPEC>;
 pub mod sspperiphid0;
 #[doc = "SSPPERIPHID1 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspperiphid1`]
 module"]
@@ -223,7 +223,7 @@ pub type SSPPERIPHID1 = crate::Reg<sspperiphid1::SSPPERIPHID1_SPEC>;
 pub mod sspperiphid1;
 #[doc = "SSPPERIPHID2 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspperiphid2`]
 module"]
@@ -232,7 +232,7 @@ pub type SSPPERIPHID2 = crate::Reg<sspperiphid2::SSPPERIPHID2_SPEC>;
 pub mod sspperiphid2;
 #[doc = "SSPPERIPHID3 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sspperiphid3`]
 module"]
@@ -241,7 +241,7 @@ pub type SSPPERIPHID3 = crate::Reg<sspperiphid3::SSPPERIPHID3_SPEC>;
 pub mod sspperiphid3;
 #[doc = "SSPPCELLID0 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssppcellid0`]
 module"]
@@ -250,7 +250,7 @@ pub type SSPPCELLID0 = crate::Reg<ssppcellid0::SSPPCELLID0_SPEC>;
 pub mod ssppcellid0;
 #[doc = "SSPPCELLID1 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssppcellid1`]
 module"]
@@ -259,7 +259,7 @@ pub type SSPPCELLID1 = crate::Reg<ssppcellid1::SSPPCELLID1_SPEC>;
 pub mod ssppcellid1;
 #[doc = "SSPPCELLID2 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssppcellid2`]
 module"]
@@ -268,7 +268,7 @@ pub type SSPPCELLID2 = crate::Reg<ssppcellid2::SSPPCELLID2_SPEC>;
 pub mod ssppcellid2;
 #[doc = "SSPPCELLID3 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssppcellid3`]
 module"]
diff --git a/src/spi0/sspcpsr.rs b/src/spi0/sspcpsr.rs
index faf3ebf27..a33fd13b5 100644
--- a/src/spi0/sspcpsr.rs
+++ b/src/spi0/sspcpsr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Clock prescale register, SSPCPSR on page 3-8  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcpsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspcpsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcpsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPCPSR_SPEC;
 impl crate::RegisterSpec for SSPCPSR_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs
index 62df85ffd..af346a6cb 100644
--- a/src/spi0/sspcr0.rs
+++ b/src/spi0/sspcr0.rs
@@ -28,6 +28,7 @@ impl From<FRF_A> for u8 {
 impl crate::FieldSpec for FRF_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FRF_A {}
 #[doc = "Field `FRF` reader - Frame format."]
 pub type FRF_R = crate::FieldReader<FRF_A>;
 impl FRF_R {
@@ -153,7 +154,7 @@ impl W {
 }
 #[doc = "Control register 0, SSPCR0 on page 3-4  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPCR0_SPEC;
 impl crate::RegisterSpec for SSPCR0_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspcr1.rs b/src/spi0/sspcr1.rs
index 1d0f306b8..83310a02c 100644
--- a/src/spi0/sspcr1.rs
+++ b/src/spi0/sspcr1.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Control register 1, SSPCR1 on page 3-5  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspcr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPCR1_SPEC;
 impl crate::RegisterSpec for SSPCR1_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspdmacr.rs b/src/spi0/sspdmacr.rs
index 713ed08e8..6ce7cebd5 100644
--- a/src/spi0/sspdmacr.rs
+++ b/src/spi0/sspdmacr.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "DMA control register, SSPDMACR on page 3-12  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspdmacr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspdmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPDMACR_SPEC;
 impl crate::RegisterSpec for SSPDMACR_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs
index c438c31c6..06c13eccf 100644
--- a/src/spi0/sspdr.rs
+++ b/src/spi0/sspdr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Data register, SSPDR on page 3-6  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspdr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPDR_SPEC;
 impl crate::RegisterSpec for SSPDR_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspicr.rs b/src/spi0/sspicr.rs
index 1f25518a8..68fd651b9 100644
--- a/src/spi0/sspicr.rs
+++ b/src/spi0/sspicr.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Interrupt clear register, SSPICR on page 3-11  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspicr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPICR_SPEC;
 impl crate::RegisterSpec for SSPICR_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspimsc.rs b/src/spi0/sspimsc.rs
index 24c8f2d25..230de5c9c 100644
--- a/src/spi0/sspimsc.rs
+++ b/src/spi0/sspimsc.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspimsc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspimsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspimsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPIMSC_SPEC;
 impl crate::RegisterSpec for SSPIMSC_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspmis.rs b/src/spi0/sspmis.rs
index 1329ba084..72600f22f 100644
--- a/src/spi0/sspmis.rs
+++ b/src/spi0/sspmis.rs
@@ -32,7 +32,7 @@ impl R {
 }
 #[doc = "Masked interrupt status register, SSPMIS on page 3-11  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPMIS_SPEC;
 impl crate::RegisterSpec for SSPMIS_SPEC {
     type Ux = u32;
diff --git a/src/spi0/ssppcellid0.rs b/src/spi0/ssppcellid0.rs
index b8e8f7aac..f96cb220f 100644
--- a/src/spi0/ssppcellid0.rs
+++ b/src/spi0/ssppcellid0.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPCELLID0_SPEC;
 impl crate::RegisterSpec for SSPPCELLID0_SPEC {
     type Ux = u32;
diff --git a/src/spi0/ssppcellid1.rs b/src/spi0/ssppcellid1.rs
index 7510668af..2f3e8065f 100644
--- a/src/spi0/ssppcellid1.rs
+++ b/src/spi0/ssppcellid1.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPCELLID1_SPEC;
 impl crate::RegisterSpec for SSPPCELLID1_SPEC {
     type Ux = u32;
diff --git a/src/spi0/ssppcellid2.rs b/src/spi0/ssppcellid2.rs
index 8e2e677ee..52ba674e7 100644
--- a/src/spi0/ssppcellid2.rs
+++ b/src/spi0/ssppcellid2.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPCELLID2_SPEC;
 impl crate::RegisterSpec for SSPPCELLID2_SPEC {
     type Ux = u32;
diff --git a/src/spi0/ssppcellid3.rs b/src/spi0/ssppcellid3.rs
index d4bf3d482..598248987 100644
--- a/src/spi0/ssppcellid3.rs
+++ b/src/spi0/ssppcellid3.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssppcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPCELLID3_SPEC;
 impl crate::RegisterSpec for SSPPCELLID3_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspperiphid0.rs b/src/spi0/sspperiphid0.rs
index 42cf2dd49..917e032bd 100644
--- a/src/spi0/sspperiphid0.rs
+++ b/src/spi0/sspperiphid0.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPERIPHID0_SPEC;
 impl crate::RegisterSpec for SSPPERIPHID0_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspperiphid1.rs b/src/spi0/sspperiphid1.rs
index 9495b3aef..b36a466bc 100644
--- a/src/spi0/sspperiphid1.rs
+++ b/src/spi0/sspperiphid1.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPERIPHID1_SPEC;
 impl crate::RegisterSpec for SSPPERIPHID1_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspperiphid2.rs b/src/spi0/sspperiphid2.rs
index abe13bc7d..2799786fc 100644
--- a/src/spi0/sspperiphid2.rs
+++ b/src/spi0/sspperiphid2.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPERIPHID2_SPEC;
 impl crate::RegisterSpec for SSPPERIPHID2_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspperiphid3.rs b/src/spi0/sspperiphid3.rs
index 16e371536..df336579c 100644
--- a/src/spi0/sspperiphid3.rs
+++ b/src/spi0/sspperiphid3.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPPERIPHID3_SPEC;
 impl crate::RegisterSpec for SSPPERIPHID3_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspris.rs b/src/spi0/sspris.rs
index f986c00f2..99dda4194 100644
--- a/src/spi0/sspris.rs
+++ b/src/spi0/sspris.rs
@@ -32,7 +32,7 @@ impl R {
 }
 #[doc = "Raw interrupt status register, SSPRIS on page 3-10  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPRIS_SPEC;
 impl crate::RegisterSpec for SSPRIS_SPEC {
     type Ux = u32;
diff --git a/src/spi0/sspsr.rs b/src/spi0/sspsr.rs
index 145a7eca8..50ba9f040 100644
--- a/src/spi0/sspsr.rs
+++ b/src/spi0/sspsr.rs
@@ -39,7 +39,7 @@ impl R {
 }
 #[doc = "Status register, SSPSR on page 3-7  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sspsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSPSR_SPEC;
 impl crate::RegisterSpec for SSPSR_SPEC {
     type Ux = u32;
diff --git a/src/syscfg.rs b/src/syscfg.rs
index 06df3a0b0..94962f0a2 100644
--- a/src/syscfg.rs
+++ b/src/syscfg.rs
@@ -60,7 +60,7 @@ impl RegisterBlock {
 #[doc = "PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask  
  Set a bit high to enable NMI from that IRQ  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc0_nmi_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_nmi_mask`]
 module"]
@@ -71,7 +71,7 @@ pub mod proc0_nmi_mask;
 #[doc = "PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask  
  Set a bit high to enable NMI from that IRQ  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc1_nmi_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_nmi_mask`]
 module"]
@@ -81,7 +81,7 @@ pub type PROC1_NMI_MASK = crate::Reg<proc1_nmi_mask::PROC1_NMI_MASK_SPEC>;
 pub mod proc1_nmi_mask;
 #[doc = "PROC_CONFIG (rw) register accessor: Configuration for processors  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc_config`]
 module"]
@@ -94,7 +94,7 @@ pub mod proc_config;
  If you're feeling brave, you can bypass to save two cycles of input  
  latency. This register applies to GPIO 0...29.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc_in_sync_bypass`]
 module"]
@@ -111,7 +111,7 @@ pub mod proc_in_sync_bypass;
  If you're feeling brave, you can bypass to save two cycles of input  
  latency. This register applies to GPIO 30...35 (the QSPI IOs).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc_in_sync_bypass_hi`]
 module"]
@@ -124,7 +124,7 @@ pub type PROC_IN_SYNC_BYPASS_HI = crate::Reg<proc_in_sync_bypass_hi::PROC_IN_SYN
 pub mod proc_in_sync_bypass_hi;
 #[doc = "DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbgforce::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgforce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dbgforce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgforce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dbgforce`]
 module"]
@@ -134,7 +134,7 @@ pub mod dbgforce;
 #[doc = "MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.  
  Use with extreme caution  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mempowerdown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mempowerdown`]
 module"]
diff --git a/src/syscfg/dbgforce.rs b/src/syscfg/dbgforce.rs
index 5610506df..709e8a910 100644
--- a/src/syscfg/dbgforce.rs
+++ b/src/syscfg/dbgforce.rs
@@ -112,7 +112,7 @@ impl W {
 }
 #[doc = "Directly control the SWD debug port of either processor  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbgforce::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgforce::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dbgforce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgforce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBGFORCE_SPEC;
 impl crate::RegisterSpec for DBGFORCE_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs
index 255cb702f..8b256d4ef 100644
--- a/src/syscfg/mempowerdown.rs
+++ b/src/syscfg/mempowerdown.rs
@@ -129,7 +129,7 @@ impl W {
 #[doc = "Control power downs to memories. Set high to power down memories.  
  Use with extreme caution  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mempowerdown::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mempowerdown::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEMPOWERDOWN_SPEC;
 impl crate::RegisterSpec for MEMPOWERDOWN_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/proc0_nmi_mask.rs b/src/syscfg/proc0_nmi_mask.rs
index 76d02c5ae..28acb6caa 100644
--- a/src/syscfg/proc0_nmi_mask.rs
+++ b/src/syscfg/proc0_nmi_mask.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<PROC0_NMI_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Processor core 0 NMI source mask  
  Set a bit high to enable NMI from that IRQ  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc0_nmi_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_NMI_MASK_SPEC;
 impl crate::RegisterSpec for PROC0_NMI_MASK_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/proc1_nmi_mask.rs b/src/syscfg/proc1_nmi_mask.rs
index ca0b40bec..79cf8e682 100644
--- a/src/syscfg/proc1_nmi_mask.rs
+++ b/src/syscfg/proc1_nmi_mask.rs
@@ -7,16 +7,11 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<PROC1_NMI_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Processor core 1 NMI source mask  
  Set a bit high to enable NMI from that IRQ  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc1_nmi_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_NMI_MASK_SPEC;
 impl crate::RegisterSpec for PROC1_NMI_MASK_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs
index 6358aff53..467ef6250 100644
--- a/src/syscfg/proc_config.rs
+++ b/src/syscfg/proc_config.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Configuration for processors  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC_CONFIG_SPEC;
 impl crate::RegisterSpec for PROC_CONFIG_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs
index 52db7ddc6..614eaa2d1 100644
--- a/src/syscfg/proc_in_sync_bypass.rs
+++ b/src/syscfg/proc_in_sync_bypass.rs
@@ -27,7 +27,7 @@ impl W {
  If you're feeling brave, you can bypass to save two cycles of input  
  latency. This register applies to GPIO 0...29.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC_IN_SYNC_BYPASS_SPEC;
 impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_SPEC {
     type Ux = u32;
diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs
index 28e7a8072..7ea140a10 100644
--- a/src/syscfg/proc_in_sync_bypass_hi.rs
+++ b/src/syscfg/proc_in_sync_bypass_hi.rs
@@ -29,7 +29,7 @@ impl W {
  If you're feeling brave, you can bypass to save two cycles of input  
  latency. This register applies to GPIO 30...35 (the QSPI IOs).  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC_IN_SYNC_BYPASS_HI_SPEC;
 impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_HI_SPEC {
     type Ux = u32;
diff --git a/src/sysinfo.rs b/src/sysinfo.rs
index 6396a522d..83648114b 100644
--- a/src/sysinfo.rs
+++ b/src/sysinfo.rs
@@ -25,7 +25,7 @@ impl RegisterBlock {
 }
 #[doc = "CHIP_ID (r) register accessor: JEDEC JEP-106 compliant chip identifier.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`chip_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@chip_id`]
 module"]
@@ -34,7 +34,7 @@ pub type CHIP_ID = crate::Reg<chip_id::CHIP_ID_SPEC>;
 pub mod chip_id;
 #[doc = "PLATFORM (r) register accessor: Platform register. Allows software to know what environment it is running in.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@platform`]
 module"]
@@ -43,7 +43,7 @@ pub type PLATFORM = crate::Reg<platform::PLATFORM_SPEC>;
 pub mod platform;
 #[doc = "GITREF_RP2040 (r) register accessor: Git hash of the chip source. Used to identify chip version.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`gitref_rp2040::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gitref_rp2040`]
 module"]
diff --git a/src/sysinfo/chip_id.rs b/src/sysinfo/chip_id.rs
index 8801dc74e..696549b6e 100644
--- a/src/sysinfo/chip_id.rs
+++ b/src/sysinfo/chip_id.rs
@@ -25,7 +25,7 @@ impl R {
 }
 #[doc = "JEDEC JEP-106 compliant chip identifier.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`chip_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHIP_ID_SPEC;
 impl crate::RegisterSpec for CHIP_ID_SPEC {
     type Ux = u32;
diff --git a/src/sysinfo/gitref_rp2040.rs b/src/sysinfo/gitref_rp2040.rs
index 400ea57b5..2c13aed67 100644
--- a/src/sysinfo/gitref_rp2040.rs
+++ b/src/sysinfo/gitref_rp2040.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<GITREF_RP2040_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Git hash of the chip source. Used to identify chip version.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`gitref_rp2040::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GITREF_RP2040_SPEC;
 impl crate::RegisterSpec for GITREF_RP2040_SPEC {
     type Ux = u32;
diff --git a/src/sysinfo/platform.rs b/src/sysinfo/platform.rs
index 42b7f4f9d..427d6161d 100644
--- a/src/sysinfo/platform.rs
+++ b/src/sysinfo/platform.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Platform register. Allows software to know what environment it is running in.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PLATFORM_SPEC;
 impl crate::RegisterSpec for PLATFORM_SPEC {
     type Ux = u32;
diff --git a/src/tbman.rs b/src/tbman.rs
index 85ad7fd3e..46b9e0171 100644
--- a/src/tbman.rs
+++ b/src/tbman.rs
@@ -12,7 +12,7 @@ impl RegisterBlock {
 }
 #[doc = "PLATFORM (r) register accessor: Indicates the type of platform in use  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@platform`]
 module"]
diff --git a/src/tbman/platform.rs b/src/tbman/platform.rs
index c0bacd525..48fa07d84 100644
--- a/src/tbman/platform.rs
+++ b/src/tbman/platform.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Indicates the type of platform in use  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PLATFORM_SPEC;
 impl crate::RegisterSpec for PLATFORM_SPEC {
     type Ux = u32;
diff --git a/src/timer.rs b/src/timer.rs
index e61a6f28b..1ac64ee02 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -127,7 +127,7 @@ impl RegisterBlock {
 #[doc = "TIMEHW (w) register accessor: Write to bits 63:32 of time  
  always write timelw before timehw  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timehw`]
 module"]
@@ -138,7 +138,7 @@ pub mod timehw;
 #[doc = "TIMELW (w) register accessor: Write to bits 31:0 of time  
  writes do not get copied to time until timehw is written  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timelw`]
 module"]
@@ -149,7 +149,7 @@ pub mod timelw;
 #[doc = "TIMEHR (r) register accessor: Read from bits 63:32 of time  
  always read timelr before timehr  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timehr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timehr`]
 module"]
@@ -159,7 +159,7 @@ pub type TIMEHR = crate::Reg<timehr::TIMEHR_SPEC>;
 pub mod timehr;
 #[doc = "TIMELR (r) register accessor: Read from bits 31:0 of time  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timelr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timelr`]
 module"]
@@ -171,7 +171,7 @@ pub mod timelr;
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`alarm0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@alarm0`]
 module"]
@@ -186,7 +186,7 @@ pub mod alarm0;
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`alarm1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@alarm1`]
 module"]
@@ -201,7 +201,7 @@ pub mod alarm1;
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`alarm2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@alarm2`]
 module"]
@@ -216,7 +216,7 @@ pub mod alarm2;
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`alarm3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@alarm3`]
 module"]
@@ -231,7 +231,7 @@ pub mod alarm3;
  Alarms automatically disarm upon firing, but writing ones here  
  will disarm immediately without waiting to fire.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`armed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@armed`]
 module"]
@@ -243,7 +243,7 @@ pub type ARMED = crate::Reg<armed::ARMED_SPEC>;
 pub mod armed;
 #[doc = "TIMERAWH (r) register accessor: Raw read from bits 63:32 of time (no side effects)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timerawh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timerawh`]
 module"]
@@ -252,7 +252,7 @@ pub type TIMERAWH = crate::Reg<timerawh::TIMERAWH_SPEC>;
 pub mod timerawh;
 #[doc = "TIMERAWL (r) register accessor: Raw read from bits 31:0 of time (no side effects)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`timerawl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@timerawl`]
 module"]
@@ -261,7 +261,7 @@ pub type TIMERAWL = crate::Reg<timerawl::TIMERAWL_SPEC>;
 pub mod timerawl;
 #[doc = "DBGPAUSE (rw) register accessor: Set bits high to enable pause when the corresponding debug ports are active  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbgpause::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgpause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dbgpause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgpause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dbgpause`]
 module"]
@@ -270,7 +270,7 @@ pub type DBGPAUSE = crate::Reg<dbgpause::DBGPAUSE_SPEC>;
 pub mod dbgpause;
 #[doc = "PAUSE (rw) register accessor: Set high to pause the timer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`pause::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`pause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@pause`]
 module"]
@@ -279,7 +279,7 @@ pub type PAUSE = crate::Reg<pause::PAUSE_SPEC>;
 pub mod pause;
 #[doc = "INTR (rw) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -288,7 +288,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -297,7 +297,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -306,7 +306,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/timer/alarm0.rs b/src/timer/alarm0.rs
index f1e81b6ed..ba59909d2 100644
--- a/src/timer/alarm0.rs
+++ b/src/timer/alarm0.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<ALARM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Arm alarm 0, and configure the time it will fire.  
  Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.  
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`alarm0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ALARM0_SPEC;
 impl crate::RegisterSpec for ALARM0_SPEC {
     type Ux = u32;
diff --git a/src/timer/alarm1.rs b/src/timer/alarm1.rs
index 777798520..dcc4c13fd 100644
--- a/src/timer/alarm1.rs
+++ b/src/timer/alarm1.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<ALARM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Arm alarm 1, and configure the time it will fire.  
  Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.  
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`alarm1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ALARM1_SPEC;
 impl crate::RegisterSpec for ALARM1_SPEC {
     type Ux = u32;
diff --git a/src/timer/alarm2.rs b/src/timer/alarm2.rs
index fc9df4b3b..14f036606 100644
--- a/src/timer/alarm2.rs
+++ b/src/timer/alarm2.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<ALARM2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Arm alarm 2, and configure the time it will fire.  
  Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.  
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`alarm2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ALARM2_SPEC;
 impl crate::RegisterSpec for ALARM2_SPEC {
     type Ux = u32;
diff --git a/src/timer/alarm3.rs b/src/timer/alarm3.rs
index 1cfb87e31..478331087 100644
--- a/src/timer/alarm3.rs
+++ b/src/timer/alarm3.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<ALARM3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Arm alarm 3, and configure the time it will fire.  
  Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.  
  The alarm will disarm itself once it fires, and can  
  be disarmed early using the ARMED status register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`alarm3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ALARM3_SPEC;
 impl crate::RegisterSpec for ALARM3_SPEC {
     type Ux = u32;
diff --git a/src/timer/armed.rs b/src/timer/armed.rs
index b904725f3..0e562155b 100644
--- a/src/timer/armed.rs
+++ b/src/timer/armed.rs
@@ -26,7 +26,7 @@ impl W {
  Alarms automatically disarm upon firing, but writing ones here  
  will disarm immediately without waiting to fire.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`armed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`armed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARMED_SPEC;
 impl crate::RegisterSpec for ARMED_SPEC {
     type Ux = u32;
diff --git a/src/timer/dbgpause.rs b/src/timer/dbgpause.rs
index d13345ae0..297ed6942 100644
--- a/src/timer/dbgpause.rs
+++ b/src/timer/dbgpause.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Set bits high to enable pause when the corresponding debug ports are active  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dbgpause::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgpause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dbgpause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgpause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBGPAUSE_SPEC;
 impl crate::RegisterSpec for DBGPAUSE_SPEC {
     type Ux = u32;
diff --git a/src/timer/inte.rs b/src/timer/inte.rs
index 585e887fb..d219e793e 100644
--- a/src/timer/inte.rs
+++ b/src/timer/inte.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/timer/intf.rs b/src/timer/intf.rs
index 6f93aeaf9..7ab273da0 100644
--- a/src/timer/intf.rs
+++ b/src/timer/intf.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/timer/intr.rs b/src/timer/intr.rs
index 571158973..58e42f857 100644
--- a/src/timer/intr.rs
+++ b/src/timer/intr.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/timer/ints.rs b/src/timer/ints.rs
index 07c304dee..bca66ef87 100644
--- a/src/timer/ints.rs
+++ b/src/timer/ints.rs
@@ -32,7 +32,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/timer/pause.rs b/src/timer/pause.rs
index 754e0f3d9..1a466e292 100644
--- a/src/timer/pause.rs
+++ b/src/timer/pause.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Set high to pause the timer  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`pause::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`pause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PAUSE_SPEC;
 impl crate::RegisterSpec for PAUSE_SPEC {
     type Ux = u32;
diff --git a/src/timer/timehr.rs b/src/timer/timehr.rs
index d2b74ad15..89cf98f65 100644
--- a/src/timer/timehr.rs
+++ b/src/timer/timehr.rs
@@ -5,15 +5,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<TIMEHR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read from bits 63:32 of time  
  always read timelr before timehr  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timehr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMEHR_SPEC;
 impl crate::RegisterSpec for TIMEHR_SPEC {
     type Ux = u32;
diff --git a/src/timer/timehw.rs b/src/timer/timehw.rs
index 86dfb59ab..6d5a3eb41 100644
--- a/src/timer/timehw.rs
+++ b/src/timer/timehw.rs
@@ -9,7 +9,7 @@ impl W {}
 #[doc = "Write to bits 63:32 of time  
  always write timelw before timehw  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMEHW_SPEC;
 impl crate::RegisterSpec for TIMEHW_SPEC {
     type Ux = u32;
diff --git a/src/timer/timelr.rs b/src/timer/timelr.rs
index c61b62115..923307f9f 100644
--- a/src/timer/timelr.rs
+++ b/src/timer/timelr.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<TIMELR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read from bits 31:0 of time  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timelr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMELR_SPEC;
 impl crate::RegisterSpec for TIMELR_SPEC {
     type Ux = u32;
diff --git a/src/timer/timelw.rs b/src/timer/timelw.rs
index 0ef1b5cb6..0d60f88b9 100644
--- a/src/timer/timelw.rs
+++ b/src/timer/timelw.rs
@@ -9,7 +9,7 @@ impl W {}
 #[doc = "Write to bits 31:0 of time  
  writes do not get copied to time until timehw is written  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMELW_SPEC;
 impl crate::RegisterSpec for TIMELW_SPEC {
     type Ux = u32;
diff --git a/src/timer/timerawh.rs b/src/timer/timerawh.rs
index 6606249a8..2316a4707 100644
--- a/src/timer/timerawh.rs
+++ b/src/timer/timerawh.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<TIMERAWH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw read from bits 63:32 of time (no side effects)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timerawh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMERAWH_SPEC;
 impl crate::RegisterSpec for TIMERAWH_SPEC {
     type Ux = u32;
diff --git a/src/timer/timerawl.rs b/src/timer/timerawl.rs
index d64a58ffd..7dd332b1b 100644
--- a/src/timer/timerawl.rs
+++ b/src/timer/timerawl.rs
@@ -5,14 +5,9 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<TIMERAWL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw read from bits 31:0 of time (no side effects)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`timerawl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMERAWL_SPEC;
 impl crate::RegisterSpec for TIMERAWL_SPEC {
     type Ux = u32;
diff --git a/src/uart0.rs b/src/uart0.rs
index fd19a9339..cb779858f 100644
--- a/src/uart0.rs
+++ b/src/uart0.rs
@@ -141,7 +141,7 @@ impl RegisterBlock {
 }
 #[doc = "UARTDR (rw) register accessor: Data Register, UARTDR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartdr`]
 module"]
@@ -150,7 +150,7 @@ pub type UARTDR = crate::Reg<uartdr::UARTDR_SPEC>;
 pub mod uartdr;
 #[doc = "UARTRSR (rw) register accessor: Receive Status Register/Error Clear Register, UARTRSR/UARTECR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartrsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartrsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartrsr`]
 module"]
@@ -159,7 +159,7 @@ pub type UARTRSR = crate::Reg<uartrsr::UARTRSR_SPEC>;
 pub mod uartrsr;
 #[doc = "UARTFR (r) register accessor: Flag Register, UARTFR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartfr`]
 module"]
@@ -168,7 +168,7 @@ pub type UARTFR = crate::Reg<uartfr::UARTFR_SPEC>;
 pub mod uartfr;
 #[doc = "UARTILPR (rw) register accessor: IrDA Low-Power Counter Register, UARTILPR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartilpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartilpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartilpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartilpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartilpr`]
 module"]
@@ -177,7 +177,7 @@ pub type UARTILPR = crate::Reg<uartilpr::UARTILPR_SPEC>;
 pub mod uartilpr;
 #[doc = "UARTIBRD (rw) register accessor: Integer Baud Rate Register, UARTIBRD  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartibrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartibrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartibrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartibrd`]
 module"]
@@ -186,7 +186,7 @@ pub type UARTIBRD = crate::Reg<uartibrd::UARTIBRD_SPEC>;
 pub mod uartibrd;
 #[doc = "UARTFBRD (rw) register accessor: Fractional Baud Rate Register, UARTFBRD  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartfbrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartfbrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfbrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartfbrd`]
 module"]
@@ -195,7 +195,7 @@ pub type UARTFBRD = crate::Reg<uartfbrd::UARTFBRD_SPEC>;
 pub mod uartfbrd;
 #[doc = "UARTLCR_H (rw) register accessor: Line Control Register, UARTLCR_H  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartlcr_h::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartlcr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartlcr_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlcr_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartlcr_h`]
 module"]
@@ -204,7 +204,7 @@ pub type UARTLCR_H = crate::Reg<uartlcr_h::UARTLCR_H_SPEC>;
 pub mod uartlcr_h;
 #[doc = "UARTCR (rw) register accessor: Control Register, UARTCR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartcr`]
 module"]
@@ -213,7 +213,7 @@ pub type UARTCR = crate::Reg<uartcr::UARTCR_SPEC>;
 pub mod uartcr;
 #[doc = "UARTIFLS (rw) register accessor: Interrupt FIFO Level Select Register, UARTIFLS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartifls::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartifls::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartifls::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartifls`]
 module"]
@@ -222,7 +222,7 @@ pub type UARTIFLS = crate::Reg<uartifls::UARTIFLS_SPEC>;
 pub mod uartifls;
 #[doc = "UARTIMSC (rw) register accessor: Interrupt Mask Set/Clear Register, UARTIMSC  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartimsc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartimsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartimsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartimsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartimsc`]
 module"]
@@ -231,7 +231,7 @@ pub type UARTIMSC = crate::Reg<uartimsc::UARTIMSC_SPEC>;
 pub mod uartimsc;
 #[doc = "UARTRIS (r) register accessor: Raw Interrupt Status Register, UARTRIS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartris`]
 module"]
@@ -240,7 +240,7 @@ pub type UARTRIS = crate::Reg<uartris::UARTRIS_SPEC>;
 pub mod uartris;
 #[doc = "UARTMIS (r) register accessor: Masked Interrupt Status Register, UARTMIS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartmis`]
 module"]
@@ -249,7 +249,7 @@ pub type UARTMIS = crate::Reg<uartmis::UARTMIS_SPEC>;
 pub mod uartmis;
 #[doc = "UARTICR (rw) register accessor: Interrupt Clear Register, UARTICR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uarticr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uarticr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uarticr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uarticr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uarticr`]
 module"]
@@ -258,7 +258,7 @@ pub type UARTICR = crate::Reg<uarticr::UARTICR_SPEC>;
 pub mod uarticr;
 #[doc = "UARTDMACR (rw) register accessor: DMA Control Register, UARTDMACR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartdmacr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartdmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartdmacr`]
 module"]
@@ -267,7 +267,7 @@ pub type UARTDMACR = crate::Reg<uartdmacr::UARTDMACR_SPEC>;
 pub mod uartdmacr;
 #[doc = "UARTPERIPHID0 (r) register accessor: UARTPeriphID0 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartperiphid0`]
 module"]
@@ -276,7 +276,7 @@ pub type UARTPERIPHID0 = crate::Reg<uartperiphid0::UARTPERIPHID0_SPEC>;
 pub mod uartperiphid0;
 #[doc = "UARTPERIPHID1 (r) register accessor: UARTPeriphID1 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartperiphid1`]
 module"]
@@ -285,7 +285,7 @@ pub type UARTPERIPHID1 = crate::Reg<uartperiphid1::UARTPERIPHID1_SPEC>;
 pub mod uartperiphid1;
 #[doc = "UARTPERIPHID2 (r) register accessor: UARTPeriphID2 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartperiphid2`]
 module"]
@@ -294,7 +294,7 @@ pub type UARTPERIPHID2 = crate::Reg<uartperiphid2::UARTPERIPHID2_SPEC>;
 pub mod uartperiphid2;
 #[doc = "UARTPERIPHID3 (r) register accessor: UARTPeriphID3 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartperiphid3`]
 module"]
@@ -303,7 +303,7 @@ pub type UARTPERIPHID3 = crate::Reg<uartperiphid3::UARTPERIPHID3_SPEC>;
 pub mod uartperiphid3;
 #[doc = "UARTPCELLID0 (r) register accessor: UARTPCellID0 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartpcellid0`]
 module"]
@@ -312,7 +312,7 @@ pub type UARTPCELLID0 = crate::Reg<uartpcellid0::UARTPCELLID0_SPEC>;
 pub mod uartpcellid0;
 #[doc = "UARTPCELLID1 (r) register accessor: UARTPCellID1 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartpcellid1`]
 module"]
@@ -321,7 +321,7 @@ pub type UARTPCELLID1 = crate::Reg<uartpcellid1::UARTPCELLID1_SPEC>;
 pub mod uartpcellid1;
 #[doc = "UARTPCELLID2 (r) register accessor: UARTPCellID2 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartpcellid2`]
 module"]
@@ -330,7 +330,7 @@ pub type UARTPCELLID2 = crate::Reg<uartpcellid2::UARTPCELLID2_SPEC>;
 pub mod uartpcellid2;
 #[doc = "UARTPCELLID3 (r) register accessor: UARTPCellID3 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@uartpcellid3`]
 module"]
diff --git a/src/uart0/uartcr.rs b/src/uart0/uartcr.rs
index dae084b70..0fa9e0394 100644
--- a/src/uart0/uartcr.rs
+++ b/src/uart0/uartcr.rs
@@ -188,7 +188,7 @@ impl W {
 }
 #[doc = "Control Register, UARTCR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTCR_SPEC;
 impl crate::RegisterSpec for UARTCR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartdmacr.rs b/src/uart0/uartdmacr.rs
index b9507f10d..7540239bb 100644
--- a/src/uart0/uartdmacr.rs
+++ b/src/uart0/uartdmacr.rs
@@ -53,7 +53,7 @@ impl W {
 }
 #[doc = "DMA Control Register, UARTDMACR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartdmacr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartdmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTDMACR_SPEC;
 impl crate::RegisterSpec for UARTDMACR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs
index 536a5856a..4f115df44 100644
--- a/src/uart0/uartdr.rs
+++ b/src/uart0/uartdr.rs
@@ -51,7 +51,7 @@ impl W {
 }
 #[doc = "Data Register, UARTDR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartdr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTDR_SPEC;
 impl crate::RegisterSpec for UARTDR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartfbrd.rs b/src/uart0/uartfbrd.rs
index b3ff61846..535f80b6f 100644
--- a/src/uart0/uartfbrd.rs
+++ b/src/uart0/uartfbrd.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Fractional Baud Rate Register, UARTFBRD  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartfbrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartfbrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfbrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTFBRD_SPEC;
 impl crate::RegisterSpec for UARTFBRD_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartfr.rs b/src/uart0/uartfr.rs
index 5c0a90224..49cb7d668 100644
--- a/src/uart0/uartfr.rs
+++ b/src/uart0/uartfr.rs
@@ -67,7 +67,7 @@ impl R {
 }
 #[doc = "Flag Register, UARTFR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTFR_SPEC;
 impl crate::RegisterSpec for UARTFR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartibrd.rs b/src/uart0/uartibrd.rs
index 737df2372..c3f86fecc 100644
--- a/src/uart0/uartibrd.rs
+++ b/src/uart0/uartibrd.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Integer Baud Rate Register, UARTIBRD  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartibrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartibrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartibrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTIBRD_SPEC;
 impl crate::RegisterSpec for UARTIBRD_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uarticr.rs b/src/uart0/uarticr.rs
index 4102b4406..8bfb38b2d 100644
--- a/src/uart0/uarticr.rs
+++ b/src/uart0/uarticr.rs
@@ -173,7 +173,7 @@ impl W {
 }
 #[doc = "Interrupt Clear Register, UARTICR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uarticr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uarticr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uarticr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uarticr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTICR_SPEC;
 impl crate::RegisterSpec for UARTICR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartifls.rs b/src/uart0/uartifls.rs
index beb565e1e..ce1621d35 100644
--- a/src/uart0/uartifls.rs
+++ b/src/uart0/uartifls.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Interrupt FIFO Level Select Register, UARTIFLS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartifls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartifls::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartifls::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTIFLS_SPEC;
 impl crate::RegisterSpec for UARTIFLS_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartilpr.rs b/src/uart0/uartilpr.rs
index e8568c88b..a45bd41ab 100644
--- a/src/uart0/uartilpr.rs
+++ b/src/uart0/uartilpr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "IrDA Low-Power Counter Register, UARTILPR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartilpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartilpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartilpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartilpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTILPR_SPEC;
 impl crate::RegisterSpec for UARTILPR_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartimsc.rs b/src/uart0/uartimsc.rs
index e34234078..3b79a4361 100644
--- a/src/uart0/uartimsc.rs
+++ b/src/uart0/uartimsc.rs
@@ -173,7 +173,7 @@ impl W {
 }
 #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartimsc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartimsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartimsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartimsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTIMSC_SPEC;
 impl crate::RegisterSpec for UARTIMSC_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartlcr_h.rs b/src/uart0/uartlcr_h.rs
index f06de8392..826348443 100644
--- a/src/uart0/uartlcr_h.rs
+++ b/src/uart0/uartlcr_h.rs
@@ -113,7 +113,7 @@ impl W {
 }
 #[doc = "Line Control Register, UARTLCR_H  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartlcr_h::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartlcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartlcr_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlcr_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTLCR_H_SPEC;
 impl crate::RegisterSpec for UARTLCR_H_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartmis.rs b/src/uart0/uartmis.rs
index 6e6a75b24..4f8979e70 100644
--- a/src/uart0/uartmis.rs
+++ b/src/uart0/uartmis.rs
@@ -81,7 +81,7 @@ impl R {
 }
 #[doc = "Masked Interrupt Status Register, UARTMIS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTMIS_SPEC;
 impl crate::RegisterSpec for UARTMIS_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartpcellid0.rs b/src/uart0/uartpcellid0.rs
index 267869f30..6bd1c6a1f 100644
--- a/src/uart0/uartpcellid0.rs
+++ b/src/uart0/uartpcellid0.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPCellID0 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPCELLID0_SPEC;
 impl crate::RegisterSpec for UARTPCELLID0_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartpcellid1.rs b/src/uart0/uartpcellid1.rs
index 3a6e0aaa8..44830afb1 100644
--- a/src/uart0/uartpcellid1.rs
+++ b/src/uart0/uartpcellid1.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPCellID1 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPCELLID1_SPEC;
 impl crate::RegisterSpec for UARTPCELLID1_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartpcellid2.rs b/src/uart0/uartpcellid2.rs
index aca6be310..0d31829c9 100644
--- a/src/uart0/uartpcellid2.rs
+++ b/src/uart0/uartpcellid2.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPCellID2 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPCELLID2_SPEC;
 impl crate::RegisterSpec for UARTPCELLID2_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartpcellid3.rs b/src/uart0/uartpcellid3.rs
index 20c3cbbd8..ecaa57ab1 100644
--- a/src/uart0/uartpcellid3.rs
+++ b/src/uart0/uartpcellid3.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPCellID3 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartpcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPCELLID3_SPEC;
 impl crate::RegisterSpec for UARTPCELLID3_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartperiphid0.rs b/src/uart0/uartperiphid0.rs
index 2adb7b15b..91df29626 100644
--- a/src/uart0/uartperiphid0.rs
+++ b/src/uart0/uartperiphid0.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPeriphID0 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPERIPHID0_SPEC;
 impl crate::RegisterSpec for UARTPERIPHID0_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartperiphid1.rs b/src/uart0/uartperiphid1.rs
index 83365ed0c..70aeaf2fc 100644
--- a/src/uart0/uartperiphid1.rs
+++ b/src/uart0/uartperiphid1.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "UARTPeriphID1 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPERIPHID1_SPEC;
 impl crate::RegisterSpec for UARTPERIPHID1_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartperiphid2.rs b/src/uart0/uartperiphid2.rs
index 814a1623a..1df7543cf 100644
--- a/src/uart0/uartperiphid2.rs
+++ b/src/uart0/uartperiphid2.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "UARTPeriphID2 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPERIPHID2_SPEC;
 impl crate::RegisterSpec for UARTPERIPHID2_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartperiphid3.rs b/src/uart0/uartperiphid3.rs
index f0469f93b..79d10ea06 100644
--- a/src/uart0/uartperiphid3.rs
+++ b/src/uart0/uartperiphid3.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "UARTPeriphID3 Register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTPERIPHID3_SPEC;
 impl crate::RegisterSpec for UARTPERIPHID3_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartris.rs b/src/uart0/uartris.rs
index fc94789fc..6d3705c00 100644
--- a/src/uart0/uartris.rs
+++ b/src/uart0/uartris.rs
@@ -81,7 +81,7 @@ impl R {
 }
 #[doc = "Raw Interrupt Status Register, UARTRIS  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTRIS_SPEC;
 impl crate::RegisterSpec for UARTRIS_SPEC {
     type Ux = u32;
diff --git a/src/uart0/uartrsr.rs b/src/uart0/uartrsr.rs
index cf629b0cb..4a692dfba 100644
--- a/src/uart0/uartrsr.rs
+++ b/src/uart0/uartrsr.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`uartrsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartrsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`uartrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UARTRSR_SPEC;
 impl crate::RegisterSpec for UARTRSR_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_dpram.rs b/src/usbctrl_dpram.rs
index d0daf7a2a..12a6c8df9 100644
--- a/src/usbctrl_dpram.rs
+++ b/src/usbctrl_dpram.rs
@@ -48,7 +48,7 @@ impl RegisterBlock {
 }
 #[doc = "SETUP_PACKET_LOW (rw) register accessor: Bytes 0-3 of the SETUP packet from the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_low::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`setup_packet_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@setup_packet_low`]
 module"]
@@ -57,7 +57,7 @@ pub type SETUP_PACKET_LOW = crate::Reg<setup_packet_low::SETUP_PACKET_LOW_SPEC>;
 pub mod setup_packet_low;
 #[doc = "SETUP_PACKET_HIGH (rw) register accessor: Bytes 4-7 of the setup packet from the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_high::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`setup_packet_high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@setup_packet_high`]
 module"]
@@ -66,7 +66,7 @@ pub type SETUP_PACKET_HIGH = crate::Reg<setup_packet_high::SETUP_PACKET_HIGH_SPE
 pub mod setup_packet_high;
 #[doc = "EP_CONTROL (rw) register accessor: -  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_control`]
 module"]
@@ -75,7 +75,7 @@ pub type EP_CONTROL = crate::Reg<ep_control::EP_CONTROL_SPEC>;
 pub mod ep_control;
 #[doc = "EP_BUFFER_CONTROL (rw) register accessor: -  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_buffer_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_buffer_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_buffer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_buffer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_buffer_control`]
 module"]
@@ -84,7 +84,7 @@ pub type EP_BUFFER_CONTROL = crate::Reg<ep_buffer_control::EP_BUFFER_CONTROL_SPE
 pub mod ep_buffer_control;
 #[doc = "EPX_CONTROL (rw) register accessor: EPx Control (Host-mode only!)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`epx_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`epx_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`epx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@epx_control`]
 module"]
diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs
index c977f2907..7102a0cfe 100644
--- a/src/usbctrl_dpram/ep_buffer_control.rs
+++ b/src/usbctrl_dpram/ep_buffer_control.rs
@@ -63,6 +63,7 @@ impl From<DOUBLE_BUFFER_ISO_OFFSET_A> for u8 {
 impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DOUBLE_BUFFER_ISO_OFFSET_A {}
 #[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.  
  For a non Isochronous endpoint the offset is always 64 bytes."]
 pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader<DOUBLE_BUFFER_ISO_OFFSET_A>;
@@ -102,7 +103,7 @@ impl DOUBLE_BUFFER_ISO_OFFSET_R {
 #[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.  
  For a non Isochronous endpoint the offset is always 64 bytes."]
 pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> =
-    crate::FieldWriterSafe<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A>;
+    crate::FieldWriter<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A, crate::Safe>;
 impl<'a, REG> DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -294,7 +295,7 @@ impl W {
 }
 #[doc = "-  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_buffer_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_buffer_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_buffer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_buffer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_BUFFER_CONTROL_SPEC;
 impl crate::RegisterSpec for EP_BUFFER_CONTROL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_dpram/ep_control.rs b/src/usbctrl_dpram/ep_control.rs
index ffaae0931..a7775ab29 100644
--- a/src/usbctrl_dpram/ep_control.rs
+++ b/src/usbctrl_dpram/ep_control.rs
@@ -42,6 +42,7 @@ impl From<ENDPOINT_TYPE_A> for u8 {
 impl crate::FieldSpec for ENDPOINT_TYPE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for ENDPOINT_TYPE_A {}
 #[doc = "Field `ENDPOINT_TYPE` reader - "]
 pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
 impl ENDPOINT_TYPE_R {
@@ -78,7 +79,7 @@ impl ENDPOINT_TYPE_R {
     }
 }
 #[doc = "Field `ENDPOINT_TYPE` writer - "]
-pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
+pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENDPOINT_TYPE_A, crate::Safe>;
 impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -226,7 +227,7 @@ impl W {
 }
 #[doc = "-  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_CONTROL_SPEC;
 impl crate::RegisterSpec for EP_CONTROL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_dpram/epx_control.rs b/src/usbctrl_dpram/epx_control.rs
index f045155f7..72422918c 100644
--- a/src/usbctrl_dpram/epx_control.rs
+++ b/src/usbctrl_dpram/epx_control.rs
@@ -38,6 +38,7 @@ impl From<ENDPOINT_TYPE_A> for u8 {
 impl crate::FieldSpec for ENDPOINT_TYPE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for ENDPOINT_TYPE_A {}
 #[doc = "Field `ENDPOINT_TYPE` reader - "]
 pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
 impl ENDPOINT_TYPE_R {
@@ -74,7 +75,7 @@ impl ENDPOINT_TYPE_R {
     }
 }
 #[doc = "Field `ENDPOINT_TYPE` writer - "]
-pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
+pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENDPOINT_TYPE_A, crate::Safe>;
 impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -211,7 +212,7 @@ impl W {
 }
 #[doc = "EPx Control (Host-mode only!)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`epx_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`epx_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`epx_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epx_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EPX_CONTROL_SPEC;
 impl crate::RegisterSpec for EPX_CONTROL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_dpram/setup_packet_high.rs b/src/usbctrl_dpram/setup_packet_high.rs
index 277833734..884207541 100644
--- a/src/usbctrl_dpram/setup_packet_high.rs
+++ b/src/usbctrl_dpram/setup_packet_high.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Bytes 4-7 of the setup packet from the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_high::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`setup_packet_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SETUP_PACKET_HIGH_SPEC;
 impl crate::RegisterSpec for SETUP_PACKET_HIGH_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_dpram/setup_packet_low.rs b/src/usbctrl_dpram/setup_packet_low.rs
index feac492d8..96743d82a 100644
--- a/src/usbctrl_dpram/setup_packet_low.rs
+++ b/src/usbctrl_dpram/setup_packet_low.rs
@@ -53,7 +53,7 @@ impl W {
 }
 #[doc = "Bytes 0-3 of the SETUP packet from the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`setup_packet_low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup_packet_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`setup_packet_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SETUP_PACKET_LOW_SPEC;
 impl crate::RegisterSpec for SETUP_PACKET_LOW_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs.rs b/src/usbctrl_regs.rs
index 621027c35..ea7ec9dca 100644
--- a/src/usbctrl_regs.rs
+++ b/src/usbctrl_regs.rs
@@ -232,7 +232,7 @@ impl RegisterBlock {
 }
 #[doc = "ADDR_ENDP (rw) register accessor: Device address and endpoint control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`addr_endp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`addr_endp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_endp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@addr_endp`]
 module"]
@@ -241,7 +241,7 @@ pub type ADDR_ENDP = crate::Reg<addr_endp::ADDR_ENDP_SPEC>;
 pub mod addr_endp;
 #[doc = "HOST_ADDR_ENDP (rw) register accessor: Interrupt endpoints. Only valid in HOST mode.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`host_addr_endp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_addr_endp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`host_addr_endp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_addr_endp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@host_addr_endp`]
 module"]
@@ -250,7 +250,7 @@ pub type HOST_ADDR_ENDP = crate::Reg<host_addr_endp::HOST_ADDR_ENDP_SPEC>;
 pub mod host_addr_endp;
 #[doc = "MAIN_CTRL (rw) register accessor: Main control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`main_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`main_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@main_ctrl`]
 module"]
@@ -259,7 +259,7 @@ pub type MAIN_CTRL = crate::Reg<main_ctrl::MAIN_CTRL_SPEC>;
 pub mod main_ctrl;
 #[doc = "SOF_WR (w) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sof_wr`]
 module"]
@@ -268,7 +268,7 @@ pub type SOF_WR = crate::Reg<sof_wr::SOF_WR_SPEC>;
 pub mod sof_wr;
 #[doc = "SOF_RD (r) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sof_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sof_rd`]
 module"]
@@ -277,7 +277,7 @@ pub type SOF_RD = crate::Reg<sof_rd::SOF_RD_SPEC>;
 pub mod sof_rd;
 #[doc = "SIE_CTRL (rw) register accessor: SIE control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sie_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sie_ctrl`]
 module"]
@@ -286,7 +286,7 @@ pub type SIE_CTRL = crate::Reg<sie_ctrl::SIE_CTRL_SPEC>;
 pub mod sie_ctrl;
 #[doc = "SIE_STATUS (rw) register accessor: SIE status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sie_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sie_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sie_status`]
 module"]
@@ -295,7 +295,7 @@ pub type SIE_STATUS = crate::Reg<sie_status::SIE_STATUS_SPEC>;
 pub mod sie_status;
 #[doc = "INT_EP_CTRL (rw) register accessor: interrupt endpoint control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`int_ep_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ep_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`int_ep_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ep_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@int_ep_ctrl`]
 module"]
@@ -304,7 +304,7 @@ pub type INT_EP_CTRL = crate::Reg<int_ep_ctrl::INT_EP_CTRL_SPEC>;
 pub mod int_ep_ctrl;
 #[doc = "BUFF_STATUS (rw) register accessor: Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`buff_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`buff_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@buff_status`]
 module"]
@@ -313,7 +313,7 @@ pub type BUFF_STATUS = crate::Reg<buff_status::BUFF_STATUS_SPEC>;
 pub mod buff_status;
 #[doc = "BUFF_CPU_SHOULD_HANDLE (r) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`buff_cpu_should_handle::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@buff_cpu_should_handle`]
 module"]
@@ -322,7 +322,7 @@ pub type BUFF_CPU_SHOULD_HANDLE = crate::Reg<buff_cpu_should_handle::BUFF_CPU_SH
 pub mod buff_cpu_should_handle;
 #[doc = "EP_ABORT (rw) register accessor: Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_abort::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_abort`]
 module"]
@@ -331,7 +331,7 @@ pub type EP_ABORT = crate::Reg<ep_abort::EP_ABORT_SPEC>;
 pub mod ep_abort;
 #[doc = "EP_ABORT_DONE (rw) register accessor: Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort_done::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_abort_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_abort_done`]
 module"]
@@ -340,7 +340,7 @@ pub type EP_ABORT_DONE = crate::Reg<ep_abort_done::EP_ABORT_DONE_SPEC>;
 pub mod ep_abort_done;
 #[doc = "EP_STALL_ARM (rw) register accessor: Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_stall_arm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_stall_arm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_stall_arm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_stall_arm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_stall_arm`]
 module"]
@@ -349,7 +349,7 @@ pub type EP_STALL_ARM = crate::Reg<ep_stall_arm::EP_STALL_ARM_SPEC>;
 pub mod ep_stall_arm;
 #[doc = "NAK_POLL (rw) register accessor: Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nak_poll::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nak_poll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`nak_poll::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nak_poll::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@nak_poll`]
 module"]
@@ -358,7 +358,7 @@ pub type NAK_POLL = crate::Reg<nak_poll::NAK_POLL_SPEC>;
 pub mod nak_poll;
 #[doc = "EP_STATUS_STALL_NAK (rw) register accessor: Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_status_stall_nak::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ep_status_stall_nak::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ep_status_stall_nak`]
 module"]
@@ -367,7 +367,7 @@ pub type EP_STATUS_STALL_NAK = crate::Reg<ep_status_stall_nak::EP_STATUS_STALL_N
 pub mod ep_status_stall_nak;
 #[doc = "USB_MUXING (rw) register accessor: Where to connect the USB controller. Should be to_phy by default.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usb_muxing::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_muxing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`usb_muxing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_muxing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@usb_muxing`]
 module"]
@@ -376,7 +376,7 @@ pub type USB_MUXING = crate::Reg<usb_muxing::USB_MUXING_SPEC>;
 pub mod usb_muxing;
 #[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`usb_pwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@usb_pwr`]
 module"]
@@ -385,7 +385,7 @@ pub type USB_PWR = crate::Reg<usb_pwr::USB_PWR_SPEC>;
 pub mod usb_pwr;
 #[doc = "USBPHY_DIRECT (rw) register accessor: This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`usbphy_direct::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@usbphy_direct`]
 module"]
@@ -394,7 +394,7 @@ pub type USBPHY_DIRECT = crate::Reg<usbphy_direct::USBPHY_DIRECT_SPEC>;
 pub mod usbphy_direct;
 #[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: Override enable for each control in usbphy_direct  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`usbphy_direct_override::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@usbphy_direct_override`]
 module"]
@@ -403,7 +403,7 @@ pub type USBPHY_DIRECT_OVERRIDE = crate::Reg<usbphy_direct_override::USBPHY_DIRE
 pub mod usbphy_direct_override;
 #[doc = "USBPHY_TRIM (rw) register accessor: Used to adjust trim values of USB phy pull down resistors.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`usbphy_trim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@usbphy_trim`]
 module"]
@@ -412,7 +412,7 @@ pub type USBPHY_TRIM = crate::Reg<usbphy_trim::USBPHY_TRIM_SPEC>;
 pub mod usbphy_trim;
 #[doc = "INTR (r) register accessor: Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intr`]
 module"]
@@ -421,7 +421,7 @@ pub type INTR = crate::Reg<intr::INTR_SPEC>;
 pub mod intr;
 #[doc = "INTE (rw) register accessor: Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@inte`]
 module"]
@@ -430,7 +430,7 @@ pub type INTE = crate::Reg<inte::INTE_SPEC>;
 pub mod inte;
 #[doc = "INTF (rw) register accessor: Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@intf`]
 module"]
@@ -439,7 +439,7 @@ pub type INTF = crate::Reg<intf::INTF_SPEC>;
 pub mod intf;
 #[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
diff --git a/src/usbctrl_regs/addr_endp.rs b/src/usbctrl_regs/addr_endp.rs
index e69f85ebb..657abf7b0 100644
--- a/src/usbctrl_regs/addr_endp.rs
+++ b/src/usbctrl_regs/addr_endp.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Device address and endpoint control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`addr_endp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_endp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`addr_endp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_endp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ADDR_ENDP_SPEC;
 impl crate::RegisterSpec for ADDR_ENDP_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/buff_cpu_should_handle.rs b/src/usbctrl_regs/buff_cpu_should_handle.rs
index b16e18a1e..70ec4346c 100644
--- a/src/usbctrl_regs/buff_cpu_should_handle.rs
+++ b/src/usbctrl_regs/buff_cpu_should_handle.rs
@@ -228,7 +228,7 @@ impl R {
 }
 #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`buff_cpu_should_handle::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFF_CPU_SHOULD_HANDLE_SPEC;
 impl crate::RegisterSpec for BUFF_CPU_SHOULD_HANDLE_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/buff_status.rs b/src/usbctrl_regs/buff_status.rs
index 5a7a8f5b3..a658710f4 100644
--- a/src/usbctrl_regs/buff_status.rs
+++ b/src/usbctrl_regs/buff_status.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`buff_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`buff_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFF_STATUS_SPEC;
 impl crate::RegisterSpec for BUFF_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/ep_abort.rs b/src/usbctrl_regs/ep_abort.rs
index 597ae38ad..ad40d1dc2 100644
--- a/src/usbctrl_regs/ep_abort.rs
+++ b/src/usbctrl_regs/ep_abort.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_abort::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_ABORT_SPEC;
 impl crate::RegisterSpec for EP_ABORT_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/ep_abort_done.rs b/src/usbctrl_regs/ep_abort_done.rs
index 730066382..cbb4c8e1a 100644
--- a/src/usbctrl_regs/ep_abort_done.rs
+++ b/src/usbctrl_regs/ep_abort_done.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_abort_done::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_abort_done::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_abort_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_ABORT_DONE_SPEC;
 impl crate::RegisterSpec for EP_ABORT_DONE_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/ep_stall_arm.rs b/src/usbctrl_regs/ep_stall_arm.rs
index 07f33ae92..4d1d45a5c 100644
--- a/src/usbctrl_regs/ep_stall_arm.rs
+++ b/src/usbctrl_regs/ep_stall_arm.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_stall_arm::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_stall_arm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_stall_arm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_stall_arm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_STALL_ARM_SPEC;
 impl crate::RegisterSpec for EP_STALL_ARM_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/ep_status_stall_nak.rs b/src/usbctrl_regs/ep_status_stall_nak.rs
index 6458a1cf6..cc46a4ec7 100644
--- a/src/usbctrl_regs/ep_status_stall_nak.rs
+++ b/src/usbctrl_regs/ep_status_stall_nak.rs
@@ -488,7 +488,7 @@ impl W {
 }
 #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ep_status_stall_nak::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ep_status_stall_nak::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EP_STATUS_STALL_NAK_SPEC;
 impl crate::RegisterSpec for EP_STATUS_STALL_NAK_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/host_addr_endp.rs b/src/usbctrl_regs/host_addr_endp.rs
index 98e813c05..7d2054855 100644
--- a/src/usbctrl_regs/host_addr_endp.rs
+++ b/src/usbctrl_regs/host_addr_endp.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Interrupt endpoints. Only valid in HOST mode.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`host_addr_endp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_addr_endp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`host_addr_endp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_addr_endp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_ADDR_ENDP_SPEC;
 impl crate::RegisterSpec for HOST_ADDR_ENDP_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/int_ep_ctrl.rs b/src/usbctrl_regs/int_ep_ctrl.rs
index 9a2797a76..5dcdd089c 100644
--- a/src/usbctrl_regs/int_ep_ctrl.rs
+++ b/src/usbctrl_regs/int_ep_ctrl.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "interrupt endpoint control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`int_ep_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ep_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`int_ep_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ep_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_EP_CTRL_SPEC;
 impl crate::RegisterSpec for INT_EP_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/inte.rs b/src/usbctrl_regs/inte.rs
index 2bd0946d8..5d27187fa 100644
--- a/src/usbctrl_regs/inte.rs
+++ b/src/usbctrl_regs/inte.rs
@@ -308,7 +308,7 @@ impl W {
 }
 #[doc = "Interrupt Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTE_SPEC;
 impl crate::RegisterSpec for INTE_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/intf.rs b/src/usbctrl_regs/intf.rs
index 3a5fb3f64..309b7c03e 100644
--- a/src/usbctrl_regs/intf.rs
+++ b/src/usbctrl_regs/intf.rs
@@ -308,7 +308,7 @@ impl W {
 }
 #[doc = "Interrupt Force  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTF_SPEC;
 impl crate::RegisterSpec for INTF_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/intr.rs b/src/usbctrl_regs/intr.rs
index 3738efb2f..b90e785ad 100644
--- a/src/usbctrl_regs/intr.rs
+++ b/src/usbctrl_regs/intr.rs
@@ -144,7 +144,7 @@ impl R {
 }
 #[doc = "Raw Interrupts  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_SPEC;
 impl crate::RegisterSpec for INTR_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/ints.rs b/src/usbctrl_regs/ints.rs
index 9154e7a74..3d47c9bb6 100644
--- a/src/usbctrl_regs/ints.rs
+++ b/src/usbctrl_regs/ints.rs
@@ -144,7 +144,7 @@ impl R {
 }
 #[doc = "Interrupt status after masking &amp; forcing  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
 impl crate::RegisterSpec for INTS_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/main_ctrl.rs b/src/usbctrl_regs/main_ctrl.rs
index 65d7bd8c9..5aff8831c 100644
--- a/src/usbctrl_regs/main_ctrl.rs
+++ b/src/usbctrl_regs/main_ctrl.rs
@@ -53,7 +53,7 @@ impl W {
 }
 #[doc = "Main control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`main_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`main_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`main_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_CTRL_SPEC;
 impl crate::RegisterSpec for MAIN_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/nak_poll.rs b/src/usbctrl_regs/nak_poll.rs
index d132486dc..ef24d278d 100644
--- a/src/usbctrl_regs/nak_poll.rs
+++ b/src/usbctrl_regs/nak_poll.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`nak_poll::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nak_poll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`nak_poll::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nak_poll::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NAK_POLL_SPEC;
 impl crate::RegisterSpec for NAK_POLL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/sie_ctrl.rs b/src/usbctrl_regs/sie_ctrl.rs
index c49bffb7c..aedf1e4ca 100644
--- a/src/usbctrl_regs/sie_ctrl.rs
+++ b/src/usbctrl_regs/sie_ctrl.rs
@@ -368,7 +368,7 @@ impl W {
 }
 #[doc = "SIE control register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sie_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sie_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SIE_CTRL_SPEC;
 impl crate::RegisterSpec for SIE_CTRL_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs
index 56bea6d3d..6900d753c 100644
--- a/src/usbctrl_regs/sie_status.rs
+++ b/src/usbctrl_regs/sie_status.rs
@@ -28,6 +28,7 @@ impl From<LINE_STATE_A> for u8 {
 impl crate::FieldSpec for LINE_STATE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for LINE_STATE_A {}
 #[doc = "Field `LINE_STATE` reader - USB bus line state"]
 pub type LINE_STATE_R = crate::FieldReader<LINE_STATE_A>;
 impl LINE_STATE_R {
@@ -375,7 +376,7 @@ impl W {
 }
 #[doc = "SIE status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sie_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sie_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sie_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SIE_STATUS_SPEC;
 impl crate::RegisterSpec for SIE_STATUS_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/sof_rd.rs b/src/usbctrl_regs/sof_rd.rs
index 841ab00e9..2965542f9 100644
--- a/src/usbctrl_regs/sof_rd.rs
+++ b/src/usbctrl_regs/sof_rd.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sof_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SOF_RD_SPEC;
 impl crate::RegisterSpec for SOF_RD_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/sof_wr.rs b/src/usbctrl_regs/sof_wr.rs
index e5f59e1fe..8b0f89c42 100644
--- a/src/usbctrl_regs/sof_wr.rs
+++ b/src/usbctrl_regs/sof_wr.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SOF_WR_SPEC;
 impl crate::RegisterSpec for SOF_WR_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/usb_muxing.rs b/src/usbctrl_regs/usb_muxing.rs
index 7b5b1c9ae..d2f5886b7 100644
--- a/src/usbctrl_regs/usb_muxing.rs
+++ b/src/usbctrl_regs/usb_muxing.rs
@@ -68,7 +68,7 @@ impl W {
 }
 #[doc = "Where to connect the USB controller. Should be to_phy by default.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usb_muxing::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_muxing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`usb_muxing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_muxing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USB_MUXING_SPEC;
 impl crate::RegisterSpec for USB_MUXING_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/usb_pwr.rs b/src/usbctrl_regs/usb_pwr.rs
index 18c2502cc..f57d71938 100644
--- a/src/usbctrl_regs/usb_pwr.rs
+++ b/src/usbctrl_regs/usb_pwr.rs
@@ -98,7 +98,7 @@ impl W {
 }
 #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`usb_pwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_pwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USB_PWR_SPEC;
 impl crate::RegisterSpec for USB_PWR_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/usbphy_direct.rs b/src/usbctrl_regs/usbphy_direct.rs
index 92262e905..ff1b22065 100644
--- a/src/usbctrl_regs/usbphy_direct.rs
+++ b/src/usbctrl_regs/usbphy_direct.rs
@@ -291,7 +291,7 @@ impl W {
 }
 #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`usbphy_direct::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USBPHY_DIRECT_SPEC;
 impl crate::RegisterSpec for USBPHY_DIRECT_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/usbphy_direct_override.rs b/src/usbctrl_regs/usbphy_direct_override.rs
index f0e4ede99..b2ed7063f 100644
--- a/src/usbctrl_regs/usbphy_direct_override.rs
+++ b/src/usbctrl_regs/usbphy_direct_override.rs
@@ -234,7 +234,7 @@ impl W {
 }
 #[doc = "Override enable for each control in usbphy_direct  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`usbphy_direct_override::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct_override::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USBPHY_DIRECT_OVERRIDE_SPEC;
 impl crate::RegisterSpec for USBPHY_DIRECT_OVERRIDE_SPEC {
     type Ux = u32;
diff --git a/src/usbctrl_regs/usbphy_trim.rs b/src/usbctrl_regs/usbphy_trim.rs
index 072f3d20d..b2bb6be02 100644
--- a/src/usbctrl_regs/usbphy_trim.rs
+++ b/src/usbctrl_regs/usbphy_trim.rs
@@ -54,7 +54,7 @@ impl W {
 }
 #[doc = "Used to adjust trim values of USB phy pull down resistors.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`usbphy_trim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_trim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct USBPHY_TRIM_SPEC;
 impl crate::RegisterSpec for USBPHY_TRIM_SPEC {
     type Ux = u32;
diff --git a/src/vreg_and_chip_reset.rs b/src/vreg_and_chip_reset.rs
index 89f9ef0fb..1ff88571c 100644
--- a/src/vreg_and_chip_reset.rs
+++ b/src/vreg_and_chip_reset.rs
@@ -24,7 +24,7 @@ impl RegisterBlock {
 }
 #[doc = "VREG (rw) register accessor: Voltage regulator control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`vreg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vreg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`vreg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@vreg`]
 module"]
@@ -33,7 +33,7 @@ pub type VREG = crate::Reg<vreg::VREG_SPEC>;
 pub mod vreg;
 #[doc = "BOD (rw) register accessor: brown-out detection control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bod::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`bod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bod`]
 module"]
@@ -42,7 +42,7 @@ pub type BOD = crate::Reg<bod::BOD_SPEC>;
 pub mod bod;
 #[doc = "CHIP_RESET (rw) register accessor: Chip reset control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chip_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@chip_reset`]
 module"]
diff --git a/src/vreg_and_chip_reset/bod.rs b/src/vreg_and_chip_reset/bod.rs
index ca8451f8e..b3c203ce3 100644
--- a/src/vreg_and_chip_reset/bod.rs
+++ b/src/vreg_and_chip_reset/bod.rs
@@ -106,7 +106,7 @@ impl W {
 }
 #[doc = "brown-out detection control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`bod::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`bod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOD_SPEC;
 impl crate::RegisterSpec for BOD_SPEC {
     type Ux = u32;
diff --git a/src/vreg_and_chip_reset/chip_reset.rs b/src/vreg_and_chip_reset/chip_reset.rs
index f8d0ef6f2..1f27bc4e2 100644
--- a/src/vreg_and_chip_reset/chip_reset.rs
+++ b/src/vreg_and_chip_reset/chip_reset.rs
@@ -52,7 +52,7 @@ impl W {
 }
 #[doc = "Chip reset control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`chip_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHIP_RESET_SPEC;
 impl crate::RegisterSpec for CHIP_RESET_SPEC {
     type Ux = u32;
diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs
index fe1362f68..b057f7178 100644
--- a/src/vreg_and_chip_reset/vreg.rs
+++ b/src/vreg_and_chip_reset/vreg.rs
@@ -52,6 +52,7 @@ impl From<VSEL_A> for u8 {
 impl crate::FieldSpec for VSEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for VSEL_A {}
 #[doc = "Field `VSEL` reader - Output voltage select for on-chip voltage regulator."]
 pub type VSEL_R = crate::FieldReader<VSEL_A>;
 impl VSEL_R {
@@ -244,7 +245,7 @@ impl W {
 }
 #[doc = "Voltage regulator control and status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`vreg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`vreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VREG_SPEC;
 impl crate::RegisterSpec for VREG_SPEC {
     type Ux = u32;
diff --git a/src/watchdog.rs b/src/watchdog.rs
index 1be794984..3d649d8f8 100644
--- a/src/watchdog.rs
+++ b/src/watchdog.rs
@@ -82,7 +82,7 @@ impl RegisterBlock {
  The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.  
  The watchdog can be triggered in software.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -93,7 +93,7 @@ pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 pub mod ctrl;
 #[doc = "LOAD (w) register accessor: Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@load`]
 module"]
@@ -102,7 +102,7 @@ pub type LOAD = crate::Reg<load::LOAD_SPEC>;
 pub mod load;
 #[doc = "REASON (r) register accessor: Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`reason::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@reason`]
 module"]
@@ -111,7 +111,7 @@ pub type REASON = crate::Reg<reason::REASON_SPEC>;
 pub mod reason;
 #[doc = "SCRATCH0 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch0`]
 module"]
@@ -120,7 +120,7 @@ pub type SCRATCH0 = crate::Reg<scratch0::SCRATCH0_SPEC>;
 pub mod scratch0;
 #[doc = "SCRATCH1 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch1`]
 module"]
@@ -129,7 +129,7 @@ pub type SCRATCH1 = crate::Reg<scratch1::SCRATCH1_SPEC>;
 pub mod scratch1;
 #[doc = "SCRATCH2 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch2`]
 module"]
@@ -138,7 +138,7 @@ pub type SCRATCH2 = crate::Reg<scratch2::SCRATCH2_SPEC>;
 pub mod scratch2;
 #[doc = "SCRATCH3 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch3`]
 module"]
@@ -147,7 +147,7 @@ pub type SCRATCH3 = crate::Reg<scratch3::SCRATCH3_SPEC>;
 pub mod scratch3;
 #[doc = "SCRATCH4 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch4`]
 module"]
@@ -156,7 +156,7 @@ pub type SCRATCH4 = crate::Reg<scratch4::SCRATCH4_SPEC>;
 pub mod scratch4;
 #[doc = "SCRATCH5 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch5`]
 module"]
@@ -165,7 +165,7 @@ pub type SCRATCH5 = crate::Reg<scratch5::SCRATCH5_SPEC>;
 pub mod scratch5;
 #[doc = "SCRATCH6 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch6`]
 module"]
@@ -174,7 +174,7 @@ pub type SCRATCH6 = crate::Reg<scratch6::SCRATCH6_SPEC>;
 pub mod scratch6;
 #[doc = "SCRATCH7 (rw) register accessor: Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`scratch7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@scratch7`]
 module"]
@@ -183,7 +183,7 @@ pub type SCRATCH7 = crate::Reg<scratch7::SCRATCH7_SPEC>;
 pub mod scratch7;
 #[doc = "TICK (rw) register accessor: Controls the tick generator  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`tick::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tick::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`tick::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tick::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@tick`]
 module"]
diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs
index 001919eca..7545ff0e0 100644
--- a/src/watchdog/ctrl.rs
+++ b/src/watchdog/ctrl.rs
@@ -92,7 +92,7 @@ impl W {
  The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.  
  The watchdog can be triggered in software.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/load.rs b/src/watchdog/load.rs
index 2825a6257..681d43fb4 100644
--- a/src/watchdog/load.rs
+++ b/src/watchdog/load.rs
@@ -12,7 +12,7 @@ impl W {
 }
 #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).  
 
-You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOAD_SPEC;
 impl crate::RegisterSpec for LOAD_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/reason.rs b/src/watchdog/reason.rs
index 7820acdd6..4b14bb1f0 100644
--- a/src/watchdog/reason.rs
+++ b/src/watchdog/reason.rs
@@ -18,7 +18,7 @@ impl R {
 }
 #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`reason::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REASON_SPEC;
 impl crate::RegisterSpec for REASON_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch0.rs b/src/watchdog/scratch0.rs
index a2eae729a..332e9e25e 100644
--- a/src/watchdog/scratch0.rs
+++ b/src/watchdog/scratch0.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH0_SPEC;
 impl crate::RegisterSpec for SCRATCH0_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch1.rs b/src/watchdog/scratch1.rs
index 0bb7e84bc..de7eb191d 100644
--- a/src/watchdog/scratch1.rs
+++ b/src/watchdog/scratch1.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH1_SPEC;
 impl crate::RegisterSpec for SCRATCH1_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch2.rs b/src/watchdog/scratch2.rs
index 32f137a3d..90746b509 100644
--- a/src/watchdog/scratch2.rs
+++ b/src/watchdog/scratch2.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH2_SPEC;
 impl crate::RegisterSpec for SCRATCH2_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch3.rs b/src/watchdog/scratch3.rs
index ac456ffae..a52020428 100644
--- a/src/watchdog/scratch3.rs
+++ b/src/watchdog/scratch3.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH3_SPEC;
 impl crate::RegisterSpec for SCRATCH3_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch4.rs b/src/watchdog/scratch4.rs
index 70cc061ee..1a3552b13 100644
--- a/src/watchdog/scratch4.rs
+++ b/src/watchdog/scratch4.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH4_SPEC;
 impl crate::RegisterSpec for SCRATCH4_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch5.rs b/src/watchdog/scratch5.rs
index f4326a151..e08712d65 100644
--- a/src/watchdog/scratch5.rs
+++ b/src/watchdog/scratch5.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH5_SPEC;
 impl crate::RegisterSpec for SCRATCH5_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch6.rs b/src/watchdog/scratch6.rs
index f6b084e35..5f0434bfb 100644
--- a/src/watchdog/scratch6.rs
+++ b/src/watchdog/scratch6.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH6_SPEC;
 impl crate::RegisterSpec for SCRATCH6_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/scratch7.rs b/src/watchdog/scratch7.rs
index 7366acd53..d5080e8e0 100644
--- a/src/watchdog/scratch7.rs
+++ b/src/watchdog/scratch7.rs
@@ -7,15 +7,10 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<SCRATCH7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Scratch register. Information persists through soft reset of the chip.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SCRATCH7_SPEC;
 impl crate::RegisterSpec for SCRATCH7_SPEC {
     type Ux = u32;
diff --git a/src/watchdog/tick.rs b/src/watchdog/tick.rs
index 8a5a257d2..b069c7aad 100644
--- a/src/watchdog/tick.rs
+++ b/src/watchdog/tick.rs
@@ -52,7 +52,7 @@ impl W {
 }
 #[doc = "Controls the tick generator  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`tick::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tick::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`tick::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tick::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TICK_SPEC;
 impl crate::RegisterSpec for TICK_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl.rs b/src/xip_ctrl.rs
index 7e89236fa..ef30b5de3 100644
--- a/src/xip_ctrl.rs
+++ b/src/xip_ctrl.rs
@@ -63,7 +63,7 @@ impl RegisterBlock {
 }
 #[doc = "CTRL (rw) register accessor: Cache control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -72,7 +72,7 @@ pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 pub mod ctrl;
 #[doc = "FLUSH (rw) register accessor: Cache Flush control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`flush::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flush::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@flush`]
 module"]
@@ -81,7 +81,7 @@ pub type FLUSH = crate::Reg<flush::FLUSH_SPEC>;
 pub mod flush;
 #[doc = "STAT (r) register accessor: Cache Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@stat`]
 module"]
@@ -93,7 +93,7 @@ pub mod stat;
  i.e. when an XIP access is serviced directly from cached data.  
  Write any value to clear.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctr_hit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctr_hit`]
 module"]
@@ -108,7 +108,7 @@ pub mod ctr_hit;
  whether the cache is hit or not. This includes noncacheable accesses.  
  Write any value to clear.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctr_acc`]
 module"]
@@ -120,7 +120,7 @@ pub type CTR_ACC = crate::Reg<ctr_acc::CTR_ACC_SPEC>;
 pub mod ctr_acc;
 #[doc = "STREAM_ADDR (rw) register accessor: FIFO stream address  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`stream_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@stream_addr`]
 module"]
@@ -129,7 +129,7 @@ pub type STREAM_ADDR = crate::Reg<stream_addr::STREAM_ADDR_SPEC>;
 pub mod stream_addr;
 #[doc = "STREAM_CTR (rw) register accessor: FIFO stream control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`stream_ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@stream_ctr`]
 module"]
@@ -141,7 +141,7 @@ pub mod stream_ctr;
  This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
  the DMA to bus stalls caused by other XIP traffic.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`stream_fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@stream_fifo`]
 module"]
diff --git a/src/xip_ctrl/ctr_acc.rs b/src/xip_ctrl/ctr_acc.rs
index f22926893..952d34324 100644
--- a/src/xip_ctrl/ctr_acc.rs
+++ b/src/xip_ctrl/ctr_acc.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CTR_ACC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Cache Access counter  
  A 32 bit saturating counter that increments upon each XIP access,  
  whether the cache is hit or not. This includes noncacheable accesses.  
  Write any value to clear.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTR_ACC_SPEC;
 impl crate::RegisterSpec for CTR_ACC_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/ctr_hit.rs b/src/xip_ctrl/ctr_hit.rs
index 1ec689767..61a1f916c 100644
--- a/src/xip_ctrl/ctr_hit.rs
+++ b/src/xip_ctrl/ctr_hit.rs
@@ -7,18 +7,13 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<CTR_HIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Cache Hit counter  
  A 32 bit saturating counter that increments upon each cache hit,  
  i.e. when an XIP access is serviced directly from cached data.  
  Write any value to clear.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctr_hit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTR_HIT_SPEC;
 impl crate::RegisterSpec for CTR_HIT_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs
index 30068d207..9fef1cd2b 100644
--- a/src/xip_ctrl/ctrl.rs
+++ b/src/xip_ctrl/ctrl.rs
@@ -109,7 +109,7 @@ impl W {
 }
 #[doc = "Cache control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/flush.rs b/src/xip_ctrl/flush.rs
index 8598d60d1..08288bbec 100644
--- a/src/xip_ctrl/flush.rs
+++ b/src/xip_ctrl/flush.rs
@@ -39,7 +39,7 @@ impl W {
 }
 #[doc = "Cache Flush control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`flush::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flush::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`flush::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flush::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FLUSH_SPEC;
 impl crate::RegisterSpec for FLUSH_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/stat.rs b/src/xip_ctrl/stat.rs
index b5710094b..069007650 100644
--- a/src/xip_ctrl/stat.rs
+++ b/src/xip_ctrl/stat.rs
@@ -33,7 +33,7 @@ impl R {
 }
 #[doc = "Cache Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STAT_SPEC;
 impl crate::RegisterSpec for STAT_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs
index 384aaf518..9958bb7b8 100644
--- a/src/xip_ctrl/stream_addr.rs
+++ b/src/xip_ctrl/stream_addr.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "FIFO stream address  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`stream_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STREAM_ADDR_SPEC;
 impl crate::RegisterSpec for STREAM_ADDR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs
index 430b2d567..2d5a661f2 100644
--- a/src/xip_ctrl/stream_ctr.rs
+++ b/src/xip_ctrl/stream_ctr.rs
@@ -51,7 +51,7 @@ impl W {
 }
 #[doc = "FIFO stream control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`stream_ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STREAM_CTR_SPEC;
 impl crate::RegisterSpec for STREAM_CTR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ctrl/stream_fifo.rs b/src/xip_ctrl/stream_fifo.rs
index 1d7533062..13c382a4a 100644
--- a/src/xip_ctrl/stream_fifo.rs
+++ b/src/xip_ctrl/stream_fifo.rs
@@ -5,17 +5,12 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<STREAM_FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO stream data  
  Streamed data is buffered here, for retrieval by the system DMA.  
  This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing  
  the DMA to bus stalls caused by other XIP traffic.  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`stream_fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STREAM_FIFO_SPEC;
 impl crate::RegisterSpec for STREAM_FIFO_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi.rs b/src/xip_ssi.rs
index 71ff0a4de..dc8e7b96c 100644
--- a/src/xip_ssi.rs
+++ b/src/xip_ssi.rs
@@ -175,7 +175,7 @@ impl RegisterBlock {
 }
 #[doc = "CTRLR0 (rw) register accessor: Control register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrlr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrlr0`]
 module"]
@@ -184,7 +184,7 @@ pub type CTRLR0 = crate::Reg<ctrlr0::CTRLR0_SPEC>;
 pub mod ctrlr0;
 #[doc = "CTRLR1 (rw) register accessor: Master Control register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrlr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrlr1`]
 module"]
@@ -193,7 +193,7 @@ pub type CTRLR1 = crate::Reg<ctrlr1::CTRLR1_SPEC>;
 pub mod ctrlr1;
 #[doc = "SSIENR (rw) register accessor: SSI Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssienr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssienr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssienr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssienr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssienr`]
 module"]
@@ -202,7 +202,7 @@ pub type SSIENR = crate::Reg<ssienr::SSIENR_SPEC>;
 pub mod ssienr;
 #[doc = "MWCR (rw) register accessor: Microwire Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mwcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`mwcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@mwcr`]
 module"]
@@ -211,7 +211,7 @@ pub type MWCR = crate::Reg<mwcr::MWCR_SPEC>;
 pub mod mwcr;
 #[doc = "SER (rw) register accessor: Slave enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ser::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ser::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ser`]
 module"]
@@ -220,7 +220,7 @@ pub type SER = crate::Reg<ser::SER_SPEC>;
 pub mod ser;
 #[doc = "BAUDR (rw) register accessor: Baud rate  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`baudr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`baudr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baudr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@baudr`]
 module"]
@@ -229,7 +229,7 @@ pub type BAUDR = crate::Reg<baudr::BAUDR_SPEC>;
 pub mod baudr;
 #[doc = "TXFTLR (rw) register accessor: TX FIFO threshold level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txftlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`txftlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txftlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@txftlr`]
 module"]
@@ -238,7 +238,7 @@ pub type TXFTLR = crate::Reg<txftlr::TXFTLR_SPEC>;
 pub mod txftlr;
 #[doc = "RXFTLR (rw) register accessor: RX FIFO threshold level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxftlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxftlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rxftlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxftlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rxftlr`]
 module"]
@@ -247,7 +247,7 @@ pub type RXFTLR = crate::Reg<rxftlr::RXFTLR_SPEC>;
 pub mod rxftlr;
 #[doc = "TXFLR (r) register accessor: TX FIFO level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@txflr`]
 module"]
@@ -256,7 +256,7 @@ pub type TXFLR = crate::Reg<txflr::TXFLR_SPEC>;
 pub mod txflr;
 #[doc = "RXFLR (r) register accessor: RX FIFO level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rxflr`]
 module"]
@@ -265,7 +265,7 @@ pub type RXFLR = crate::Reg<rxflr::RXFLR_SPEC>;
 pub mod rxflr;
 #[doc = "SR (r) register accessor: Status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@sr`]
 module"]
@@ -274,7 +274,7 @@ pub type SR = crate::Reg<sr::SR_SPEC>;
 pub mod sr;
 #[doc = "IMR (rw) register accessor: Interrupt mask  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@imr`]
 module"]
@@ -283,7 +283,7 @@ pub type IMR = crate::Reg<imr::IMR_SPEC>;
 pub mod imr;
 #[doc = "ISR (r) register accessor: Interrupt status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@isr`]
 module"]
@@ -292,7 +292,7 @@ pub type ISR = crate::Reg<isr::ISR_SPEC>;
 pub mod isr;
 #[doc = "RISR (r) register accessor: Raw interrupt status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`risr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@risr`]
 module"]
@@ -301,7 +301,7 @@ pub type RISR = crate::Reg<risr::RISR_SPEC>;
 pub mod risr;
 #[doc = "TXOICR (r) register accessor: TX FIFO overflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`txoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@txoicr`]
 module"]
@@ -310,7 +310,7 @@ pub type TXOICR = crate::Reg<txoicr::TXOICR_SPEC>;
 pub mod txoicr;
 #[doc = "RXOICR (r) register accessor: RX FIFO overflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rxoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rxoicr`]
 module"]
@@ -319,7 +319,7 @@ pub type RXOICR = crate::Reg<rxoicr::RXOICR_SPEC>;
 pub mod rxoicr;
 #[doc = "RXUICR (r) register accessor: RX FIFO underflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rxuicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rxuicr`]
 module"]
@@ -328,7 +328,7 @@ pub type RXUICR = crate::Reg<rxuicr::RXUICR_SPEC>;
 pub mod rxuicr;
 #[doc = "MSTICR (r) register accessor: Multi-master interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`msticr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@msticr`]
 module"]
@@ -337,7 +337,7 @@ pub type MSTICR = crate::Reg<msticr::MSTICR_SPEC>;
 pub mod msticr;
 #[doc = "ICR (r) register accessor: Interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`icr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@icr`]
 module"]
@@ -346,7 +346,7 @@ pub type ICR = crate::Reg<icr::ICR_SPEC>;
 pub mod icr;
 #[doc = "DMACR (rw) register accessor: DMA control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dmacr`]
 module"]
@@ -355,7 +355,7 @@ pub type DMACR = crate::Reg<dmacr::DMACR_SPEC>;
 pub mod dmacr;
 #[doc = "DMATDLR (rw) register accessor: DMA TX data level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmatdlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatdlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dmatdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmatdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dmatdlr`]
 module"]
@@ -364,7 +364,7 @@ pub type DMATDLR = crate::Reg<dmatdlr::DMATDLR_SPEC>;
 pub mod dmatdlr;
 #[doc = "DMARDLR (rw) register accessor: DMA RX data level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmardlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmardlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dmardlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmardlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dmardlr`]
 module"]
@@ -373,7 +373,7 @@ pub type DMARDLR = crate::Reg<dmardlr::DMARDLR_SPEC>;
 pub mod dmardlr;
 #[doc = "IDR (r) register accessor: Identification register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@idr`]
 module"]
@@ -382,7 +382,7 @@ pub type IDR = crate::Reg<idr::IDR_SPEC>;
 pub mod idr;
 #[doc = "SSI_VERSION_ID (r) register accessor: Version ID  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ssi_version_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ssi_version_id`]
 module"]
@@ -391,7 +391,7 @@ pub type SSI_VERSION_ID = crate::Reg<ssi_version_id::SSI_VERSION_ID_SPEC>;
 pub mod ssi_version_id;
 #[doc = "DR0 (rw) register accessor: Data Register 0 (of 36)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dr0`]
 module"]
@@ -400,7 +400,7 @@ pub type DR0 = crate::Reg<dr0::DR0_SPEC>;
 pub mod dr0;
 #[doc = "RX_SAMPLE_DLY (rw) register accessor: RX sample delay  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rx_sample_dly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_sample_dly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`rx_sample_dly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sample_dly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@rx_sample_dly`]
 module"]
@@ -409,7 +409,7 @@ pub type RX_SAMPLE_DLY = crate::Reg<rx_sample_dly::RX_SAMPLE_DLY_SPEC>;
 pub mod rx_sample_dly;
 #[doc = "SPI_CTRLR0 (rw) register accessor: SPI control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`spi_ctrlr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrlr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@spi_ctrlr0`]
 module"]
@@ -418,7 +418,7 @@ pub type SPI_CTRLR0 = crate::Reg<spi_ctrlr0::SPI_CTRLR0_SPEC>;
 pub mod spi_ctrlr0;
 #[doc = "TXD_DRIVE_EDGE (rw) register accessor: TX drive edge  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txd_drive_edge::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txd_drive_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`txd_drive_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txd_drive_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@txd_drive_edge`]
 module"]
diff --git a/src/xip_ssi/baudr.rs b/src/xip_ssi/baudr.rs
index 1b6fce8e8..8da5c41b0 100644
--- a/src/xip_ssi/baudr.rs
+++ b/src/xip_ssi/baudr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Baud rate  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`baudr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`baudr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baudr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BAUDR_SPEC;
 impl crate::RegisterSpec for BAUDR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/ctrlr0.rs b/src/xip_ssi/ctrlr0.rs
index 7c6221a3f..67ef0e77f 100644
--- a/src/xip_ssi/ctrlr0.rs
+++ b/src/xip_ssi/ctrlr0.rs
@@ -42,6 +42,7 @@ impl From<TMOD_A> for u8 {
 impl crate::FieldSpec for TMOD_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TMOD_A {}
 #[doc = "Field `TMOD` reader - Transfer mode"]
 pub type TMOD_R = crate::FieldReader<TMOD_A>;
 impl TMOD_R {
@@ -78,7 +79,7 @@ impl TMOD_R {
     }
 }
 #[doc = "Field `TMOD` writer - Transfer mode"]
-pub type TMOD_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, TMOD_A>;
+pub type TMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TMOD_A, crate::Safe>;
 impl<'a, REG> TMOD_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -147,6 +148,7 @@ impl From<SPI_FRF_A> for u8 {
 impl crate::FieldSpec for SPI_FRF_A {
     type Ux = u8;
 }
+impl crate::IsEnum for SPI_FRF_A {}
 #[doc = "Field `SPI_FRF` reader - SPI frame format"]
 pub type SPI_FRF_R = crate::FieldReader<SPI_FRF_A>;
 impl SPI_FRF_R {
@@ -334,7 +336,7 @@ impl W {
 }
 #[doc = "Control register 0  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrlr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRLR0_SPEC;
 impl crate::RegisterSpec for CTRLR0_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/ctrlr1.rs b/src/xip_ssi/ctrlr1.rs
index 774910136..a5c5d8fb1 100644
--- a/src/xip_ssi/ctrlr1.rs
+++ b/src/xip_ssi/ctrlr1.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Master Control register 1  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrlr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRLR1_SPEC;
 impl crate::RegisterSpec for CTRLR1_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/dmacr.rs b/src/xip_ssi/dmacr.rs
index 49ba1b124..6642c973b 100644
--- a/src/xip_ssi/dmacr.rs
+++ b/src/xip_ssi/dmacr.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "DMA control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMACR_SPEC;
 impl crate::RegisterSpec for DMACR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/dmardlr.rs b/src/xip_ssi/dmardlr.rs
index 8e4be1c5f..d48177d51 100644
--- a/src/xip_ssi/dmardlr.rs
+++ b/src/xip_ssi/dmardlr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "DMA RX data level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmardlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmardlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dmardlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmardlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMARDLR_SPEC;
 impl crate::RegisterSpec for DMARDLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/dmatdlr.rs b/src/xip_ssi/dmatdlr.rs
index f9cd31035..43dd1eb51 100644
--- a/src/xip_ssi/dmatdlr.rs
+++ b/src/xip_ssi/dmatdlr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "DMA TX data level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dmatdlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatdlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dmatdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmatdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMATDLR_SPEC;
 impl crate::RegisterSpec for DMATDLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/dr0.rs b/src/xip_ssi/dr0.rs
index db1f94def..ad1830620 100644
--- a/src/xip_ssi/dr0.rs
+++ b/src/xip_ssi/dr0.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "Data Register 0 (of 36)  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DR0_SPEC;
 impl crate::RegisterSpec for DR0_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/icr.rs b/src/xip_ssi/icr.rs
index b800917b5..b7df737bb 100644
--- a/src/xip_ssi/icr.rs
+++ b/src/xip_ssi/icr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`icr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ICR_SPEC;
 impl crate::RegisterSpec for ICR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/idr.rs b/src/xip_ssi/idr.rs
index e7d0c696f..bcf865a7d 100644
--- a/src/xip_ssi/idr.rs
+++ b/src/xip_ssi/idr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Identification register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`idr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IDR_SPEC;
 impl crate::RegisterSpec for IDR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/imr.rs b/src/xip_ssi/imr.rs
index ecc016a9a..df7afba74 100644
--- a/src/xip_ssi/imr.rs
+++ b/src/xip_ssi/imr.rs
@@ -98,7 +98,7 @@ impl W {
 }
 #[doc = "Interrupt mask  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IMR_SPEC;
 impl crate::RegisterSpec for IMR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/isr.rs b/src/xip_ssi/isr.rs
index 4583ceb54..96b7f06b0 100644
--- a/src/xip_ssi/isr.rs
+++ b/src/xip_ssi/isr.rs
@@ -46,7 +46,7 @@ impl R {
 }
 #[doc = "Interrupt status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ISR_SPEC;
 impl crate::RegisterSpec for ISR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/msticr.rs b/src/xip_ssi/msticr.rs
index 80f4b4e5e..a0de65852 100644
--- a/src/xip_ssi/msticr.rs
+++ b/src/xip_ssi/msticr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Multi-master interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`msticr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MSTICR_SPEC;
 impl crate::RegisterSpec for MSTICR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/mwcr.rs b/src/xip_ssi/mwcr.rs
index 78e88d6ed..52dd821b5 100644
--- a/src/xip_ssi/mwcr.rs
+++ b/src/xip_ssi/mwcr.rs
@@ -53,7 +53,7 @@ impl W {
 }
 #[doc = "Microwire Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`mwcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`mwcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MWCR_SPEC;
 impl crate::RegisterSpec for MWCR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/risr.rs b/src/xip_ssi/risr.rs
index 7a85ad74d..9991af671 100644
--- a/src/xip_ssi/risr.rs
+++ b/src/xip_ssi/risr.rs
@@ -46,7 +46,7 @@ impl R {
 }
 #[doc = "Raw interrupt status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`risr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RISR_SPEC;
 impl crate::RegisterSpec for RISR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/rx_sample_dly.rs b/src/xip_ssi/rx_sample_dly.rs
index 07e61c663..cb7d0ad5a 100644
--- a/src/xip_ssi/rx_sample_dly.rs
+++ b/src/xip_ssi/rx_sample_dly.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "RX sample delay  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rx_sample_dly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_sample_dly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rx_sample_dly::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sample_dly::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_SAMPLE_DLY_SPEC;
 impl crate::RegisterSpec for RX_SAMPLE_DLY_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/rxflr.rs b/src/xip_ssi/rxflr.rs
index c35634473..5b2f3792e 100644
--- a/src/xip_ssi/rxflr.rs
+++ b/src/xip_ssi/rxflr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "RX FIFO level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFLR_SPEC;
 impl crate::RegisterSpec for RXFLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/rxftlr.rs b/src/xip_ssi/rxftlr.rs
index 63ae9087e..faa73c23e 100644
--- a/src/xip_ssi/rxftlr.rs
+++ b/src/xip_ssi/rxftlr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "RX FIFO threshold level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxftlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxftlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rxftlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxftlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFTLR_SPEC;
 impl crate::RegisterSpec for RXFTLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/rxoicr.rs b/src/xip_ssi/rxoicr.rs
index dd990abb3..6d1b7577c 100644
--- a/src/xip_ssi/rxoicr.rs
+++ b/src/xip_ssi/rxoicr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "RX FIFO overflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rxoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXOICR_SPEC;
 impl crate::RegisterSpec for RXOICR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/rxuicr.rs b/src/xip_ssi/rxuicr.rs
index 6201e3bf5..8b8e79960 100644
--- a/src/xip_ssi/rxuicr.rs
+++ b/src/xip_ssi/rxuicr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "RX FIFO underflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`rxuicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXUICR_SPEC;
 impl crate::RegisterSpec for RXUICR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/ser.rs b/src/xip_ssi/ser.rs
index 39966b034..ecea7687e 100644
--- a/src/xip_ssi/ser.rs
+++ b/src/xip_ssi/ser.rs
@@ -31,7 +31,7 @@ impl W {
 }
 #[doc = "Slave enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ser::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ser::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ser::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SER_SPEC;
 impl crate::RegisterSpec for SER_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/xip_ssi/spi_ctrlr0.rs
index e025f4861..c94db53c9 100644
--- a/src/xip_ssi/spi_ctrlr0.rs
+++ b/src/xip_ssi/spi_ctrlr0.rs
@@ -24,6 +24,7 @@ impl From<TRANS_TYPE_A> for u8 {
 impl crate::FieldSpec for TRANS_TYPE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TRANS_TYPE_A {}
 #[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"]
 pub type TRANS_TYPE_R = crate::FieldReader<TRANS_TYPE_A>;
 impl TRANS_TYPE_R {
@@ -104,6 +105,7 @@ impl From<INST_L_A> for u8 {
 impl crate::FieldSpec for INST_L_A {
     type Ux = u8;
 }
+impl crate::IsEnum for INST_L_A {}
 #[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"]
 pub type INST_L_R = crate::FieldReader<INST_L_A>;
 impl INST_L_R {
@@ -140,7 +142,7 @@ impl INST_L_R {
     }
 }
 #[doc = "Field `INST_L` writer - Instruction length (0/4/8/16b)"]
-pub type INST_L_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INST_L_A>;
+pub type INST_L_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INST_L_A, crate::Safe>;
 impl<'a, REG> INST_L_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -281,7 +283,7 @@ impl W {
 }
 #[doc = "SPI control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrlr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrlr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`spi_ctrlr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrlr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_CTRLR0_SPEC;
 impl crate::RegisterSpec for SPI_CTRLR0_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/sr.rs b/src/xip_ssi/sr.rs
index adf8d46fb..738f3bc1c 100644
--- a/src/xip_ssi/sr.rs
+++ b/src/xip_ssi/sr.rs
@@ -53,7 +53,7 @@ impl R {
 }
 #[doc = "Status register  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/ssi_version_id.rs b/src/xip_ssi/ssi_version_id.rs
index 97b1d5847..a2bf5be2f 100644
--- a/src/xip_ssi/ssi_version_id.rs
+++ b/src/xip_ssi/ssi_version_id.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "Version ID  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssi_version_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSI_VERSION_ID_SPEC;
 impl crate::RegisterSpec for SSI_VERSION_ID_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/ssienr.rs b/src/xip_ssi/ssienr.rs
index 32c7dca35..11da8fc78 100644
--- a/src/xip_ssi/ssienr.rs
+++ b/src/xip_ssi/ssienr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "SSI Enable  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ssienr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssienr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ssienr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssienr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSIENR_SPEC;
 impl crate::RegisterSpec for SSIENR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/txd_drive_edge.rs b/src/xip_ssi/txd_drive_edge.rs
index e111cf304..14cc39486 100644
--- a/src/xip_ssi/txd_drive_edge.rs
+++ b/src/xip_ssi/txd_drive_edge.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "TX drive edge  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txd_drive_edge::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txd_drive_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`txd_drive_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txd_drive_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXD_DRIVE_EDGE_SPEC;
 impl crate::RegisterSpec for TXD_DRIVE_EDGE_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/txflr.rs b/src/xip_ssi/txflr.rs
index e84cb9dc7..08e20d97e 100644
--- a/src/xip_ssi/txflr.rs
+++ b/src/xip_ssi/txflr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "TX FIFO level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFLR_SPEC;
 impl crate::RegisterSpec for TXFLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/txftlr.rs b/src/xip_ssi/txftlr.rs
index add51d481..8040b0876 100644
--- a/src/xip_ssi/txftlr.rs
+++ b/src/xip_ssi/txftlr.rs
@@ -23,7 +23,7 @@ impl W {
 }
 #[doc = "TX FIFO threshold level  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txftlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txftlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`txftlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txftlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFTLR_SPEC;
 impl crate::RegisterSpec for TXFTLR_SPEC {
     type Ux = u32;
diff --git a/src/xip_ssi/txoicr.rs b/src/xip_ssi/txoicr.rs
index f1e4ea1f9..d2aa47d5f 100644
--- a/src/xip_ssi/txoicr.rs
+++ b/src/xip_ssi/txoicr.rs
@@ -11,7 +11,7 @@ impl R {
 }
 #[doc = "TX FIFO overflow interrupt clear  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`txoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXOICR_SPEC;
 impl crate::RegisterSpec for TXOICR_SPEC {
     type Ux = u32;
diff --git a/src/xosc.rs b/src/xosc.rs
index 5602a887a..8c80e2e87 100644
--- a/src/xosc.rs
+++ b/src/xosc.rs
@@ -35,7 +35,7 @@ impl RegisterBlock {
 }
 #[doc = "CTRL (rw) register accessor: Crystal Oscillator Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ctrl`]
 module"]
@@ -44,7 +44,7 @@ pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 pub mod ctrl;
 #[doc = "STATUS (rw) register accessor: Crystal Oscillator Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@status`]
 module"]
@@ -58,7 +58,7 @@ pub mod status;
  WARNING: stop the PLLs before selecting dormant mode  
  WARNING: setup the irq before selecting dormant mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant`]
 module"]
@@ -72,7 +72,7 @@ pub type DORMANT = crate::Reg<dormant::DORMANT_SPEC>;
 pub mod dormant;
 #[doc = "STARTUP (rw) register accessor: Controls the startup delay  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`startup::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+You can [`read`](crate::Reg::read) this register and get [`startup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`startup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@startup`]
 module"]
diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs
index 3251a3d4c..4009d57a0 100644
--- a/src/xosc/ctrl.rs
+++ b/src/xosc/ctrl.rs
@@ -26,6 +26,7 @@ impl From<FREQ_RANGE_A> for u16 {
 impl crate::FieldSpec for FREQ_RANGE_A {
     type Ux = u16;
 }
+impl crate::IsEnum for FREQ_RANGE_A {}
 #[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."]
 pub type FREQ_RANGE_R = crate::FieldReader<FREQ_RANGE_A>;
 impl FREQ_RANGE_R {
@@ -111,6 +112,7 @@ impl From<ENABLE_A> for u16 {
 impl crate::FieldSpec for ENABLE_A {
     type Ux = u16;
 }
+impl crate::IsEnum for ENABLE_A {}
 #[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.  
  If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.  
  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
@@ -188,7 +190,7 @@ impl W {
 }
 #[doc = "Crystal Oscillator Control  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CTRL_SPEC;
 impl crate::RegisterSpec for CTRL_SPEC {
     type Ux = u32;
diff --git a/src/xosc/dormant.rs b/src/xosc/dormant.rs
index 05a6f0650..86bba6a62 100644
--- a/src/xosc/dormant.rs
+++ b/src/xosc/dormant.rs
@@ -7,11 +7,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-impl core::fmt::Debug for crate::generic::Reg<DORMANT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Crystal Oscillator pause control  
  This is used to save power by pausing the XOSC  
@@ -20,7 +15,7 @@ impl W {}
  WARNING: stop the PLLs before selecting dormant mode  
  WARNING: setup the irq before selecting dormant mode  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_SPEC;
 impl crate::RegisterSpec for DORMANT_SPEC {
     type Ux = u32;
diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs
index 7bb4f02a9..2ff02a859 100644
--- a/src/xosc/startup.rs
+++ b/src/xosc/startup.rs
@@ -38,7 +38,7 @@ impl W {
 }
 #[doc = "Controls the startup delay  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`startup::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`startup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`startup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STARTUP_SPEC;
 impl crate::RegisterSpec for STARTUP_SPEC {
     type Ux = u32;
diff --git a/src/xosc/status.rs b/src/xosc/status.rs
index 519761725..c83d00f3a 100644
--- a/src/xosc/status.rs
+++ b/src/xosc/status.rs
@@ -26,6 +26,7 @@ impl From<FREQ_RANGE_A> for u8 {
 impl crate::FieldSpec for FREQ_RANGE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FREQ_RANGE_A {}
 #[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"]
 pub type FREQ_RANGE_R = crate::FieldReader<FREQ_RANGE_A>;
 impl FREQ_RANGE_R {
@@ -101,7 +102,7 @@ impl W {
 }
 #[doc = "Crystal Oscillator Status  
 
-You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+You can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
     type Ux = u32;
diff --git a/svd/rp2040.yaml b/svd/rp2040.yaml
index 982f49c5b..c5a11218c 100644
--- a/svd/rp2040.yaml
+++ b/svd/rp2040.yaml
@@ -5,22 +5,22 @@ DMA:
     _modify:
       "CHAIN_TO":
         description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n
-        Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
+                     Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
   CH0_AL1_CTRL:
     _modify:
       "CHAIN_TO":
         description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n
-        Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
+                     Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
   CH0_AL2_CTRL:
     _modify:
       "CHAIN_TO":
         description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n
-        Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
+                     Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
   CH0_AL3_CTRL:
     _modify:
       "CHAIN_TO":
         description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n
-        Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
+                      Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."
 
   "CH*_CTRL*":
     "TREQ_SEL":
diff --git a/update.sh b/update.sh
index d07489d44..f1fee2505 100755
--- a/update.sh
+++ b/update.sh
@@ -5,11 +5,11 @@ SVDTOOLS="${SVDTOOLS:-svdtools}"
 
 set -ex
 
-cargo install --version 0.32.0 svd2rust
-cargo install --version 0.11.1  form
+cargo install --version 0.33.5 svd2rust
+cargo install --version 0.12.1 form
 rustup component add rustfmt
 if [ "$SVDTOOLS" == "svdtools" ]; then
-    cargo install --version 0.3.12 svdtools
+    cargo install --version 0.3.18 svdtools
 else
     python3 -mvenv --clear .venv
     source .venv/bin/activate