diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs
index ce44b8c5b..d0ad6f030 100644
--- a/src/busctrl/perfsel0.rs
+++ b/src/busctrl/perfsel0.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL0_A> for u8 {
impl crate::FieldSpec for PERFSEL0_A {
type Ux = u8;
}
+impl crate::IsEnum for PERFSEL0_A {}
#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL0_R = crate::FieldReader<PERFSEL0_A>;
impl PERFSEL0_R {
diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs
index 01daabc0f..6ab405886 100644
--- a/src/busctrl/perfsel1.rs
+++ b/src/busctrl/perfsel1.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL1_A> for u8 {
impl crate::FieldSpec for PERFSEL1_A {
type Ux = u8;
}
+impl crate::IsEnum for PERFSEL1_A {}
#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
impl PERFSEL1_R {
diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs
index 1a39e60f0..92cdfd6ed 100644
--- a/src/busctrl/perfsel2.rs
+++ b/src/busctrl/perfsel2.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL2_A> for u8 {
impl crate::FieldSpec for PERFSEL2_A {
type Ux = u8;
}
+impl crate::IsEnum for PERFSEL2_A {}
#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL2_R = crate::FieldReader<PERFSEL2_A>;
impl PERFSEL2_R {
diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs
index 2f34e1e83..99a44aa2e 100644
--- a/src/busctrl/perfsel3.rs
+++ b/src/busctrl/perfsel3.rs
@@ -58,6 +58,7 @@ impl From<PERFSEL3_A> for u8 {
impl crate::FieldSpec for PERFSEL3_A {
type Ux = u8;
}
+impl crate::IsEnum for PERFSEL3_A {}
#[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL3_R = crate::FieldReader<PERFSEL3_A>;
impl PERFSEL3_R {
diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs
index b22f652f0..de65efafd 100644
--- a/src/clocks/clk_adc_ctrl.rs
+++ b/src/clocks/clk_adc_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs
index 4edce962e..99ba69170 100644
--- a/src/clocks/clk_gpout0_ctrl.rs
+++ b/src/clocks/clk_gpout0_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs
index eab13e0a1..6b961b31d 100644
--- a/src/clocks/clk_gpout1_ctrl.rs
+++ b/src/clocks/clk_gpout1_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs
index 25badf597..efed7791d 100644
--- a/src/clocks/clk_gpout2_ctrl.rs
+++ b/src/clocks/clk_gpout2_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs
index b5b5ed98d..f2705b447 100644
--- a/src/clocks/clk_gpout3_ctrl.rs
+++ b/src/clocks/clk_gpout3_ctrl.rs
@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs
index 3e2ef59ee..3a1fe3097 100644
--- a/src/clocks/clk_peri_ctrl.rs
+++ b/src/clocks/clk_peri_ctrl.rs
@@ -32,6 +32,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs
index a81dc5705..4ebedca44 100644
--- a/src/clocks/clk_ref_ctrl.rs
+++ b/src/clocks/clk_ref_ctrl.rs
@@ -24,6 +24,7 @@ impl From<SRC_A> for u8 {
impl crate::FieldSpec for SRC_A {
type Ux = u8;
}
+impl crate::IsEnum for SRC_A {}
#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"]
pub type SRC_R = crate::FieldReader<SRC_A>;
impl SRC_R {
@@ -98,6 +99,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs
index 6adf1f9a7..20e8ba905 100644
--- a/src/clocks/clk_rtc_ctrl.rs
+++ b/src/clocks/clk_rtc_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs
index 2a489cfbc..39d3643e7 100644
--- a/src/clocks/clk_sys_ctrl.rs
+++ b/src/clocks/clk_sys_ctrl.rs
@@ -85,6 +85,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs
index b67c9bbb3..ffc6002e2 100644
--- a/src/clocks/clk_usb_ctrl.rs
+++ b/src/clocks/clk_usb_ctrl.rs
@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
impl crate::FieldSpec for AUXSRC_A {
type Ux = u8;
}
+impl crate::IsEnum for AUXSRC_A {}
#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
impl AUXSRC_R {
diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs
index bfcf72e23..8a16364a4 100644
--- a/src/clocks/fc0_src.rs
+++ b/src/clocks/fc0_src.rs
@@ -46,6 +46,7 @@ impl From<FC0_SRC_A> for u8 {
impl crate::FieldSpec for FC0_SRC_A {
type Ux = u8;
}
+impl crate::IsEnum for FC0_SRC_A {}
#[doc = "Field `FC0_SRC` reader - "]
pub type FC0_SRC_R = crate::FieldReader<FC0_SRC_A>;
impl FC0_SRC_R {
diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs
index 36865c3d9..374051e49 100644
--- a/src/dma/ch/ch_al1_ctrl.rs
+++ b/src/dma/ch/ch_al1_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
impl crate::FieldSpec for DATA_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for DATA_SIZE_A {}
#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
impl crate::FieldSpec for RING_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for RING_SIZE_A {}
#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
impl crate::FieldSpec for TREQ_SEL_A {
type Ux = u8;
}
+impl crate::IsEnum for TREQ_SEL_A {}
#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ"]
diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs
index dcf6e4082..0acf45d7e 100644
--- a/src/dma/ch/ch_al2_ctrl.rs
+++ b/src/dma/ch/ch_al2_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
impl crate::FieldSpec for DATA_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for DATA_SIZE_A {}
#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
impl crate::FieldSpec for RING_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for RING_SIZE_A {}
#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
impl crate::FieldSpec for TREQ_SEL_A {
type Ux = u8;
}
+impl crate::IsEnum for TREQ_SEL_A {}
#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ"]
diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs
index f4ea5fd08..b40fb969e 100644
--- a/src/dma/ch/ch_al3_ctrl.rs
+++ b/src/dma/ch/ch_al3_ctrl.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
impl crate::FieldSpec for DATA_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for DATA_SIZE_A {}
#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
impl crate::FieldSpec for RING_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for RING_SIZE_A {}
#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
impl crate::FieldSpec for TREQ_SEL_A {
type Ux = u8;
}
+impl crate::IsEnum for TREQ_SEL_A {}
#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ"]
diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs
index af5e735ef..058b47977 100644
--- a/src/dma/ch/ch_ctrl_trig.rs
+++ b/src/dma/ch/ch_ctrl_trig.rs
@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
impl crate::FieldSpec for DATA_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for DATA_SIZE_A {}
#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
impl crate::FieldSpec for RING_SIZE_A {
type Ux = u8;
}
+impl crate::IsEnum for RING_SIZE_A {}
#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
impl crate::FieldSpec for TREQ_SEL_A {
type Ux = u8;
}
+impl crate::IsEnum for TREQ_SEL_A {}
#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ"]
diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs
index 1e4432c05..9f8a68a54 100644
--- a/src/dma/sniff_ctrl.rs
+++ b/src/dma/sniff_ctrl.rs
@@ -38,6 +38,7 @@ impl From<CALC_A> for u8 {
impl crate::FieldSpec for CALC_A {
type Ux = u8;
}
+impl crate::IsEnum for CALC_A {}
#[doc = "Field `CALC` reader - "]
pub type CALC_R = crate::FieldReader<CALC_A>;
impl CALC_R {
diff --git a/src/generic.rs b/src/generic.rs
index db0f701ae..a2ae6aa05 100644
--- a/src/generic.rs
+++ b/src/generic.rs
@@ -50,6 +50,8 @@ pub trait FieldSpec: Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux: Copy + PartialEq + From<Self>;
}
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
@@ -340,15 +342,13 @@ impl<FI> BitReader<FI> {
pub struct Safe;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe;
-#[doc = " Write field Proxy with unsafe `bits`"]
-pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
-#[doc = " Write field Proxy with safe `bits`"]
-pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
-impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+ raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
- REG::Ux: From<FI::Ux>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
@@ -362,6 +362,13 @@ where
pub const fn offset(&self) -> u8 {
self.o
}
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+ REG: Writable + RegisterSpec,
+ FI: FieldSpec,
+ REG::Ux: From<FI::Ux>,
+{
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
@@ -373,41 +380,29 @@ where
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
- #[doc = " Writes `variant` to the field"]
- #[inline(always)]
- pub fn variant(self, variant: FI) -> &'a mut W<REG> {
- unsafe { self.bits(FI::Ux::from(variant)) }
- }
}
-impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
- #[doc = " Field width"]
- pub const WIDTH: u8 = WI;
- #[doc = " Field width"]
- #[inline(always)]
- pub const fn width(&self) -> u8 {
- WI
- }
- #[doc = " Field offset"]
- #[inline(always)]
- pub const fn offset(&self) -> u8 {
- self.o
- }
#[doc = " Writes raw bits to the field"]
#[inline(always)]
- pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
- self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
- self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
- self.w
+ pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+ unsafe { self.bits(value) }
}
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+ REG: Writable + RegisterSpec,
+ FI: IsEnum,
+ REG::Ux: From<FI::Ux>,
+{
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
- self.bits(FI::Ux::from(variant))
+ unsafe { self.bits(FI::Ux::from(variant)) }
}
}
macro_rules! bit_proxy {
diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs
index a210ffffa..5be55a2d4 100644
--- a/src/i2c0/ic_con.rs
+++ b/src/i2c0/ic_con.rs
@@ -95,6 +95,7 @@ impl From<SPEED_A> for u8 {
impl crate::FieldSpec for SPEED_A {
type Ux = u8;
}
+impl crate::IsEnum for SPEED_A {}
#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs
index f0b9aee22..a4a0307a7 100644
--- a/src/io_bank0/gpio/gpio_ctrl.rs
+++ b/src/io_bank0/gpio/gpio_ctrl.rs
@@ -40,6 +40,7 @@ impl From<FUNCSEL_A> for u8 {
impl crate::FieldSpec for FUNCSEL_A {
type Ux = u8;
}
+impl crate::IsEnum for FUNCSEL_A {}
#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
pub type FUNCSEL_R = crate::FieldReader<FUNCSEL_A>;
impl FUNCSEL_R {
@@ -204,6 +205,7 @@ impl From<OUTOVER_A> for u8 {
impl crate::FieldSpec for OUTOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for OUTOVER_A {}
#[doc = "Field `OUTOVER` reader - "]
pub type OUTOVER_R = crate::FieldReader<OUTOVER_A>;
impl OUTOVER_R {
@@ -240,7 +242,7 @@ impl OUTOVER_R {
}
}
#[doc = "Field `OUTOVER` writer - "]
-pub type OUTOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OUTOVER_A>;
+pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>;
impl<'a, REG> OUTOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -291,6 +293,7 @@ impl From<OEOVER_A> for u8 {
impl crate::FieldSpec for OEOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for OEOVER_A {}
#[doc = "Field `OEOVER` reader - "]
pub type OEOVER_R = crate::FieldReader<OEOVER_A>;
impl OEOVER_R {
@@ -327,7 +330,7 @@ impl OEOVER_R {
}
}
#[doc = "Field `OEOVER` writer - "]
-pub type OEOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OEOVER_A>;
+pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>;
impl<'a, REG> OEOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -378,6 +381,7 @@ impl From<INOVER_A> for u8 {
impl crate::FieldSpec for INOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for INOVER_A {}
#[doc = "Field `INOVER` reader - "]
pub type INOVER_R = crate::FieldReader<INOVER_A>;
impl INOVER_R {
@@ -414,7 +418,7 @@ impl INOVER_R {
}
}
#[doc = "Field `INOVER` writer - "]
-pub type INOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INOVER_A>;
+pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>;
impl<'a, REG> INOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -465,6 +469,7 @@ impl From<IRQOVER_A> for u8 {
impl crate::FieldSpec for IRQOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for IRQOVER_A {}
#[doc = "Field `IRQOVER` reader - "]
pub type IRQOVER_R = crate::FieldReader<IRQOVER_A>;
impl IRQOVER_R {
@@ -501,7 +506,7 @@ impl IRQOVER_R {
}
}
#[doc = "Field `IRQOVER` writer - "]
-pub type IRQOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IRQOVER_A>;
+pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>;
impl<'a, REG> IRQOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs
index c91a7f94c..3b7e36ce6 100644
--- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs
+++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs
@@ -25,6 +25,7 @@ impl From<FUNCSEL_A> for u8 {
impl crate::FieldSpec for FUNCSEL_A {
type Ux = u8;
}
+impl crate::IsEnum for FUNCSEL_A {}
#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table
31 == NULL"]
pub type FUNCSEL_R = crate::FieldReader<FUNCSEL_A>;
@@ -103,6 +104,7 @@ impl From<OUTOVER_A> for u8 {
impl crate::FieldSpec for OUTOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for OUTOVER_A {}
#[doc = "Field `OUTOVER` reader - "]
pub type OUTOVER_R = crate::FieldReader<OUTOVER_A>;
impl OUTOVER_R {
@@ -139,7 +141,7 @@ impl OUTOVER_R {
}
}
#[doc = "Field `OUTOVER` writer - "]
-pub type OUTOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OUTOVER_A>;
+pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>;
impl<'a, REG> OUTOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -190,6 +192,7 @@ impl From<OEOVER_A> for u8 {
impl crate::FieldSpec for OEOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for OEOVER_A {}
#[doc = "Field `OEOVER` reader - "]
pub type OEOVER_R = crate::FieldReader<OEOVER_A>;
impl OEOVER_R {
@@ -226,7 +229,7 @@ impl OEOVER_R {
}
}
#[doc = "Field `OEOVER` writer - "]
-pub type OEOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, OEOVER_A>;
+pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>;
impl<'a, REG> OEOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -277,6 +280,7 @@ impl From<INOVER_A> for u8 {
impl crate::FieldSpec for INOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for INOVER_A {}
#[doc = "Field `INOVER` reader - "]
pub type INOVER_R = crate::FieldReader<INOVER_A>;
impl INOVER_R {
@@ -313,7 +317,7 @@ impl INOVER_R {
}
}
#[doc = "Field `INOVER` writer - "]
-pub type INOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INOVER_A>;
+pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>;
impl<'a, REG> INOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -364,6 +368,7 @@ impl From<IRQOVER_A> for u8 {
impl crate::FieldSpec for IRQOVER_A {
type Ux = u8;
}
+impl crate::IsEnum for IRQOVER_A {}
#[doc = "Field `IRQOVER` reader - "]
pub type IRQOVER_R = crate::FieldReader<IRQOVER_A>;
impl IRQOVER_R {
@@ -400,7 +405,7 @@ impl IRQOVER_R {
}
}
#[doc = "Field `IRQOVER` writer - "]
-pub type IRQOVER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IRQOVER_A>;
+pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>;
impl<'a, REG> IRQOVER_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/lib.rs b/src/lib.rs
index 094585a0a..aac510aa9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,11 +1,11 @@
-#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.32.0 ( ))
+#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.33.0 ( ))
You can find an overview of the generated API [here].
API features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
-[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api
+[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs
index 98bfa5b24..997530f36 100644
--- a/src/pads_bank0/gpio.rs
+++ b/src/pads_bank0/gpio.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs
index 7b909ce86..8dce419b1 100644
--- a/src/pads_bank0/swclk.rs
+++ b/src/pads_bank0/swclk.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs
index 4df05995e..e58c5df07 100644
--- a/src/pads_bank0/swd.rs
+++ b/src/pads_bank0/swd.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs
index 96d9229fc..44c8b5fb8 100644
--- a/src/pads_qspi/gpio_qspi_sclk.rs
+++ b/src/pads_qspi/gpio_qspi_sclk.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs
index cd34d33d7..c34836c86 100644
--- a/src/pads_qspi/gpio_qspi_sd0.rs
+++ b/src/pads_qspi/gpio_qspi_sd0.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs
index 073b9f561..7dc43cccf 100644
--- a/src/pads_qspi/gpio_qspi_sd1.rs
+++ b/src/pads_qspi/gpio_qspi_sd1.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs
index 738b7ef2b..798ba6c72 100644
--- a/src/pads_qspi/gpio_qspi_sd2.rs
+++ b/src/pads_qspi/gpio_qspi_sd2.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs
index da18ad2c0..fbfc826b1 100644
--- a/src/pads_qspi/gpio_qspi_sd3.rs
+++ b/src/pads_qspi/gpio_qspi_sd3.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs
index de88f61b0..ecf3ab793 100644
--- a/src/pads_qspi/gpio_qspi_ss.rs
+++ b/src/pads_qspi/gpio_qspi_ss.rs
@@ -42,6 +42,7 @@ impl From<DRIVE_A> for u8 {
impl crate::FieldSpec for DRIVE_A {
type Ux = u8;
}
+impl crate::IsEnum for DRIVE_A {}
#[doc = "Field `DRIVE` reader - Drive strength."]
pub type DRIVE_R = crate::FieldReader<DRIVE_A>;
impl DRIVE_R {
@@ -78,7 +79,7 @@ impl DRIVE_R {
}
}
#[doc = "Field `DRIVE` writer - Drive strength."]
-pub type DRIVE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRIVE_A>;
+pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>;
impl<'a, REG> DRIVE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs
index 991645642..affbcda85 100644
--- a/src/pwm/ch/csr.rs
+++ b/src/pwm/ch/csr.rs
@@ -42,6 +42,7 @@ impl From<DIVMODE_A> for u8 {
impl crate::FieldSpec for DIVMODE_A {
type Ux = u8;
}
+impl crate::IsEnum for DIVMODE_A {}
#[doc = "Field `DIVMODE` reader - "]
pub type DIVMODE_R = crate::FieldReader<DIVMODE_A>;
impl DIVMODE_R {
@@ -78,7 +79,7 @@ impl DIVMODE_R {
}
}
#[doc = "Field `DIVMODE` writer - "]
-pub type DIVMODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DIVMODE_A>;
+pub type DIVMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DIVMODE_A, crate::Safe>;
impl<'a, REG> DIVMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs
index 66bbef5e0..3cc84fdc3 100644
--- a/src/rosc/ctrl.rs
+++ b/src/rosc/ctrl.rs
@@ -33,6 +33,7 @@ impl From<FREQ_RANGE_A> for u16 {
impl crate::FieldSpec for FREQ_RANGE_A {
type Ux = u16;
}
+impl crate::IsEnum for FREQ_RANGE_A {}
#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring
LOW uses stages 0 to 7
MEDIUM uses stages 0 to 5
@@ -132,6 +133,7 @@ impl From<ENABLE_A> for u16 {
impl crate::FieldSpec for ENABLE_A {
type Ux = u16;
}
+impl crate::IsEnum for ENABLE_A {}
#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE
The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up
The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
diff --git a/src/rosc/div.rs b/src/rosc/div.rs
index d79cf2155..0de4297c6 100644
--- a/src/rosc/div.rs
+++ b/src/rosc/div.rs
@@ -24,6 +24,7 @@ impl From<DIV_A> for u16 {
impl crate::FieldSpec for DIV_A {
type Ux = u16;
}
+impl crate::IsEnum for DIV_A {}
#[doc = "Field `DIV` reader - set to 0xaa0 + div where
div = 0 divides by 32
div = 1-31 divides by div
diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs
index d7c9b6476..0a2274252 100644
--- a/src/rosc/freqa.rs
+++ b/src/rosc/freqa.rs
@@ -37,6 +37,7 @@ impl From<PASSWD_A> for u16 {
impl crate::FieldSpec for PASSWD_A {
type Ux = u16;
}
+impl crate::IsEnum for PASSWD_A {}
#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0"]
pub type PASSWD_R = crate::FieldReader<PASSWD_A>;
diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs
index c87b40ad0..0e5410146 100644
--- a/src/rosc/freqb.rs
+++ b/src/rosc/freqb.rs
@@ -37,6 +37,7 @@ impl From<PASSWD_A> for u16 {
impl crate::FieldSpec for PASSWD_A {
type Ux = u16;
}
+impl crate::IsEnum for PASSWD_A {}
#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0"]
pub type PASSWD_R = crate::FieldReader<PASSWD_A>;
diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs
index 62df85ffd..7f612d9a1 100644
--- a/src/spi0/sspcr0.rs
+++ b/src/spi0/sspcr0.rs
@@ -28,6 +28,7 @@ impl From<FRF_A> for u8 {
impl crate::FieldSpec for FRF_A {
type Ux = u8;
}
+impl crate::IsEnum for FRF_A {}
#[doc = "Field `FRF` reader - Frame format."]
pub type FRF_R = crate::FieldReader<FRF_A>;
impl FRF_R {
diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs
index c977f2907..b70bf404c 100644
--- a/src/usbctrl_dpram/ep_buffer_control.rs
+++ b/src/usbctrl_dpram/ep_buffer_control.rs
@@ -63,6 +63,7 @@ impl From<DOUBLE_BUFFER_ISO_OFFSET_A> for u8 {
impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A {
type Ux = u8;
}
+impl crate::IsEnum for DOUBLE_BUFFER_ISO_OFFSET_A {}
#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
For a non Isochronous endpoint the offset is always 64 bytes."]
pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader<DOUBLE_BUFFER_ISO_OFFSET_A>;
@@ -102,7 +103,7 @@ impl DOUBLE_BUFFER_ISO_OFFSET_R {
#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
For a non Isochronous endpoint the offset is always 64 bytes."]
pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> =
- crate::FieldWriterSafe<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A>;
+ crate::FieldWriter<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A, crate::Safe>;
impl<'a, REG> DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/usbctrl_dpram/ep_control.rs b/src/usbctrl_dpram/ep_control.rs
index ffaae0931..8e406060c 100644
--- a/src/usbctrl_dpram/ep_control.rs
+++ b/src/usbctrl_dpram/ep_control.rs
@@ -42,6 +42,7 @@ impl From<ENDPOINT_TYPE_A> for u8 {
impl crate::FieldSpec for ENDPOINT_TYPE_A {
type Ux = u8;
}
+impl crate::IsEnum for ENDPOINT_TYPE_A {}
#[doc = "Field `ENDPOINT_TYPE` reader - "]
pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
impl ENDPOINT_TYPE_R {
@@ -78,7 +79,7 @@ impl ENDPOINT_TYPE_R {
}
}
#[doc = "Field `ENDPOINT_TYPE` writer - "]
-pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
+pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENDPOINT_TYPE_A, crate::Safe>;
impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/usbctrl_dpram/epx_control.rs b/src/usbctrl_dpram/epx_control.rs
index f045155f7..b10a604bb 100644
--- a/src/usbctrl_dpram/epx_control.rs
+++ b/src/usbctrl_dpram/epx_control.rs
@@ -38,6 +38,7 @@ impl From<ENDPOINT_TYPE_A> for u8 {
impl crate::FieldSpec for ENDPOINT_TYPE_A {
type Ux = u8;
}
+impl crate::IsEnum for ENDPOINT_TYPE_A {}
#[doc = "Field `ENDPOINT_TYPE` reader - "]
pub type ENDPOINT_TYPE_R = crate::FieldReader<ENDPOINT_TYPE_A>;
impl ENDPOINT_TYPE_R {
@@ -74,7 +75,7 @@ impl ENDPOINT_TYPE_R {
}
}
#[doc = "Field `ENDPOINT_TYPE` writer - "]
-pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ENDPOINT_TYPE_A>;
+pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENDPOINT_TYPE_A, crate::Safe>;
impl<'a, REG> ENDPOINT_TYPE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs
index 56bea6d3d..822e9746a 100644
--- a/src/usbctrl_regs/sie_status.rs
+++ b/src/usbctrl_regs/sie_status.rs
@@ -28,6 +28,7 @@ impl From<LINE_STATE_A> for u8 {
impl crate::FieldSpec for LINE_STATE_A {
type Ux = u8;
}
+impl crate::IsEnum for LINE_STATE_A {}
#[doc = "Field `LINE_STATE` reader - USB bus line state"]
pub type LINE_STATE_R = crate::FieldReader<LINE_STATE_A>;
impl LINE_STATE_R {
diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs
index fe1362f68..c695f6db7 100644
--- a/src/vreg_and_chip_reset/vreg.rs
+++ b/src/vreg_and_chip_reset/vreg.rs
@@ -52,6 +52,7 @@ impl From<VSEL_A> for u8 {
impl crate::FieldSpec for VSEL_A {
type Ux = u8;
}
+impl crate::IsEnum for VSEL_A {}
#[doc = "Field `VSEL` reader - Output voltage select for on-chip voltage regulator."]
pub type VSEL_R = crate::FieldReader<VSEL_A>;
impl VSEL_R {
diff --git a/src/xip_ssi/ctrlr0.rs b/src/xip_ssi/ctrlr0.rs
index 7c6221a3f..3f3a3def6 100644
--- a/src/xip_ssi/ctrlr0.rs
+++ b/src/xip_ssi/ctrlr0.rs
@@ -42,6 +42,7 @@ impl From<TMOD_A> for u8 {
impl crate::FieldSpec for TMOD_A {
type Ux = u8;
}
+impl crate::IsEnum for TMOD_A {}
#[doc = "Field `TMOD` reader - Transfer mode"]
pub type TMOD_R = crate::FieldReader<TMOD_A>;
impl TMOD_R {
@@ -78,7 +79,7 @@ impl TMOD_R {
}
}
#[doc = "Field `TMOD` writer - Transfer mode"]
-pub type TMOD_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, TMOD_A>;
+pub type TMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TMOD_A, crate::Safe>;
impl<'a, REG> TMOD_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
@@ -147,6 +148,7 @@ impl From<SPI_FRF_A> for u8 {
impl crate::FieldSpec for SPI_FRF_A {
type Ux = u8;
}
+impl crate::IsEnum for SPI_FRF_A {}
#[doc = "Field `SPI_FRF` reader - SPI frame format"]
pub type SPI_FRF_R = crate::FieldReader<SPI_FRF_A>;
impl SPI_FRF_R {
diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/xip_ssi/spi_ctrlr0.rs
index e025f4861..0eca1e48c 100644
--- a/src/xip_ssi/spi_ctrlr0.rs
+++ b/src/xip_ssi/spi_ctrlr0.rs
@@ -24,6 +24,7 @@ impl From<TRANS_TYPE_A> for u8 {
impl crate::FieldSpec for TRANS_TYPE_A {
type Ux = u8;
}
+impl crate::IsEnum for TRANS_TYPE_A {}
#[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"]
pub type TRANS_TYPE_R = crate::FieldReader<TRANS_TYPE_A>;
impl TRANS_TYPE_R {
@@ -104,6 +105,7 @@ impl From<INST_L_A> for u8 {
impl crate::FieldSpec for INST_L_A {
type Ux = u8;
}
+impl crate::IsEnum for INST_L_A {}
#[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"]
pub type INST_L_R = crate::FieldReader<INST_L_A>;
impl INST_L_R {
@@ -140,7 +142,7 @@ impl INST_L_R {
}
}
#[doc = "Field `INST_L` writer - Instruction length (0/4/8/16b)"]
-pub type INST_L_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INST_L_A>;
+pub type INST_L_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INST_L_A, crate::Safe>;
impl<'a, REG> INST_L_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs
index 3251a3d4c..fd98731fe 100644
--- a/src/xosc/ctrl.rs
+++ b/src/xosc/ctrl.rs
@@ -26,6 +26,7 @@ impl From<FREQ_RANGE_A> for u16 {
impl crate::FieldSpec for FREQ_RANGE_A {
type Ux = u16;
}
+impl crate::IsEnum for FREQ_RANGE_A {}
#[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."]
pub type FREQ_RANGE_R = crate::FieldReader<FREQ_RANGE_A>;
impl FREQ_RANGE_R {
@@ -111,6 +112,7 @@ impl From<ENABLE_A> for u16 {
impl crate::FieldSpec for ENABLE_A {
type Ux = u16;
}
+impl crate::IsEnum for ENABLE_A {}
#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.
If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.
The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
diff --git a/src/xosc/status.rs b/src/xosc/status.rs
index 519761725..3eef1b613 100644
--- a/src/xosc/status.rs
+++ b/src/xosc/status.rs
@@ -26,6 +26,7 @@ impl From<FREQ_RANGE_A> for u8 {
impl crate::FieldSpec for FREQ_RANGE_A {
type Ux = u8;
}
+impl crate::IsEnum for FREQ_RANGE_A {}
#[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"]
pub type FREQ_RANGE_R = crate::FieldReader<FREQ_RANGE_A>;
impl FREQ_RANGE_R {
diff --git a/svd/rp2040.svd.patched b/svd/rp2040.svd.patched
index e1995c90c..a57dfd308 100644
--- a/svd/rp2040.svd.patched
+++ b/svd/rp2040.svd.patched
@@ -282,14 +282,14 @@
<field>
<name>DFS_32</name>
<description>Data frame size in 32b transfer mode\n
- Value of n -> n+1 clocks per frame.</description>
+ Value of n -> n+1 clocks per frame.</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CFS</name>
<description>Control frame size\n
- Value of n -> n+1 clocks per frame.</description>
+ Value of n -> n+1 clocks per frame.</description>
<bitRange>[15:12]</bitRange>
<access>read-write</access>
</field>
@@ -422,8 +422,8 @@
<field>
<name>SER</name>
<description>For each bit:\n
- 0 -> slave not selected\n
- 1 -> slave selected</description>
+ 0 -> slave not selected\n
+ 1 -> slave selected</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
@@ -1347,7 +1347,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -1467,7 +1467,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -1587,7 +1587,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -1707,7 +1707,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -1783,7 +1783,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
@@ -1861,7 +1861,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -2019,7 +2019,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
@@ -2107,7 +2107,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
@@ -2195,7 +2195,7 @@
<fields>
<field>
<name>INT</name>
- <description>Integer component of the divisor, 0 -> divide by 2^16</description>
+ <description>Integer component of the divisor, 0 -> divide by 2^16</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
@@ -2241,7 +2241,7 @@
<field>
<name>TIMEOUT</name>
<description>This is expressed as a number of clk_ref cycles\n
- and must be >= 2x clk_ref_freq/min_clk_tst_freq</description>
+ and must be >= 2x clk_ref_freq/min_clk_tst_freq</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
@@ -4271,7 +4271,7 @@
</field>
<field>
<name>FUNCSEL</name>
- <description>0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins.</description>
+ <description>0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
@@ -6258,7 +6258,7 @@
</field>
<field>
<name>FUNCSEL</name>
- <description>0-31 -> selects pin function according to the gpio table\n
+ <description>0-31 -> selects pin function according to the gpio table\n
31 == NULL</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
@@ -7598,7 +7598,7 @@
<enumeratedValues>
<enumeratedValue>
<name>3v3</name>
- <description>Set voltage to 3.3V (DVDD >= 2V5)</description>
+ <description>Set voltage to 3.3V (DVDD >= 2V5)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
@@ -7843,7 +7843,7 @@
<enumeratedValues>
<enumeratedValue>
<name>3v3</name>
- <description>Set voltage to 3.3V (DVDD >= 2V5)</description>
+ <description>Set voltage to 3.3V (DVDD >= 2V5)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
@@ -9379,7 +9379,7 @@
<fields>
<field>
<name>RXIFLSEL</name>
- <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.</description>
+ <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.</description>
<bitRange>[5:3]</bitRange>
<access>read-write</access>
</field>
@@ -10641,7 +10641,7 @@
<name>IC_SAR</name>
<description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
- Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values.</description>
+ Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
@@ -12860,7 +12860,7 @@
<fields>
<field>
<name>THRESH</name>
- <description>DREQ/IRQ asserted when level >= threshold</description>
+ <description>DREQ/IRQ asserted when level >= threshold</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
@@ -13075,7 +13075,7 @@
<name>PH_ADV</name>
<description>Advance the phase of the counter by 1 count, while it is running.\n
Self-clearing. Write a 1, and poll until low. Counter must be running\n
- at less than full speed (div_int + div_frac / 16 > 1)</description>
+ at less than full speed (div_int + div_frac / 16 > 1)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<modifiedWriteValues>clear</modifiedWriteValues>
@@ -14865,7 +14865,7 @@
<name>TREQ_SEL</name>
<description>Select a Transfer Request signal.\n
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
- 0x0 to 0x3a -> select DREQ n as TREQ</description>
+ 0x0 to 0x3a -> select DREQ n as TREQ</description>
<bitRange>[20:15]</bitRange>
<access>read-write</access>
<enumeratedValues>
@@ -15112,7 +15112,7 @@
</field>
<field>
<name>RING_SIZE</name>
- <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+ <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
<bitRange>[9:6]</bitRange>
<access>read-write</access>
@@ -15233,7 +15233,7 @@
<name>TREQ_SEL</name>
<description>Select a Transfer Request signal.\n
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
- 0x0 to 0x3a -> select DREQ n as TREQ</description>
+ 0x0 to 0x3a -> select DREQ n as TREQ</description>
<bitRange>[20:15]</bitRange>
<access>read-write</access>
<enumeratedValues>
@@ -15480,7 +15480,7 @@
</field>
<field>
<name>RING_SIZE</name>
- <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+ <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
<bitRange>[9:6]</bitRange>
<access>read-write</access>
@@ -15624,7 +15624,7 @@
<name>TREQ_SEL</name>
<description>Select a Transfer Request signal.\n
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
- 0x0 to 0x3a -> select DREQ n as TREQ</description>
+ 0x0 to 0x3a -> select DREQ n as TREQ</description>
<bitRange>[20:15]</bitRange>
<access>read-write</access>
<enumeratedValues>
@@ -15871,7 +15871,7 @@
</field>
<field>
<name>RING_SIZE</name>
- <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+ <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
<bitRange>[9:6]</bitRange>
<access>read-write</access>
@@ -16015,7 +16015,7 @@
<name>TREQ_SEL</name>
<description>Select a Transfer Request signal.\n
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
- 0x0 to 0x3a -> select DREQ n as TREQ</description>
+ 0x0 to 0x3a -> select DREQ n as TREQ</description>
<bitRange>[20:15]</bitRange>
<access>read-write</access>
<enumeratedValues>
@@ -16262,7 +16262,7 @@
</field>
<field>
<name>RING_SIZE</name>
- <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+ <description>Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
<bitRange>[9:6]</bitRange>
<access>read-write</access>
@@ -17712,7 +17712,7 @@
<fields>
<field>
<name>INT_EP_ACTIVE</name>
- <description>Host: Enable interrupt endpoint 1 -> 15</description>
+ <description>Host: Enable interrupt endpoint 1 -> 15</description>
<bitRange>[15:1]</bitRange>
<access>read-write</access>
</field>
@@ -19733,8 +19733,8 @@
<register>
<name>INPUT_SYNC_BYPASS</name>
<description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
- 0 -> input is synchronized (default)\n
- 1 -> synchronizer is bypassed\n
+ 0 -> input is synchronized (default)\n
+ 1 -> synchronizer is bypassed\n
If in doubt, leave this register as all zeroes.</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
@@ -20417,7 +20417,7 @@
<fields>
<field>
<name>GPIO_OUT</name>
- <description>Set output level (1/0 -> high/low) for GPIO0...29.\n
+ <description>Set output level (1/0 -> high/low) for GPIO0...29.\n
Reading back gives the last value written, NOT the input value from the pins.\n
If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n
the result is as though the write from core 0 took place first,\n
@@ -20477,7 +20477,7 @@
<fields>
<field>
<name>GPIO_OE</name>
- <description>Set output enable (1/0 -> output/input) for GPIO0...29.\n
+ <description>Set output enable (1/0 -> output/input) for GPIO0...29.\n
Reading back gives the last value written.\n
If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n
the result is as though the write from core 0 took place first,\n
@@ -20537,7 +20537,7 @@
<fields>
<field>
<name>GPIO_HI_OUT</name>
- <description>Set output level (1/0 -> high/low) for QSPI IO0...5.\n
+ <description>Set output level (1/0 -> high/low) for QSPI IO0...5.\n
Reading back gives the last value written, NOT the input value from the pins.\n
If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n
the result is as though the write from core 0 took place first,\n
@@ -20597,7 +20597,7 @@
<fields>
<field>
<name>GPIO_HI_OE</name>
- <description>Set output enable (1/0 -> output/input) for QSPI IO0...5.\n
+ <description>Set output enable (1/0 -> output/input) for QSPI IO0...5.\n
Reading back gives the last value written.\n
If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n
the result is as though the write from core 0 took place first,\n
@@ -20652,9 +20652,9 @@
<register>
<name>FIFO_ST</name>
<description>Status register for inter-core FIFOs (mailboxes).\n
- There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n
- Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n
- Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n
+ There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n
+ Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n
+ Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000002</resetValue>