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Non-Debug Reset #4

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enfreck opened this issue Feb 3, 2025 · 1 comment
Open

Non-Debug Reset #4

enfreck opened this issue Feb 3, 2025 · 1 comment

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@enfreck
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enfreck commented Feb 3, 2025

I'm trying to compile this core without SRC1_DBGC_EN set. However, I get an error on line 552 of scr1_pipe_top.sv stating that rst_n is declared implicitly. Is this wire supposed to be pipe_rst_n from the module input?
@enfreck
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enfreck commented Feb 3, 2025

Additionally, exu_busy comes up with an implicitly defined warning on line 435 of scr1_pipe_top.sv

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@enfreck