From 2956be349ff4b7a13dcf768cb20b550698ae557d Mon Sep 17 00:00:00 2001 From: Maleehaakbar Date: Wed, 4 Dec 2024 00:06:59 +0500 Subject: [PATCH] implement mtvt CSR --- src/Emulator/Cores/RiscV/RegisterDescription.cs | 3 ++- src/Emulator/Cores/RiscV/RiscV32Registers.cs | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/Emulator/Cores/RiscV/RegisterDescription.cs b/src/Emulator/Cores/RiscV/RegisterDescription.cs index e4df2214f..fa19d6d71 100644 --- a/src/Emulator/Cores/RiscV/RegisterDescription.cs +++ b/src/Emulator/Cores/RiscV/RegisterDescription.cs @@ -393,7 +393,8 @@ public static void AddCSRFeature(ref List features, uint r csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MEDELEG, registerWidth, "medeleg", intType, "csr")); csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MIDELEG, registerWidth, "mideleg", intType, "csr")); } - + + csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MTVT, registerWidth, "mtvt","", "csr")); csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MSTATUS, registerWidth, "mstatus", "", "csr")); csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MISA, registerWidth, "misa", "", "csr")); csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MIE, registerWidth, "mie", "mie_type", "csr")); diff --git a/src/Emulator/Cores/RiscV/RiscV32Registers.cs b/src/Emulator/Cores/RiscV/RiscV32Registers.cs index 118e963d3..6164eb3a9 100644 --- a/src/Emulator/Cores/RiscV/RiscV32Registers.cs +++ b/src/Emulator/Cores/RiscV/RiscV32Registers.cs @@ -278,6 +278,18 @@ public RegisterValue SPTBR } } [Register] + public RegisterValue MTVT + { + get + { + return GetRegisterValue32((int)RiscV32Registers.MTVT); + } + set + { + SetRegisterValue32((int)RiscV32Registers.MTVT, value); + } + } + [Register] public RegisterValue MSTATUS { get @@ -773,6 +785,7 @@ protected override void InitializeRegisters() { RiscV32Registers.STVAL, new CPURegister(388, 32, isGeneral: false, isReadonly: false, aliases: new [] { "STVAL" }) }, { RiscV32Registers.SIP, new CPURegister(389, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SIP" }) }, { RiscV32Registers.SATP, new CPURegister(449, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SATP", "SPTBR" }) }, + { RiscV32Registers.MTVT, new CPURegister(775, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MTVT" }) }, { RiscV32Registers.MSTATUS, new CPURegister(833, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MSTATUS" }) }, { RiscV32Registers.MISA, new CPURegister(834, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MISA" }) }, { RiscV32Registers.MEDELEG, new CPURegister(835, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MEDELEG" }) }, @@ -811,6 +824,7 @@ public enum RiscV32Registers SIP = 389, SATP = 449, SPTBR = 449, + MTVT= 775, MSTATUS = 833, MISA = 834, MEDELEG = 835,