diff --git a/arch/ext/Zca.yaml b/arch/ext/Zca.yaml new file mode 100644 index 000000000..f3c3de73f --- /dev/null +++ b/arch/ext/Zca.yaml @@ -0,0 +1,17 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +Zca: + long_name: Common compressed instructions + description: | + TODO + type: unprivileged + company: + name: RISC-V International + url: https://riscv.org + versions: + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main diff --git a/backends/arch_gen/lib/arch_gen.rb b/backends/arch_gen/lib/arch_gen.rb index 1c03e9b35..6681f4fb4 100644 --- a/backends/arch_gen/lib/arch_gen.rb +++ b/backends/arch_gen/lib/arch_gen.rb @@ -742,7 +742,7 @@ def maybe_add_csr(csr_name, extra_env = {}) arch_def_mock.define_singleton_method(:possible_xlens) do pos_xlen_local end - impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1]) } + impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1], nil) } arch_def_mock.define_singleton_method(:implemented_extensions) do impl_ext end @@ -1001,7 +1001,7 @@ def maybe_add_inst(inst_name, extra_env = {}) arch_def_mock = Object.new arch_def_mock.define_singleton_method(:fully_configured?) { true } arch_def_mock.define_singleton_method(:possible_xlens) { possible_xlens } - impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1]) } + impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1], nil) } arch_def_mock.define_singleton_method(:implemented_extensions) do impl_ext end diff --git a/backends/cfg_html_doc/templates/ext.adoc.erb b/backends/cfg_html_doc/templates/ext.adoc.erb index b3844b233..1808e4941 100644 --- a/backends/cfg_html_doc/templates/ext.adoc.erb +++ b/backends/cfg_html_doc/templates/ext.adoc.erb @@ -7,23 +7,26 @@ Implemented Version:: <%= ext_version.version %> == Versions <%- ext.versions.each do |v| -%> -<%- implemented = arch_def.implemented_extensions.include?(ExtensionVersion.new(ext.name, v["version"])) -%> -<%= v["version"] %>:: +<%- implemented = arch_def.implemented_extensions.include?(v) -%> +<%= v.version %>:: Ratification date::: - <%= v["ratification_date"] %> - <%- if v.key?("changes") -%> + <%= v.ratification_date %> + <%- unless v.changes.empty? -%> Changes::: - <%= v["changes"] %> + + <% v.changes.each do |c| -%> + * <%= c %> + <% end -%> + <%- end -%> - <%- if v.key?("url") -%> + <%- unless v.url.nil? -%> Ratification document::: - <%= v["url"] %> + <%= v.url %> <%- end -%> - <%- if v.key?("implies") -%> + <%- unless v.implications.empty? -%> Implies::: - <%- implications = v["implies"][0].is_a?(Array) ? v["implies"] : [v["implies"]] -%> - <%- implications.each do |i| -%> - * `<%= i[0] %>` version <%= i[1] %> + <%- v.implications.each do |i| -%> + * `<%= i.name %>` version <%= i.version %> <%- end -%> <%- end -%> <%- end -%> diff --git a/backends/crd_doc/templates/crd.adoc.erb b/backends/crd_doc/templates/crd.adoc.erb index e17221661..a3906d2ab 100644 --- a/backends/crd_doc/templates/crd.adoc.erb +++ b/backends/crd_doc/templates/crd.adoc.erb @@ -277,30 +277,29 @@ Requirement <%= req.name %> only apply when <%= req.when_pretty %>. *Version Requirement*: <%= ext_req.version_requirement %> + <% ext_db.versions.each do |v| -%> -<%= v["version"] %>:: +<%= v.version %>:: State::: - <%= v["state"] %> - <% if v["state"] == "ratified" -%> + <%= v.state %> + <% if v.state == "ratified" -%> Ratification date::: - <%= v["ratification_date"] %> + <%= v.ratification_date %> <% end # if %> - <% if v.key?("changes") -%> + <% if v.changes.size > 0 -%> Changes::: - <% v["changes"].each do |c| -%> + <% v.changes.each do |c| -%> * <%= c %> <% end -%> <% end -%> - <% if v.key?("url") -%> + <% unless v.url.nil? -%> Ratification document::: - <%= v["url"] %> + <%= v.url %> <% end -%> - <% if v.key?("implies") -%> + <% if v.implications.size > 0 -%> Implies::: - <% implications = v["implies"][0].is_a?(Array) ? v["implies"] : [v["implies"]] -%> - <% implications.each do |i| -%> - * `<%= i[0] %>` version <%= i[1] %> + <% v.implications.each do |i| -%> + * `<%= i.name %>` version <%= i.version %> <% end -%> <% end -%> <% end -%> diff --git a/backends/ext_pdf_doc/tasks.rake b/backends/ext_pdf_doc/tasks.rake index f1d018f56..a7546f5c4 100644 --- a/backends/ext_pdf_doc/tasks.rake +++ b/backends/ext_pdf_doc/tasks.rake @@ -149,9 +149,9 @@ rule %r{#{$root}/gen/ext_pdf_doc/.*/adoc/.*_extension\.adoc} => proc { |tname| if ENV.key?("EXT_VERSION") ENV["EXT_VERSION"] else - ext.versions.max { |a, b| Gem::Version.new(a["version"]) <=> Gem::Version.new(b["version"]) }["version"] + ext.versions.max { |a, b| a.version <=> b.version }.version end - ext_version = ext.versions.find { |v| v["version"] == version_num } + ext_version = ext.versions.find { |v| v.version == version_num } FileUtils.mkdir_p File.dirname(t.name) File.write t.name, AsciidocUtils.resolve_links(arch_def.find_replace_links(erb.result(binding))) end diff --git a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb index bce3131e6..ee5eb803a 100644 --- a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb +++ b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb @@ -1,9 +1,9 @@ [[header]] :description: <%= ext.long_name %> (<%= ext.name %>) -:revdate: <%= ext_version.key?("ratification_date") ? ext_version["ratification_date"] : Date.today %> -:revnumber: <%= ext_version["version"] %> +:revdate: <%= ext_version.ratification_date.nil? ? Date.today : ext_version.ratification_date %> +:revnumber: <%= ext_version.version %> :revmark: <%= - case ext_version["state"] + case ext_version.state when "ratified" <<~STATE This document is in the http://riscv.org/spec-state[Ratified state] + \\ @@ -14,12 +14,12 @@ STATE when "frozen" <<~FROZEN_STATE - This document is in the http://riscv.org/spec-state[Frozen state]. - - Change is extremely unlikely. - A high threshold will be used, and a change will only occur because of some truly - critical issue being identified during the public review cycle. - Any other desired or needed changes can be the subject of a follow-on new extension. + This document is in the http://riscv.org/spec-state[Frozen state]. + \\ + + \\ + Change is extremely unlikely. + \\ + A high threshold will be used, and a change will only occur because of some truly + \\ + critical issue being identified during the public review cycle. + \\ + Any other desired or needed changes can be the subject of a follow-on new extension. + \\ FROZEN_STATE when "development" <<~DEV_STATE @@ -28,7 +28,7 @@ Change should be expected + \\ DEV_STATE else - raise "TODO: #{ext_version["state"]} description" + raise "TODO: #{ext_version.state} description" end %> :company: <%= ext.company.nil? ? "unknown" : ext.company["name"] %> @@ -41,7 +41,7 @@ :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center] :back-cover-image: image:riscv-horizontal-color.svg[opacity=25%] <%- end -%> -<%- unless ext_version["state"] == "ratified" -%> +<%- if ext_version.state == "development" -%> :page-background-image: image:draft.png[opacity=20%] <%- end -%> // Settings @@ -85,7 +85,7 @@ endif::[] // Preamble <%= - case ext_version["state"] + case ext_version.state when "ratified" <<~RATIFIED_STATE [WARNING] @@ -115,7 +115,7 @@ endif::[] ==== DEV_STATE else - raise "TODO: #{ext_version["state"]} description" + raise "TODO: #{ext_version.state} description" end %> @@ -123,17 +123,17 @@ endif::[] == Copyright and license information This document is released under the <%= ext.doc_license.nil? ? "unknown" : ext.doc_license["url"] %>[<%= ext.doc_license.nil? ? "unknown" : ext.doc_license["name"] %>]. -Copyright <%= ext_version["ratification_date"].nil? ? Date.today.year : ext_version["ratification_date"].split("-")[0] %> by <%= ext.company.nil? ? "unknown" : ext.company["name"] %>. +Copyright <%= ext_version.ratification_date.nil? ? Date.today.year : ext_version.ratification_date.split("-")[0] %> by <%= ext.company.nil? ? "unknown" : ext.company["name"] %>. [preface] == Acknowledgements <%- ext.versions.each do |version| -%> -Contributors to version <%= version["version"] %> of the specification (in alphabetical order) include: + +Contributors to version <%= version.version %> of the specification (in alphabetical order) include: + -<%- unless version["contributors"].nil? -%> -<%- version["contributors"].sort { |a, b| a["name"].split(" ").last <=> b["name"].split(" ").last }.each do |c| -%> - * <%= c["name"] %> <<%= c["email"] %>> (<%= c["company"] %>) +<%- unless version.contributors.empty? -%> +<%- version.contributors.sort { |a, b| a.name.split(" ").last <=> b.name.split(" ").last }.each do |c| -%> + * <%= c.name %> <<%= c.email %>> (<%= c.company %>) <%- end -%> <%- end -%> @@ -149,21 +149,29 @@ The following versions have been defined: <%- ext.versions.each do |version| -%> -- -Version:: <%= version["version"] %> -State:: <%= version["state"] %> -<%- if version.key?("ratification_date") && !version["ratification_date"].nil? -%> -Ratification Date:: <%= version["ratification_date"] %> +Version:: <%= version.version %> +State:: <%= version.state %> +<%- unless version.ratification_date.nil? -%> +Ratification Date:: <%= version.ratification_date %> <%- end -%> -<%- if version.key?("url") -%> -Design document:: <%= version["url"] %> +<%- unless version.url.nil? -%> +Design document:: <%= version.url %> <%- end -%> -<%- if version.key?("changes") -%> +<%- unless version.changes.empty? -%> Changes:: -<%= version["changes"] %> + + <% version.changes.each do |c| -%> + * <%= c %> + <% end -%> + <%- end -%> -<%- unless version["implies"].nil? || version["implies"].empty? -%> +<%- unless version.implications.empty? -%> Implies:: -* <%= version["implies"].map { |name, version| "#{name} (#{version})" }.join("\n* ") %> +* <%= version.implications.map { |i| "#{i.name} (#{i.version})" }.join("\n* ") %> +<%- unless version.requirements.empty? -%> +Requires:: +<%= version.requirements.to_asciidoc %> +<%- end -%> <%- end -%> -- <%- end -%> @@ -176,13 +184,22 @@ Implies:: <%- unless ext.implies.nil? -%> === Sub-extensions -The following sub-extensions are defined: +<%- if ext.implies.size > 1 -%> +<%= ext.name %> defines the following #{ext.implies.size} sub-extensions: +<%- else -%> +<%= ext.name %> defines a single sub-extension: +<%- end -%> <%- ext.implies.each do |sub_ext| -%> ==== <%= sub_ext.name %> <%= arch_def.extension(sub_ext.name).description %> +<%- unless sub_ext.requirements.empty? -%> +<%= sub_ext.name %> requires: +<%= sub_ext.requirements.to_asciidoc %> +<%- end -%> + <%- end -%> <%- end -%> @@ -194,14 +211,14 @@ The following <%= ext.instructions.size %> instructions are added by this extens [%autowidth] |=== -| RV32 | RV64 | Mnemonic | Instruction | <%= ext.versions.map { |v| "v#{v["version"]}" }.join(" | ") %> +| RV32 | RV64 | Mnemonic | Instruction | <%= ext.versions.map { |v| "v#{v.version}" }.join(" | ") %> <%- ext.instructions.each do |i| -%> | <%= i.rv32? ? "✓" : "" %> | <%= i.rv64? ? "✓" : "" %> | `<%= i.name %> <%= i.assembly.gsub("x", "r").strip %>` | xref:insns-<%= i.name.gsub('.', '_') %>[<%= i.long_name %>] -| <%= ext.versions.map { |v| i.defined_by?(ext.name, v["version"]) ? "✓" : "" }.join(" | ") %> +| <%= ext.versions.map { |v| i.defined_by?(ext.name, v.version) ? "✓" : "" }.join(" | ") %> <%- end -%> |=== @@ -230,14 +247,14 @@ The following <%= ext.csrs.size %> are added by this extension. [%autowidth] |=== -| RV32 | RV64 | CSR | Name | <%= ext.versions.map { |v| "v#{v["version"]}" }.join(" | ") %> +| RV32 | RV64 | CSR | Name | <%= ext.versions.map { |v| "v#{v.version}" }.join(" | ") %> <%- ext.csrs.each do |csr| -%> | <%= csr.defined_in_base32? ? "✓" : "" %> | <%= csr.defined_in_base64? ? "✓" : "" %> | xref:csrs-<%= csr.name.gsub('.', '_') %>[<%= csr.name %>] | <%= csr.long_name %> -| <%= ext.versions.map { |v| csr.defined_by?(ext.name, v["version"]) ? "✓" : "" }.join(" | ") %> +| <%= ext.versions.map { |v| csr.defined_by?(ext.name, v.version) ? "✓" : "" }.join(" | ") %> <%- end -%> |=== diff --git a/backends/manual/templates/ext.adoc.erb b/backends/manual/templates/ext.adoc.erb index 211fd068b..410576a9c 100644 --- a/backends/manual/templates/ext.adoc.erb +++ b/backends/manual/templates/ext.adoc.erb @@ -5,28 +5,29 @@ == Versions <%- ext.versions.each do |v| -%> -<%= v["version"] %>:: +<%= v.version %>:: State::: - <%= v["state"] %> - <%- if v["state"] == "ratified" -%> + <%= v.state %> + <%- if v.state == "ratified" -%> Ratification date::: - <%= v["ratification_date"] %> + <%= v.ratification_date %> <%- end -%> - <%- if v.key?("changes") -%> + <%- unless v.changes.empty? -%> Changes::: - <%- v["changes"].each do |change| %> + + <%- v.changes.each do |change| %> * <%= change %> <%- end -%> + <%- end -%> - <%- if v.key?("url") -%> + <%- unless v.url.nil? -%> Ratification document::: - <%= v["url"] %> + <%= v.url %> <%- end -%> - <%- if v.key?("implies") -%> + <%- unless v.implications -%> Implies::: - <%- implications = v["implies"][0].is_a?(Array) ? v["implies"] : [v["implies"]] -%> - <%- implications.each do |i| -%> - * `<%= i[0] %>` version <%= i[1] %> + <%- v.implications.each do |i| -%> + * `<%= i.name %>` version <%= i.version %> <%- end -%> <%- end -%> <%- end -%> @@ -35,7 +36,7 @@ <%= ext.description %> -<%- insts = arch_def.instructions.select { |i| ext.versions.any? { |v| i.defined_by?(ext.name, v["version"]) } } -%> +<%- insts = arch_def.instructions.select { |i| ext.versions.any? { |v| i.defined_by?(ext.name, v.version) } } -%> <%- unless insts.empty? -%> == Instructions diff --git a/backends/manual/templates/param_list.adoc.erb b/backends/manual/templates/param_list.adoc.erb index 8e0fb65cf..518e38253 100644 --- a/backends/manual/templates/param_list.adoc.erb +++ b/backends/manual/templates/param_list.adoc.erb @@ -1,7 +1,7 @@ = Architectural Parameters <%- - params = manual_version.extensions.map{ |e| e.params(arch_def) }.flatten.uniq(&:name).sort_by!(&:name) + params = manual_version.extensions.map{ |e| e.params }.flatten.uniq(&:name).sort_by!(&:name) -%> The following <%= params.size %> parameters are defined in this manual: diff --git a/backends/profile_doc/templates/profile_pdf.adoc.erb b/backends/profile_doc/templates/profile_pdf.adoc.erb index 4d03f12ba..2e7674a95 100644 --- a/backends/profile_doc/templates/profile_pdf.adoc.erb +++ b/backends/profile_doc/templates/profile_pdf.adoc.erb @@ -416,12 +416,12 @@ Version<%= ext_req.version_requirement %> .Status |=== -| Profile | v<%= ext.versions.map { |v| v["version"] }.join(" | v") %> +| Profile | v<%= ext.versions.map { |v| v.version }.join(" | v") %> <%- profile_family.profiles.each do |profile| -%> | <%= profile.marketing_name %> | <%= ext.versions.map do |v| - mandatory = profile.mandatory_extension_requirements.any? { |req| req.satisfied_by?(ext.name, v["version"]) } - optional = profile.optional_extension_requirements.any? { |req| req.satisfied_by?(ext.name, v["version"]) } + mandatory = profile.mandatory_extension_requirements.any? { |req| req.satisfied_by?(ext.name, v.version) } + optional = profile.optional_extension_requirements.any? { |req| req.satisfied_by?(ext.name, v.version) } if mandatory "mandatory" elsif optional @@ -435,26 +435,25 @@ end.join(" | ") -%> |=== <%- ext.versions.each do |v| -%> -<%= v["version"] %>:: +<%= v.version %>:: Ratification date::: - <%= v["ratification_date"] %> - <%- if v.key?("changes") -%> + <%= v.ratification_date %> + <%- unless v.changes.empty? -%> Changes::: - <%- v["changes"].each do |c| -%> + <%- v.changes.each do |c| -%> * <%= c %> <%- end -%> <%- end -%> - <%- if v.key?("url") -%> + <%- unless v.url.nil? -%> Ratification document::: - <%= v["url"] %> + <%= v.url %> <%- end -%> - <%- if v.key?("implies") -%> + <%- unless v.implications -%> Implies::: - <%- implications = v["implies"][0].is_a?(Array) ? v["implies"] : [v["implies"]] -%> - <%- implications.each do |i| -%> - * `<%= i[0] %>` version <%= i[1] %> + <%- v.implications.each do |i| -%> + * `<%= i.name %>` version <%= i.version %> <%- end -%> <%- end -%> <%- end -%> diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 032163b6b..d56bcd6bd 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -57,6 +57,39 @@ Xqci: - [Xqcilo, "0.1.0"] - [Xqcilsm, "0.1.0"] - [Xqcisls, "0.1.0"] + - version: "0.4.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.c.extu instruction + - Fix description and functionality of qc.shladd instruction + implies: + - [Xqcia, "0.2.0"] + - [Xqciac, "0.2.0"] + - [Xqcibi, "0.2.0"] + - [Xqcibm, "0.2.0"] + - [Xqcicli, "0.2.0"] + - [Xqcicm, "0.2.0"] + - [Xqcics, "0.2.0"] + - [Xqcicsr, "0.2.0"] + - [Xqciint, "0.2.0"] + - [Xqcilb, "0.2.0"] + - [Xqcili, "0.2.0"] + - [Xqcilia, "0.2.0"] + - [Xqcilo, "0.2.0"] + - [Xqcilsm, "0.2.0"] + - [Xqcisls, "0.2.0"] + requires: + name: Zca + version: ">= 1.0.0" description: | The Xqci extension includes a set of instructions that improve RISC-V code density and performance in microontrollers. It fills several gaps: @@ -114,6 +147,238 @@ Xqci: follow the guidance for 48-bit instructions in the RISC-V standard, but are not allocated in reserved custom space since no such space has been defined by RISC-V International. + Extension-specific instruction formats :: + -- + QC.EAI format used for 48-bit instructions that operate on 32-bit immediate argument. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |rd + ^|7 + ^|5 + |Destination register + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |f1 + ^|15 + ^|1 + |Secondary function field + + |imm[31:0] + ^|16 + ^|32 + |Immediate operand of 32 bits + |=== + + -- + QC.EI format used for 48-bit instructions that operate on 26-bit immediate argument, including loads. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |rd + ^|7 + ^|5 + |Destination register + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument + + |imm[9:0] + ^|20 + ^|10 + |Immediate operand of 26 bits, the 10 LSBs + + |func2 + ^|30 + ^|2 + |Secondary function field + + |imm[25:10] + ^|32 + ^|16 + |Immediate operand of 26 bits, the 16 MSBs + |=== + + -- + QC.EB format used for 48-bit branch instructions that compare register with 16-bit immediate. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:1,11] + ^|7 + ^|5 + |Bits of immediate value of branch target + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument + + |func5 + ^|20 + ^|5 + |Secondary function field + + |imm[12,10:5] + ^|25 + ^|7 + |Bits of immediate value of branch target + + |simm[15:0] + ^|32 + ^|16 + |Immediate operand of 16 bits to compare with register + |=== + + -- + QC.EJ format used for 48-bit jump/call instructions with 32-bit immediate target address. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:1,11] + ^|7 + ^|5 + |Bits of immediate value of branch target + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |func2 + ^|15 + ^|2 + |Secondary function field + + |imm[15:13] + ^|17 + ^|3 + |Bits of immediate value of branch target + + |func5 + ^|20 + ^|5 + |Secondary function field + + |imm[12,10:5] + ^|25 + ^|7 + |Bits of immediate value of branch target + + |imm[31:16] + ^|32 + ^|16 + |The 16 MSBs of immediate value of branch target + |=== + + -- + QC.ES format used for 48-bit store instructions with 26-bit immediate offset. + -- + + [%autowidth.stretch] + |=== + |Field|Start bit|Width|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:0] + ^|7 + ^|5 + |Immediate operand of 26 bits offset, the 5 LSBs + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument used as base address + + |rs2 + ^|20 + ^|5 + |Register argument to be saved + + |imm[9:5] + ^|25 + ^|5 + |Immediate operand of 26 bits offset, the 5 bits + + |func2 + ^|30 + ^|2 + |Secondary function field + + |imm[25:10] + ^|32 + ^|16 + |Immediate operand of 26 bits offset, the 16 MSBs + |=== doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml index 13b260f82..f4e7919b0 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml @@ -14,6 +14,18 @@ Xqcia: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcia extension includes eleven instructions to perform integer arithmetic. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index 84ceb036a..9bc4d4981 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -14,6 +14,20 @@ Xqciac: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.shladd instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common address calculations. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml index 07777b070..7b010a25c 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml @@ -14,6 +14,19 @@ Xqcibi: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcibi extension includes twelve conditional branch instructions that use an immediate operand for a source. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml index b42c3dbb3..3d8f0b639 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml @@ -14,6 +14,20 @@ Xqcibm: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.c.extu instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcibm extension includes thirty eight instructions that perform bit manipulation, include insertion and extraction. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml index da997c7a5..523f6c8f9 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml @@ -14,6 +14,18 @@ Xqcicli: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcicli extension includes twelve instructions that conditionally load an immediate value. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml index afe63c5be..c66c8d1be 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml @@ -14,6 +14,19 @@ Xqcicm: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcicm extension includes thirteen conditional move instructions. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml index a67445bac..55541cbc1 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml @@ -14,6 +14,18 @@ Xqcics: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcics extension includes eight conditional select instructions. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml index 5e98e9c32..fe9437a47 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml @@ -14,6 +14,18 @@ Xqcicsr: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml index 6c7dee2e6..23629d36f 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml @@ -14,6 +14,19 @@ Xqciint: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciint extension includes eleven instructions to accelerate interrupt servicing by performing common actions during ISR prologue/epilogue. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml index 716e3112c..6bde4f5a0 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml @@ -14,6 +14,19 @@ Xqcilb: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcilb extension includes two 48-bit instructions to encode a long branch. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml index 8f2bf5b38..249e7894d 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml @@ -14,6 +14,18 @@ Xqcili: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcili extension includes a two instructions that load large immediates than is available with the base RISC-V ISA. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml index 1f02fd595..988462207 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml @@ -14,6 +14,19 @@ Xqcilia: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcilia extension includes eight 48-bit instructions that perform arithmetic using large immediates. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml index 4278826ac..0b20a7d41 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml @@ -14,6 +14,19 @@ Xqcilo: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset larger than can be found in the base RISC-V ISA. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml index 2abb91120..1a573f94f 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml @@ -14,6 +14,18 @@ Xqcilsm: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqcilsm extension includes six instructions that transfer multiple values between registers and memory. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml index fc08bf02b..844c7b62b 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml @@ -14,6 +14,18 @@ Xqcisls: - name: Derek Hower company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com + - version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction description: | The Xqsls extension includes five load and three store instructions with a scaled index addressing mode. diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml index 5509ff950..85a2fbe7d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml @@ -4,6 +4,7 @@ qc.addsat: long_name: Saturating signed addition description: | Add signed values `rs1` and `rs2`, saturate the signed result, and write to `rd`. + Instruction encoded in R instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml index 2e2393a77..60f03c623 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml @@ -4,6 +4,7 @@ qc.addusat: long_name: Saturating unsigned addition description: | Add unsigned values `rs1` and `rs2`, saturate the unsigned result, and write to `rd`. + Instruction encoded in R instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml index 78e7612dc..afb720627 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml @@ -4,6 +4,7 @@ qc.beqi: long_name: Branch on equal (Immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is equal to the signed immediate + Instruction encoded in BI instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml index 538d174ec..a6a163c02 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml @@ -4,6 +4,7 @@ qc.bgei: long_name: Branch on greater than or equal (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is greater than or equal to the immediate. + Instruction encoded in BI instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml index e90ada532..6124c7adf 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml @@ -4,6 +4,7 @@ qc.bgeui: long_name: Branch on greater than or equal unsigned (immediate) description: | Branches to `PC` + `offset` if the unsigned value in `rs1` is greater than or equal to the unsigned immediate. + Instruction encoded in BI instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml index 6f2e2cf69..a0622f36b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml @@ -4,6 +4,7 @@ qc.blti: long_name: Branch on less than (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is less than the immediate. + Instruction encoded in BI instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml index 0cbe5b5b2..10313fefc 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml @@ -4,6 +4,7 @@ qc.bltui: long_name: Branch on less than unsigned (immediate) description: | Branches to `PC` + `offset` if the unsigned value in `rs1` is less than the unsigned immediate. + Instruction encoded in BI instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml index aae448fd0..337d5fa7b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml @@ -3,7 +3,8 @@ qc.bnei: long_name: Branch on not equal (immediate) description: | - Branches to `PC` + `offset` if the value in `rs1` is not equal to the signed immediate + Branches to `PC` + `offset` if the value in `rs1` is not equal to the signed immediate. + Instruction encoded in BI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml index bb406f320..8b5311449 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml @@ -3,7 +3,8 @@ qc.brev32: long_name: Reverse bit order description: | - Reverses the bit order of `rs1` and writes the result to `rd` + Reverses the bit order of `rs1` and writes the result to `rd`. + Instruction encoded in I instruction format definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bexti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bexti.yaml index 7ceb94186..5c3db911a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bexti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bexti.yaml @@ -5,6 +5,7 @@ qc.c.bexti: description: | This instruction returns a single bit extracted from `rd`. The index is read from the lower log2(XLEN) bits of `shamt`. + Instruction encoded in CB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml index 050e2c550..3395e4d07 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml @@ -5,6 +5,7 @@ qc.c.bseti: description: | This instruction returns `rd` with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of `shamt`. + Instruction encoded in CB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml index 3c852338b..ccc9e031a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml @@ -4,6 +4,7 @@ qc.c.clrint: long_name: Clear interrupt (Register) description: | Clear interrupt, interrupt number is in `rs1`. + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml index 639f51e2a..0ed13b33e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml @@ -4,6 +4,7 @@ qc.c.delay: long_name: Delay execution description: | Delay execution for given `imm` amount of cycles. + Instruction encoded in CI instruction format. definedBy: Xqcipr assembly: " imm" base: 32 diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml index 53c23b389..529dfbcdf 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml @@ -5,6 +5,7 @@ qc.c.di: description: | Globally disable interrupts. Equivalent to "csrrci `zero`, `mstatus`, 8". + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml index d511d2c7d..a74b9ddd8 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml @@ -5,6 +5,7 @@ qc.c.dir: description: | Globally disable interrupts, write previous value of `mstatus` to `rd`. Equivalent to "csrrci `rd`, `mstatus`, 8". + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml index 530cd9980..64acbf444 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml @@ -5,6 +5,7 @@ qc.c.ei: description: | Globally enable interrupts. Equivalent to "csrrsi `zero`, `mstatus`, 8". + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml index 94beb9abf..5884651e0 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml @@ -5,6 +5,7 @@ qc.c.eir: description: | Globally restore interrupts, write `rs1` to `mstatus`. Equivalent to "csrrs `zero`, `mstatus`, `rs1`". + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml index 4d4a96695..d008fee90 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml @@ -5,6 +5,7 @@ qc.c.extu: description: | Extract a subset of bits from `rd` starting from LSB. The width of the subset is determined by (`width_minus1`[4:0] + 1) (1..32). + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci @@ -16,6 +17,7 @@ qc.c.extu: variables: - name: width_minus1 location: 6-2 + not: [0,1,2,3] - name: rd location: 11-7 access: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml index 022b51ba4..dab829d1f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml @@ -4,6 +4,7 @@ qc.c.mienter.nest: Machine mode interrupt enter, interrupt nesting is enabled. Interrupt frame is saved in the stack. Interrupts are enabled. + Instruction encoded in CI instruction format. assembly: "" definedBy: anyOf: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml index f44fbac83..7ebeff6ae 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml @@ -6,6 +6,7 @@ qc.c.mienter: Machine mode interrupt enter, interrupt nesting is disabled. Interrupt frame is saved in the stack. Interrupts are disabled. + Instruction encoded in CI instruction format. assembly: "" definedBy: anyOf: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml index efb32a214..b13f1854a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml @@ -5,6 +5,7 @@ qc.c.mileaveret: description: | Machine mode interrupt exit. Interrupt frame is restored from the stack. + Instruction encoded in CI instruction format. assembly: "" definedBy: anyOf: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml index 9523a5211..92a315d95 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml @@ -4,6 +4,7 @@ qc.c.mnret: long_name: Machine NMI Return description: | Returns from an NMI in M-mode. + Instruction encoded in CI instruction format. assembly: "" definedBy: Xqcipr access: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml index f1a0eda3c..c77721b0a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml @@ -4,6 +4,7 @@ qc.c.mret: long_name: Machine Exception Return description: | Returns from an exception in M-mode. + Instruction encoded in CI instruction format. assembly: "" definedBy: Xqcipr access: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml index a148ba06d..dee64c34b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml @@ -4,6 +4,7 @@ qc.c.muladdi: long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and an unsigned immediate + Instruction encoded in CL instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml index b53e950ca..0018f9307 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml @@ -4,6 +4,7 @@ qc.c.mveqz: long_name: Conditional Move if equal to zero description: | Move `rs1` to `rd` if `rd` == 0, keep `rd` value otherwise + Instruction encoded in CL instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml index 43707acba..1ce5a11d1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml @@ -4,6 +4,7 @@ qc.c.setint: long_name: Set interrupt (Register) description: | Set interrupt, interrupt number is in `rs1`. + Instruction encoded in CI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml index 9d370fe8b..2881c6b5a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml @@ -8,6 +8,7 @@ qc.clo: Accordingly, if the input is ~0, the output is XLEN, and if the most-significant bit of the input is a 0, the output is 0. output written to the `rd` + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml index 82c37a201..35ab46d99 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml @@ -4,6 +4,7 @@ qc.clrinti: long_name: Clear interrupt (Immediate) description: | Clear interrupt, interrupt number is in `imm` (0 - 1023). + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml index ece7ee6ab..5ee5320f1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml @@ -5,6 +5,7 @@ qc.compress2: description: | Bit compression (every 2nd bit) of `rs1`, zero-pad bits [31:16] of the result. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci @@ -28,4 +29,4 @@ qc.compress2: operation(): | XReg b0 = {X[rs1][14],X[rs1][12],X[rs1][10],X[rs1][8],X[rs1][6],X[rs1][4],X[rs1][2],X[rs1][0]}; XReg b1 = {X[rs1][30],X[rs1][28],X[rs1][26],X[rs1][24],X[rs1][22],X[rs1][20],X[rs1][18],X[rs1][16]}; - X[rd] = {16'b0,b1[7:0],b0[7:0]}; \ No newline at end of file + X[rd] = {16'b0,b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml index d50eda25c..d3cb468f6 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml @@ -5,6 +5,7 @@ qc.compress3: description: | Bit compression (every 3rd bit) of `rs1`, zero-pad bits [31:11] of the result. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci @@ -28,4 +29,4 @@ qc.compress3: operation(): | XReg b0 = {X[rs1][21],X[rs1][18],X[rs1][15],X[rs1][12],X[rs1][9],X[rs1][6],X[rs1][3],X[rs1][0]}; XReg b1 = {5'b0,X[rs1][30],X[rs1][27],X[rs1][24]}; - X[rd] = {21'b0,b1[2:0],b0[7:0]}; \ No newline at end of file + X[rd] = {21'b0,b1[2:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml index 2e340ecd2..61534aebb 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml @@ -10,11 +10,13 @@ qc.csrrwr: The initial value in `rs1` is written to the CSR. If `rd`=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci - Xqcicsr assembly: xd, xs1, xs2 + base: 32 encoding: match: 1000110----------000-----1110011 variables: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml index f22ba945a..0630327b2 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml @@ -10,11 +10,13 @@ qc.csrrwri: The 5-bit uimm field is zero-extended and written to the CSR. If `rd`=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci - Xqcicsr assembly: " xd, imm, xs2" + base: 32 encoding: match: 1000111----------000-----1110011 variables: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml index bb93dce36..618253d5a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml @@ -7,7 +7,8 @@ qc.cto: and progressing to the MSB. Accordingly, if the input is ~0, the output is XLEN, and if the least-significant bit of the input is a 0, the output is 0. - Output written to `rd` + Output written to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml index d555a9b43..545821091 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml @@ -4,6 +4,7 @@ qc.e.addai: long_name: Add immediate description: | Add a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml index 712a19a52..09c6ad3ac 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml @@ -5,6 +5,7 @@ qc.e.addi: description: | Add a sign-extended 26-bit immediate `imm` to the value in `rs1`, and store the result in `rd`. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml index a16a99183..17961fd8f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml @@ -4,6 +4,7 @@ qc.e.andai: long_name: And immediate description: | And a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml index b19099ab2..9545cb84d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml @@ -5,6 +5,7 @@ qc.e.andi: description: | And a sign-extended 26-bit immediate `imm` to the value in `rs1`, and store the result in `rd`. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml index 04873eb1b..cb436c36d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml @@ -4,6 +4,7 @@ qc.e.beqi: long_name: Branch on equal (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is equal to the signed immediate `imm` + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml index 1e54de03b..aaf0a0f1c 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml @@ -4,6 +4,7 @@ qc.e.bgei: long_name: Branch on greater than or equal (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is greater than or equal to the immediate `imm`. + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml index bb07feeaf..b8e9a2db1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml @@ -4,6 +4,7 @@ qc.e.bgeui: long_name: Branch on greater than or equal unsigned (immediate) description: | Branches to `PC` + `offset` if the unsigned value in `rs1` is greater than or equal to the unsigned immediate `imm`. + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml index 5a8a69580..c80927350 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml @@ -4,6 +4,7 @@ qc.e.blti: long_name: Branch on less than (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is less than the immediate `imm`. + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml index ef7f8bc39..61dfb0f6b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml @@ -4,6 +4,7 @@ qc.e.bltui: long_name: Branch on less than unsigned (immediate) description: | Branches to `PC` + `offset` if the unsigned value in `rs1` is less than the unsigned immediate `imm`. + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml index a6540436a..ae0b60cbf 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml @@ -4,6 +4,7 @@ qc.e.bnei: long_name: Branch on not equal (immediate) description: | Branches to `PC` + `offset` if the value in `rs1` is not equal to the signed immediate `imm`. + Instruction encoded in QC.EB instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml index 251ecf414..b5ad36972 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml @@ -3,7 +3,8 @@ qc.e.j: long_name: Jump description: | - Jump to a PC-relative offset + Jump to a PC-relative offset. + Instruction encoded in QC.EJ instruction format. definedBy: anyOf: - Xqci @@ -23,4 +24,4 @@ qc.e.j: vs: always vu: always operation(): | - jump_halfword($pc + imm); \ No newline at end of file + jump_halfword($pc + imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml index 5cdccbb16..13884d800 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml @@ -3,7 +3,8 @@ qc.e.jal: long_name: Jump and link description: | - Jump to a PC-relative offset and store the return + Jump to a PC-relative offset and store the return. + Instruction encoded in QC.EJ instruction format. address in x1. definedBy: anyOf: diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml index 1c06cd9a6..241e1393c 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml @@ -6,6 +6,7 @@ qc.e.lb: Load 8 bits of data into register `rd` from an address formed by adding `rs1` to a signed offset `imm`. Sign extend the result. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml index 26383d0d2..d72fcda50 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml @@ -6,6 +6,7 @@ qc.e.lbu: Load 8 bits of data into register `rd` from an address formed by adding `rs1` to a signed offset `imm`. Zero extend the result. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml index 31e93000b..4615a0fb2 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml @@ -6,6 +6,7 @@ qc.e.lh: Load 16 bits of data into register `rd` from an address formed by adding `rs1` to a signed offset `imm`. Sign extend the result. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml index 92b10a051..00e113663 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml @@ -6,6 +6,7 @@ qc.e.lhu: Load 16 bits of data into register `rd` from an address formed by adding `rs1` to a signed offset `imm`. Zero extend the result. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml index 28f47994a..4aab4cbe6 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml @@ -4,6 +4,7 @@ qc.e.li: long_name: Load immediate large description: | Loads the 32-bit immediate `imm` into `rd`. + Instruction encoded in QC.EAI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml index eabbf5b46..ed5625d25 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml @@ -6,6 +6,7 @@ qc.e.lw: Load 32 bits of data into register `rd` from an address formed by adding `rs1` to a signed offset `imm`. Sign extend the result. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml index fec85c557..f91cca29e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml @@ -4,6 +4,7 @@ qc.e.orai: long_name: Or immediate description: | Or a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml index 24fb92c24..5050786d8 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml @@ -5,6 +5,7 @@ qc.e.ori: description: | Or a sign-extended 26-bit immediate `imm` to the value in `rs1`, and store the result in `rd`. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml index cdb888cd9..d80178088 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml @@ -5,6 +5,7 @@ qc.e.sb: description: | Store 8 bits of data from register `rs2` to an address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml index 881aeb72f..4763870d1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml @@ -5,6 +5,7 @@ qc.e.sh: description: | Store 16 bits of data from register `rs2` to an address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml index a2dad3d43..ca82ce071 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml @@ -5,6 +5,7 @@ qc.e.sw: description: | Store 32 bits of data from register `rs2` to an address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml index 2d79140ac..bd9dd6436 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml @@ -4,6 +4,7 @@ qc.e.xorai: long_name: Exclusive Or immediate description: | Exclusive or a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml index 6510d9bea..e82f982e6 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml @@ -5,6 +5,7 @@ qc.e.xori: description: | Exclusive or a sign-extended 26-bit immediate `imm` to the value in `rs1`, and store the result in `rd`. + Instruction encoded in QC.EI instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml index e0d7e5009..0d383f181 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml @@ -5,6 +5,7 @@ qc.expand2: description: | Bit expansion (every 2nd bit) of `rs1`, bits [31:16] of `rs1` are ignored. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci @@ -30,4 +31,4 @@ qc.expand2: XReg b1 = {X[rs1][7],X[rs1][7],X[rs1][6],X[rs1][6],X[rs1][5],X[rs1][5],X[rs1][4],X[rs1][4]}; XReg b2 = {X[rs1][11],X[rs1][11],X[rs1][10],X[rs1][10],X[rs1][9],X[rs1][9],X[rs1][8],X[rs1][8]}; XReg b3 = {X[rs1][15],X[rs1][15],X[rs1][14],X[rs1][14],X[rs1][13],X[rs1][13],X[rs1][12],X[rs1][12]}; - X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; \ No newline at end of file + X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml index 6b97fe24f..fc2e91807 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml @@ -5,6 +5,7 @@ qc.expand3: description: | Bit expansion (every 3rd bit) of `rs1`, bits [31:11] of `rs1` are ignored. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci @@ -30,4 +31,4 @@ qc.expand3: XReg b1 = {X[rs1][5],X[rs1][4],X[rs1][4],X[rs1][4],X[rs1][3],X[rs1][3],X[rs1][3],X[rs1][2]}; XReg b2 = {X[rs1][7],X[rs1][7],X[rs1][7],X[rs1][6],X[rs1][6],X[rs1][6],X[rs1][5],X[rs1][5]}; XReg b3 = {X[rs1][10],X[rs1][10],X[rs1][9],X[rs1][9],X[rs1][9],X[rs1][8],X[rs1][8],X[rs1][8]}; - X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; \ No newline at end of file + X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml index 13d38ae33..45a365659 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml @@ -6,6 +6,7 @@ qc.ext: Extract a subset of bits from `rs1` into `rd`, and sign-extend the result. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml index 2100c46c3..fb48525b0 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml @@ -6,6 +6,7 @@ qc.extd: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset (into the pair) of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml index 682e518ea..0b4813b25 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml @@ -6,6 +6,7 @@ qc.extdpr: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml index 2cc1af974..eead67a9f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml @@ -6,6 +6,7 @@ qc.extdprh: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [23:16]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml index 96aada66f..e48d1fecb 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml @@ -6,6 +6,7 @@ qc.extdr: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml index 36af0bb02..49b702dc6 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml @@ -6,6 +6,7 @@ qc.extdu: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset (into the pair) of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml index c9ec8fd20..af868e572 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml @@ -6,6 +6,7 @@ qc.extdupr: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml index a0de345d4..b2816fa6f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml @@ -6,6 +6,7 @@ qc.extduprh: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [23:16]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml index a28c117e4..7359cc390 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml @@ -6,6 +6,7 @@ qc.extdur: Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml index ab926ebb9..ecf58a900 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml @@ -6,6 +6,7 @@ qc.extu: Extract a subset of bits from `rs1` into `rd`. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml index b3f20411a..1f084925b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml @@ -6,6 +6,7 @@ qc.insb: Insertion of a subset of bits from `rs1` into `rd`. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml index 5fdecb684..4c530794e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml @@ -11,6 +11,7 @@ qc.insbh: The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. In case when width + offset <= 32, the destination register is left unchanged. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml index 147bb1c4e..ad6002fe5 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml @@ -11,6 +11,7 @@ qc.insbhr: The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [15:0]. In case when width + offset <= 32, the destination register is left unchanged. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml index ac0e3afc4..cdd55e99d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml @@ -6,6 +6,7 @@ qc.insbi: Insertion of a subset of bits of an `imm` into `rd`. The width of the subset is determined by (`width_minus1` + 1) (1..32), and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml index 6f3da2380..a98bda7e3 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml @@ -6,6 +6,7 @@ qc.insbpr: Insertion of a subset of bits from `rs1` into `rd`. The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml index c04e2eb28..fe11a523b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml @@ -6,6 +6,7 @@ qc.insbprh: Insertion of a subset of bits from `rs1` into `rd`. The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [23:15]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml index 514336c5b..5e0c3971b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml @@ -6,6 +6,7 @@ qc.insbr: Insertion of a subset of bits from `rs1` into `rd`. The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml index f41fb3bd0..0aa22c7c9 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml @@ -6,6 +6,7 @@ qc.insbri: Insertion of a subset of bits of an `imm` into `rd`. The width of the subset is determined by `rs1` bits [31:16] + 1, and the offset of the subset is determined by `rs1` bits [15:0]. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml index 07f944840..c7758eb99 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml @@ -4,6 +4,7 @@ qc.li: long_name: Load immediate large description: | Loads the 20-bit immediate `imm` into `rd`. + Instruction encoded in U instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml index e0b2d1283..0ca3d8c7a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml @@ -3,7 +3,8 @@ qc.lieq: long_name: Conditional load immediate if equal (Register) description: | - Move `simm` to `rd` if the value in `rs1` is equal to value `rs2` + Move `simm` to `rd` if the value in `rs1` is equal to value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml index f681b122a..7b5d233cf 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml @@ -3,7 +3,8 @@ qc.lieqi: long_name: Conditional load immediate if equal (Immediate) description: | - Move `simm` to `rd` if the value in `rs1` is equal to value `imm` + Move `simm` to `rd` if the value in `rs1` is equal to value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml index c59cc0b36..ad90fcede 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml @@ -3,7 +3,8 @@ qc.lige: long_name: Conditional load immediate if great or equal than (Register) description: | - Move `simm` to `rd` if the value in `rs1` is great or equal than value `rs2` + Move `simm` to `rd` if the value in `rs1` is great or equal than value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml index 382e579e6..92ce3c2df 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml @@ -3,7 +3,8 @@ qc.ligei: long_name: Conditional load immediate if great or equal than (Immediate) description: | - Move `simm` to `rd` if the value in `rs1` is great or equal than value `imm` + Move `simm` to `rd` if the value in `rs1` is great or equal than value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml index 24b2dccc0..7690c1556 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml @@ -3,7 +3,8 @@ qc.ligeu: long_name: Conditional load immediate if great or equal than unsigned (Register) description: | - Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2` + Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml index 928f72b85..abd815cff 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml @@ -3,7 +3,8 @@ qc.ligeui: long_name: Conditional load immediate if great or equal than unsigned (Immediate) description: | - Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `imm` + Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml index 136ed5b97..94e8dab39 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml @@ -3,7 +3,8 @@ qc.lilt: long_name: Conditional load immediate if less than (Register) description: | - Move `simm` to `rd` if the value in `rs1` is less than value `rs2` + Move `simm` to `rd` if the value in `rs1` is less than value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml index 3e7659090..e115ec2ec 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml @@ -3,7 +3,8 @@ qc.lilti: long_name: Conditional load immediate if less than (Immediate) description: | - Move `simm` to `rd` if the value in `rs1` is less than value `imm` + Move `simm` to `rd` if the value in `rs1` is less than value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml index 143d58c51..dcbf9639b 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml @@ -3,7 +3,8 @@ qc.liltu: long_name: Conditional load immediate if less than unsigned (Register) description: | - Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2` + Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml index 0cc17a5e7..25d9da2b7 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml @@ -3,7 +3,8 @@ qc.liltui: long_name: Conditional load immediate if less than unsigned (Immediate) description: | - Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `imm` + Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml index 31269195a..a9159c58a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml @@ -3,7 +3,8 @@ qc.line: long_name: Conditional load immediate if not equal (Register) description: | - Move `simm` to `rd` if the value in `rs1` is not equal to value `rs2` + Move `simm` to `rd` if the value in `rs1` is not equal to value `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml index 338fd06a4..a90869a0e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml @@ -3,7 +3,8 @@ qc.linei: long_name: Conditional load immediate if not equal (Immediate) description: | - Move `simm` to `rd` if the value in `rs1` is not equal to value `imm` + Move `simm` to `rd` if the value in `rs1` is not equal to value `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml index 5f61b6759..46e53e581 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml @@ -6,6 +6,7 @@ qc.lrb: Load 8 bits of data into register `rd` from an address formed by adding `rs1` to `rs2`, shifted by `shamt`. Sign extend the result. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml index fda7f6c76..d81cd949f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml @@ -5,6 +5,7 @@ qc.lrbu: description: | Load 8 bits of data into register `rd` from an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml index 37cfd5bcc..09f1f7c96 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml @@ -6,6 +6,7 @@ qc.lrh: Load 16 bits of data into register `rd` from an address formed by adding `rs1` to `rs2`, shifted by `shamt`. Sign extend the result. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml index 1d6338e3e..e7fc6c704 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml @@ -5,6 +5,7 @@ qc.lrhu: description: | Load 16 bits of data into register `rd` from an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml index 86e0ecd9c..8d8b737bc 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml @@ -5,6 +5,7 @@ qc.lrw: description: | Load 32 bits of data into register `rd` from an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml index 08637ed24..642ead1ef 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml @@ -4,7 +4,8 @@ qc.lwm: long_name: Load word multiple description: | Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. - The number of words is in `rs2` + The number of words is in `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml index 22a3ed7f6..8478d4574 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml @@ -5,6 +5,7 @@ qc.lwmi: description: | Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. The number of words is in the `length` immediate. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml index e587df7b3..afcdcbb41 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml @@ -3,7 +3,8 @@ qc.muladdi: long_name: Multiply and accumulate (Immediate) description: | - Increments `rd` by the multiplication of `rs1` and a signed immediate `imm` + Increments `rd` by the multiplication of `rs1` and a signed immediate `imm`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml index 1e40de3dc..7adee48fd 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml @@ -3,7 +3,8 @@ qc.mveq: long_name: Conditional move if equal (Register) description: | - Move `rs3` to `rd` if the value in `rs1` is equal to value `rs2` + Move `rs3` to `rd` if the value in `rs1` is equal to value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml index bfdce877c..2ea4f49de 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml @@ -3,7 +3,8 @@ qc.mveqi: long_name: Conditional move if equal (Immediate) description: | - Move `rs3` to `rd` if the value in `rs1` is equal to value of `imm` + Move `rs3` to `rd` if the value in `rs1` is equal to value of `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml index a802fea9c..a0e0d5568 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml @@ -3,7 +3,8 @@ qc.mvge: long_name: Conditional move if great or equal than (Register) description: | - Move `rs3` to `rd` if the value in `rs1` is great or equal than value `rs2` + Move `rs3` to `rd` if the value in `rs1` is great or equal than value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml index ea54adc4e..012fe0af3 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml @@ -3,7 +3,8 @@ qc.mvgei: long_name: Conditional move if great or equal than (Immediate) description: | - Move `rs3` to `rd` if the value in `rs1` is great or equal than value of `imm` + Move `rs3` to `rd` if the value in `rs1` is great or equal than value of `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml index c48a42f67..22abbdfca 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml @@ -3,7 +3,8 @@ qc.mvgeu: long_name: Conditional move if great or equal than unsigned (Register) description: | - Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2` + Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml index b319de84a..612385d29 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml @@ -3,7 +3,8 @@ qc.mvgeui: long_name: Conditional move if great or equal than unsigned (Immediate) description: | - Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value of `imm` + Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value of `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml index 0310aa549..b78b23d0d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml @@ -3,7 +3,8 @@ qc.mvlt: long_name: Conditional move if less than (Register) description: | - Move `rs3` to `rd` if the value in `rs1` is less than value `rs2` + Move `rs3` to `rd` if the value in `rs1` is less than value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml index 2a127cd00..f5cef4a63 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml @@ -3,7 +3,8 @@ qc.mvlti: long_name: Conditional move if less than (Immediate) description: | - Move `rs3` to `rd` if the value in `rs1` is less than value of `imm` + Move `rs3` to `rd` if the value in `rs1` is less than value of `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml index 6c69241c6..c3bdce7e7 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml @@ -3,7 +3,8 @@ qc.mvltu: long_name: Conditional move if less than unsigned (Register) description: | - Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2` + Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml index ed9cae8f0..c633dbb10 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml @@ -3,7 +3,8 @@ qc.mvltui: long_name: Conditional move if less than unsigned (Immediate) description: | - Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value of `imm` + Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value of `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml index 2ed9d9f53..8a347044a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml @@ -3,7 +3,8 @@ qc.mvne: long_name: Conditional move if not equal (Register) description: | - Move `rs3` to `rd` if the value in `rs1` is not equal to value `rs2` + Move `rs3` to `rd` if the value in `rs1` is not equal to value `rs2`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml index 1827345ca..86995c60f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml @@ -3,7 +3,8 @@ qc.mvnei: long_name: Conditional move if not equal (Immediate) description: | - Move `rs3` to `rd` if the value in `rs1` is not equal to value `imm` + Move `rs3` to `rd` if the value in `rs1` is not equal to value `imm`. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml index ab20f585e..9c675cf3f 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml @@ -7,6 +7,7 @@ qc.norm: Exponent written in bits[7:0] of the result. Mantissa written in bits[31:8] of the result. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml index 484b8d9dc..c0eec0af1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml @@ -7,6 +7,7 @@ qc.normeu: Even exponent written in bits[7:0] of the result. Mantissa (based on even exponent) written in bits[31:8] of the result. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml index 55ab4a470..e4350d46d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml @@ -7,6 +7,7 @@ qc.normu: Exponent written in bits[7:0] of the result. Mantissa written in bits[31:8] of the result. Write result to `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml index 463853d43..d811c38ea 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml @@ -4,7 +4,8 @@ qc.selecteqi: long_name: Select load immediate or register if equal (Immediate) description: | Move `rs2` to `rd` if the value in `rd` is equal to value `imm`, - move `rs3` to `rd` otherwise + move `rs3` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml index 69d3e02f5..0273c9cf5 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml @@ -4,7 +4,8 @@ qc.selectieq: long_name: Select load immediate or register if equal (Register) description: | Move `rs2` to `rd` if the value in `rd` is equal to value `rs1`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml index 85120c815..499b07433 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml @@ -4,7 +4,8 @@ qc.selectieqi: long_name: Select load immediate or register if equal (Immediate) description: | Move `rs2` to `rd` if the value in `rd` is equal to value `imm`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml index 895781a00..80691ac68 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml @@ -4,7 +4,8 @@ qc.selectiieq: long_name: Select load immediate if equal (Register) description: | Move `simm1` to `rd` if the value in `rd` is equal to value `rs1`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml index ba0dedf6a..c6d462e5d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml @@ -4,7 +4,8 @@ qc.selectiine: long_name: Select load immediate if not equal (Register) description: | Move `simm1` to `rd` if the value in `rd` is not equal to value `rs1`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml index ee27d47bb..a0f26f92d 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml @@ -4,7 +4,8 @@ qc.selectine: long_name: Select load immediate or register if not equal (Register) description: | Move `rs2` to `rd` if the value in `rd` is not equal to value `rs1`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml index 19a875bb4..254ee7df4 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml @@ -4,7 +4,8 @@ qc.selectinei: long_name: Select load immediate or register if not equal (Immediate) description: | Move `rs2` to `rd` if the value in `rd` is not equal to value `imm`, - move `simm2` to `rd` otherwise + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml index 8867f3c9f..92b436883 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml @@ -4,7 +4,8 @@ qc.selectnei: long_name: Select load immediate or register if not equal (Immediate) description: | Move `rs2` to `rd` if the value in `rd` is not equal to value `imm`, - move `rs3` to `rd` otherwise + move `rs3` to `rd` otherwise. + Instruction encoded in R4 instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml index 92e66cda9..d7818eb17 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml @@ -4,6 +4,7 @@ qc.setinti: long_name: Set interrupt (Immediate) description: | Set interrupt, interrupt number is in `imm` (0 - 1023). + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml index 8c7177a4c..0ef7e78ee 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml @@ -5,6 +5,7 @@ qc.setwm: description: | Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). The number of writes is in `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml index 778b3c40f..ded59f997 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml @@ -5,6 +5,7 @@ qc.setwmi: description: | Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). The number of writes is in length. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml index 80caea6ae..05704bc10 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml @@ -4,6 +4,7 @@ qc.shladd: long_name: Shift left and add (immediate) description: | Left shift _rs1_ by _shamt_ and add the value in _rs2_. + Instruction encoded in R instruction format. definedBy: anyOf: - name: Xqci @@ -15,7 +16,7 @@ qc.shladd: variables: - name: shamt location: 29-25 - left_shift: 3 + not: [0,1,2,3] - name: rs2 location: 24-20 not: 0 diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml index 82e356bf9..1bd147212 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml @@ -5,6 +5,7 @@ qc.slasat: description: | Left shift `rs1` by the value of `rs2`, and saturate the signed result. The number of words is in `length`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml index 328d52ad4..b19b3bed5 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml @@ -5,6 +5,7 @@ qc.sllsat: description: | Left shift `rs1` by the value of `rs2`, and saturate the unsigned result. The number of words is in `length`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml index e3c7d85f9..08f8a4417 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml @@ -5,6 +5,7 @@ qc.srb: description: | Store 8 bits of data from register `rs3` to an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml index 9c907469d..a94293eb5 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml @@ -5,6 +5,7 @@ qc.srh: description: | Store 16 bits of data from register `rs3` to an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml index 774238a0b..957f2346a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml @@ -5,6 +5,7 @@ qc.srw: description: | Store 32 bits of data from register `rs3` to an address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml index 77b8ba24e..31a988b30 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml @@ -4,6 +4,7 @@ qc.subsat: long_name: Saturating signed subtraction description: | Subtract signed values `rs1` and `rs2`, saturate the signed result, and write to `rd`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml index 8f04c251c..5e44aceef 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml @@ -4,6 +4,7 @@ qc.subusat: long_name: Saturating unsigned subtraction description: | Subtract unsigned values `rs1` and `rs2`, saturate the unsigned result, and write to `rd`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml index 63180e6b6..0f8cd7602 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml @@ -5,6 +5,7 @@ qc.swm: description: | Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). The number of words is in `rs2`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml index 5fecdad43..b6587ad71 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml @@ -5,6 +5,7 @@ qc.swmi: description: | Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). The number of words is in `length` immediate. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml index 6cac9e532..57bdc045c 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml @@ -6,6 +6,7 @@ qc.wrap: If `rs1` >= `rs2` perform subtraction between `rs1` and `rs2`. If `rs1` < 0, perform addition between `rs1` and `rs2`, else, select `rs1`. The result is stored in `rd`. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci @@ -34,4 +35,4 @@ qc.wrap: ? rs1_value - X[rs2] : (($signed(rs1_value) < 0) ? (rs1_value + X[rs2]) - : rs1_value); \ No newline at end of file + : rs1_value); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml index d32f799c2..a96d7b718 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml @@ -6,6 +6,7 @@ qc.wrapi: If `rs1` >= `imm` perform subtraction between `rs1` and `imm`. If `rs1` < 0, perform addition between `rs1` and `imm`, else, select `rs1`. The result is stored in `rd`. + Instruction encoded in I instruction format. definedBy: anyOf: - Xqci @@ -34,4 +35,4 @@ qc.wrapi: ? rs1_value - imm : (($signed(rs1_value) < 0) ? (rs1_value + imm) - : rs1_value); \ No newline at end of file + : rs1_value); diff --git a/lib/arch_def.rb b/lib/arch_def.rb index 3374c9925..91e4875eb 100644 --- a/lib/arch_def.rb +++ b/lib/arch_def.rb @@ -348,7 +348,7 @@ def implemented_extensions @implemented_extensions = [] if @arch_def.key?("implemented_extensions") @arch_def["implemented_extensions"].each do |e| - @implemented_extensions << ExtensionVersion.new(e["name"], e["version"]) + @implemented_extensions << ExtensionVersion.new(e["name"], e["version"], self) end end @implemented_extensions diff --git a/lib/arch_obj_models/crd.rb b/lib/arch_obj_models/crd.rb index a83abd998..ec048c4e7 100644 --- a/lib/arch_obj_models/crd.rb +++ b/lib/arch_obj_models/crd.rb @@ -267,7 +267,7 @@ def all_in_scope_ext_params raise "There is no param '#{param_name}' in extension '#{ext_crd["name"]}" if param_db.nil? next unless ext_db.versions.any? do |ver| - Gem::Requirement.new(ext_crd["version"]).satisfied_by?(Gem::Version.new(ver["version"])) && + Gem::Requirement.new(ext_crd["version"]).satisfied_by?(ver.version) && param_db.defined_in_extension_version?(ver["version"]) end @@ -301,7 +301,7 @@ def in_scope_ext_params(ext_req) raise "There is no param '#{param_name}' in extension '#{ext_crd["name"]}" if ext_param_db.nil? next unless ext_db.versions.any? do |ver| - Gem::Requirement.new(ext_crd["version"]).satisfied_by?(Gem::Version.new(ver["version"])) && + Gem::Requirement.new(ext_crd["version"]).satisfied_by?(ver.version) && ext_param_db.defined_in_extension_version?(ver["version"]) end @@ -323,8 +323,8 @@ def all_out_of_scope_params next if all_in_scope_ext_params.any? { |c| c.param_db.name == param_db.name } next unless ext_db.versions.any? do |ver| - Gem::Requirement.new(ext_req.version_requirement).satisfied_by?(Gem::Version.new(ver["version"])) && - param_db.defined_in_extension_version?(ver["version"]) + Gem::Requirement.new(ext_req.version_requirement).satisfied_by?(ver.version) && + param_db.defined_in_extension_version?(ver.version) end @all_out_of_scope_params << param_db diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index 7dc5ee7a9..77613e8ee 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -536,10 +536,8 @@ def wavedrom_desc(arch_def, effective_xlen, exclude_unimplemented: false, option desc["reg"] << { "bits" => n, type: 1 } end if arch_def.partially_configured? && field.optional_in_cfg?(arch_def) - puts "#{name}.#{field.name} is OPTIONAL #{optional_type}" desc["reg"] << { "bits" => field.location(arch_def, effective_xlen).size, "name" => field.name, type: optional_type } else - puts "#{name}.#{field.name} is NOT OPTIONAL 3" desc["reg"] << { "bits" => field.location(arch_def, effective_xlen).size, "name" => field.name, type: 3 } end last_idx = field.location(arch_def, effective_xlen).max diff --git a/lib/arch_obj_models/extension.rb b/lib/arch_obj_models/extension.rb index f63b9f68b..1396767c0 100644 --- a/lib/arch_obj_models/extension.rb +++ b/lib/arch_obj_models/extension.rb @@ -138,7 +138,11 @@ def doc_license # @return [Array] versions hash from config def versions - @data["versions"] + return @versions unless @versions.nil? + + @versions = @data["versions"].map do |v| + ExtensionVersion.new(name, v["version"], arch_def) + end end # @return [Array] Ratified versions hash from config @@ -146,22 +150,22 @@ def ratified_versions @data["versions"].select { |v| v["state"] == "ratified" } end - # @return [String] Mimumum defined version of this extension + # @return [Gem::Version] Mimumum defined version of this extension def min_version - versions.map { |v| Gem::Version.new(v["version"]) }.min + versions.map { |v| v.version }.min end - # @return [String] Maximum defined version of this extension + # @return [Gem::Version] Maximum defined version of this extension def max_version - versions.map { |v| Gem::Version.new(v["version"]) }.max + versions.map { |v| v.version }.max end - # @return [String] Mimumum defined ratified version of this extension + # @return [Gem::Version] Mimumum defined ratified version of this extension # @return [nil] if there is no ratified version def min_ratified_version return nil if ratified_versions.empty? - ratified_versions.map { |v| Gem::Version.new(v["version"]) }.min + ratified_versions.map { |v| v.version }.min end # @return [Array] List of parameters added by this extension @@ -196,9 +200,9 @@ def implies(version_requirement = ">= 0") next when Array if v["implies"][0].is_a?(Array) - implications += v["implies"].map { |e| ExtensionVersion.new(e[0], e[1])} + implications += v["implies"].map { |e| ExtensionVersion.new(e[0], e[1], @arch_def)} else - implications << ExtensionVersion.new(v["implies"][0], v["implies"][1]) + implications << ExtensionVersion.new(v["implies"][0], v["implies"][1], @arch_def) end end end @@ -222,7 +226,7 @@ def instructions def csrs return @csrs unless @csrs.nil? - @csrs = arch_def.csrs.select { |csr| csr.defined_by?(ExtensionVersion.new(name, max_version)) } + @csrs = arch_def.csrs.select { |csr| csr.defined_by?(ExtensionVersion.new(name, max_version, @arch_def)) } end # @return [Array] the list of CSRs implemented by this extension (may be empty) @@ -232,7 +236,7 @@ def implemented_csrs(archdef) return @implemented_csrs unless @implemented_csrs.nil? @implemented_csrs = archdef.implemented_csrs.select do |csr| - versions.any? { |ver| csr.defined_by?(ExtensionVersion.new(name, ver["version"])) } + versions.any? { |ver| csr.defined_by?(ExtensionVersion.new(name, ver["version"], @arch_def)) } end end @@ -243,7 +247,7 @@ def implemented_instructions(archdef) return @implemented_instructions unless @implemented_instructions.nil? @implemented_instructions = archdef.implemented_instructions.select do |inst| - versions.any? { |ver| inst.defined_by?(ExtensionVersion.new(name, ver["version"])) } + versions.any? { |ver| inst.defined_by?(ExtensionVersion.new(name, ver["version"], @arch_def)) } end end @@ -297,23 +301,46 @@ class ExtensionVersion # @return [Gem::Version] Version of the extension attr_reader :version + # @return [Extension] Extension + attr_reader :ext # @param name [#to_s] The extension name # @param version [Integer,String] The version specifier # @param arch_def [ArchDef] The architecture definition - def initialize(name, version) + def initialize(name, version, arch_def) @name = name.to_s @version = Gem::Version.new(version) + @arch_def = arch_def + unless arch_def.nil? + @ext = arch_def.extension(@name) + raise "Extension #{name} not found in arch def" if @ext.nil? + + @data = @ext.data["versions"].find { |v| v["version"] == version.to_s } + raise "Extension #{name} version #{version} not found in arch def" if @data.nil? + end end - # @return Extension the extension object - def ext(arch_def) - arch_def.extension(name) + # @return [String] The state of the extension version ('ratified', 'developemnt', etc) + def state = @data["state"] + + def ratification_date = @data["ratification_date"] + + def changes = @data["changes"].nil? ? [] : @data["changes"] + + def url = @data["url"] + + def contributors + return @contributors unless @contributors.nil? + + @contributors = [] + @data["contributors"].each do |c| + @contributors << Person.new(c) + end end # @return [Array] The list of parameters for this extension version - def params(arch_def) - ext(arch_def).params.select { |p| p.defined_in_extension_version?(@version) } + def params + @ext.params.select { |p| p.defined_in_extension_version?(@version) } end def to_s @@ -337,6 +364,42 @@ def ==(other) end end + def requirements + r = case @data["requires"] + when nil + AlwaysTrueSchemaCondition.new + when Hash + SchemaCondition.new(@data["requires"]) + else + SchemaCondition.new({"oneOf" => [@data["requires"]]}) + end + if @data.key?("implies") + rs = [r] + implications.map { |e| e.requirements } + rs = rs.reject { |r| r.empty? } + unless rs.empty? + r = SchemaCondition.all_of(*rs.map { |r| r.to_h }) + end + end + r + end + + def implications + return @implications unless @implications.nil? + + @implications = [] + case @data["implies"] + when nil + return @implications + when Array + if @data["implies"][0].is_a?(Array) + @implications += @data["implies"].map { |e| ExtensionVersion.new(e[0], e[1], @arch_def)} + else + @implications << ExtensionVersion.new(@data["implies"][0], @data["implies"][1], @arch_def) + end + end + @implications + end + # @param ext_name [String] Extension name # @param ext_version_requirements [Number,String,Array] Extension version requirements, taking the same inputs as Gem::Requirement # @see https://docs.ruby-lang.org/en/3.0/Gem/Requirement.html#method-c-new Gem::Requirement#new @@ -418,7 +481,7 @@ def satisfying_versions(archdef) return [] if ext.nil? ext.versions.select { |v| @requirement.satisfied_by?(Gem::Version.new(v["version"])) }.map do |v| - ExtensionVersion.new(@name, v["version"]) + ExtensionVersion.new(@name, v["version"], archdef) end end diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb index 92c9a7640..8daaa54be 100644 --- a/lib/arch_obj_models/instruction.rb +++ b/lib/arch_obj_models/instruction.rb @@ -289,7 +289,7 @@ def pretty_name elsif excludes.size == 1 "#{name} != #{excludes[0]}" else - "#{name} != {#{excludes[0].join(',')}}" + "#{name} != {#{excludes.join(',')}}" end end diff --git a/lib/arch_obj_models/manual.rb b/lib/arch_obj_models/manual.rb index 049ed1c47..78df1c388 100644 --- a/lib/arch_obj_models/manual.rb +++ b/lib/arch_obj_models/manual.rb @@ -102,7 +102,7 @@ def extensions next end - @extensions << ExtensionVersion.new(ext[0], ext[1]) + @extensions << ExtensionVersion.new(ext[0], ext[1], arch_def) end @extensions end diff --git a/lib/arch_obj_models/obj.rb b/lib/arch_obj_models/obj.rb index 7ed012adb..6bf7b40e2 100644 --- a/lib/arch_obj_models/obj.rb +++ b/lib/arch_obj_models/obj.rb @@ -269,6 +269,10 @@ def initialize(composition_hash) @hsh = composition_hash end + def to_h = @hsh + + def empty? = false + VERSION_REQ_REGEX = /^((>=)|(>)|(~>)|(<)|(<=)|(=))?\s*[0-9]+(\.[0-9]+(\.[0-9]+(-[a-fA-F0-9]+)?)?)?$/ def is_a_version_requirement(ver) case ver @@ -351,6 +355,45 @@ def first_requirement(req = @hsh) end end + # combine all conds into one using AND + def self.all_of(*conds) + cond = SchemaCondition.new({ + "allOf" => conds + }) + + SchemaCondition.new(cond.minimize) + end + + # @return [Object] Schema for this condition, with basic logic minimization + def minimize(hsh = @hsh) + case hsh + when Hash + if hsh.key?("name") + hsh + else + min_ary = key = nil + if hsh.key?("allOf") + min_ary = hsh["allOf"].map { |element| minimize(element) } + key = "allOf" + elsif hsh.key?("anyOf") + min_ary = hsh["anyOf"].map { |element| minimize(element) } + key = "anyOf" + elsif hsh.key?("oneOf") + min_ary = hsh["oneOf"].map { |element| minimize(element) } + key = "oneOf" + end + min_ary = min_ary.uniq! + if min_ary.size == 1 + min_ary.first + else + { key => min_ary } + end + end + else + hsh + end + end + def to_rb_helper(hsh) if hsh.is_a?(Hash) if hsh.key?("name") @@ -428,4 +471,8 @@ class AlwaysTrueSchemaCondition def to_rb = "true" def satisfied_by? = true + + def empty? = true + + def to_h = {} end diff --git a/lib/resolver.rb b/lib/resolver.rb new file mode 100644 index 000000000..2427ff5b9 --- /dev/null +++ b/lib/resolver.rb @@ -0,0 +1,20 @@ +# given an architecture folder, resolves inheritance and expands some fields + +require "pathname" + +class Resolver + def initialize(arch_folder) + @dir = Pathname.new(arch_folder).realpath + end + + def resolve_all(output_folder) + Dir.glob(@dir / "**" / "*.yaml") do |f| + resolve(f, "#{output_folder}/#{f.gsub("#{@dir.to_s}/", "")}") + end + end + + def resolve(input_file, output_file) + obj = YamlLoader.load(input_file, permitted_classes: [Date]) + File.write(output_file, YAML::dump(obj)) + end +end \ No newline at end of file diff --git a/lib/yaml_resolver.py b/lib/yaml_resolver.py new file mode 100644 index 000000000..47e6c87f3 --- /dev/null +++ b/lib/yaml_resolver.py @@ -0,0 +1,131 @@ +import glob, os + +from copy import deepcopy +from tqdm import tqdm +from ruamel.yaml import YAML +from mergedeep import merge, Strategy + +OUT_DIR="arch_resolved" +UDB_ROOT=os.path.dirname(os.path.dirname(os.path.realpath(__file__))) + +yaml = YAML(typ="rt") +yaml.default_flow_style = False +yaml.preserve_quotes = True + + +def read_yaml(file_path): + with open(file_path, 'r') as file: + data = yaml.load(file) + return data + +def write_yaml(file_path, data): + with open(file_path, 'w') as file: + yaml.dump(data, file) + +def dig(obj, *keys): + if len(keys) == 0: + return obj + + try: + next_obj = obj[keys[0]] + if len(keys) == 1: + return next_obj + else: + return dig(next_obj, *keys[1:]) + except KeyError: + return None + +resolved_objs = {} +def resolve(path, rel_path, arch_root): + if path in resolved_objs: + return resolved_objs[path] + else: + unresolved_data = read_yaml(path) + resolved_objs[path] = _resolve(unresolved_data, [], rel_path, unresolved_data, arch_root) + return resolved_objs[path] + +def _resolve(obj, obj_path, obj_file_path, doc_obj, arch_root): + if not (isinstance(obj, list) or isinstance(obj, dict)): + return obj + + if isinstance(obj, list): + obj = list(map(lambda o: _resolve(o, obj_path, obj_file_path, doc_obj, arch_root), obj)) + return obj + + if "$inherits" in obj: + # handle the inherits key first so that any override will have priority + inherits_targets = [obj["$inherits"]] if isinstance(obj["$inherits"], str) else obj["$inherits"] + obj["$child_of"] = obj["$inherits"] + + new_obj = yaml.load("{}") + + for inherits_target in inherits_targets: + ref_file_path = inherits_target.split("#")[0] + ref_obj_path = inherits_target.split("#")[1].split("/")[1:] + + ref_obj = None + if ref_file_path == "": + ref_file_path = obj_file_path + # this is a reference in the same document + ref_obj = dig(doc_obj, *ref_obj_path) + if ref_obj == None: + raise ValueError(f"{ref_obj_path} cannot be found in #{doc_obj}") + ref_obj = _resolve(ref_obj, ref_obj_path, ref_file_path, doc_obj, arch_root) + else: + # this is a reference to another doc + if not os.path.exists(os.path.join(UDB_ROOT, arch_root, ref_file_path)): + raise ValueError(f"{ref_file_path} does not exist in {arch_root}/") + ref_file_full_path = os.path.join(UDB_ROOT, arch_root, ref_file_path) + + ref_doc_obj = resolve(ref_file_full_path, ref_file_path, arch_root) + ref_obj = dig(ref_doc_obj, *ref_obj_path) + + ref_obj = _resolve(ref_obj, ref_obj_path, ref_file_path, ref_doc_obj, arch_root) + + for key in ref_obj: + if isinstance(new_obj.get(key), dict): + merge(new_obj[key], ref_obj, strategy=Strategy.REPLACE) + else: + new_obj[key] = deepcopy(ref_obj[key]) + + print(f"{obj_file_path} {obj_path} inherits {ref_file_path} {ref_obj_path}") + ref_obj["$parent_of"] = f"{obj_file_path}#/{"/".join(obj_path)}" + + del obj["$inherits"] + + # now new_obj is the child and obj is the parent + # merge them + keys = [] + for key in obj.keys(): + keys.append(key) + for key in new_obj.keys(): + if keys.count(key) == 0: + keys.append(key) + + final_obj = yaml.load('{}') + for key in keys: + if not key in obj: + final_obj[key] = new_obj[key] + elif not key in new_obj: + final_obj[key] = _resolve(obj[key], obj_path + [key], obj_file_path, doc_obj, arch_root) + else: + if isinstance(new_obj[key], dict): + if not isinstance(new_obj[key], dict): + raise ValueError("should be a hash") + final_obj[key] = merge(yaml.load('{}'), new_obj[key], obj[key], strategy=Strategy.REPLACE) + else: + final_obj[key] = _resolve(obj[key], obj_path + [key], obj_file_path, doc_obj, arch_root) + + + return final_obj + else: + for key in obj: + obj[key] = _resolve(obj[key], obj_path + [key], obj_file_path, doc_obj, arch_root) + + return obj + +arch_paths = glob.glob("arch/**/*.yaml", recursive=True, root_dir=UDB_ROOT) +for arch_path in tqdm(arch_paths): + resolved_arch_path = f"{UDB_ROOT}/{OUT_DIR}/{arch_path}" + os.makedirs(os.path.dirname(resolved_arch_path), exist_ok=True) + write_yaml(resolved_arch_path, resolve(arch_path, os.path.join(*arch_path.split("/")[1:]), "arch")) diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 153cc96c1..5b184fcdf 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -40,7 +40,7 @@ }, "requirement_string": { "type": "string", - "pattern": "^((>=)|(>)|(~>)|(<)|(<=)|(=))?\\s*[0-9]+(\\.[0-9]+(\\.[0-9]+(-[a-fA-F0-9]+)?)?)?$" + "pattern": "^((>=)|(>)|(~>)|(<)|(<=)|(=))\\s*[0-9]+(\\.[0-9]+(\\.[0-9]+(-[a-fA-F0-9]+)?)?)?$" }, "version_requirements": { "description": "A (set of) version requirments",