diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index df2c5c28f..09efc1ea8 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -235,6 +235,11 @@ config MSM_REMOTE_SPINLOCK_SFPB config MSM_ADM3 bool +config MSM_MDP31 + bool + depends on ARCH_QSD8X50 + default y + config PERFLOCK depends on CPU_FREQ depends on ARCH_MSM8960 || ARCH_MSM8X60 || ARCH_QSD8X50 || ARCH_MSM7X30 || ARCH_MSM7X00A || ARCH_MSM7X27A || ARCH_MSM7X25 diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/arch/arm/mach-msm/include/mach/msm_fb.h index c9ae12900..ad6d1470b 100644 --- a/arch/arm/mach-msm/include/mach/msm_fb.h +++ b/arch/arm/mach-msm/include/mach/msm_fb.h @@ -18,13 +18,31 @@ #define _MSM_FB_H_ #include -#include +#include +#include +#include struct mddi_info; /* output interface format */ #define MSM_MDP_OUT_IF_FMT_RGB565 0 #define MSM_MDP_OUT_IF_FMT_RGB666 1 +#define MSM_MDP_OUT_IF_FMT_RGB888 2 + +/* mdp override operations */ +#define MSM_MDP_PANEL_IGNORE_PIXEL_DATA (1 << 0) +#define MSM_MDP_PANEL_FLIP_UD (1 << 1) +#define MSM_MDP_PANEL_FLIP_LR (1 << 2) +#define MSM_MDP4_MDDI_DMA_SWITCH (1 << 3) +#define MSM_MDP_DMA_PACK_ALIGN_LSB (1 << 4) +#define MSM_MDP_RGB_PANEL_SELF_REFRESH (1 << 5) + +/* mddi type */ +#define MSM_MDP_MDDI_TYPE_I 0 +#define MSM_MDP_MDDI_TYPE_II 1 + +/* lcdc override operations */ +#define MSM_MDP_LCDC_DMA_PACK_ALIGN_LSB (1 << 0) struct msm_fb_data { int xres; /* x resolution in pixels */ @@ -43,11 +61,29 @@ enum { MSM_MDDI_EMDH_INTERFACE, MSM_EBI2_INTERFACE, MSM_LCDC_INTERFACE, + MSM_TV_INTERFACE, - MSM_MDP_NUM_INTERFACES = MSM_LCDC_INTERFACE + 1, + MSM_MDP_NUM_INTERFACES = MSM_TV_INTERFACE + 1 }; #define MSMFB_CAP_PARTIAL_UPDATES (1 << 0) +#define MSMFB_CAP_CABC (1 << 1) + +struct msm_lcdc_timing { + unsigned int clk_rate; /* dclk freq */ + unsigned int hsync_pulse_width; /* in dclks */ + unsigned int hsync_back_porch; /* in dclks */ + unsigned int hsync_front_porch; /* in dclks */ + unsigned int hsync_skew; /* in dclks */ + unsigned int vsync_pulse_width; /* in lines */ + unsigned int vsync_back_porch; /* in lines */ + unsigned int vsync_front_porch; /* in lines */ + + /* control signal polarity */ + unsigned int vsync_act_low:1; + unsigned int hsync_act_low:1; + unsigned int den_act_low:1; +}; struct msm_panel_data { /* turns off the fb memory */ @@ -58,9 +94,15 @@ struct msm_panel_data { int (*blank)(struct msm_panel_data *); /* turns on the panel */ int (*unblank)(struct msm_panel_data *); + /* for msmfb shutdown() */ + int (*shutdown)(struct msm_panel_data *); void (*wait_vsync)(struct msm_panel_data *); void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *); void (*clear_vsync)(struct msm_panel_data *); + void (*dump_vsync)(void); + /* change timing on the fly */ + int (*adjust_timing)(struct msm_panel_data *, struct msm_lcdc_timing *, + u32 xres, u32 yres); /* from the enum above */ unsigned interface_type; /* data to be passed to the fb driver */ @@ -68,6 +110,33 @@ struct msm_panel_data { /* capabilities supported by the panel */ uint32_t caps; + /* + * For samsung driver IC, we always need to indicate where + * to draw. So we pass update_into to mddi client. + * + */ + struct { + int left; + int top; + int eright; /* exclusive */ + int ebottom; /* exclusive */ + } update_info; +}; + +enum { + MDP_DMA_P = 0, + MDP_DMA_S, +}; + +struct msm_mdp_platform_data { + /* from the enum above */ + int dma_channel; + unsigned overrides; + unsigned color_format; + int tearing_check; + unsigned sync_config; + unsigned sync_thresh; + unsigned sync_start_pos; }; struct msm_mddi_client_data { @@ -76,6 +145,8 @@ struct msm_mddi_client_data { void (*activate_link)(struct msm_mddi_client_data *); void (*remote_write)(struct msm_mddi_client_data *, uint32_t val, uint32_t reg); + void (*remote_write_vals)(struct msm_mddi_client_data *, uint8_t * val, + uint32_t reg, unsigned int nr_bytes); uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg); void (*auto_hibernate)(struct msm_mddi_client_data *, int); /* custom data that needs to be passed from the board file to a @@ -94,10 +165,11 @@ struct msm_mddi_platform_data { void (*fixup)(uint16_t *mfr_name, uint16_t *product_id); int vsync_irq; - + struct resource *fb_resource; /*optional*/ /* number of clients in the list that follows */ int num_clients; + unsigned type; /* array of client information of clients */ struct { unsigned product_id; /* mfr id in top 16 bits, product id @@ -120,27 +192,12 @@ struct msm_mddi_platform_data { } client_platform_data[]; }; -struct msm_lcdc_timing { - unsigned int clk_rate; /* dclk freq */ - unsigned int hsync_pulse_width; /* in dclks */ - unsigned int hsync_back_porch; /* in dclks */ - unsigned int hsync_front_porch; /* in dclks */ - unsigned int hsync_skew; /* in dclks */ - unsigned int vsync_pulse_width; /* in lines */ - unsigned int vsync_back_porch; /* in lines */ - unsigned int vsync_front_porch; /* in lines */ - - /* control signal polarity */ - unsigned int vsync_act_low:1; - unsigned int hsync_act_low:1; - unsigned int den_act_low:1; -}; - struct msm_lcdc_panel_ops { int (*init)(struct msm_lcdc_panel_ops *); int (*uninit)(struct msm_lcdc_panel_ops *); int (*blank)(struct msm_lcdc_panel_ops *); int (*unblank)(struct msm_lcdc_panel_ops *); + int (*shutdown)(struct msm_lcdc_panel_ops *); }; struct msm_lcdc_platform_data { @@ -149,10 +206,21 @@ struct msm_lcdc_platform_data { int fb_id; struct msm_fb_data *fb_data; struct resource *fb_resource; + unsigned overrides; +}; + +struct msm_tvenc_platform_data { + struct msm_tvenc_panel_ops *panel_ops; + int fb_id; + struct msm_fb_data *fb_data; + struct resource *fb_resource; + int (*video_relay)(int on_off); }; struct mdp_blit_req; struct fb_info; +struct mdp_overlay; +struct msmfb_overlay_data; struct mdp_device { struct device dev; void (*dma)(struct mdp_device *mdp, uint32_t addr, @@ -161,9 +229,60 @@ struct mdp_device { void (*dma_wait)(struct mdp_device *mdp, int interface); int (*blit)(struct mdp_device *mdp, struct fb_info *fb, struct mdp_blit_req *req); +#ifdef CONFIG_FB_MSM_OVERLAY + int (*overlay_get)(struct mdp_device *mdp, struct fb_info *fb, + struct mdp_overlay *req); + int (*overlay_set)(struct mdp_device *mdp, struct fb_info *fb, + struct mdp_overlay *req); + int (*overlay_unset)(struct mdp_device *mdp, struct fb_info *fb, + int ndx); + int (*overlay_play)(struct mdp_device *mdp, struct fb_info *fb, + struct msmfb_overlay_data *req, struct file **p_src_file); +#endif void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id); + void (*configure_dma)(struct mdp_device *mdp); int (*check_output_format)(struct mdp_device *mdp, int bpp); int (*set_output_format)(struct mdp_device *mdp, int bpp); + void (*set_panel_size)(struct mdp_device *mdp, int width, int height); + unsigned color_format; + unsigned overrides; + uint32_t width; /*panel width*/ + uint32_t height; /*panel height*/ +}; + +struct msmfb_info { + struct fb_info *fb; + struct msm_panel_data *panel; + int xres; + int yres; + unsigned output_format; + unsigned yoffset; + unsigned frame_requested; + unsigned frame_done; + int sleeping; + unsigned update_frame; + struct { + int left; + int top; + int eright; /* exclusive */ + int ebottom; /* exclusive */ + } update_info; + char *black; + struct early_suspend earlier_suspend; + struct early_suspend early_suspend; + struct wake_lock idle_lock; + spinlock_t update_lock; + struct mutex panel_init_lock; + wait_queue_head_t frame_wq; + struct workqueue_struct *resume_workqueue; + struct work_struct resume_work; + struct work_struct msmfb_resume_work; + struct msmfb_callback dma_callback; + struct msmfb_callback vsync_callback; + struct hrtimer fake_vsync; + ktime_t vsync_request_time; + unsigned fb_resumed; + struct ion_client *iclient; }; struct class_interface; @@ -171,6 +290,24 @@ int register_mdp_client(struct class_interface *class_intf); /**** private client data structs go below this line ***/ +/* + * Panel private data, include backlight stuff + * 9/28 09', Jay + * */ +struct panel_data { + int panel_id; + u32 caps; + int shrink; + /* backlight data */ + u8 *pwm; + int min_level; + /* default_br used in turn on backlight, must sync with setting in user space */ + int default_br; + int (*shrink_br)(int brightness); + int (*change_cabcmode)(struct msm_mddi_client_data *client_data, + int mode, u8 dimming); +}; + struct msm_mddi_bridge_platform_data { /* from board file */ int (*init)(struct msm_mddi_bridge_platform_data *, @@ -182,22 +319,27 @@ struct msm_mddi_bridge_platform_data { struct msm_mddi_client_data *); int (*unblank)(struct msm_mddi_bridge_platform_data *, struct msm_mddi_client_data *); + int (*shutdown)(struct msm_mddi_bridge_platform_data *, + struct msm_mddi_client_data *); struct msm_fb_data fb_data; - - /* board file will identify what capabilities the panel supports */ - uint32_t panel_caps; + struct panel_data panel_conf; + /* for those MDDI client which need to re-position display region + after each update or static electricity strike. It should be + implemented in board-xxx-panel due to the function itself need to + send the screen dimensional info of screen to MDDI client. + */ + void (*adjust)(struct msm_mddi_client_data *); +#define SAMSUNG_D 0 +#define SAMSUNG_S6 1 + int bridge_type; + int panel_type; + uint32_t caps; + /* backlight data */ + u8 *pwm; }; - -struct mdp_v4l2_req; -int msm_fb_v4l2_enable(struct mdp_overlay *req, bool enable, void **par); -int msm_fb_v4l2_update(void *par, - unsigned long srcp0_addr, unsigned long srcp0_size, - unsigned long srcp1_addr, unsigned long srcp1_size, - unsigned long srcp2_addr, unsigned long srcp2_size); - /* - * This is used to communicate event between msm_fb, mddi, mddi_client, + * This is used to communicate event between msm_fb, mddi, mddi_client, * and board. * It's mainly used to reset the display system. * Also, it is used for battery power policy. @@ -209,11 +351,24 @@ int msm_fb_v4l2_update(void *par, extern int register_display_notifier(struct notifier_block *nb); extern int display_notifier_call_chain(unsigned long val, void *data); - + #define display_notifier(fn, pri) { \ static struct notifier_block fn##_nb = \ { .notifier_call = fn, .priority = pri }; \ register_display_notifier(&fn##_nb); \ } +#if (defined(CONFIG_USB_FUNCTION_PROJECTOR) || defined(CONFIG_USB_ANDROID_PROJECTOR)) +/* For USB Projector to quick access the frame buffer info */ +struct msm_fb_info { + unsigned char *fb_addr; + int msmfb_area; + int xres; + int yres; +}; + +extern int msmfb_get_var(struct msm_fb_info *tmp); +extern int msmfb_get_fb_area(void); +#endif + #endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 888e906d0..a564a0324 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2380,36 +2380,7 @@ config FB_PUV3_UNIGFX Choose this option if you want to use the Unigfx device as a framebuffer device. Without the support of PCI & AGP. -if ARCH_MSM8X60 -# source "drivers/video/msm_8x60/Kconfig" -endif - -if ARCH_MSM7X30 && !FB_MSM_NEW - source "drivers/video/msm_7x30/Kconfig" -endif - -if FB_MSM_NEW - source "drivers/video/msm/Kconfig" -endif - -if (ARCH_MSM8960 || ARCH_MSM7X27A) -# source "drivers/video/msm/Kconfig" -endif - -config FB_MSM_NEW - bool - prompt "Use new CAF msm_fb stuff" - depends on ARCH_MSM7X30 - default n - -config FB_MSM_OVERLAY_LEGACY - bool - prompt "A small hack for ioctl backward compatible before ICS" - depends on FB_MSM_OVERLAY - default n if ARCH_MSM8960 - default n if ARCH_MSM8X60 - default n if ARCH_MSM7X30 - +source "drivers/video/msm/Kconfig" source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index af1ed296e..073eb5816 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -137,24 +137,7 @@ obj-y += omap2/ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o obj-$(CONFIG_FB_CARMINE) += carminefb.o obj-$(CONFIG_FB_MB862XX) += mb862xx/ - -ifeq ($(CONFIG_ARCH_MSM8960),y) - obj-$(CONFIG_FB_MSM) += msm/ -else - ifeq ($(CONFIG_ARCH_MSM8X60),y) - obj-$(CONFIG_FB_MSM) += msm_8x60/ - else - ifeq ($(CONFIG_ARCH_MSM7X27A),y) - obj-$(CONFIG_FB_MSM) += msm_7x27A/ - else - ifeq ($(CONFIG_FB_MSM_NEW),y) - obj-$(CONFIG_FB_MSM) += msm/ - else - obj-$(CONFIG_FB_MSM) += msm_7x30/ - endif - endif - endif -endif +obj-$(CONFIG_FB_MSM) += msm/ obj-$(CONFIG_FB_NUC900) += nuc900fb.o obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig index 41d36751d..259dbe1e5 100644 --- a/drivers/video/msm/Kconfig +++ b/drivers/video/msm/Kconfig @@ -1,1029 +1,50 @@ - -source "drivers/video/msm/vidc/Kconfig" - config FB_MSM - tristate "MSM Framebuffer support" + tristate "MSM Framebuffer" depends on FB && ARCH_MSM - select FB_BACKLIGHT if FB_MSM_BACKLIGHT - select NEW_LEDS - select LEDS_CLASS select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - ---help--- - Support for MSM Framebuffer. - -if FB_MSM - -config FB_MSM_BACKLIGHT - bool "Support for backlight control" default y - ---help--- - Say Y here if you want to control the backlight of your display. - -config FB_MSM_LOGO - bool "MSM Frame Buffer Logo" - default n - ---help--- - Show /initlogo.rle during boot. - -config FB_MSM_LCDC_HW - bool - default n - -config FB_MSM_TRIPLE_BUFFER - bool "Support for triple frame buffer" - default n - -config FB_MSM_MDP_HW - bool - default n - -choice - prompt "MDP HW version" - default FB_MSM_MDP22 - -config FB_MSM_MDP22 - select FB_MSM_MDP_HW - bool "MDP HW ver2.2" - ---help--- - Support for MSM MDP HW revision 2.2 - Say Y here if this is msm7201 variant platform. -config FB_MSM_MDP30 - select FB_MSM_LCDC_HW - bool "MDP HW ver3.0" - ---help--- - Support for MSM MDP HW revision 3.0 - Say Y here if this is msm7x25 variant platform. - -config FB_MSM_MDP303 - depends on FB_MSM_MDP30 - select FB_MSM_MDP_HW - bool "MDP HW ver3.03" - default n - ---help--- - Support for MSM MDP HW revision 3.03. This is a new version of - MDP3.0 which has the required functionality to support the features - required for msm7x2xA platform. - Say Y here if this is msm7x2xA variant platform. - -config FB_MSM_MDP31 - select FB_MSM_LCDC_HW - select FB_MSM_MDP_HW - bool "MDP HW ver3.1" - ---help--- - Support for MSM MDP HW revision 3.1 - Say Y here if this is msm8x50 variant platform. - -config FB_MSM_MDP40 - select FB_MSM_LCDC_HW - select FB_MSM_MDP_HW - bool "MDP HW ver4.0" - ---help--- - Support for MSM MDP HW revision 4.0 - Say Y here if this is msm7x30 variant platform. - -config FB_MSM_MDSS - bool "MDSS HW" - ---help--- - The Mobile Display Sub System (MDSS) driver supports devices which - contain MDSS hardware block. - - The MDSS driver implements frame buffer interface to provide access to - the display hardware and provide a way for users to display graphics - on connected display panels. - -config FB_MSM_MDP_NONE - bool "MDP HW None" - ---help--- - Say Y here if this is mdm platform. - -endchoice - -config FB_MSM_EBI2 - bool - default n - -config FB_MSM_MDDI - bool - default n +config FB_MSM_LEGACY_MDP + bool "MSM Legacy MDP (qsd8k)" + depends on FB_MSM && (MSM_MDP31 || MSM_MDP22) + default y -config FB_MSM_MIPI_DSI - bool - default n +config FB_MSM_MDP_PPP + bool "MSM MDP PPP" + depends on FB_MSM_LEGACY_MDP + default y config FB_MSM_LCDC - bool - default n - -config FB_MSM_LVDS - bool - default n - -config FB_MSM_OVERLAY - depends on FB_MSM_MDP40 && ANDROID_PMEM - bool "MDP4 overlay support" - default n - -config FB_MSM_DTV - depends on FB_MSM_OVERLAY - bool - default n - -config FB_MSM_EXTMDDI - bool - default n - -config FB_MSM_TVOUT - bool - default n - -config FB_MSM_MDDI_TOSHIBA_COMMON - bool - select FB_MSM_MDDI - default n - -config FB_MSM_MDDI_TOSHIBA_COMMON_VGA - bool - select FB_MSM_MDDI_TOSHIBA_COMMON - default n - -config FB_MSM_MDDI_ORISE - bool - select FB_MSM_MDDI - default n - -config FB_MSM_MDDI_QUICKVX - bool - select FB_MSM_MDDI - default n - -config FB_MSM_MDDI_AUTO_DETECT - bool - select FB_MSM_MDDI - default n - -config FB_MSM_LCDC_AUTO_DETECT - bool - select FB_MSM_LCDC - default n - -config FB_MSM_LCDC_PANEL - bool - select FB_MSM_LCDC - default n - -config FB_MSM_MIPI_DSI_TOSHIBA - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_LGIT - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_RENESAS - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_TRULY - bool - select FB_MSM_MIPI_DSI - -config FB_MSM_MIPI_DSI_SIMULATOR - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_NOVATEK - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_NT35510 - bool - select FB_MSM_MIPI_DSI - -config FB_MSM_MIPI_DSI_ORISE - bool - select FB_MSM_MIPI_DSI - default n - -config FB_MSM_MIPI_DSI_NT35516 - bool - select FB_MSM_MIPI_DSI - -config FB_MSM_MIPI_DSI_NT35590 - bool - select FB_MSM_MIPI_DSI - -config FB_MSM_MIPI_DSI_TC358764_DSI2LVDS - bool - select FB_MSM_MIPI_DSI - ---help--- - Support for Toshiba MIPI DSI-to-LVDS bridge. - The chip supports 1366x768 24-bit - using a single LVDS link - and up to WUXGA 1920x1200 18-bit - using a dual LVDS link. - -config FB_MSM_LCDC_ST15_WXGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_ST15_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC ST1.5 Panel" - select FB_MSM_LCDC_ST15_WXGA - ---help--- - Support for ST1.5 WXGA (1366x768) panel - -config FB_MSM_LCDC_PRISM_WVGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_SAMSUNG_WSVGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_CHIMEI_WXGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_GORDON_VGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_TOSHIBA_WVGA_PT - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_TOSHIBA_FWVGA_PT - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_SHARP_WVGA_PT - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_AUO_WVGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_TRULY_HVGA_IPS3P2335 - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_TRULY_HVGA_IPS3P2335_PT_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Truly HVGA PT Panel" - select FB_MSM_LCDC_TRULY_HVGA_IPS3P2335 - default n - ---help--- - Support for LCDC Truly HVGA PT panel - - -config FB_MSM_LCDC_SAMSUNG_OLED_PT - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_NT35582_WVGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_LCDC_WXGA - bool - select FB_MSM_LCDC_PANEL - default n - -config FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT - bool - select FB_MSM_MIPI_DSI_LGIT - default n - -config FB_MSM_LVDS_CHIMEI_WXGA - bool - select FB_MSM_LVDS - default n - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT - bool - select FB_MSM_MIPI_DSI_TOSHIBA - default n - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT - bool - select FB_MSM_MIPI_DSI_TOSHIBA - default n - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA - bool - select FB_MSM_MIPI_DSI_TOSHIBA - default n - -config FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT - bool - select FB_MSM_MIPI_DSI_NOVATEK - default n - -config FB_MSM_MIPI_NOVATEK_CMD_QHD_PT - bool - select FB_MSM_MIPI_DSI_NOVATEK - default n - -config FB_MSM_MIPI_ORISE_VIDEO_720P_PT - bool - select FB_MSM_MIPI_DSI_ORISE - default n - -config FB_MSM_MIPI_ORISE_CMD_720P_PT - bool - select FB_MSM_MIPI_DSI_ORISE - default n - -config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT - bool - select FB_MSM_MIPI_DSI_RENESAS - default n - -config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT - bool - select FB_MSM_MIPI_DSI_RENESAS - default n - -config FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT - bool - select FB_MSM_MIPI_DSI_NT35510 - default n - -config FB_MSM_MIPI_NT35510_CMD_WVGA_PT - bool - select FB_MSM_MIPI_DSI_NT35510 - default n - -config FB_MSM_MIPI_NT35516_VIDEO_QHD_PT - bool - select FB_MSM_MIPI_DSI_NT35516 - default n - -config FB_MSM_MIPI_NT35516_CMD_QHD_PT - bool - select FB_MSM_MIPI_DSI_NT35516 - default n - -config FB_MSM_MIPI_NT35590_CMD_720P_PT - bool - select FB_MSM_MIPI_DSI_NT35590 - default n - -config FB_MSM_MIPI_NT35590_VIDEO_720P_PT - bool - select FB_MSM_MIPI_DSI_NT35590 - default n - -config FB_MSM_MIPI_CHIMEI_WXGA - bool "LVDS Chimei WXGA Panel using Toshiba MIPI DSI-to-LVDS bridge." - select FB_MSM_MIPI_DSI_TC358764_DSI2LVDS - ---help--- - Support for Chimei WXGA (1366x768) panel. - The panel is using a serial LVDS input. - The panel is connected to the host - via Toshiba DSI-to-LVDS bridge. - -config FB_MSM_MIPI_CHIMEI_WUXGA - bool "LVDS Chimei WUXGA Panel using Toshiba MIPI DSI-to-LVDS bridge." - select FB_MSM_MIPI_DSI_TC358764_DSI2LVDS - ---help--- - Support for Chimei WUXGA (1920x1200) panel. - The panel is using a serial LVDS input. - The panel is connected to the host - via Toshiba DSI-to-LVDS bridge. - -config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT - bool - select FB_MSM_MIPI_DSI_TRULY - -config FB_MSM_MIPI_SIMULATOR_VIDEO - bool - select FB_MSM_MIPI_DSI_SIMULATOR - default n - -config FB_MSM_NO_MDP_PIPE_CTRL - depends on FB_MSM_OVERLAY - bool "Do not use mdp_pipe_ctrl" - ---help--- - Saying 'Y' here obsoletes the mdp_pipe_ctrl function, - which was used to control mdp-related clocks. MDP4 vsync-driven - screen updates will use a different clock control mechanism if - this is selected. - -config FB_MSM_OVERLAY0_WRITEBACK - depends on FB_MSM_OVERLAY - bool "MDP overlay0 write back mode enable" - ---help--- - Support for MDP4 OVERLAY0 write back mode - - -config FB_MSM_OVERLAY1_WRITEBACK - depends on FB_MSM_OVERLAY - bool "MDP overlay1 write back mode enable" - ---help--- - Support for MDP4 OVERLAY1 write back mode - -config FB_MSM_WRITEBACK_MSM_PANEL - depends on FB_MSM_OVERLAY - bool "MDP overlay write back panel enable" - ---help--- - Support for MDP4 OVERLAY write back mode -choice - prompt "LCD Panel" - default FB_MSM_MDDI_AUTO_DETECT - -config FB_MSM_VISION_PANEL - depends on FB_MSM_LCDC_HW && MACH_VISION - bool "LCDC Vision WVGA Panels" - select FB_MSM_LCDC_PANEL - ---help--- - Support for Vision WVGA (800x480) panels - -config FB_MSM_SAGA_PANEL - depends on FB_MSM_LCDC_HW && MACH_SAGA - bool "LCDC Saga WVGA Panels" - select FB_MSM_LCDC_PANEL - ---help--- - Support for Saga WVGA (800x480) panels - -config FB_MSM_SPADE_PANEL - depends on FB_MSM_LCDC_HW && MACH_SPADE - bool "LCDC Spade WVGA Panels" - select FB_MSM_LCDC_PANEL - ---help--- - Support for Spade WVGA (800x480) panels - -config FB_MSM_LCDC_PRISM_WVGA_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Prism WVGA Panel" - select FB_MSM_LCDC_PRISM_WVGA - ---help--- - Support for LCDC Prism WVGA (800x480) panel - -config FB_MSM_LCDC_SAMSUNG_WSVGA_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Samsung WSVGA Panel" - select FB_MSM_LCDC_SAMSUNG_WSVGA - ---help--- - Support for LCDC Samsung WSVGA (1024x600) panel - -config FB_MSM_LCDC_CHIMEI_WXGA_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Chimei WXGA Panel" - select FB_MSM_LCDC_CHIMEI_WXGA - ---help--- - Support for LCDC Chimei WXGA (1366x768) panel - -config FB_MSM_LCDC_GORDON_VGA_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Gordon VGA Panel" - select FB_MSM_LCDC_GORDON_VGA - ---help--- - Support for LCDC Gordon VGA (480x640) panel - -config FB_MSM_LCDC_TOSHIBA_WVGA_PT_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Toshiba WVGA PT Panel" - select FB_MSM_LCDC_TOSHIBA_WVGA_PT - ---help--- - Support for LCDC Toshiba WVGA PT (480x800) panel - -config FB_MSM_LCDC_TOSHIBA_FWVGA_PT_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Toshiba FWVGA PT Panel" - select FB_MSM_LCDC_TOSHIBA_FWVGA_PT - ---help--- - Support for LCDC Toshiba FWVGA PT (480x864) panel. This - configuration has to be selected to support the Toshiba - FWVGA (480x864) portrait panel. - -config FB_MSM_LCDC_SHARP_WVGA_PT_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Sharp WVGA PT Panel" - select FB_MSM_LCDC_SHARP_WVGA_PT - ---help--- - Support for LCDC Sharp WVGA PT (480x800) panel - -config FB_MSM_LCDC_AUO_WVGA_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC AUO WVGA Panel" - select FB_MSM_LCDC_AUO_WVGA - ---help--- - Support for LCDC AUO WVGA(480x800) panel - -config FB_MSM_LCDC_NT35582_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC NT35582 WVGA Panel" - select FB_MSM_LCDC_NT35582_WVGA - ---help--- - Support for LCDC NT35582 WVGA(480x800) panel - -config FB_MSM_LCDC_SAMSUNG_OLED_PT_PANEL - depends on FB_MSM_LCDC_HW - bool "LCDC Samsung OLED PT Panel" - select FB_MSM_LCDC_SAMSUNG_OLED_PT - ---help--- - Support for LCDC Samsung OLED PT (480x800) panel - -config FB_MSM_LVDS_CHIMEI_WXGA_PANEL - bool "LVDS Chimei WXGA Panel" - select FB_MSM_LVDS_CHIMEI_WXGA - ---help--- - Support for LVDS Chimei WXGA(1366x768) panel - -config FB_MSM_LVDS_FRC_FHD_PANEL - bool "LVDS FRC FHD Panel" - select FB_MSM_LVDS_FRC_FHD - ---help--- - Support for LVDS Frc FHD(1920x1080) panel - FRC(Frame Rate Converter) uses LVDS as input - interface. It is treated as a HDMI panel with - 1920x1080 resolution. - -config FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM - depends on FB_MSM_LCDC_HW - bool "MDDI Panel Auto Detect + LCDC Prism WVGA" - select FB_MSM_MDDI_AUTO_DETECT - select FB_MSM_LCDC_PRISM_WVGA - select FB_MSM_LCDC_GORDON_VGA - select FB_MSM_LCDC_WXGA - select FB_MSM_LCDC_TOSHIBA_WVGA_PT - select FB_MSM_LCDC_TOSHIBA_FWVGA_PT - select FB_MSM_LCDC_SHARP_WVGA_PT - select FB_MSM_LCDC_ST15_WXGA - ---help--- - Support for MDDI panel auto detect. - If it can't find any MDDI panel, it will load an LCDC panel. - -config FB_MSM_MIPI_PANEL_DETECT - bool "MIPI Panel Detect" - select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA - select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT - select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT - select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT - select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT - select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT - select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT - select FB_MSM_MIPI_NT35510_CMD_WVGA_PT - select FB_MSM_MIPI_ORISE_VIDEO_720P_PT - select FB_MSM_MIPI_ORISE_CMD_720P_PT - select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT - select FB_MSM_MIPI_NT35516_CMD_QHD_PT - select FB_MSM_MIPI_NT35590_CMD_720P_PT - select FB_MSM_MIPI_NT35590_VIDEO_720P_PT - select FB_MSM_MIPI_SIMULATOR_VIDEO - select FB_MSM_MIPI_CHIMEI_WXGA - select FB_MSM_MIPI_CHIMEI_WUXGA - ---help--- - Support for MIPI panel auto detect - -config FB_MSM_MDDI_PANEL_AUTO_DETECT - bool "MDDI Panel Auto Detect" - select FB_MSM_MDDI_AUTO_DETECT - ---help--- - Support for MDDI panel auto detect - -config FB_MSM_LCDC_PANEL_AUTO_DETECT - bool "LCDC Panel Auto Detect" - select FB_MSM_LCDC_AUTO_DETECT - select FB_MSM_LCDC_SAMSUNG_WSVGA - select FB_MSM_LCDC_AUO_WVGA - select FB_MSM_LCDC_NT35582_WVGA - select FB_MSM_LCDC_SAMSUNG_OLED_PT - ---help--- - Support for LCDC panel auto detect - -config FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT - bool "LCDC + MIPI Panel Auto Detect" - select FB_MSM_LCDC_AUTO_DETECT - select FB_MSM_LCDC_SAMSUNG_WSVGA - select FB_MSM_LCDC_AUO_WVGA - select FB_MSM_LCDC_SAMSUNG_OLED_PT - select FB_MSM_LCDC_NT35582_WVGA - select FB_MSM_LCDC_TOSHIBA_FWVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT - select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT - select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT - select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT - select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT - select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT - select FB_MSM_MIPI_NT35510_CMD_WVGA_PT - select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT - select FM_MSM_MIPI_NT35516_CMD_QHD_PT - select FM_MSM_MIPI_NT35590_CMD_720P_PT - select FM_MSM_MIPI_NT35590_VIDEO_720P_PT - select FB_MSM_MIPI_SIMULATOR_VIDEO - ---help--- - Support for LCDC + MIPI panel auto detect - -config FB_MSM_LVDS_MIPI_PANEL_DETECT - bool "LVDS + MIPI Panel Auto Detect" - select FB_MSM_LVDS_CHIMEI_WXGA - select FB_MSM_LVDS_FRC_FHD - select FB_MSM_MIPI_NT35590_VIDEO_720P_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT - select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA - select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT - select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT - select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT - select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT - select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT - select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT - select FB_MSM_MIPI_NT35510_CMD_WVGA_PT - select FB_MSM_MIPI_NT35590_CMD_720P_PT - select FB_MSM_MIPI_ORISE_VIDEO_720P_PT - select FB_MSM_MIPI_ORISE_CMD_720P_PT - select FB_MSM_MIPI_SIMULATOR_VIDEO - select FB_MSM_MIPI_CHIMEI_WXGA - select FB_MSM_MIPI_CHIMEI_WUXGA - ---help--- - Support for LVDS + MIPI panel auto detect - -config FB_MSM_MDDI_PRISM_WVGA - bool "MDDI Prism WVGA Panel" - select FB_MSM_MDDI - ---help--- - Support for MDDI Prism WVGA (800x480) panel - -config FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT - bool "MDDI Toshiba WVGA Portrait Panel" - select FB_MSM_MDDI_TOSHIBA_COMMON - ---help--- - Support for MDDI Toshiba WVGA (480x800) panel - -config FB_MSM_MDDI_TOSHIBA_VGA - bool "MDDI Toshiba VGA Panel" - select FB_MSM_MDDI_TOSHIBA_COMMON_VGA - ---help--- - Support for MDDI Toshiba VGA (480x640) and QCIF (176x220) panel - -config FB_MSM_MDDI_TOSHIBA_WVGA - bool "MDDI Toshiba WVGA panel" - select FB_MSM_MDDI_TOSHIBA_COMMON - ---help--- - Support for MDDI Toshiba (800x480) WVGA panel - -config FB_MSM_MDDI_SHARP_QVGA_128x128 - bool "MDDI Sharp QVGA Dual Panel" - select FB_MSM_MDDI - ---help--- - Support for MDDI Sharp QVGA (240x320) and 128x128 dual panel - -config FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT_PANEL - bool "MIPI LG Display WXGA PT Panel" - select FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT_PANEL - bool "MIPI Toshiba WVGA PT Panel" - select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT_PANEL - bool "MIPI Toshiba WSVGA PT Panel" - select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT - -config FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA_PANEL - bool "MIPI Toshiba WUXGA (1920x1200) Panel" - select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA - -config FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT_PANEL - bool "MIPI NOVATEK VIDEO QHD PT Panel" - select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT - -config FB_MSM_MIPI_NOVATEK_CMD_QHD_PT_PANEL - bool "MIPI NOVATEK CMD QHD PT Panel" - select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT - -config FB_MSM_MIPI_ORISE_VIDEO_720P_PT_PANEL - bool "MIPI ORISE VIDEO 720P PT Panel" - select FB_MSM_MIPI_ORISE_VIDEO_720P_PT - -config FB_MSM_MIPI_ORISE_CMD_720P_PT_PANEL - bool "MIPI ORISE CMD 720P PT Panel" - select FB_MSM_MIPI_ORISE_CMD_720P_PT - -config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT_PANEL - bool "MIPI Renesas Video FWVGA PT Panel" - select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT - -config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL - bool "MIPI Renesas Command FWVGA PT Panel" - select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT - -config FB_MSM_MIPI_CHIMEI_WXGA_PANEL - bool "MIPI Chimei WXGA PT Panel" - select FB_MSM_MIPI_CHIMEI_WXGA - -config FB_MSM_MIPI_CHIMEI_WUXGA_PANEL - bool "MIPI Chimei WUXGA Panel" - select FB_MSM_MIPI_CHIMEI_WUXGA - -config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT_PANEL - bool "MIPI Truly Video WVGA PT Panel" - select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT - -config FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT_PANEL - bool "MIPI NT35510 Video WVGA PT Panel" - select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT - -config FB_MSM_MIPI_NT35510_CMD_WVGA_PT_PANEL - bool "MIPI NT35510 Command WVGA PT Panel" - select FB_MSM_MIPI_NT35510_CMD_WVGA_PT - -config FB_MSM_MIPI_NT35516_VIDEO_QHD_PT_PANEL - bool "MIPI NT35516 Video qHD PT Panel" - select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT - -config FB_MSM_MIPI_NT35516_CMD_QHD_PT_PANEL - bool "MIPI NT35516 Command qHD PT Panel" - select FB_MSM_MIPI_NT35516_CMD_QHD_PT - -config FB_MSM_MIPI_NT35590_CMD_720P_PT_PANEL - bool "MIPI NT35590 Command 720p PT Panel" - select FB_MSM_MIPI_NT35590_CMD_720P_PT - ---help--- - Support for Truly NT35590 panel. This - panel supports MIPI DSI interface in - Command mode. The panel resolution is - 720p (720x1280). - -config FB_MSM_MIPI_NT35590_VIDEO_720P_PT_PANEL - bool "MIPI NT35590 Video 720p PT Panel" - select FB_MSM_MIPI_NT35590_VIDEO_720P_PT - ---help--- - Support for Truly NT35590 panel. This - panel supports MIPI DSI interface in - Video mode. The panel resolution is - 720p (720x1280). - -config FB_MSM_MIPI_SIMULATOR_VIDEO_PANEL - bool "MIPI Simulator Video Panel" - select FB_MSM_MIPI_SIMULATOR_VIDEO - -config FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF - bool "EBI2 TMD QVGA Epson QCIF Dual Panel" - select FB_MSM_EBI2 - ---help--- - Support for EBI2 TMD QVGA (240x320) and Epson QCIF (176x220) panel - -config FB_MSM_HDMI_AS_PRIMARY - depends on FB_MSM_HDMI_COMMON - bool "Use HDMI as primary panel" - ---help--- - Support for using HDMI as primary - -config FB_MSM_PANEL_NONE - bool "NONE" - ---help--- - This will disable LCD panel -endchoice - -config LGIT_VIDEO_WXGA_CABC - bool "Content Adaptive Backlight Control on LGIT WXGA Panel" + bool "Support for integrated LCD controller in MDP3/4" + depends on FB_MSM && (MSM_MDP31 || MSM_MDP40) default y - depends on FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT_PANEL - help - Enable CABC(Content Apaptive Backlight Control) on LGIT Panel - to reduce power consumption - -choice - prompt "Secondary LCD Panel" - depends on FB_MSM_MDP31 - default FB_MSM_SECONDARY_PANEL_NONE - -config FB_MSM_LCDC_EXTERNAL_WXGA - depends on FB_MSM_MDP31 - bool "External WXGA on LCDC" - select FB_MSM_LCDC_PANEL - ---help--- - Support for external WXGA display (1280x720) - -config FB_MSM_HDMI_SII_EXTERNAL_720P - depends on FB_MSM_MDP31 - bool "External SiI9022 HDMI 720P" - select FB_MSM_LCDC_PANEL - ---help--- - Support for external HDMI 720p display (1280x720p) - Using SiI9022 chipset - -config FB_MSM_SECONDARY_PANEL_NONE - bool "NONE" - ---help--- - No secondary panel -endchoice - -config FB_MSM_LCDC_DSUB - depends on FB_MSM_LCDC_SAMSUNG_WSVGA && FB_MSM_MDP40 && FB_MSM_LCDC_HW - bool "External DSUB support" - default n - ---help--- - Support for external DSUB (VGA) display up to 1440x900. The DSUB - display shares the same video bus as the primary LCDC attached display. - Typically only one of the two displays can be used at one time. - -config FB_MSM_EXT_INTERFACE_COMMON - bool - default n - -config FB_MSM_HDMI_COMMON - bool - default n - -config FB_MSM_HDMI_3D - bool - default n - -config FB_MSM_HDMI_ADV7520_PANEL - depends on FB_MSM_MDP40 && FB_MSM_OVERLAY - bool "LCDC HDMI ADV7520 720p Panel" - select FB_MSM_DTV - select FB_MSM_EXT_INTERFACE_COMMON - select FB_MSM_HDMI_COMMON - default n - ---help--- - Support for LCDC 720p HDMI panel attached to ADV7520 -config FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - depends on FB_MSM_HDMI_ADV7520_PANEL - bool "Use HDCP mode" - default y - ---help--- - Support for HDCP mode for ADV7520 HDMI 720p Panel - Choose to enable HDCP - - -config FB_MSM_HDMI_MSM_PANEL - depends on FB_MSM_MDP40 - bool "MSM HDMI 1080p Panel" - select FB_MSM_DTV - select FB_MSM_EXT_INTERFACE_COMMON - select FB_MSM_HDMI_COMMON - select FB_MSM_HDMI_3D - default n - ---help--- - Support for 480p/720p/1080i/1080p output through MSM HDMI - -config FB_MSM_HDMI_MSM_PANEL_DVI_SUPPORT - depends on FB_MSM_HDMI_MSM_PANEL - bool "Use DVI mode" - default n - ---help--- - Support for DVI mode for MSM HDMI 1080p Panel - -config FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT - depends on FB_MSM_HDMI_MSM_PANEL - bool "Enable CEC" - default n - ---help--- - Support for HDMI CEC Feature - Choose to enable CEC - -config FB_MSM_HDMI_MHL_9244 - depends on FB_MSM_HDMI_MSM_PANEL - bool 'SI_MHL 9244 support' - default n - ---help--- - Support the HDMI to MHL conversion. - MHL (Mobile High-Definition Link) technology - uses USB connector to output HDMI content +config FB_MSM_MDDI + bool "Support for MSM MDDI controllers" + depends on FB_MSM + default y -config FB_MSM_HDMI_MHL_8334 - depends on FB_MSM_HDMI_MSM_PANEL - bool 'SI_MHL 8334 support ' +config FB_MSM_MDDI_EPSON + bool "Support for Epson MDDI panels" + depends on FB_MSM_MDDI default n - ---help--- - Support the HDMI to MHL conversion. - MHL (Mobile High-Definition Link) technology - uses USB connector to output HDMI content - -choice - depends on (FB_MSM_MDP22 || FB_MSM_MDP31 || FB_MSM_MDP40) - prompt "TVOut Region" - default FB_MSM_TVOUT_NONE - -config FB_MSM_TVOUT_NTSC_M - bool "NTSC M" - select FB_MSM_TVOUT - select FB_MSM_EXT_INTERFACE_COMMON - ---help--- - Support for NTSC M region (North American and Korea) - -config FB_MSM_TVOUT_NTSC_J - bool "NTSC J" - select FB_MSM_TVOUT - select FB_MSM_EXT_INTERFACE_COMMON - ---help--- - Support for NTSC J region (Japan) -config FB_MSM_TVOUT_PAL_BDGHIN - bool "PAL BDGHIN" - select FB_MSM_TVOUT - select FB_MSM_EXT_INTERFACE_COMMON - ---help--- - Support for PAL BDGHIN region (Non-argentina PAL-N) - -config FB_MSM_TVOUT_PAL_M - bool "PAL M" - select FB_MSM_TVOUT - select FB_MSM_EXT_INTERFACE_COMMON - ---help--- - Support for PAL M region - -config FB_MSM_TVOUT_PAL_N - bool "PAL N" - select FB_MSM_TVOUT - select FB_MSM_EXT_INTERFACE_COMMON - ---help--- - Support for PAL N region (Argentina PAL-N) - -config FB_MSM_TVOUT_NONE - bool "NONE" - ---help--- - This will disable TV Out functionality. -endchoice - -config FB_MSM_TVOUT_SVIDEO - bool "TVOut on S-video" - depends on FB_MSM_TVOUT +config FB_MSM_MDDI_NOVTEC + bool "Support for Novtec MDDI panels" + depends on FB_MSM_MDDI default n - ---help--- - Selects whether the TVOut signal uses S-video. - Choose n for composite output. - -choice - depends on FB_MSM_MDP22 - prompt "External MDDI" - default FB_MSM_EXTMDDI_SVGA - -config FB_MSM_EXTMDDI_SVGA - bool "External MDDI SVGA" - select FB_MSM_MDDI - select FB_MSM_EXTMDDI - ---help--- - Support for MSM SVGA (800x600) external MDDI panel - -config FB_MSM_EXTMDDI_NONE - bool "NONE" - ---help--- - This will disable External MDDI functionality. -endchoice -choice - prompt "Default framebuffer color depth" - depends on FB_MSM_MDP40 || FB_MSM_MDP31 || FB_MSM_MDP303 - default FB_MSM_DEFAULT_DEPTH_RGBA8888 - -config FB_MSM_DEFAULT_DEPTH_RGB565 - bool "16 bits per pixel (RGB565)" - -config FB_MSM_DEFAULT_DEPTH_ARGB8888 - bool "32 bits per pixel (ARGB8888)" - -config FB_MSM_DEFAULT_DEPTH_RGBA8888 - bool "32 bits per pixel (RGBA8888)" - -endchoice - -config FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL - bool "EBI2 Epson QVGA Panel" - select FB_MSM_EBI2 +config MSM_HDMI + bool "Support for HDMI in QCT platform" + depends on MSM_MDP31 default n - ---help--- - Support for EBI2 Epson QVGA (240x320) panel -config FB_MSM_EBI2_PANEL_DETECT - bool "EBI2 Panel Detect" - select FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL - default n - ---help--- - Support for EBI2 panel auto detect +config FB_MSM_LOGO + bool "Use boot splashscreen" + depends on FB_MSM + default y + help + Use logo.rle splash screen at startup -if FB_MSM_MDSS - source "drivers/video/msm/mdss/Kconfig" -endif -endif diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile index b4d2acf2f..696960dba 100644 --- a/drivers/video/msm/Makefile +++ b/drivers/video/msm/Makefile @@ -1,205 +1,35 @@ -ifeq ($(CONFIG_FB_MSM_MDSS),y) -obj-y += mdss/ -else -obj-y := msm_fb.o - -obj-$(CONFIG_FB_MSM_LOGO) += logo.o -obj-$(CONFIG_FB_BACKLIGHT) += msm_fb_bl.o - -ifeq ($(CONFIG_FB_MSM_MDP_HW),y) -# MDP -obj-y += mdp.o - -obj-$(CONFIG_DEBUG_FS) += mdp_debugfs.o - -ifeq ($(CONFIG_FB_MSM_MDP40),y) -obj-y += mdp4_util.o -else -obj-y += mdp_hw_init.o -obj-y += mdp_ppp.o -ifeq ($(CONFIG_FB_MSM_MDP31),y) -obj-y += mdp_ppp_v31.o -else -obj-y += mdp_ppp_v20.o -endif -endif - -ifeq ($(CONFIG_FB_MSM_OVERLAY),y) -obj-y += mdp4_overlay.o -obj-$(CONFIG_FB_MSM_LCDC) += mdp4_overlay_lcdc.o -ifeq ($(CONFIG_FB_MSM_MIPI_DSI),y) -obj-y += mdp4_overlay_dsi_video.o -obj-y += mdp4_overlay_dsi_cmd.o -else -obj-$(CONFIG_FB_MSM_MDDI) += mdp4_overlay_mddi.o -endif -else -obj-y += mdp_dma_lcdc.o -endif - -obj-$(CONFIG_FB_MSM_MDP303) += mdp_dma_dsi_video.o - -ifeq ($(CONFIG_FB_MSM_DTV),y) -obj-y += mdp4_dtv.o -obj-y += mdp4_overlay_dtv.o -endif - -obj-y += mdp_dma.o -obj-y += mdp_dma_s.o -obj-y += mdp_vsync.o -obj-y += mdp_cursor.o -obj-y += mdp_dma_tv.o -obj-$(CONFIG_ARCH_MSM7X27A) += msm_dss_io_7x27a.o -obj-$(CONFIG_ARCH_MSM8X60) += msm_dss_io_8x60.o -obj-$(CONFIG_ARCH_MSM8960) += msm_dss_io_8960.o - -# EBI2 -obj-$(CONFIG_FB_MSM_EBI2) += ebi2_lcd.o -# LCDC -obj-$(CONFIG_FB_MSM_LCDC) += lcdc.o - -# LVDS -obj-$(CONFIG_FB_MSM_LVDS) += lvds.o - -# MDDI -msm_mddi-objs := mddi.o mddihost.o mddihosti.o -obj-$(CONFIG_FB_MSM_MDDI) += msm_mddi.o - -# External MDDI -msm_mddi_ext-objs := mddihost_e.o mddi_ext.o -obj-$(CONFIG_FB_MSM_EXTMDDI) += msm_mddi_ext.o - -# MIPI gereric -msm_mipi-objs := mipi_dsi.o mipi_dsi_host.o -obj-$(CONFIG_FB_MSM_MIPI_DSI) += msm_mipi.o - -# MIPI manufacture -obj-$(CONFIG_FB_MSM_MIPI_DSI_TOSHIBA) += mipi_toshiba.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_NOVATEK) += mipi_novatek.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_ORISE) += mipi_orise.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_RENESAS) += mipi_renesas.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_TRULY) += mipi_truly.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35510) += mipi_NT35510.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35516) += mipi_truly_tft540960_1_e.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35590) += mipi_NT35590.o -obj-$(CONFIG_FB_MSM_MIPI_DSI_SIMULATOR) += mipi_simulator.o - -# MIPI Bridge -obj-$(CONFIG_FB_MSM_MIPI_DSI_TC358764_DSI2LVDS) += mipi_tc358764_dsi2lvds.o - -# TVEnc -obj-$(CONFIG_FB_MSM_TVOUT) += tvenc.o -ifeq ($(CONFIG_FB_MSM_OVERLAY),y) -obj-$(CONFIG_FB_MSM_TVOUT) += mdp4_overlay_atv.o -endif - -# MSM FB Panel -obj-y += msm_fb_panel.o -obj-$(CONFIG_FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF) += ebi2_tmd20.o -obj-$(CONFIG_FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF) += ebi2_l2f.o - -ifeq ($(CONFIG_FB_MSM_MDDI_AUTO_DETECT),y) -obj-y += mddi_prism.o -obj-y += mddi_toshiba.o -obj-y += mddi_toshiba_vga.o -obj-y += mddi_toshiba_wvga_pt.o -obj-y += mddi_toshiba_wvga.o -obj-y += mddi_sharp.o -obj-y += mddi_orise.o -obj-y += mddi_quickvx.o -else -obj-$(CONFIG_FB_MSM_MDDI_PRISM_WVGA) += mddi_prism.o -obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_COMMON) += mddi_toshiba.o -obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_COMMON_VGA) += mddi_toshiba_vga.o -obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT) += mddi_toshiba_wvga_pt.o -obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA) += mddi_toshiba_wvga.o -obj-$(CONFIG_FB_MSM_MDDI_SHARP_QVGA_128x128) += mddi_sharp.o -obj-$(CONFIG_FB_MSM_MDDI_ORISE) += mddi_orise.o -obj-$(CONFIG_FB_MSM_MDDI_QUICKVX) += mddi_quickvx.o +# core framebuffer +# +obj-y := msm_fb.o +ifeq ($(CONFIG_FB_MSM_LOGO),y) +obj-y += logo.o endif -ifeq ($(CONFIG_FB_MSM_MIPI_PANEL_DETECT),y) -obj-y += mipi_toshiba_video_wvga_pt.o mipi_toshiba_video_wsvga_pt.o mipi_toshiba_video_wuxga.o -obj-y += mipi_novatek_video_qhd_pt.o mipi_novatek_cmd_qhd_pt.o -obj-y += mipi_orise_video_720p_pt.o mipi_orise_cmd_720p_pt.o -obj-y += mipi_renesas_video_fwvga_pt.o mipi_renesas_cmd_fwvga_pt.o -obj-y += mipi_NT35510_video_wvga_pt.o mipi_NT35510_cmd_wvga_pt.o -obj-y += mipi_truly_tft540960_1_e_video_qhd_pt.o mipi_truly_tft540960_1_e_cmd_qhd_pt.o -obj-y += mipi_NT35590_cmd_720p_pt.o mipi_NT35590_video_720p_pt.o -obj-y += mipi_chimei_wxga_pt.o -obj-y += mipi_chimei_wuxga.o -obj-y += mipi_truly_video_wvga_pt.o -else -obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT) += mipi_toshiba_video_wvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT) += mipi_toshiba_video_wsvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA) += mipi_toshiba_video_wuxga.o -obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT) += mipi_novatek_video_qhd_pt.o -obj-$(CONFIG_FB_MSM_MIPI_ORISE_VIDEO_720P_PT) += mipi_orise_video_720p_pt.o -obj-$(CONFIG_FB_MSM_MIPI_ORISE_CMD_720P_PT) += mipi_orise_cmd_720p_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT) += mipi_novatek_cmd_qhd_pt.o -obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT) += mipi_renesas_cmd_fwvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT) += mipi_truly_video_wvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35510_CMD_WVGA_PT) += mipi_NT35510_cmd_wvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT) += mipi_NT35510_video_wvga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35516_CMD_QHD_PT) += mipi_truly_tft540960_1_e_cmd_qhd_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35516_VIDEO_QHD_PT) += mipi_truly_tft540960_1_e_video_qhd_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35590_CMD_720P_PT) += mipi_NT35590_cmd_720p_pt.o -obj-$(CONFIG_FB_MSM_MIPI_NT35590_VIDEO_720P_PT) += mipi_NT35590_video_720p_pt.o -obj-$(CONFIG_FB_MSM_MIPI_SIMULATOR_VIDEO) += mipi_simulator_video.o -obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WXGA) += mipi_chimei_wxga_pt.o -obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WUXGA) += mipi_chimei_wuxga.o -endif +# MDP DMA/PPP engine +# +obj-y += mdp.o -obj-$(CONFIG_FB_MSM_LCDC_PANEL) += lcdc_panel.o -obj-$(CONFIG_FB_MSM_LCDC_PRISM_WVGA) += lcdc_prism.o -obj-$(CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA) += lcdc_samsung_wsvga.o -obj-$(CONFIG_FB_MSM_LCDC_CHIMEI_WXGA) += lcdc_chimei_wxga.o -obj-$(CONFIG_FB_MSM_LCDC_NT35582_WVGA) += lcdc_nt35582_wvga.o -obj-$(CONFIG_FB_MSM_LCDC_EXTERNAL_WXGA) += lcdc_external.o -obj-$(CONFIG_FB_MSM_HDMI_SII_EXTERNAL_720P) += hdmi_sii9022.o -obj-$(CONFIG_FB_MSM_LCDC_GORDON_VGA) += lcdc_gordon.o -obj-$(CONFIG_FB_MSM_LCDC_WXGA) += lcdc_wxga.o -obj-$(CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT) += lcdc_toshiba_wvga_pt.o -obj-$(CONFIG_FB_MSM_LCDC_TOSHIBA_FWVGA_PT) += lcdc_toshiba_fwvga_pt.o -obj-$(CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT) += lcdc_sharp_wvga_pt.o -obj-$(CONFIG_FB_MSM_LCDC_AUO_WVGA) += lcdc_auo_wvga.o -obj-$(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) += lcdc_samsung_oled_pt.o -obj-$(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) += adv7520.o -obj-$(CONFIG_FB_MSM_LCDC_ST15_WXGA) += lcdc_st15.o -obj-$(CONFIG_FB_MSM_LVDS_CHIMEI_WXGA) += lvds_chimei_wxga.o -obj-$(CONFIG_FB_MSM_LVDS_FRC_FHD) += lvds_frc_fhd.o -obj-$(CONFIG_FB_MSM_HDMI_MSM_PANEL) += hdmi_msm.o -obj-$(CONFIG_FB_MSM_EXT_INTERFACE_COMMON) += external_common.o -obj-$(CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335) += lcdc_truly_ips3p2335.o +obj-$(CONFIG_MSM_MDP40) += mdp_hw40.o -obj-$(CONFIG_FB_MSM_TVOUT) += tvout_msm.o +obj-$(CONFIG_FB_MSM_LEGACY_MDP) += mdp_hw_legacy.o -ccflags-y := -I$(src)/mhl -obj-$(CONFIG_FB_MSM_HDMI_MHL_8334) += mhl-8334.o -mhl-8334-objs += mhl/mhl_8334.o -mhl-8334-objs += mhl/mhl_i2c_utils.o +obj-$(CONFIG_FB_MSM_MDP_PPP) += mdp_ppp.o +obj-$(CONFIG_MSM_MDP22) += mdp_ppp22.o +obj-$(CONFIG_MSM_MDP31) += mdp_ppp31.o -obj-$(CONFIG_FB_MSM_EXTMDDI_SVGA) += mddi_ext_lcd.o +# MDDI interface +# +obj-$(CONFIG_FB_MSM_MDDI) += mddi.o -obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_wfd_writeback_panel.o -obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_wfd_writeback.o -obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_overlay_writeback.o -else -obj-$(CONFIG_FB_MSM_EBI2) += ebi2_host.o -obj-$(CONFIG_FB_MSM_EBI2) += ebi2_lcd.o -obj-y += msm_fb_panel.o -obj-$(CONFIG_FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL) += ebi2_epson_s1d_qvga.o -endif -endif +# MDDI client/panel drivers +# +obj-$(CONFIG_FB_MSM_MDDI) += mddi_client_simple.o +obj-$(CONFIG_FB_MSM_MDDI) += mddi_client_toshiba.o +obj-$(CONFIG_FB_MSM_MDDI_NOVTEC) += mddi_client_novb9f6_5582.o +obj-$(CONFIG_FB_MSM_MDDI_EPSON) += mddi_client_epson.o -obj-$(CONFIG_FB_MSM_SAGA_PANEL) += lcdc_sony_wvga.o -obj-$(CONFIG_FB_MSM_SPADE_PANEL) += lcdc_spade_wvga.o -obj-$(CONFIG_FB_MSM_VISION_PANEL) += lcdc_sony_wvga.o lcdc_samsung_s6e63m0_wvga.o lcdc_samsung_tl2796a_wvga.o +# MDP LCD controller driver +obj-$(CONFIG_FB_MSM_LCDC) += mdp_lcdc.o -obj-$(CONFIG_MSM_VIDC_1080P) += vidc/ -obj-$(CONFIG_MSM_VIDC_720P) += vidc/ -clean: - rm *.o .*cmd +obj-$(CONFIG_MSM_HDMI) += hdmi/ diff --git a/drivers/video/msm/adv7520.c b/drivers/video/msm/adv7520.c deleted file mode 100644 index 0e83d0fb5..000000000 --- a/drivers/video/msm/adv7520.c +++ /dev/null @@ -1,1035 +0,0 @@ -/* Copyright (c) 2010,2012, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "msm_fb.h" - -#define DEBUG -#define DEV_DBG_PREFIX "HDMI: " - -#include "external_common.h" - -/* #define PORT_DEBUG */ -/* #define TESTING_FORCE_480p */ - -#define HPD_DUTY_CYCLE 4 /*secs*/ - -static struct external_common_state_type hdmi_common; - -static struct i2c_client *hclient; -static struct clk *tv_enc_clk; - -static bool chip_power_on = FALSE; /* For chip power on/off */ -static bool enable_5v_on = FALSE; -static bool hpd_power_on = FALSE; -static atomic_t comm_power_on; /* For dtv power on/off (I2C) */ -static int suspend_count; - -static u8 reg[256]; /* HDMI panel registers */ - -struct hdmi_data { - struct msm_hdmi_platform_data *pd; - struct work_struct isr_work; -}; -static struct hdmi_data *dd; -static struct work_struct hpd_timer_work; - -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT -static struct work_struct hdcp_handle_work; -static int hdcp_activating; -static DEFINE_MUTEX(hdcp_state_mutex); -static int has_hdcp_hw_support = true; -#endif - -static struct timer_list hpd_timer; -static struct timer_list hpd_duty_timer; -static struct work_struct hpd_duty_work; -static unsigned int monitor_sense; -static boolean hpd_cable_chg_detected; - -static struct pm_qos_request pm_qos_req; - -/* Change HDMI state */ -static void change_hdmi_state(int online) -{ - if (!external_common_state) - return; - - mutex_lock(&external_common_state_hpd_mutex); - external_common_state->hpd_state = online; - mutex_unlock(&external_common_state_hpd_mutex); - - if (!external_common_state->uevent_kobj) - return; - - if (online) { - kobject_uevent(external_common_state->uevent_kobj, - KOBJ_ONLINE); - switch_set_state(&external_common_state->sdev, 1); - } else { - kobject_uevent(external_common_state->uevent_kobj, - KOBJ_OFFLINE); - switch_set_state(&external_common_state->sdev, 0); - } - DEV_INFO("adv7520_uevent: %d [suspend# %d]\n", online, suspend_count); -} - - -/* - * Read a value from a register on ADV7520 device - * If sucessfull returns value read , otherwise error. - */ -static u8 adv7520_read_reg(struct i2c_client *client, u8 reg) -{ - int err; - struct i2c_msg msg[2]; - u8 reg_buf[] = { reg }; - u8 data_buf[] = { 0 }; - - if (!client->adapter) - return -ENODEV; - if (!atomic_read(&comm_power_on)) { - DEV_WARN("%s: WARN: missing GPIO power\n", __func__); - return -ENODEV; - } - - msg[0].addr = client->addr; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = reg_buf; - - msg[1].addr = client->addr; - msg[1].flags = I2C_M_RD; - msg[1].len = 1; - msg[1].buf = data_buf; - - err = i2c_transfer(client->adapter, msg, 2); - - if (err < 0) { - DEV_INFO("%s: I2C err: %d\n", __func__, err); - return err; - } - -#ifdef PORT_DEBUG - DEV_INFO("HDMI[%02x] [R] %02x\n", reg, data); -#endif - return *data_buf; -} - -/* - * Write a value to a register on adv7520 device. - * Returns zero if successful, or non-zero otherwise. - */ -static int adv7520_write_reg(struct i2c_client *client, u8 reg, u8 val) -{ - int err; - struct i2c_msg msg[1]; - unsigned char data[2]; - - if (!client->adapter) - return -ENODEV; - if (!atomic_read(&comm_power_on)) { - DEV_WARN("%s: WARN: missing GPIO power\n", __func__); - return -ENODEV; - } - - msg->addr = client->addr; - msg->flags = 0; - msg->len = 2; - msg->buf = data; - data[0] = reg; - data[1] = val; - - err = i2c_transfer(client->adapter, msg, 1); - if (err >= 0) - return 0; -#ifdef PORT_DEBUG - DEV_INFO("HDMI[%02x] [W] %02x [%d]\n", reg, val, err); -#endif - return err; -} - -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT -static void adv7520_close_hdcp_link(void) -{ - if (!external_common_state->hdcp_active && !hdcp_activating) - return; - - DEV_INFO("HDCP: Close link\n"); - - reg[0xD5] = adv7520_read_reg(hclient, 0xD5); - reg[0xD5] &= 0xFE; - adv7520_write_reg(hclient, 0xD5, (u8)reg[0xD5]); - - reg[0x16] = adv7520_read_reg(hclient, 0x16); - reg[0x16] &= 0xFE; - adv7520_write_reg(hclient, 0x16, (u8)reg[0x16]); - - /* UnMute Audio */ - adv7520_write_reg(hclient, 0x0C, (u8)0x84); - - external_common_state->hdcp_active = FALSE; - mutex_lock(&hdcp_state_mutex); - hdcp_activating = FALSE; - mutex_unlock(&hdcp_state_mutex); -} - -static void adv7520_comm_power(int on, int show); -static void adv7520_hdcp_enable(struct work_struct *work) -{ - DEV_INFO("HDCP: Start reg[0xaf]=%02x (mute audio)\n", reg[0xaf]); - - adv7520_comm_power(1, 1); - - /* Mute Audio */ - adv7520_write_reg(hclient, 0x0C, (u8)0xC3); - - msleep(200); - /* Wait for BKSV ready interrupt */ - /* Read BKSV's keys from HDTV */ - reg[0xBF] = adv7520_read_reg(hclient, 0xBF); - reg[0xC0] = adv7520_read_reg(hclient, 0xC0); - reg[0xC1] = adv7520_read_reg(hclient, 0xC1); - reg[0xC2] = adv7520_read_reg(hclient, 0xC2); - reg[0xc3] = adv7520_read_reg(hclient, 0xC3); - - DEV_DBG("HDCP: BKSV={%02x,%02x,%02x,%02x,%02x}\n", reg[0xbf], reg[0xc0], - reg[0xc1], reg[0xc2], reg[0xc3]); - - /* Is SINK repeater */ - reg[0xBE] = adv7520_read_reg(hclient, 0xBE); - if (~(reg[0xBE] & 0x40)) { - ; /* compare with revocation list */ - /* Check 20 1's and 20 zero's */ - } else { - /* Don't implement HDCP if sink as a repeater */ - adv7520_write_reg(hclient, 0x0C, (u8)0x84); - mutex_lock(&hdcp_state_mutex); - hdcp_activating = FALSE; - mutex_unlock(&hdcp_state_mutex); - DEV_WARN("HDCP: Sink Repeater (%02x), (unmute audio)\n", - reg[0xbe]); - - adv7520_comm_power(0, 1); - return; - } - - msleep(200); - reg[0xB8] = adv7520_read_reg(hclient, 0xB8); - DEV_INFO("HDCP: Status reg[0xB8] is %02x\n", reg[0xb8]); - if (reg[0xb8] & 0x40) { - /* UnMute Audio */ - adv7520_write_reg(hclient, 0x0C, (u8)0x84); - DEV_INFO("HDCP: A/V content Encrypted (unmute audio)\n"); - external_common_state->hdcp_active = TRUE; - } - adv7520_comm_power(0, 1); - - mutex_lock(&hdcp_state_mutex); - hdcp_activating = FALSE; - mutex_unlock(&hdcp_state_mutex); -} -#endif - -static int adv7520_read_edid_block(int block, uint8 *edid_buf) -{ - u8 r = 0; - int ret; - struct i2c_msg msg[] = { - { .addr = reg[0x43] >> 1, - .flags = 0, - .len = 1, - .buf = &r }, - { .addr = reg[0x43] >> 1, - .flags = I2C_M_RD, - .len = 0x100, - .buf = edid_buf } }; - - if (block > 0) - return 0; - ret = i2c_transfer(hclient->adapter, msg, 2); - DEV_DBG("EDID block: addr=%02x, ret=%d\n", reg[0x43] >> 1, ret); - return (ret < 2) ? -ENODEV : 0; -} - -static void adv7520_read_edid(void) -{ - external_common_state->read_edid_block = adv7520_read_edid_block; - if (hdmi_common_read_edid()) { - u8 timeout; - DEV_INFO("%s: retry\n", __func__); - adv7520_write_reg(hclient, 0xc9, 0x13); - msleep(500); - timeout = (adv7520_read_reg(hclient, 0x96) & (1 << 2)); - if (timeout) { - hdmi_common_read_edid(); - } - } -} - -static void adv7520_chip_on(void) -{ - if (!chip_power_on) { - /* Get the current register holding the power bit. */ - unsigned long reg0xaf = adv7520_read_reg(hclient, 0xaf); - - dd->pd->core_power(1, 1); - - /* Set the HDMI select bit. */ - set_bit(1, ®0xaf); - DEV_INFO("%s: turn on chip power\n", __func__); - adv7520_write_reg(hclient, 0x41, 0x10); - adv7520_write_reg(hclient, 0xaf, (u8)reg0xaf); - chip_power_on = TRUE; - } else - DEV_INFO("%s: chip already has power\n", __func__); -} - -static void adv7520_chip_off(void) -{ - if (chip_power_on) { -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (has_hdcp_hw_support) - adv7520_close_hdcp_link(); -#endif - - DEV_INFO("%s: turn off chip power\n", __func__); - adv7520_write_reg(hclient, 0x41, 0x50); - dd->pd->core_power(0, 1); - chip_power_on = FALSE; - } else - DEV_INFO("%s: chip is already off\n", __func__); - - monitor_sense = 0; - hpd_cable_chg_detected = FALSE; - - if (enable_5v_on) { - dd->pd->enable_5v(0); - enable_5v_on = FALSE; - } -} - -/* Power ON/OFF ADV7520 chip */ -static void adv7520_isr_w(struct work_struct *work); -static void adv7520_comm_power(int on, int show) -{ - if (!on) - atomic_dec(&comm_power_on); - dd->pd->comm_power(on, 0/*show*/); - if (on) - atomic_inc(&comm_power_on); -} - -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT -static void adv7520_start_hdcp(void); -#endif -static int adv7520_power_on(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd = platform_get_drvdata(pdev); - - clk_prepare_enable(tv_enc_clk); - external_common_state->dev = &pdev->dev; - if (mfd != NULL) { - DEV_INFO("adv7520_power: ON (%dx%d %d)\n", - mfd->var_xres, mfd->var_yres, mfd->var_pixclock); - hdmi_common_get_video_format_from_drv_data(mfd); - } - - adv7520_comm_power(1, 1); - /* Check if HPD is signaled */ - if (adv7520_read_reg(hclient, 0x42) & (1 << 6)) { - DEV_INFO("power_on: cable detected\n"); - monitor_sense = adv7520_read_reg(hclient, 0xC6); -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (has_hdcp_hw_support) { - if (!hdcp_activating) - adv7520_start_hdcp(); - } -#endif - } else - DEV_INFO("power_on: cable NOT detected\n"); - adv7520_comm_power(0, 1); - pm_qos_update_request(&pm_qos_req, msm_cpuidle_get_deep_idle_latency()); - - return 0; -} - -static int adv7520_power_off(struct platform_device *pdev) -{ - DEV_INFO("power_off\n"); - adv7520_comm_power(1, 1); - adv7520_chip_off(); - pm_qos_update_request(&pm_qos_req, PM_QOS_DEFAULT_VALUE); - adv7520_comm_power(0, 1); - clk_disable_unprepare(tv_enc_clk); - return 0; -} - - -/* AV7520 chip specific initialization */ -static void adv7520_chip_init(void) -{ - /* Initialize the variables used to read/write the ADV7520 chip. */ - memset(®, 0xff, sizeof(reg)); - - /* Get the values from the "Fixed Registers That Must Be Set". */ - reg[0x98] = adv7520_read_reg(hclient, 0x98); - reg[0x9c] = adv7520_read_reg(hclient, 0x9c); - reg[0x9d] = adv7520_read_reg(hclient, 0x9d); - reg[0xa2] = adv7520_read_reg(hclient, 0xa2); - reg[0xa3] = adv7520_read_reg(hclient, 0xa3); - reg[0xde] = adv7520_read_reg(hclient, 0xde); - - /* Get the "HDMI/DVI Selection" register. */ - reg[0xaf] = adv7520_read_reg(hclient, 0xaf); - - /* Read Packet Memory I2C Address */ - reg[0x45] = adv7520_read_reg(hclient, 0x45); - - /* Hard coded values provided by ADV7520 data sheet. */ - reg[0x98] = 0x03; - reg[0x9c] = 0x38; - reg[0x9d] = 0x61; - reg[0xa2] = 0x94; - reg[0xa3] = 0x94; - reg[0xde] = 0x88; - - /* Set the HDMI select bit. */ - reg[0xaf] |= 0x16; - - /* Set the audio related registers. */ - reg[0x01] = 0x00; - reg[0x02] = 0x2d; - reg[0x03] = 0x80; - reg[0x0a] = 0x4d; - reg[0x0b] = 0x0e; - reg[0x0c] = 0x84; - reg[0x0d] = 0x10; - reg[0x12] = 0x00; - reg[0x14] = 0x00; - reg[0x15] = 0x20; - reg[0x44] = 0x79; - reg[0x73] = 0x01; - reg[0x76] = 0x00; - - /* Set 720p display related registers */ - reg[0x16] = 0x00; - - reg[0x18] = 0x46; - reg[0x55] = 0x00; - reg[0x3c] = 0x04; - - /* Set Interrupt Mask register for HPD/HDCP */ - reg[0x94] = 0xC0; -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (has_hdcp_hw_support) - reg[0x95] = 0xC0; - else - reg[0x95] = 0x00; -#else - reg[0x95] = 0x00; -#endif - adv7520_write_reg(hclient, 0x94, reg[0x94]); - adv7520_write_reg(hclient, 0x95, reg[0x95]); - - /* Set Packet Memory I2C Address */ - reg[0x45] = 0x74; - - /* Set the values from the "Fixed Registers That Must Be Set". */ - adv7520_write_reg(hclient, 0x98, reg[0x98]); - adv7520_write_reg(hclient, 0x9c, reg[0x9c]); - adv7520_write_reg(hclient, 0x9d, reg[0x9d]); - adv7520_write_reg(hclient, 0xa2, reg[0xa2]); - adv7520_write_reg(hclient, 0xa3, reg[0xa3]); - adv7520_write_reg(hclient, 0xde, reg[0xde]); - - /* Set the "HDMI/DVI Selection" register. */ - adv7520_write_reg(hclient, 0xaf, reg[0xaf]); - - /* Set EDID Monitor address */ - reg[0x43] = 0x7E; - adv7520_write_reg(hclient, 0x43, reg[0x43]); - - /* Enable the i2s audio input. */ - adv7520_write_reg(hclient, 0x01, reg[0x01]); - adv7520_write_reg(hclient, 0x02, reg[0x02]); - adv7520_write_reg(hclient, 0x03, reg[0x03]); - adv7520_write_reg(hclient, 0x0a, reg[0x0a]); - adv7520_write_reg(hclient, 0x0b, reg[0x0b]); - adv7520_write_reg(hclient, 0x0c, reg[0x0c]); - adv7520_write_reg(hclient, 0x0d, reg[0x0d]); - adv7520_write_reg(hclient, 0x12, reg[0x12]); - adv7520_write_reg(hclient, 0x14, reg[0x14]); - adv7520_write_reg(hclient, 0x15, reg[0x15]); - adv7520_write_reg(hclient, 0x44, reg[0x44]); - adv7520_write_reg(hclient, 0x73, reg[0x73]); - adv7520_write_reg(hclient, 0x76, reg[0x76]); - - /* Enable 720p display */ - adv7520_write_reg(hclient, 0x16, reg[0x16]); - adv7520_write_reg(hclient, 0x18, reg[0x18]); - adv7520_write_reg(hclient, 0x55, reg[0x55]); - adv7520_write_reg(hclient, 0x3c, reg[0x3c]); - - /* Set Packet Memory address to avoid conflict - with Bosch Accelerometer */ - adv7520_write_reg(hclient, 0x45, reg[0x45]); - - /* Ensure chip is in low-power state */ - adv7520_write_reg(hclient, 0x41, 0x50); -} - -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT -static void adv7520_start_hdcp(void) -{ - mutex_lock(&hdcp_state_mutex); - if (hdcp_activating) { - DEV_WARN("adv7520_timer: HDCP already" - " activating, skipping\n"); - mutex_unlock(&hdcp_state_mutex); - return; - } - hdcp_activating = TRUE; - mutex_unlock(&hdcp_state_mutex); - - del_timer(&hpd_duty_timer); - - adv7520_comm_power(1, 1); - - if (!enable_5v_on) { - dd->pd->enable_5v(1); - enable_5v_on = TRUE; - adv7520_chip_on(); - } - - /* request for HDCP */ - reg[0xaf] = adv7520_read_reg(hclient, 0xaf); - reg[0xaf] |= 0x90; - adv7520_write_reg(hclient, 0xaf, reg[0xaf]); - reg[0xaf] = adv7520_read_reg(hclient, 0xaf); - - reg[0xba] = adv7520_read_reg(hclient, 0xba); - reg[0xba] |= 0x10; - adv7520_write_reg(hclient, 0xba, reg[0xba]); - reg[0xba] = adv7520_read_reg(hclient, 0xba); - adv7520_comm_power(0, 1); - - DEV_INFO("HDCP: reg[0xaf]=0x%02x, reg[0xba]=0x%02x, waiting for BKSV\n", - reg[0xaf], reg[0xba]); - - /* will check for HDCP Error or BKSV ready */ - mod_timer(&hpd_duty_timer, jiffies + HZ/2); -} -#endif - -static void adv7520_hpd_timer_w(struct work_struct *work) -{ - if (!external_common_state->hpd_feature_on) { - DEV_INFO("adv7520_timer: skipping, feature off\n"); - return; - } - - if ((monitor_sense & 0x4) && !external_common_state->hpd_state) { - int timeout; - DEV_DBG("adv7520_timer: Cable Detected\n"); - adv7520_comm_power(1, 1); - adv7520_chip_on(); - - if (hpd_cable_chg_detected) { - hpd_cable_chg_detected = FALSE; - /* Ensure 5V to read EDID */ - if (!enable_5v_on) { - dd->pd->enable_5v(1); - enable_5v_on = TRUE; - } - msleep(500); - timeout = (adv7520_read_reg(hclient, 0x96) & (1 << 2)); - if (timeout) { - DEV_DBG("adv7520_timer: EDID-Ready..\n"); - adv7520_read_edid(); - } else - DEV_DBG("adv7520_timer: EDID TIMEOUT (C9=%02x)" - "\n", adv7520_read_reg(hclient, 0xC9)); - } -#ifdef TESTING_FORCE_480p - external_common_state->disp_mode_list.num_of_elements = 1; - external_common_state->disp_mode_list.disp_mode_list[0] = - HDMI_VFRMT_720x480p60_16_9; -#endif - adv7520_comm_power(0, 1); -#ifndef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - /* HDMI_5V_EN not needed anymore */ - if (enable_5v_on) { - DEV_DBG("adv7520_timer: EDID done, no HDCP, 5V not " - "needed anymore\n"); - dd->pd->enable_5v(0); - enable_5v_on = FALSE; - } -#endif - change_hdmi_state(1); - } else if (external_common_state->hpd_state) { - adv7520_comm_power(1, 1); - adv7520_chip_off(); - adv7520_comm_power(0, 1); - DEV_DBG("adv7520_timer: Cable Removed\n"); - change_hdmi_state(0); - } -} - -static void adv7520_hpd_timer_f(unsigned long data) -{ - schedule_work(&hpd_timer_work); -} - -static void adv7520_isr_w(struct work_struct *work) -{ - static int state_count; - static u8 last_reg0x96; - u8 reg0xc8; - u8 reg0x96; -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - static u8 last_reg0x97; - u8 reg0x97 = 0; -#endif - if (!external_common_state->hpd_feature_on) { - DEV_DBG("adv7520_irq: skipping, hpd off\n"); - return; - } - - adv7520_comm_power(1, 1); - reg0x96 = adv7520_read_reg(hclient, 0x96); -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (has_hdcp_hw_support) { - reg0x97 = adv7520_read_reg(hclient, 0x97); - /* Clearing the Interrupts */ - adv7520_write_reg(hclient, 0x97, reg0x97); - } -#endif - /* Clearing the Interrupts */ - adv7520_write_reg(hclient, 0x96, reg0x96); - - if ((reg0x96 == 0xC0) || (reg0x96 & 0x40)) { -#ifdef DEBUG - unsigned int hpd_state = adv7520_read_reg(hclient, 0x42); -#endif - monitor_sense = adv7520_read_reg(hclient, 0xC6); - DEV_DBG("adv7520_irq: reg[0x42]=%02x && reg[0xC6]=%02x\n", - hpd_state, monitor_sense); - - if (!enable_5v_on) { - dd->pd->enable_5v(1); - enable_5v_on = TRUE; - } - if (!hpd_power_on) { - dd->pd->core_power(1, 1); - hpd_power_on = TRUE; - } - - /* Timer for catching interrupt debouning */ - DEV_DBG("adv7520_irq: Timer in .5sec\n"); - hpd_cable_chg_detected = TRUE; - mod_timer(&hpd_timer, jiffies + HZ/2); - } -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (has_hdcp_hw_support) { - if (hdcp_activating) { - /* HDCP controller error Interrupt */ - if (reg0x97 & 0x80) { - DEV_ERR("adv7520_irq: HDCP_ERROR\n"); - state_count = 0; - adv7520_close_hdcp_link(); - /* BKSV Ready interrupts */ - } else if (reg0x97 & 0x40) { - DEV_INFO("adv7520_irq: BKSV keys ready, Begin" - " HDCP encryption\n"); - state_count = 0; - schedule_work(&hdcp_handle_work); - } else if (++state_count > 2 && (monitor_sense & 0x4)) { - DEV_INFO("adv7520_irq: Still waiting for BKSV," - "restart HDCP\n"); - hdcp_activating = FALSE; - state_count = 0; - adv7520_chip_off(); - adv7520_start_hdcp(); - } - reg0xc8 = adv7520_read_reg(hclient, 0xc8); - DEV_INFO("adv7520_irq: DDC controller reg[0xC8]=0x%02x," - "state_count=%d, monitor_sense=%x\n", - reg0xc8, state_count, monitor_sense); - } else if (!external_common_state->hdcp_active - && (monitor_sense & 0x4)) { - DEV_INFO("adv7520_irq: start HDCP with" - " monitor sense\n"); - state_count = 0; - adv7520_start_hdcp(); - } else - state_count = 0; - if (last_reg0x97 != reg0x97 || last_reg0x96 != reg0x96) - DEV_DBG("adv7520_irq: reg[0x96]=%02x " - "reg[0x97]=%02x: HDCP: %d\n", reg0x96, reg0x97, - external_common_state->hdcp_active); - last_reg0x97 = reg0x97; - } else { - if (last_reg0x96 != reg0x96) - DEV_DBG("adv7520_irq: reg[0x96]=%02x\n", reg0x96); - } -#else - if (last_reg0x96 != reg0x96) - DEV_DBG("adv7520_irq: reg[0x96]=%02x\n", reg0x96); -#endif - last_reg0x96 = reg0x96; - adv7520_comm_power(0, 1); -} - -static void adv7520_hpd_duty_work(struct work_struct *work) -{ - if (!external_common_state->hpd_feature_on) { - DEV_WARN("%s: hpd feature is off, skipping\n", __func__); - return; - } - - dd->pd->core_power(1, 0); - msleep(10); - adv7520_isr_w(NULL); - dd->pd->core_power(0, 0); -} - -static void adv7520_hpd_duty_timer_f(unsigned long data) -{ - if (!external_common_state->hpd_feature_on) { - DEV_WARN("%s: hpd feature is off, skipping\n", __func__); - return; - } - - mod_timer(&hpd_duty_timer, jiffies + HPD_DUTY_CYCLE*HZ); - schedule_work(&hpd_duty_work); -} - -static const struct i2c_device_id adv7520_id[] = { - { ADV7520_DRV_NAME , 0}, - {} -}; - -static struct msm_fb_panel_data hdmi_panel_data = { - .on = adv7520_power_on, - .off = adv7520_power_off, -}; - -static struct platform_device hdmi_device = { - .name = ADV7520_DRV_NAME , - .id = 2, - .dev = { - .platform_data = &hdmi_panel_data, - } -}; - -static void adv7520_ensure_init(void) -{ - static boolean init_done; - if (!init_done) { - int rc = dd->pd->init_irq(); - if (rc) { - DEV_ERR("adv7520_init: init_irq: %d\n", rc); - return; - } - - init_done = TRUE; - } - DEV_INFO("adv7520_init: chip init\n"); - adv7520_comm_power(1, 1); - adv7520_chip_init(); - adv7520_comm_power(0, 1); -} - -static int adv7520_hpd_feature(int on) -{ - int rc = 0; - - if (!on) { - if (enable_5v_on) { - dd->pd->enable_5v(0); - enable_5v_on = FALSE; - } - if (hpd_power_on) { - dd->pd->core_power(0, 1); - hpd_power_on = FALSE; - } - - DEV_DBG("adv7520_hpd: %d: stop duty timer\n", on); - del_timer(&hpd_timer); - del_timer(&hpd_duty_timer); - external_common_state->hpd_state = 0; - } - - if (on) { - dd->pd->core_power(1, 0); - adv7520_ensure_init(); - - adv7520_comm_power(1, 1); - monitor_sense = adv7520_read_reg(hclient, 0xC6); - DEV_DBG("adv7520_irq: reg[0xC6]=%02x\n", monitor_sense); - adv7520_comm_power(0, 1); - dd->pd->core_power(0, 0); - - if (monitor_sense & 0x4) { - if (!enable_5v_on) { - dd->pd->enable_5v(1); - enable_5v_on = TRUE; - } - if (!hpd_power_on) { - dd->pd->core_power(1, 1); - hpd_power_on = TRUE; - } - - hpd_cable_chg_detected = TRUE; - mod_timer(&hpd_timer, jiffies + HZ/2); - } - - DEV_DBG("adv7520_hpd: %d start duty timer\n", on); - mod_timer(&hpd_duty_timer, jiffies + HZ/100); - } - - DEV_INFO("adv7520_hpd: %d\n", on); - return rc; -} - -static int __devinit - adv7520_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - int rc; - struct platform_device *fb_dev; - - dd = kzalloc(sizeof *dd, GFP_KERNEL); - if (!dd) { - rc = -ENOMEM; - goto probe_exit; - } - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) - return -ENODEV; - - external_common_state->dev = &client->dev; - - /* Init real i2c_client */ - hclient = client; - - i2c_set_clientdata(client, dd); - dd->pd = client->dev.platform_data; - if (!dd->pd) { - rc = -ENODEV; - goto probe_free; - } - - INIT_WORK(&dd->isr_work, adv7520_isr_w); - INIT_WORK(&hpd_timer_work, adv7520_hpd_timer_w); -#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT - if (dd->pd->check_hdcp_hw_support) - has_hdcp_hw_support = dd->pd->check_hdcp_hw_support(); - - if (has_hdcp_hw_support) - INIT_WORK(&hdcp_handle_work, adv7520_hdcp_enable); - else - DEV_INFO("%s: no hdcp hw support.\n", __func__); -#endif - - init_timer(&hpd_timer); - hpd_timer.function = adv7520_hpd_timer_f; - hpd_timer.data = (unsigned long)NULL; - hpd_timer.expires = 0xffffffff; - add_timer(&hpd_timer); - - external_common_state->hpd_feature = adv7520_hpd_feature; - DEV_INFO("adv7520_probe: HPD detection on request\n"); - init_timer(&hpd_duty_timer); - hpd_duty_timer.function = adv7520_hpd_duty_timer_f; - hpd_duty_timer.data = (unsigned long)NULL; - hpd_duty_timer.expires = 0xffffffff; - add_timer(&hpd_duty_timer); - INIT_WORK(&hpd_duty_work, adv7520_hpd_duty_work); - DEV_INFO("adv7520_probe: HPD detection ON (duty)\n"); - - fb_dev = msm_fb_add_device(&hdmi_device); - - if (fb_dev) { - rc = external_common_state_create(fb_dev); - if (rc) - goto probe_free; - } else - DEV_ERR("adv7520_probe: failed to add fb device\n"); - - if (hdmi_prim_display) - external_common_state->sdev.name = "hdmi_as_primary"; - else - external_common_state->sdev.name = "hdmi"; - - if (switch_dev_register(&external_common_state->sdev) < 0) - DEV_ERR("Hdmi switch registration failed\n"); - - return 0; - -probe_free: - kfree(dd); - dd = NULL; -probe_exit: - return rc; - -} - -static int __devexit adv7520_remove(struct i2c_client *client) -{ - if (!client->adapter) { - DEV_ERR("%s: No HDMI Device\n", __func__); - return -ENODEV; - } - switch_dev_unregister(&external_common_state->sdev); - pm_qos_remove_request(&pm_qos_req); - kfree(dd); - dd = NULL; - return 0; -} - -#ifdef CONFIG_SUSPEND -static int adv7520_i2c_suspend(struct device *dev) -{ - DEV_INFO("%s\n", __func__); - - ++suspend_count; - - if (external_common_state->hpd_feature_on) { - DEV_DBG("%s: stop duty timer\n", __func__); - del_timer(&hpd_duty_timer); - del_timer(&hpd_timer); - } - - /* Turn off LDO8 and go into low-power state */ - if (chip_power_on) { - DEV_DBG("%s: turn off power\n", __func__); - adv7520_comm_power(1, 1); - adv7520_write_reg(hclient, 0x41, 0x50); - adv7520_comm_power(0, 1); - dd->pd->core_power(0, 1); - } - - return 0; -} - -static int adv7520_i2c_resume(struct device *dev) -{ - DEV_INFO("%s\n", __func__); - - /* Turn on LDO8 and go into normal-power state */ - if (chip_power_on) { - DEV_DBG("%s: turn on power\n", __func__); - dd->pd->core_power(1, 1); - adv7520_comm_power(1, 1); - adv7520_write_reg(hclient, 0x41, 0x10); - adv7520_comm_power(0, 1); - } - - if (external_common_state->hpd_feature_on) { - DEV_DBG("%s: start duty timer\n", __func__); - mod_timer(&hpd_duty_timer, jiffies + HPD_DUTY_CYCLE*HZ); - } - - return 0; -} -#else -#define adv7520_i2c_suspend NULL -#define adv7520_i2c_resume NULL -#endif - -static const struct dev_pm_ops adv7520_device_pm_ops = { - .suspend = adv7520_i2c_suspend, - .resume = adv7520_i2c_resume, -}; - -static struct i2c_driver hdmi_i2c_driver = { - .driver = { - .name = ADV7520_DRV_NAME, - .owner = THIS_MODULE, - .pm = &adv7520_device_pm_ops, - }, - .probe = adv7520_probe, - .id_table = adv7520_id, - .remove = __devexit_p(adv7520_remove), -}; - -static int __init adv7520_init(void) -{ - int rc; - - pr_info("%s\n", __func__); - external_common_state = &hdmi_common; - external_common_state->video_resolution = HDMI_VFRMT_1280x720p60_16_9; - - tv_enc_clk = clk_get(NULL, "tv_enc_clk"); - if (IS_ERR(tv_enc_clk)) { - printk(KERN_ERR "error: can't get tv_enc_clk!\n"); - return IS_ERR(tv_enc_clk); - } - - HDMI_SETUP_LUT(640x480p60_4_3); /* 25.20MHz */ - HDMI_SETUP_LUT(720x480p60_16_9); /* 27.03MHz */ - HDMI_SETUP_LUT(1280x720p60_16_9); /* 74.25MHz */ - - HDMI_SETUP_LUT(720x576p50_16_9); /* 27.00MHz */ - HDMI_SETUP_LUT(1280x720p50_16_9); /* 74.25MHz */ - - hdmi_common_init_panel_info(&hdmi_panel_data.panel_info); - - rc = i2c_add_driver(&hdmi_i2c_driver); - if (rc) { - pr_err("hdmi_init FAILED: i2c_add_driver rc=%d\n", rc); - goto init_exit; - } - - if (machine_is_msm7x30_surf() || machine_is_msm8x55_surf()) { - short *hdtv_mux = (short *)ioremap(0x8e000170 , 0x100); - *hdtv_mux++ = 0x020b; - *hdtv_mux = 0x8000; - iounmap(hdtv_mux); - } - pm_qos_add_request(&pm_qos_req, PM_QOS_CPU_DMA_LATENCY, - PM_QOS_DEFAULT_VALUE); - - return 0; - -init_exit: - if (tv_enc_clk) - clk_put(tv_enc_clk); - return rc; -} - -static void __exit adv7520_exit(void) -{ - i2c_del_driver(&hdmi_i2c_driver); -} - -module_init(adv7520_init); -module_exit(adv7520_exit); -MODULE_LICENSE("GPL v2"); -MODULE_VERSION("0.1"); -MODULE_AUTHOR("Qualcomm Innovation Center, Inc."); -MODULE_DESCRIPTION("ADV7520 HDMI driver"); diff --git a/drivers/video/msm/ebi2_epson_s1d_qvga.c b/drivers/video/msm/ebi2_epson_s1d_qvga.c deleted file mode 100644 index 8db3cf9bf..000000000 --- a/drivers/video/msm/ebi2_epson_s1d_qvga.c +++ /dev/null @@ -1,374 +0,0 @@ -/* Copyright (c) 2012, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "msm_fb.h" - -#include -#include -#include -#include -#include -#include -#include "linux/proc_fs.h" - -#include - -#include -#include - -#include -#include - -#define CMD_NOP_C 0x00 -#define CMD_SOFT_RESET_C 0x99 -#define CMD_DISPLAY_ON_C 0xAF -#define CMD_DISPLAY_OFF_C 0xAE -#define CMD_SET_DISPLAY_C 0xCA -#define CMD_SET_DISPLAY_TIMING_C 0xA1 -#define CMD_SET_DATA_C 0xBC -#define CMD_SET_START_ADDRESS_C 0x15 -#define CMD_SET_END_ADDRESS_C 0x75 -#define CMD_RAM_WRITE_C 0x5C -#define CMD_RAM_READ_C 0x5D -#define CMD_SET_AREA_SCROLLING_C 0xAA -#define CMD_SET_DISPLAY_START_LINE_C 0xAB -#define CMD_PARTIAL_DISPLAY_IN_C 0xA8 -#define CMD_PARTIAL_DISPLAY_OUT_C 0xA9 -#define CMD_SET_DISPLAY_DATA_INTERFACE_C 0x31 -#define CMD_SET_DISPLAY_COLOR_MODE_C 0x8B -#define CMD_SELECT_MTP_ROM_MODE_C 0x65 -#define CMD_MTP_ROM_MODE_IN_C 0x67 -#define CMD_MTP_ROM_MODE_OUT_C 0x68 -#define CMD_MTP_ROM_OPERATION_IN_C 0x69 -#define CMD_MTP_ROM_OPERATION_OUT_C 0x70 -#define CMD_GATE_LINE_SCAN_MODE_C 0x6F -#define CMD_SET_AC_OPERATION_DRIVE_C 0x8C -#define CMD_SET_ELECTRONIC_CONTROL_C 0x20 -#define CMD_SET_POSITIVE_CORRECTION_CHARS_C 0x22 -#define CMD_SET_NEGATIVE_CORRECTION_CHARS_C 0x25 -#define CMD_SET_POWER_CONTROL_C 0x21 -#define CMD_SET_PARTIAL_POWER_CONTROL_C 0x23 -#define CMD_SET_8_COLOR_CONTROL_C 0x24 -#define CMD_SLEEP_IN_C 0x95 -#define CMD_SLEEP_OUT_C 0x94 -#define CMD_VDD_OFF_C 0x97 -#define CMD_VDD_ON_C 0x96 -#define CMD_STOP_OSCILLATION_C 0x93 -#define CMD_START_OSCILLATION_C 0x92 -#define CMD_TEST_SOURCE_C 0xFD -#define CMD_TEST_FUSE_C 0xFE -#define CMD_TEST_C 0xFF -#define CMD_STATUS_READ_C 0xE8 -#define CMD_REVISION_READ_C 0xE9 - -#define PANEL_WIDTH 240 -#define PANEL_HEIGHT 320 -#define ACTIVE_WIN_WIDTH PANEL_WIDTH -#define ACTIVE_WIN_HEIGHT PANEL_HEIGHT - -#define ACTIVE_WIN_H_START 0 -#define ACTIVE_WIN_V_START 0 - -#define DISP_CMD_OUT(cmd) outpw(DISP_CMD_PORT, (cmd << 1)); -#define DISP_DATA_OUT(data) outpw(DISP_DATA_PORT, (data << 1)); -#define DISP_DATA_IN() inpw(DISP_DATA_PORT); - -static void *DISP_CMD_PORT; -static void *DISP_DATA_PORT; -static boolean disp_initialized; -static boolean display_on; -static struct msm_panel_common_pdata *ebi2_epson_pdata; - -static void epson_s1d_disp_init(struct platform_device *pdev); -static int epson_s1d_disp_off(struct platform_device *pdev); -static int epson_s1d_disp_on(struct platform_device *pdev); -static void epson_s1d_disp_set_rect(int x, int y, int xres, int yres); - -static void epson_s1d_disp_set_rect(int x, int y, int xres, int yres) -{ - int right, bottom; - - if (!disp_initialized) - return; - - right = x + xres - 1; - bottom = y + yres - 1; - - x += ACTIVE_WIN_H_START; - y += ACTIVE_WIN_V_START; - right += ACTIVE_WIN_H_START; - bottom += ACTIVE_WIN_V_START; - - if ((PANEL_WIDTH > x) && - (PANEL_HEIGHT > y) && - (PANEL_WIDTH > right) && - (PANEL_HEIGHT > bottom)) { - DISP_CMD_OUT(CMD_SET_START_ADDRESS_C); - DISP_DATA_OUT((uint8)x); - DISP_DATA_OUT((uint8)(y>>8)); - DISP_DATA_OUT((uint8)y); - - DISP_CMD_OUT(CMD_SET_END_ADDRESS_C); - DISP_DATA_OUT((uint8)right); - DISP_DATA_OUT((uint8)(bottom>>8)); - DISP_DATA_OUT((uint8)bottom); - DISP_CMD_OUT(CMD_RAM_WRITE_C); - } -} - -static void epson_s1d_disp_init(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd; - - if (disp_initialized) - return; - - mfd = platform_get_drvdata(pdev); - - DISP_CMD_PORT = mfd->cmd_port; - DISP_DATA_PORT = mfd->data_port; - - disp_initialized = TRUE; -} - -static int epson_s1d_disp_off(struct platform_device *pdev) -{ - if (!disp_initialized) - epson_s1d_disp_init(pdev); - - if (display_on) { - DISP_CMD_OUT(CMD_SOFT_RESET_C); - DISP_CMD_OUT(CMD_VDD_OFF_C); - display_on = FALSE; - } - - return 0; -} - -static int epson_s1d_disp_on(struct platform_device *pdev) -{ - int i; - if (!disp_initialized) - epson_s1d_disp_init(pdev); - - if (!display_on) { - /* Enable Vdd regulator */ - DISP_CMD_OUT(CMD_VDD_ON_C); - msleep(20); - - /* Soft Reset before configuring display */ - DISP_CMD_OUT(CMD_SOFT_RESET_C); - msleep(20); - - /* Set display attributes */ - - /* GATESCAN */ - DISP_CMD_OUT(CMD_GATE_LINE_SCAN_MODE_C); - DISP_DATA_OUT(0x0); - - /* DISSET */ - DISP_CMD_OUT(CMD_SET_DISPLAY_C); - DISP_DATA_OUT(0x31); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT((uint8)((PANEL_HEIGHT - 1)>>8)); - DISP_DATA_OUT((uint8)(PANEL_HEIGHT - 1)); - DISP_DATA_OUT(0x03); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x08); - - /* VOLSET */ - DISP_CMD_OUT( - CMD_SET_ELECTRONIC_CONTROL_C); - DISP_DATA_OUT(0x10); - DISP_DATA_OUT(0x80); - DISP_DATA_OUT(0x11); - DISP_DATA_OUT(0x1B); - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x0D); - DISP_DATA_OUT(0x00); - - /* PWRCTL */ - DISP_CMD_OUT(CMD_SET_POWER_CONTROL_C); - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x24); - DISP_DATA_OUT(0x0F); - DISP_DATA_OUT(0xFE); - DISP_DATA_OUT(0x33); - DISP_DATA_OUT(0x31); - DISP_DATA_OUT(0xFF); - DISP_DATA_OUT(0x03); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x77); - DISP_DATA_OUT(0x33); - DISP_DATA_OUT(0x11); - DISP_DATA_OUT(0x44); - DISP_DATA_OUT(0x00); - - /* PPWRCTL */ - DISP_CMD_OUT(CMD_SET_PARTIAL_POWER_CONTROL_C); - DISP_DATA_OUT(0x33); - DISP_DATA_OUT(0xFF); - DISP_DATA_OUT(0x03); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x44); - DISP_DATA_OUT(0x00); - - /* SPLOUT */ - DISP_CMD_OUT(CMD_SLEEP_OUT_C); - msleep(100); - - /* DATSET */ - DISP_CMD_OUT(CMD_SET_DATA_C); - DISP_DATA_OUT(0x00); - - /* DISTMEMSET */ - DISP_CMD_OUT(CMD_SET_DISPLAY_TIMING_C); - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x2E); - DISP_DATA_OUT(0x0A); - DISP_DATA_OUT(0x2C); - DISP_DATA_OUT(0x23); - DISP_DATA_OUT(0x2F); - DISP_DATA_OUT(0x00); - - /* GAMSETP */ - DISP_CMD_OUT(CMD_SET_POSITIVE_CORRECTION_CHARS_C); - DISP_DATA_OUT(0x37); - DISP_DATA_OUT(0xFF); - DISP_DATA_OUT(0x7F); - DISP_DATA_OUT(0x15); - DISP_DATA_OUT(0x37); - DISP_DATA_OUT(0x05); - - /* GAMSETN */ - DISP_CMD_OUT(CMD_SET_NEGATIVE_CORRECTION_CHARS_C); - DISP_DATA_OUT(0x37); - DISP_DATA_OUT(0xFF); - DISP_DATA_OUT(0x7F); - DISP_DATA_OUT(0x15); - DISP_DATA_OUT(0x37); - DISP_DATA_OUT(0x05); - - /* ACDRIVE */ - DISP_CMD_OUT(CMD_SET_AC_OPERATION_DRIVE_C); - DISP_DATA_OUT(0x00); - - /* TEST */ - DISP_CMD_OUT(CMD_TEST_C); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x01); - - /* COLMOD */ - DISP_CMD_OUT(CMD_SET_DISPLAY_COLOR_MODE_C); - DISP_DATA_OUT(0x00); - - /* STADDSET */ - DISP_CMD_OUT(CMD_SET_START_ADDRESS_C); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x00); - - /* EDADDSET */ - DISP_CMD_OUT(CMD_SET_END_ADDRESS_C); - DISP_DATA_OUT(0xEF); - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x3F); - - /* Set Display Start Line */ - DISP_CMD_OUT(CMD_SET_DISPLAY_START_LINE_C); - DISP_DATA_OUT(0x00); - - /* Set Display Data Interface */ - DISP_CMD_OUT(CMD_SET_DISPLAY_DATA_INTERFACE_C); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x04); - - epson_s1d_disp_set_rect(0, - 0, - ACTIVE_WIN_WIDTH, - ACTIVE_WIN_HEIGHT); - - for (i = 0; i < (ACTIVE_WIN_WIDTH * ACTIVE_WIN_HEIGHT); i++) - outpdw(DISP_DATA_PORT, 0); - - /* DISON */ - DISP_CMD_OUT(CMD_DISPLAY_ON_C); - msleep(60); - - display_on = TRUE; - } - - return 0; -} - -static int epson_s1d_probe(struct platform_device *pdev) -{ - if (pdev->id == 0) { - ebi2_epson_pdata = pdev->dev.platform_data; - return 0; - } - - msm_fb_add_device(pdev); - return 0; -} - -static struct platform_driver this_driver = { - .probe = epson_s1d_probe, - .driver = { - .name = "ebi2_epson_s1d_qvga", - }, -}; - -static struct msm_fb_panel_data epson_s1d_panel_data = { - .on = epson_s1d_disp_on, - .off = epson_s1d_disp_off, - .set_rect = epson_s1d_disp_set_rect, -}; - -static struct platform_device this_device = { - .name = "ebi2_epson_s1d_qvga", - .id = 1, - .dev = { - .platform_data = &epson_s1d_panel_data, - } -}; - -static int __init epson_s1d_init(void) -{ - int ret; - struct msm_panel_info *pinfo; - - ret = platform_driver_register(&this_driver); - if (!ret) { - pinfo = &epson_s1d_panel_data.panel_info; - pinfo->xres = PANEL_WIDTH; - pinfo->yres = PANEL_HEIGHT; - MSM_FB_SINGLE_MODE_PANEL(pinfo); - pinfo->type = EBI2_PANEL; - pinfo->pdest = DISPLAY_1; - pinfo->wait_cycle = 0x048423E8; - pinfo->bpp = 18; - pinfo->fb_num = 2; - pinfo->lcd.vsync_enable = FALSE; - - ret = platform_device_register(&this_device); - if (ret) - platform_driver_unregister(&this_driver); - } - - return ret; -} - -module_init(epson_s1d_init); diff --git a/drivers/video/msm/ebi2_host.c b/drivers/video/msm/ebi2_host.c deleted file mode 100644 index e4eda7d35..000000000 --- a/drivers/video/msm/ebi2_host.c +++ /dev/null @@ -1,308 +0,0 @@ -/* Copyright (c) 2012, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "msm_fb.h" - -struct mdp_ccs mdp_ccs_rgb2yuv; -struct mdp_ccs mdp_ccs_yuv2rgb; - -static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST]; -static int pdev_list_cnt; -static int ebi2_host_resource_initialized; -static struct msm_panel_common_pdata *ebi2_host_pdata; - -static int ebi2_host_probe(struct platform_device *pdev); -static int ebi2_host_remove(struct platform_device *pdev); - -static int ebi2_host_runtime_suspend(struct device *dev) -{ - dev_dbg(dev, "pm_runtime: suspending...\n"); - return 0; -} - -static int ebi2_host_runtime_resume(struct device *dev) -{ - dev_dbg(dev, "pm_runtime: resuming...\n"); - return 0; -} - -static const struct dev_pm_ops ebi2_host_dev_pm_ops = { - .runtime_suspend = ebi2_host_runtime_suspend, - .runtime_resume = ebi2_host_runtime_resume, -}; - - -static struct platform_driver ebi2_host_driver = { - .probe = ebi2_host_probe, - .remove = ebi2_host_remove, - .shutdown = NULL, - .driver = { - /* - * Simulate mdp hw - */ - .name = "mdp", - .pm = &ebi2_host_dev_pm_ops, - }, -}; - -void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state, - boolean isr) -{ - return; -} -int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req) -{ - return 0; -} -int mdp_start_histogram(struct fb_info *info) -{ - return 0; -} -int mdp_stop_histogram(struct fb_info *info) -{ - return 0; -} -void mdp_refresh_screen(unsigned long data) -{ - return; -} - -static int ebi2_host_off(struct platform_device *pdev) -{ - int ret; - ret = panel_next_off(pdev); - return ret; -} - -static int ebi2_host_on(struct platform_device *pdev) -{ - int ret; - ret = panel_next_on(pdev); - return ret; -} - - -static int ebi2_host_probe(struct platform_device *pdev) -{ - struct platform_device *msm_fb_dev = NULL; - struct msm_fb_data_type *mfd; - struct msm_fb_panel_data *pdata = NULL; - int rc; - - if ((pdev->id == 0) && (pdev->num_resources > 0)) { - - ebi2_host_pdata = pdev->dev.platform_data; - - ebi2_host_resource_initialized = 1; - return 0; - } - - ebi2_host_resource_initialized = 1; - if (!ebi2_host_resource_initialized) - return -EPERM; - - mfd = platform_get_drvdata(pdev); - - if (!mfd) - return -ENODEV; - - if (mfd->key != MFD_KEY) - return -EINVAL; - - if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST) - return -ENOMEM; - - msm_fb_dev = platform_device_alloc("msm_fb", pdev->id); - if (!msm_fb_dev) - return -ENOMEM; - - /* link to the latest pdev */ - mfd->pdev = msm_fb_dev; - - if (ebi2_host_pdata) { - mfd->mdp_rev = ebi2_host_pdata->mdp_rev; - mfd->mem_hid = ebi2_host_pdata->mem_hid; - } - - /* add panel data */ - if (platform_device_add_data - (msm_fb_dev, pdev->dev.platform_data, - sizeof(struct msm_fb_panel_data))) { - pr_err("ebi2_host_probe: platform_device_add_data failed!\n"); - rc = -ENOMEM; - goto ebi2_host_probe_err; - } - /* data chain */ - pdata = msm_fb_dev->dev.platform_data; - pdata->on = ebi2_host_on; - pdata->off = ebi2_host_off; - pdata->next = pdev; - - /* set driver data */ - platform_set_drvdata(msm_fb_dev, mfd); - - rc = platform_device_add(msm_fb_dev); - if (rc) - goto ebi2_host_probe_err; - - pm_runtime_set_active(&pdev->dev); - pm_runtime_enable(&pdev->dev); - - pdev_list[pdev_list_cnt++] = pdev; - return 0; - -ebi2_host_probe_err: - platform_device_put(msm_fb_dev); - return rc; -} - -void mdp_set_dma_pan_info(struct fb_info *info, struct mdp_dirty_region *dirty, - boolean sync) -{ - struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; - struct fb_info *fbi = mfd->fbi; - struct msm_panel_info *panel_info = &mfd->panel_info; - MDPIBUF *iBuf; - int bpp = info->var.bits_per_pixel / 8; - int yres, remainder; - - if (panel_info->mode2_yres != 0) { - yres = panel_info->mode2_yres; - remainder = (fbi->fix.line_length*yres)%PAGE_SIZE; - } else { - yres = panel_info->yres; - remainder = (fbi->fix.line_length*yres)%PAGE_SIZE; - } - - if (!remainder) - remainder = PAGE_SIZE; - - down(&mfd->sem); - - iBuf = &mfd->ibuf; - /* use virtual address */ - iBuf->buf = (uint8 *) fbi->screen_base; - - if (fbi->var.yoffset < yres) { - iBuf->buf += fbi->var.xoffset * bpp; - } else if (fbi->var.yoffset >= yres && fbi->var.yoffset < 2 * yres) { - iBuf->buf += fbi->var.xoffset * bpp + yres * - fbi->fix.line_length + PAGE_SIZE - remainder; - } else { - iBuf->buf += fbi->var.xoffset * bpp + 2 * yres * - fbi->fix.line_length + 2 * (PAGE_SIZE - remainder); - } - - iBuf->ibuf_width = info->var.xres_virtual; - iBuf->bpp = bpp; - - iBuf->vsync_enable = sync; - - if (dirty) { - /* - * ToDo: dirty region check inside var.xoffset+xres - * <-> var.yoffset+yres - */ - iBuf->dma_x = dirty->xoffset % info->var.xres; - iBuf->dma_y = dirty->yoffset % info->var.yres; - iBuf->dma_w = dirty->width; - iBuf->dma_h = dirty->height; - } else { - iBuf->dma_x = 0; - iBuf->dma_y = 0; - iBuf->dma_w = info->var.xres; - iBuf->dma_h = info->var.yres; - } - mfd->ibuf_flushed = FALSE; - up(&mfd->sem); -} - -void mdp_dma_pan_update(struct fb_info *info) -{ - struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par; - MDPIBUF *iBuf; - int i, j; - uint32 data; - uint8 *src; - struct msm_fb_panel_data *pdata = - (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data; - struct fb_info *fbi = mfd->fbi; - - iBuf = &mfd->ibuf; - - if (fbi->screen_base) - invalidate_caches((unsigned long)fbi->screen_base, - (unsigned long)info->fix.smem_len, - (unsigned long)info->fix.smem_start); - - pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w, - iBuf->dma_h); - for (i = 0; i < iBuf->dma_h; i++) { - src = iBuf->buf + (fbi->fix.line_length * (iBuf->dma_y + i)) - + (iBuf->dma_x * iBuf->bpp); - for (j = 0; j < iBuf->dma_w; j++) { - data = (uint32)(*src++ >> 2) << 12; - data |= (uint32)(*src++ >> 2) << 6; - data |= (uint32)(*src++ >> 2); - data = ((data&0x1FF)<<16) | ((data&0x3FE00)>>9); - outpdw(mfd->data_port, data); - } - } -} - -static int ebi2_host_remove(struct platform_device *pdev) -{ - pm_runtime_disable(&pdev->dev); - - return 0; -} - -static int ebi2_host_register_driver(void) -{ - return platform_driver_register(&ebi2_host_driver); -} - -static int __init ebi2_host_driver_init(void) -{ - int ret; - - ret = ebi2_host_register_driver(); - if (ret) { - pr_err("ebi2_host_register_driver() failed!\n"); - return ret; - } - - return 0; -} - -module_init(ebi2_host_driver_init); diff --git a/drivers/video/msm/ebi2_l2f.c b/drivers/video/msm/ebi2_l2f.c deleted file mode 100644 index 2e944bea7..000000000 --- a/drivers/video/msm/ebi2_l2f.c +++ /dev/null @@ -1,566 +0,0 @@ -/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "msm_fb.h" - -#include -#include -#include -#include -#include -#include -#include "linux/proc_fs.h" - -#include - -#include -#include - -#include -#include - -/* The following are for MSM5100 on Gator -*/ -#ifdef FEATURE_PM1000 -#include "pm1000.h" -#endif /* FEATURE_PM1000 */ -/* The following are for MSM6050 on Bambi -*/ -#ifdef FEATURE_PMIC_LCDKBD_LED_DRIVER -#include "pm.h" -#endif /* FEATURE_PMIC_LCDKBD_LED_DRIVER */ - -#ifdef DISP_DEVICE_18BPP -#undef DISP_DEVICE_18BPP -#define DISP_DEVICE_16BPP -#endif - -#define QCIF_WIDTH 176 -#define QCIF_HEIGHT 220 - -static void *DISP_CMD_PORT; -static void *DISP_DATA_PORT; - -#define DISP_CMD_DISON 0xaf -#define DISP_CMD_DISOFF 0xae -#define DISP_CMD_DISNOR 0xa6 -#define DISP_CMD_DISINV 0xa7 -#define DISP_CMD_DISCTL 0xca -#define DISP_CMD_GCP64 0xcb -#define DISP_CMD_GCP16 0xcc -#define DISP_CMD_GSSET 0xcd -#define DISP_GS_2 0x02 -#define DISP_GS_16 0x01 -#define DISP_GS_64 0x00 -#define DISP_CMD_SLPIN 0x95 -#define DISP_CMD_SLPOUT 0x94 -#define DISP_CMD_SD_PSET 0x75 -#define DISP_CMD_MD_PSET 0x76 -#define DISP_CMD_SD_CSET 0x15 -#define DISP_CMD_MD_CSET 0x16 -#define DISP_CMD_DATCTL 0xbc -#define DISP_DATCTL_666 0x08 -#define DISP_DATCTL_565 0x28 -#define DISP_DATCTL_444 0x38 -#define DISP_CMD_RAMWR 0x5c -#define DISP_CMD_RAMRD 0x5d -#define DISP_CMD_PTLIN 0xa8 -#define DISP_CMD_PTLOUT 0xa9 -#define DISP_CMD_ASCSET 0xaa -#define DISP_CMD_SCSTART 0xab -#define DISP_CMD_VOLCTL 0xc6 -#define DISP_VOLCTL_TONE 0x80 -#define DISP_CMD_NOp 0x25 -#define DISP_CMD_OSSEL 0xd0 -#define DISP_CMD_3500KSET 0xd1 -#define DISP_CMD_3500KEND 0xd2 -#define DISP_CMD_14MSET 0xd3 -#define DISP_CMD_14MEND 0xd4 - -#define DISP_CMD_OUT(cmd) outpw(DISP_CMD_PORT, cmd); - -#define DISP_DATA_OUT(data) outpw(DISP_DATA_PORT, data); - -#define DISP_DATA_IN() inpw(DISP_DATA_PORT); - -/* Epson device column number starts at 2 -*/ -#define DISP_SET_RECT(ulhc_row, lrhc_row, ulhc_col, lrhc_col) \ - DISP_CMD_OUT(DISP_CMD_SD_PSET) \ - DISP_DATA_OUT((ulhc_row) & 0xFF) \ - DISP_DATA_OUT((ulhc_row) >> 8) \ - DISP_DATA_OUT((lrhc_row) & 0xFF) \ - DISP_DATA_OUT((lrhc_row) >> 8) \ - DISP_CMD_OUT(DISP_CMD_SD_CSET) \ - DISP_DATA_OUT(((ulhc_col)+2) & 0xFF) \ - DISP_DATA_OUT(((ulhc_col)+2) >> 8) \ - DISP_DATA_OUT(((lrhc_col)+2) & 0xFF) \ - DISP_DATA_OUT(((lrhc_col)+2) >> 8) - -#define DISP_MIN_CONTRAST 0 -#define DISP_MAX_CONTRAST 127 -#define DISP_DEFAULT_CONTRAST 80 - -#define DISP_MIN_BACKLIGHT 0 -#define DISP_MAX_BACKLIGHT 15 -#define DISP_DEFAULT_BACKLIGHT 2 - -#define WAIT_SEC(sec) mdelay((sec)/1000) - -static word disp_area_start_row; -static word disp_area_end_row; -static byte disp_contrast = DISP_DEFAULT_CONTRAST; -static boolean disp_powered_up; -static boolean disp_initialized = FALSE; -/* For some reason the contrast set at init time is not good. Need to do - * it again - */ -static boolean display_on = FALSE; -static void epsonQcif_disp_init(struct platform_device *pdev); -static void epsonQcif_disp_set_contrast(word contrast); -static void epsonQcif_disp_set_display_area(word start_row, word end_row); -static int epsonQcif_disp_off(struct platform_device *pdev); -static int epsonQcif_disp_on(struct platform_device *pdev); -static void epsonQcif_disp_set_rect(int x, int y, int xres, int yres); - -volatile word databack; -static void epsonQcif_disp_init(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd; - - int i; - - if (disp_initialized) - return; - - mfd = platform_get_drvdata(pdev); - - DISP_CMD_PORT = mfd->cmd_port; - DISP_DATA_PORT = mfd->data_port; - - /* Sleep in */ - DISP_CMD_OUT(DISP_CMD_SLPIN); - - /* Display off */ - DISP_CMD_OUT(DISP_CMD_DISOFF); - - /* Display normal */ - DISP_CMD_OUT(DISP_CMD_DISNOR); - - /* Set data mode */ - DISP_CMD_OUT(DISP_CMD_DATCTL); - DISP_DATA_OUT(DISP_DATCTL_565); - - /* Set display timing */ - DISP_CMD_OUT(DISP_CMD_DISCTL); - DISP_DATA_OUT(0x1c); /* p1 */ - DISP_DATA_OUT(0x02); /* p1 */ - DISP_DATA_OUT(0x82); /* p2 */ - DISP_DATA_OUT(0x00); /* p3 */ - DISP_DATA_OUT(0x00); /* p4 */ - DISP_DATA_OUT(0xe0); /* p5 */ - DISP_DATA_OUT(0x00); /* p5 */ - DISP_DATA_OUT(0xdc); /* p6 */ - DISP_DATA_OUT(0x00); /* p6 */ - DISP_DATA_OUT(0x02); /* p7 */ - DISP_DATA_OUT(0x00); /* p8 */ - - /* Set 64 gray scale level */ - DISP_CMD_OUT(DISP_CMD_GCP64); - DISP_DATA_OUT(0x08); /* p01 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x2a); /* p02 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x4e); /* p03 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x6b); /* p04 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x88); /* p05 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0xa3); /* p06 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0xba); /* p07 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0xd1); /* p08 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0xe5); /* p09 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0xf3); /* p10 */ - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x03); /* p11 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x13); /* p12 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x22); /* p13 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x2f); /* p14 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x3b); /* p15 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x46); /* p16 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x51); /* p17 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x5b); /* p18 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x64); /* p19 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x6c); /* p20 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x74); /* p21 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x7c); /* p22 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x83); /* p23 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x8a); /* p24 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x91); /* p25 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x98); /* p26 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x9f); /* p27 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xa6); /* p28 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xac); /* p29 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xb2); /* p30 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xb7); /* p31 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xbc); /* p32 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xc1); /* p33 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xc6); /* p34 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xcb); /* p35 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xd0); /* p36 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xd4); /* p37 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xd8); /* p38 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xdc); /* p39 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xe0); /* p40 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xe4); /* p41 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xe8); /* p42 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xec); /* p43 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xf0); /* p44 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xf4); /* p45 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xf8); /* p46 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xfb); /* p47 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xfe); /* p48 */ - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0x01); /* p49 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x03); /* p50 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x05); /* p51 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x07); /* p52 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x09); /* p53 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x0b); /* p54 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x0d); /* p55 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x0f); /* p56 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x11); /* p57 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x13); /* p58 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x15); /* p59 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x17); /* p60 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x19); /* p61 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x1b); /* p62 */ - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x1c); /* p63 */ - DISP_DATA_OUT(0x02); - - /* Set 16 gray scale level */ - DISP_CMD_OUT(DISP_CMD_GCP16); - DISP_DATA_OUT(0x1a); /* p01 */ - DISP_DATA_OUT(0x32); /* p02 */ - DISP_DATA_OUT(0x42); /* p03 */ - DISP_DATA_OUT(0x4c); /* p04 */ - DISP_DATA_OUT(0x58); /* p05 */ - DISP_DATA_OUT(0x5f); /* p06 */ - DISP_DATA_OUT(0x66); /* p07 */ - DISP_DATA_OUT(0x6b); /* p08 */ - DISP_DATA_OUT(0x70); /* p09 */ - DISP_DATA_OUT(0x74); /* p10 */ - DISP_DATA_OUT(0x78); /* p11 */ - DISP_DATA_OUT(0x7b); /* p12 */ - DISP_DATA_OUT(0x7e); /* p13 */ - DISP_DATA_OUT(0x80); /* p14 */ - DISP_DATA_OUT(0x82); /* p15 */ - - /* Set DSP column */ - DISP_CMD_OUT(DISP_CMD_MD_CSET); - DISP_DATA_OUT(0xff); - DISP_DATA_OUT(0x03); - DISP_DATA_OUT(0xff); - DISP_DATA_OUT(0x03); - - /* Set DSP page */ - DISP_CMD_OUT(DISP_CMD_MD_PSET); - DISP_DATA_OUT(0xff); - DISP_DATA_OUT(0x01); - DISP_DATA_OUT(0xff); - DISP_DATA_OUT(0x01); - - /* Set ARM column */ - DISP_CMD_OUT(DISP_CMD_SD_CSET); - DISP_DATA_OUT(0x02); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT((QCIF_WIDTH + 1) & 0xFF); - DISP_DATA_OUT((QCIF_WIDTH + 1) >> 8); - - /* Set ARM page */ - DISP_CMD_OUT(DISP_CMD_SD_PSET); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT(0x00); - DISP_DATA_OUT((QCIF_HEIGHT - 1) & 0xFF); - DISP_DATA_OUT((QCIF_HEIGHT - 1) >> 8); - - /* Set 64 gray scales */ - DISP_CMD_OUT(DISP_CMD_GSSET); - DISP_DATA_OUT(DISP_GS_64); - - DISP_CMD_OUT(DISP_CMD_OSSEL); - DISP_DATA_OUT(0); - - /* Sleep out */ - DISP_CMD_OUT(DISP_CMD_SLPOUT); - - WAIT_SEC(40000); - - /* Initialize power IC */ - DISP_CMD_OUT(DISP_CMD_VOLCTL); - DISP_DATA_OUT(DISP_VOLCTL_TONE); - - WAIT_SEC(40000); - - /* Set electronic volume, d'xx */ - DISP_CMD_OUT(DISP_CMD_VOLCTL); - DISP_DATA_OUT(DISP_DEFAULT_CONTRAST); /* value from 0 to 127 */ - - /* Initialize display data */ - DISP_SET_RECT(0, (QCIF_HEIGHT - 1), 0, (QCIF_WIDTH - 1)); - DISP_CMD_OUT(DISP_CMD_RAMWR); - for (i = 0; i < QCIF_HEIGHT * QCIF_WIDTH; i++) - DISP_DATA_OUT(0xffff); - - DISP_CMD_OUT(DISP_CMD_RAMRD); - databack = DISP_DATA_IN(); - databack = DISP_DATA_IN(); - databack = DISP_DATA_IN(); - databack = DISP_DATA_IN(); - - WAIT_SEC(80000); - - DISP_CMD_OUT(DISP_CMD_DISON); - - disp_area_start_row = 0; - disp_area_end_row = QCIF_HEIGHT - 1; - disp_powered_up = TRUE; - disp_initialized = TRUE; - epsonQcif_disp_set_display_area(0, QCIF_HEIGHT - 1); - display_on = TRUE; -} - -static void epsonQcif_disp_set_rect(int x, int y, int xres, int yres) -{ - if (!disp_initialized) - return; - - DISP_SET_RECT(y, y + yres - 1, x, x + xres - 1); - DISP_CMD_OUT(DISP_CMD_RAMWR); -} - -static void epsonQcif_disp_set_display_area(word start_row, word end_row) -{ - if (!disp_initialized) - return; - - if ((start_row == disp_area_start_row) - && (end_row == disp_area_end_row)) - return; - disp_area_start_row = start_row; - disp_area_end_row = end_row; - - /* Range checking - */ - if (end_row >= QCIF_HEIGHT) - end_row = QCIF_HEIGHT - 1; - if (start_row > end_row) - start_row = end_row; - - /* When display is not the full screen, gray scale is set to - ** 2; otherwise it is set to 64. - */ - if ((start_row == 0) && (end_row == (QCIF_HEIGHT - 1))) { - /* The whole screen */ - DISP_CMD_OUT(DISP_CMD_PTLOUT); - WAIT_SEC(10000); - DISP_CMD_OUT(DISP_CMD_DISOFF); - WAIT_SEC(100000); - DISP_CMD_OUT(DISP_CMD_GSSET); - DISP_DATA_OUT(DISP_GS_64); - WAIT_SEC(100000); - DISP_CMD_OUT(DISP_CMD_DISON); - } else { - /* partial screen */ - DISP_CMD_OUT(DISP_CMD_PTLIN); - DISP_DATA_OUT(start_row); - DISP_DATA_OUT(start_row >> 8); - DISP_DATA_OUT(end_row); - DISP_DATA_OUT(end_row >> 8); - DISP_CMD_OUT(DISP_CMD_GSSET); - DISP_DATA_OUT(DISP_GS_2); - } -} - -static int epsonQcif_disp_off(struct platform_device *pdev) -{ - if (!disp_initialized) - epsonQcif_disp_init(pdev); - - if (display_on) { - DISP_CMD_OUT(DISP_CMD_DISOFF); - DISP_CMD_OUT(DISP_CMD_SLPIN); - display_on = FALSE; - } - - return 0; -} - -static int epsonQcif_disp_on(struct platform_device *pdev) -{ - if (!disp_initialized) - epsonQcif_disp_init(pdev); - - if (!display_on) { - DISP_CMD_OUT(DISP_CMD_SLPOUT); - WAIT_SEC(40000); - DISP_CMD_OUT(DISP_CMD_DISON); - epsonQcif_disp_set_contrast(disp_contrast); - display_on = TRUE; - } - - return 0; -} - -static void epsonQcif_disp_set_contrast(word contrast) -{ - if (!disp_initialized) - return; - - /* Initialize power IC, d'24 */ - DISP_CMD_OUT(DISP_CMD_VOLCTL); - DISP_DATA_OUT(DISP_VOLCTL_TONE); - - WAIT_SEC(40000); - - /* Set electronic volume, d'xx */ - DISP_CMD_OUT(DISP_CMD_VOLCTL); - if (contrast > 127) - contrast = 127; - DISP_DATA_OUT(contrast); /* value from 0 to 127 */ - disp_contrast = (byte) contrast; -} /* End disp_set_contrast */ - -static void epsonQcif_disp_clear_screen_area( - word start_row, word end_row, word start_column, word end_column) { - int32 i; - - /* Clear the display screen */ - DISP_SET_RECT(start_row, end_row, start_column, end_column); - DISP_CMD_OUT(DISP_CMD_RAMWR); - i = (end_row - start_row + 1) * (end_column - start_column + 1); - for (; i > 0; i--) - DISP_DATA_OUT(0xffff); -} - -static int __init epsonQcif_probe(struct platform_device *pdev) -{ - msm_fb_add_device(pdev); - - return 0; -} - -static struct platform_driver this_driver = { - .probe = epsonQcif_probe, - .driver = { - .name = "ebi2_epson_qcif", - }, -}; - -static struct msm_fb_panel_data epsonQcif_panel_data = { - .on = epsonQcif_disp_on, - .off = epsonQcif_disp_off, - .set_rect = epsonQcif_disp_set_rect, -}; - -static struct platform_device this_device = { - .name = "ebi2_epson_qcif", - .id = 0, - .dev = { - .platform_data = &epsonQcif_panel_data, - } -}; - -static int __init epsonQcif_init(void) -{ - int ret; - struct msm_panel_info *pinfo; - - ret = platform_driver_register(&this_driver); - if (!ret) { - pinfo = &epsonQcif_panel_data.panel_info; - pinfo->xres = QCIF_WIDTH; - pinfo->yres = QCIF_HEIGHT; - MSM_FB_SINGLE_MODE_PANEL(pinfo); - pinfo->type = EBI2_PANEL; - pinfo->pdest = DISPLAY_2; - pinfo->wait_cycle = 0x808000; - pinfo->bpp = 16; - pinfo->fb_num = 2; - pinfo->lcd.vsync_enable = FALSE; - - ret = platform_device_register(&this_device); - if (ret) - platform_driver_unregister(&this_driver); - } - - return ret; -} - -module_init(epsonQcif_init); diff --git a/drivers/video/msm/ebi2_lcd.c b/drivers/video/msm/ebi2_lcd.c deleted file mode 100644 index a19763c46..000000000 --- a/drivers/video/msm/ebi2_lcd.c +++ /dev/null @@ -1,308 +0,0 @@ -/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "msm_fb.h" - -static int ebi2_lcd_probe(struct platform_device *pdev); -static int ebi2_lcd_remove(struct platform_device *pdev); - -static int ebi2_lcd_runtime_suspend(struct device *dev) -{ - dev_dbg(dev, "pm_runtime: suspending...\n"); - return 0; -} - -static int ebi2_lcd_runtime_resume(struct device *dev) -{ - dev_dbg(dev, "pm_runtime: resuming...\n"); - return 0; -} - -static struct dev_pm_ops ebi2_lcd_dev_pm_ops = { - .runtime_suspend = ebi2_lcd_runtime_suspend, - .runtime_resume = ebi2_lcd_runtime_resume, -}; - -static struct platform_driver ebi2_lcd_driver = { - .probe = ebi2_lcd_probe, - .remove = ebi2_lcd_remove, - .suspend = NULL, - .resume = NULL, - .shutdown = NULL, - .driver = { - .name = "ebi2_lcd", - .pm = &ebi2_lcd_dev_pm_ops, - }, -}; - -static void *ebi2_base; -static void *ebi2_lcd_cfg0; -static void *ebi2_lcd_cfg1; -static void __iomem *lcd01_base; -static void __iomem *lcd02_base; -static int lcd01_base_phys; -static int ebi2_lcd_resource_initialized; - -static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST]; -static int pdev_list_cnt; -static struct lcdc_platform_data *ebi2_pdata; - -static int ebi2_lcd_on(struct platform_device *pdev) -{ - int ret; - - if (ebi2_pdata && ebi2_pdata->lcdc_power_save) - ebi2_pdata->lcdc_power_save(1); - - ret = panel_next_on(pdev); - return ret; -} - -static int ebi2_lcd_off(struct platform_device *pdev) -{ - int ret; - - ret = panel_next_off(pdev); - - if (ebi2_pdata && ebi2_pdata->lcdc_power_save) - ebi2_pdata->lcdc_power_save(0); - - return ret; -} - -static int ebi2_lcd_probe(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd; - struct platform_device *mdp_dev = NULL; - struct msm_fb_panel_data *pdata = NULL; - int rc, i, hw_version; - - if (pdev->id == 0) { - for (i = 0; i < pdev->num_resources; i++) { - if (!strncmp(pdev->resource[i].name, "base", 4)) { - ebi2_base = ioremap(pdev->resource[i].start, - pdev->resource[i].end - - pdev->resource[i].start + 1); - if (!ebi2_base) { - printk(KERN_ERR - "ebi2_base ioremap failed!\n"); - return -ENOMEM; - } - ebi2_lcd_cfg0 = (void *)(ebi2_base + 0x20); - ebi2_lcd_cfg1 = (void *)(ebi2_base + 0x24); - } else if (!strncmp(pdev->resource[i].name, - "lcd01", 5)) { - lcd01_base_phys = pdev->resource[i].start; - lcd01_base = ioremap(pdev->resource[i].start, - pdev->resource[i].end - - pdev->resource[i].start + 1); - if (!lcd01_base) { - printk(KERN_ERR - "lcd01_base ioremap failed!\n"); - return -ENOMEM; - } - } else if (!strncmp(pdev->resource[i].name, - "lcd02", 5)) { - lcd02_base = ioremap(pdev->resource[i].start, - pdev->resource[i].end - - pdev->resource[i].start + 1); - if (!lcd02_base) { - printk(KERN_ERR - "lcd02_base ioremap failed!\n"); - return -ENOMEM; - } - } - } - ebi2_pdata = pdev->dev.platform_data; - ebi2_lcd_resource_initialized = 1; - - return 0; - } - - if (!ebi2_lcd_resource_initialized) - return -EPERM; - - mfd = platform_get_drvdata(pdev); - - if (!mfd) - return -ENODEV; - - if (mfd->key != MFD_KEY) - return -EINVAL; - - if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST) - return -ENOMEM; - - if (ebi2_base == NULL) - return -ENOMEM; - - mdp_dev = platform_device_alloc("mdp", pdev->id); - if (!mdp_dev) - return -ENOMEM; - - /* link to the latest pdev */ - mfd->pdev = mdp_dev; - mfd->dest = DISPLAY_LCD; - - /* add panel data */ - if (platform_device_add_data - (mdp_dev, pdev->dev.platform_data, - sizeof(struct msm_fb_panel_data))) { - printk(KERN_ERR "ebi2_lcd_probe: platform_device_add_data failed!\n"); - platform_device_put(mdp_dev); - return -ENOMEM; - } - - /* data chain */ - pdata = mdp_dev->dev.platform_data; - pdata->on = ebi2_lcd_on; - pdata->off = ebi2_lcd_off; - pdata->next = pdev; - - /* get/set panel specific fb info */ - mfd->panel_info = pdata->panel_info; - - hw_version = inp32((int)ebi2_base + 8); - - if (mfd->panel_info.bpp == 24) - mfd->fb_imgType = MDP_RGB_888; - else if (mfd->panel_info.bpp == 18) - mfd->fb_imgType = MDP_RGB_888; - else - mfd->fb_imgType = MDP_RGB_565; - - /* config msm ebi2 lcd register */ - if (mfd->panel_info.pdest == DISPLAY_1) { - outp32(ebi2_base, - (inp32(ebi2_base) & (~(EBI2_PRIM_LCD_CLR))) | - EBI2_PRIM_LCD_SEL); - /* - * current design has one set of cfg0/1 register to control - * both EBI2 channels. so, we're using the PRIM channel to - * configure both. - */ - outp32(ebi2_lcd_cfg0, mfd->panel_info.wait_cycle); - if (hw_version < 0x2020) { - if (mfd->panel_info.bpp == 18) - outp32(ebi2_lcd_cfg1, 0x01000000); - else - outp32(ebi2_lcd_cfg1, 0x0); - } - } else { -#ifdef DEBUG_EBI2_LCD - /* - * confliting with QCOM SURF FPGA CS. - * OEM should enable below for their CS mapping - */ - outp32(ebi2_base, (inp32(ebi2_base)&(~(EBI2_SECD_LCD_CLR))) - |EBI2_SECD_LCD_SEL); -#endif - } - - /* - * map cs (chip select) address - */ - if (mfd->panel_info.pdest == DISPLAY_1) { - mfd->cmd_port = lcd01_base; - if (hw_version >= 0x2020) { - mfd->data_port = - (void *)((uint32) mfd->cmd_port + 0x80); - mfd->data_port_phys = - (void *)(lcd01_base_phys + 0x80); - } else { - mfd->data_port = - (void *)((uint32) mfd->cmd_port + - EBI2_PRIM_LCD_RS_PIN); - mfd->data_port_phys = - (void *)(LCD_PRIM_BASE_PHYS + EBI2_PRIM_LCD_RS_PIN); - } - } else { - mfd->cmd_port = lcd01_base; - mfd->data_port = - (void *)((uint32) mfd->cmd_port + EBI2_SECD_LCD_RS_PIN); - mfd->data_port_phys = - (void *)(LCD_SECD_BASE_PHYS + EBI2_SECD_LCD_RS_PIN); - } - - /* - * set driver data - */ - platform_set_drvdata(mdp_dev, mfd); - - /* - * register in mdp driver - */ - rc = platform_device_add(mdp_dev); - if (rc) { - goto ebi2_lcd_probe_err; - } - - pm_runtime_set_active(&pdev->dev); - pm_runtime_enable(&pdev->dev); - - - pdev_list[pdev_list_cnt++] = pdev; - return 0; - - ebi2_lcd_probe_err: - platform_device_put(mdp_dev); - return rc; -} - -static int ebi2_lcd_remove(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd; - - mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); - - if (!mfd) - return 0; - - if (mfd->key != MFD_KEY) - return 0; - - iounmap(mfd->cmd_port); - pm_runtime_disable(&pdev->dev); - return 0; -} - -static int ebi2_lcd_register_driver(void) -{ - return platform_driver_register(&ebi2_lcd_driver); -} - -static int __init ebi2_lcd_driver_init(void) -{ - return ebi2_lcd_register_driver(); -} - -module_init(ebi2_lcd_driver_init); diff --git a/drivers/video/msm/ebi2_tmd20.c b/drivers/video/msm/ebi2_tmd20.c deleted file mode 100644 index 7c7b0efd3..000000000 --- a/drivers/video/msm/ebi2_tmd20.c +++ /dev/null @@ -1,1120 +0,0 @@ -/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "msm_fb.h" - -#include -#include -#include -#include -#include -#include -#include "linux/proc_fs.h" - -#include - -#include -#include - -#include -#include - -/* #define TMD20QVGA_LCD_18BPP */ -#define QVGA_WIDTH 240 -#define QVGA_HEIGHT 320 - -#ifdef TMD20QVGA_LCD_18BPP -#define DISP_QVGA_18BPP(x) ((((x)<<2) & 0x3FC00)|(( (x)<<1)& 0x1FE)) -#define DISP_REG(name) uint32 register_##name; -#define OUTPORT(x, y) outpdw(x, y) -#define INPORT(x) inpdw(x) -#else -#define DISP_QVGA_18BPP(x) (x) -#define DISP_REG(name) uint16 register_##name; -#define OUTPORT(x, y) outpw(x, y) -#define INPORT(x) intpw(x) -#endif - -static void *DISP_CMD_PORT; -static void *DISP_DATA_PORT; - -#define DISP_RNTI 0x10 - -#define DISP_CMD_OUT(cmd) OUTPORT(DISP_CMD_PORT, DISP_QVGA_18BPP(cmd)) -#define DISP_DATA_OUT(data) OUTPORT(DISP_DATA_PORT, data) -#define DISP_DATA_IN() INPORT(DISP_DATA_PORT) - -#if (defined(TMD20QVGA_LCD_18BPP)) -#define DISP_DATA_OUT_16TO18BPP(x) \ - DISP_DATA_OUT((((x)&0xf800)<<2|((x)&0x80000)>>3) \ - | (((x)&0x7e0)<<1) \ - | (((x)&0x1F)<<1|((x)&0x10)>>4)) -#else -#define DISP_DATA_OUT_16TO18BPP(x) \ - DISP_DATA_OUT(x) -#endif - -#define DISP_WRITE_OUT(addr, data) \ - register_##addr = DISP_QVGA_18BPP(data); \ - DISP_CMD_OUT(addr); \ - DISP_DATA_OUT(register_##addr); - -#define DISP_UPDATE_VALUE(addr, bitmask, data) \ - DISP_WRITE_OUT(##addr, (register_##addr & ~(bitmask)) | (data)); - -#define DISP_VAL_IF(bitvalue, bitmask) \ - ((bitvalue) ? (bitmask) : 0) - -/* QVGA = 256 x 320 */ -/* actual display is 240 x 320...offset by 0x10 */ -#define DISP_ROW_COL_TO_ADDR(row, col) ((row) * 0x100 + col) -#define DISP_SET_RECT(ulhc_row, lrhc_row, ulhc_col, lrhc_col) \ - { \ - DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \ - DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, (lrhc_col) + tmd20qvga_panel_offset); \ - DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, (ulhc_row)); \ - DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, (lrhc_row)); \ - DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \ - DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, (ulhc_row)); \ - } - -#define WAIT_MSEC(msec) mdelay(msec) - -/* - * TMD QVGA Address - */ -/* Display Control */ -#define DISP_START_OSCILLATION_ADDR 0x000 -DISP_REG(DISP_START_OSCILLATION_ADDR) -#define DISP_DRIVER_OUTPUT_CTL_ADDR 0x001 - DISP_REG(DISP_DRIVER_OUTPUT_CTL_ADDR) -#define DISP_LCD_DRIVING_SIG_ADDR 0x002 - DISP_REG(DISP_LCD_DRIVING_SIG_ADDR) -#define DISP_ENTRY_MODE_ADDR 0x003 - DISP_REG(DISP_ENTRY_MODE_ADDR) -#define DISP_DISPLAY_CTL_1_ADDR 0x007 - DISP_REG(DISP_DISPLAY_CTL_1_ADDR) -#define DISP_DISPLAY_CTL_2_ADDR 0x008 - DISP_REG(DISP_DISPLAY_CTL_2_ADDR) - -/* DISPLAY MODE 0x009 partial display not supported */ -#define DISP_POWER_SUPPLY_INTF_ADDR 0x00A - DISP_REG(DISP_POWER_SUPPLY_INTF_ADDR) - -/* DISPLAY MODE 0x00B xZoom feature is not supported */ -#define DISP_EXT_DISPLAY_CTL_1_ADDR 0x00C - DISP_REG(DISP_EXT_DISPLAY_CTL_1_ADDR) - -#define DISP_FRAME_CYCLE_CTL_ADDR 0x00D - DISP_REG(DISP_FRAME_CYCLE_CTL_ADDR) - -#define DISP_EXT_DISPLAY_CTL_2_ADDR 0x00E - DISP_REG(DISP_EXT_DISPLAY_CTL_2_ADDR) - -#define DISP_EXT_DISPLAY_CTL_3_ADDR 0x00F - DISP_REG(DISP_EXT_DISPLAY_CTL_3_ADDR) - -#define DISP_LTPS_CTL_1_ADDR 0x012 - DISP_REG(DISP_LTPS_CTL_1_ADDR) -#define DISP_LTPS_CTL_2_ADDR 0x013 - DISP_REG(DISP_LTPS_CTL_2_ADDR) -#define DISP_LTPS_CTL_3_ADDR 0x014 - DISP_REG(DISP_LTPS_CTL_3_ADDR) -#define DISP_LTPS_CTL_4_ADDR 0x018 - DISP_REG(DISP_LTPS_CTL_4_ADDR) -#define DISP_LTPS_CTL_5_ADDR 0x019 - DISP_REG(DISP_LTPS_CTL_5_ADDR) -#define DISP_LTPS_CTL_6_ADDR 0x01A - DISP_REG(DISP_LTPS_CTL_6_ADDR) -#define DISP_AMP_SETTING_ADDR 0x01C - DISP_REG(DISP_AMP_SETTING_ADDR) -#define DISP_MODE_SETTING_ADDR 0x01D - DISP_REG(DISP_MODE_SETTING_ADDR) -#define DISP_POFF_LN_SETTING_ADDR 0x01E - DISP_REG(DISP_POFF_LN_SETTING_ADDR) -/* Power Contol */ -#define DISP_POWER_CTL_1_ADDR 0x100 - DISP_REG(DISP_POWER_CTL_1_ADDR) -#define DISP_POWER_CTL_2_ADDR 0x101 - DISP_REG(DISP_POWER_CTL_2_ADDR) -#define DISP_POWER_CTL_3_ADDR 0x102 - DISP_REG(DISP_POWER_CTL_3_ADDR) -#define DISP_POWER_CTL_4_ADDR 0x103 - DISP_REG(DISP_POWER_CTL_4_ADDR) -#define DISP_POWER_CTL_5_ADDR 0x104 - DISP_REG(DISP_POWER_CTL_5_ADDR) -#define DISP_POWER_CTL_6_ADDR 0x105 - DISP_REG(DISP_POWER_CTL_6_ADDR) -#define DISP_POWER_CTL_7_ADDR 0x106 - DISP_REG(DISP_POWER_CTL_7_ADDR) -/* RAM Access */ -#define DISP_RAM_ADDR_SET_1_ADDR 0x200 - DISP_REG(DISP_RAM_ADDR_SET_1_ADDR) -#define DISP_RAM_ADDR_SET_2_ADDR 0x201 - DISP_REG(DISP_RAM_ADDR_SET_2_ADDR) -#define DISP_CMD_RAMRD DISP_CMD_RAMWR -#define DISP_CMD_RAMWR 0x202 - DISP_REG(DISP_CMD_RAMWR) -#define DISP_RAM_DATA_MASK_1_ADDR 0x203 - DISP_REG(DISP_RAM_DATA_MASK_1_ADDR) -#define DISP_RAM_DATA_MASK_2_ADDR 0x204 - DISP_REG(DISP_RAM_DATA_MASK_2_ADDR) -/* Gamma Control, Contrast, Gray Scale Setting */ -#define DISP_GAMMA_CONTROL_1_ADDR 0x300 - DISP_REG(DISP_GAMMA_CONTROL_1_ADDR) -#define DISP_GAMMA_CONTROL_2_ADDR 0x301 - DISP_REG(DISP_GAMMA_CONTROL_2_ADDR) -#define DISP_GAMMA_CONTROL_3_ADDR 0x302 - DISP_REG(DISP_GAMMA_CONTROL_3_ADDR) -#define DISP_GAMMA_CONTROL_4_ADDR 0x303 - DISP_REG(DISP_GAMMA_CONTROL_4_ADDR) -#define DISP_GAMMA_CONTROL_5_ADDR 0x304 - DISP_REG(DISP_GAMMA_CONTROL_5_ADDR) -/* Coordinate Control */ -#define DISP_VERT_SCROLL_CTL_1_ADDR 0x400 - DISP_REG(DISP_VERT_SCROLL_CTL_1_ADDR) -#define DISP_VERT_SCROLL_CTL_2_ADDR 0x401 - DISP_REG(DISP_VERT_SCROLL_CTL_2_ADDR) -#define DISP_SCREEN_1_DRV_POS_1_ADDR 0x402 - DISP_REG(DISP_SCREEN_1_DRV_POS_1_ADDR) -#define DISP_SCREEN_1_DRV_POS_2_ADDR 0x403 - DISP_REG(DISP_SCREEN_1_DRV_POS_2_ADDR) -#define DISP_SCREEN_2_DRV_POS_1_ADDR 0x404 - DISP_REG(DISP_SCREEN_2_DRV_POS_1_ADDR) -#define DISP_SCREEN_2_DRV_POS_2_ADDR 0x405 - DISP_REG(DISP_SCREEN_2_DRV_POS_2_ADDR) -#define DISP_HORZ_RAM_ADDR_POS_1_ADDR 0x406 - DISP_REG(DISP_HORZ_RAM_ADDR_POS_1_ADDR) -#define DISP_HORZ_RAM_ADDR_POS_2_ADDR 0x407 - DISP_REG(DISP_HORZ_RAM_ADDR_POS_2_ADDR) -#define DISP_VERT_RAM_ADDR_POS_1_ADDR 0x408 - DISP_REG(DISP_VERT_RAM_ADDR_POS_1_ADDR) -#define DISP_VERT_RAM_ADDR_POS_2_ADDR 0x409 - DISP_REG(DISP_VERT_RAM_ADDR_POS_2_ADDR) -#define DISP_TMD_700_ADDR 0x700 /* 0x700 */ - DISP_REG(DISP_TMD_700_ADDR) -#define DISP_TMD_015_ADDR 0x015 /* 0x700 */ - DISP_REG(DISP_TMD_015_ADDR) -#define DISP_TMD_305_ADDR 0x305 /* 0x700 */ - DISP_REG(DISP_TMD_305_ADDR) - -/* - * TMD QVGA Bit Definations - */ - -#define DISP_BIT_IB15 0x8000 -#define DISP_BIT_IB14 0x4000 -#define DISP_BIT_IB13 0x2000 -#define DISP_BIT_IB12 0x1000 -#define DISP_BIT_IB11 0x0800 -#define DISP_BIT_IB10 0x0400 -#define DISP_BIT_IB09 0x0200 -#define DISP_BIT_IB08 0x0100 -#define DISP_BIT_IB07 0x0080 -#define DISP_BIT_IB06 0x0040 -#define DISP_BIT_IB05 0x0020 -#define DISP_BIT_IB04 0x0010 -#define DISP_BIT_IB03 0x0008 -#define DISP_BIT_IB02 0x0004 -#define DISP_BIT_IB01 0x0002 -#define DISP_BIT_IB00 0x0001 -/* - * Display Control - * DISP_START_OSCILLATION_ADDR Start Oscillation - * DISP_DRIVER_OUTPUT_CTL_ADDR Driver Output Control - */ -#define DISP_BITMASK_SS DISP_BIT_IB08 -#define DISP_BITMASK_NL5 DISP_BIT_IB05 -#define DISP_BITMASK_NL4 DISP_BIT_IB04 -#define DISP_BITMASK_NL3 DISP_BIT_IB03 -#define DISP_BITMASK_NL2 DISP_BIT_IB02 -#define DISP_BITMASK_NL1 DISP_BIT_IB01 -#define DISP_BITMASK_NL0 DISP_BIT_IB00 -/* DISP_LCD_DRIVING_SIG_ADDR LCD Driving Signal Setting */ -#define DISP_BITMASK_BC DISP_BIT_IB09 -/* DISP_ENTRY_MODE_ADDR Entry Mode */ -#define DISP_BITMASK_TRI DISP_BIT_IB15 -#define DISP_BITMASK_DFM1 DISP_BIT_IB14 -#define DISP_BITMASK_DFM0 DISP_BIT_IB13 -#define DISP_BITMASK_BGR DISP_BIT_IB12 -#define DISP_BITMASK_HWM0 DISP_BIT_IB08 -#define DISP_BITMASK_ID1 DISP_BIT_IB05 -#define DISP_BITMASK_ID0 DISP_BIT_IB04 -#define DISP_BITMASK_AM DISP_BIT_IB03 -/* DISP_DISPLAY_CTL_1_ADDR Display Control (1) */ -#define DISP_BITMASK_COL1 DISP_BIT_IB15 -#define DISP_BITMASK_COL0 DISP_BIT_IB14 -#define DISP_BITMASK_VLE2 DISP_BIT_IB10 -#define DISP_BITMASK_VLE1 DISP_BIT_IB09 -#define DISP_BITMASK_SPT DISP_BIT_IB08 -#define DISP_BITMASK_PT1 DISP_BIT_IB07 -#define DISP_BITMASK_PT0 DISP_BIT_IB06 -#define DISP_BITMASK_REV DISP_BIT_IB02 -/* DISP_DISPLAY_CTL_2_ADDR Display Control (2) */ -#define DISP_BITMASK_FP3 DISP_BIT_IB11 -#define DISP_BITMASK_FP2 DISP_BIT_IB10 -#define DISP_BITMASK_FP1 DISP_BIT_IB09 -#define DISP_BITMASK_FP0 DISP_BIT_IB08 -#define DISP_BITMASK_BP3 DISP_BIT_IB03 -#define DISP_BITMASK_BP2 DISP_BIT_IB02 -#define DISP_BITMASK_BP1 DISP_BIT_IB01 -#define DISP_BITMASK_BP0 DISP_BIT_IB00 -/* DISP_POWER_SUPPLY_INTF_ADDR Power Supply IC Interface Control */ -#define DISP_BITMASK_CSE DISP_BIT_IB12 -#define DISP_BITMASK_TE DISP_BIT_IB08 -#define DISP_BITMASK_IX3 DISP_BIT_IB03 -#define DISP_BITMASK_IX2 DISP_BIT_IB02 -#define DISP_BITMASK_IX1 DISP_BIT_IB01 -#define DISP_BITMASK_IX0 DISP_BIT_IB00 -/* DISP_EXT_DISPLAY_CTL_1_ADDR External Display Interface Control (1) */ -#define DISP_BITMASK_RM DISP_BIT_IB08 -#define DISP_BITMASK_DM1 DISP_BIT_IB05 -#define DISP_BITMASK_DM0 DISP_BIT_IB04 -#define DISP_BITMASK_RIM1 DISP_BIT_IB01 -#define DISP_BITMASK_RIM0 DISP_BIT_IB00 -/* DISP_FRAME_CYCLE_CTL_ADDR Frame Frequency Adjustment Control */ -#define DISP_BITMASK_DIVI1 DISP_BIT_IB09 -#define DISP_BITMASK_DIVI0 DISP_BIT_IB08 -#define DISP_BITMASK_RTNI4 DISP_BIT_IB04 -#define DISP_BITMASK_RTNI3 DISP_BIT_IB03 -#define DISP_BITMASK_RTNI2 DISP_BIT_IB02 -#define DISP_BITMASK_RTNI1 DISP_BIT_IB01 -#define DISP_BITMASK_RTNI0 DISP_BIT_IB00 -/* DISP_EXT_DISPLAY_CTL_2_ADDR External Display Interface Control (2) */ -#define DISP_BITMASK_DIVE1 DISP_BIT_IB09 -#define DISP_BITMASK_DIVE0 DISP_BIT_IB08 -#define DISP_BITMASK_RTNE7 DISP_BIT_IB07 -#define DISP_BITMASK_RTNE6 DISP_BIT_IB06 -#define DISP_BITMASK_RTNE5 DISP_BIT_IB05 -#define DISP_BITMASK_RTNE4 DISP_BIT_IB04 -#define DISP_BITMASK_RTNE3 DISP_BIT_IB03 -#define DISP_BITMASK_RTNE2 DISP_BIT_IB02 -#define DISP_BITMASK_RTNE1 DISP_BIT_IB01 -#define DISP_BITMASK_RTNE0 DISP_BIT_IB00 -/* DISP_EXT_DISPLAY_CTL_3_ADDR External Display Interface Control (3) */ -#define DISP_BITMASK_VSPL DISP_BIT_IB04 -#define DISP_BITMASK_HSPL DISP_BIT_IB03 -#define DISP_BITMASK_VPL DISP_BIT_IB02 -#define DISP_BITMASK_EPL DISP_BIT_IB01 -#define DISP_BITMASK_DPL DISP_BIT_IB00 -/* DISP_LTPS_CTL_1_ADDR LTPS Interface Control (1) */ -#define DISP_BITMASK_CLWI3 DISP_BIT_IB11 -#define DISP_BITMASK_CLWI2 DISP_BIT_IB10 -#define DISP_BITMASK_CLWI1 DISP_BIT_IB09 -#define DISP_BITMASK_CLWI0 DISP_BIT_IB08 -#define DISP_BITMASK_CLTI1 DISP_BIT_IB01 -#define DISP_BITMASK_CLTI0 DISP_BIT_IB00 -/* DISP_LTPS_CTL_2_ADDR LTPS Interface Control (2) */ -#define DISP_BITMASK_OEVBI1 DISP_BIT_IB09 -#define DISP_BITMASK_OEVBI0 DISP_BIT_IB08 -#define DISP_BITMASK_OEVFI1 DISP_BIT_IB01 -#define DISP_BITMASK_OEVFI0 DISP_BIT_IB00 -/* DISP_LTPS_CTL_3_ADDR LTPS Interface Control (3) */ -#define DISP_BITMASK_SHI1 DISP_BIT_IB01 -#define DISP_BITMASK_SHI0 DISP_BIT_IB00 -/* DISP_LTPS_CTL_4_ADDR LTPS Interface Control (4) */ -#define DISP_BITMASK_CLWE5 DISP_BIT_IB13 -#define DISP_BITMASK_CLWE4 DISP_BIT_IB12 -#define DISP_BITMASK_CLWE3 DISP_BIT_IB11 -#define DISP_BITMASK_CLWE2 DISP_BIT_IB10 -#define DISP_BITMASK_CLWE1 DISP_BIT_IB09 -#define DISP_BITMASK_CLWE0 DISP_BIT_IB08 -#define DISP_BITMASK_CLTE3 DISP_BIT_IB03 -#define DISP_BITMASK_CLTE2 DISP_BIT_IB02 -#define DISP_BITMASK_CLTE1 DISP_BIT_IB01 -#define DISP_BITMASK_CLTE0 DISP_BIT_IB00 -/* DISP_LTPS_CTL_5_ADDR LTPS Interface Control (5) */ -#define DISP_BITMASK_OEVBE3 DISP_BIT_IB11 -#define DISP_BITMASK_OEVBE2 DISP_BIT_IB10 -#define DISP_BITMASK_OEVBE1 DISP_BIT_IB09 -#define DISP_BITMASK_OEVBE0 DISP_BIT_IB08 -#define DISP_BITMASK_OEVFE3 DISP_BIT_IB03 -#define DISP_BITMASK_OEVFE2 DISP_BIT_IB02 -#define DISP_BITMASK_OEVFE1 DISP_BIT_IB01 -#define DISP_BITMASK_OEVFE0 DISP_BIT_IB00 -/* DISP_LTPS_CTL_6_ADDR LTPS Interface Control (6) */ -#define DISP_BITMASK_SHE3 DISP_BIT_IB03 -#define DISP_BITMASK_SHE2 DISP_BIT_IB02 -#define DISP_BITMASK_SHE1 DISP_BIT_IB01 -#define DISP_BITMASK_SHE0 DISP_BIT_IB00 -/* DISP_AMP_SETTING_ADDR Amplify Setting */ -#define DISP_BITMASK_ABSW1 DISP_BIT_IB01 -#define DISP_BITMASK_ABSW0 DISP_BIT_IB00 -/* DISP_MODE_SETTING_ADDR Mode Setting */ -#define DISP_BITMASK_DSTB DISP_BIT_IB02 -#define DISP_BITMASK_STB DISP_BIT_IB00 -/* DISP_POFF_LN_SETTING_ADDR Power Off Line Setting */ -#define DISP_BITMASK_POFH3 DISP_BIT_IB03 -#define DISP_BITMASK_POFH2 DISP_BIT_IB02 -#define DISP_BITMASK_POFH1 DISP_BIT_IB01 -#define DISP_BITMASK_POFH0 DISP_BIT_IB00 - -/* Power Contol */ -/* DISP_POWER_CTL_1_ADDR Power Control (1) */ -#define DISP_BITMASK_PO DISP_BIT_IB11 -#define DISP_BITMASK_VCD DISP_BIT_IB09 -#define DISP_BITMASK_VSC DISP_BIT_IB08 -#define DISP_BITMASK_CON DISP_BIT_IB07 -#define DISP_BITMASK_ASW1 DISP_BIT_IB06 -#define DISP_BITMASK_ASW0 DISP_BIT_IB05 -#define DISP_BITMASK_OEV DISP_BIT_IB04 -#define DISP_BITMASK_OEVE DISP_BIT_IB03 -#define DISP_BITMASK_FR DISP_BIT_IB02 -#define DISP_BITMASK_D1 DISP_BIT_IB01 -#define DISP_BITMASK_D0 DISP_BIT_IB00 -/* DISP_POWER_CTL_2_ADDR Power Control (2) */ -#define DISP_BITMASK_DC4 DISP_BIT_IB15 -#define DISP_BITMASK_DC3 DISP_BIT_IB14 -#define DISP_BITMASK_SAP2 DISP_BIT_IB13 -#define DISP_BITMASK_SAP1 DISP_BIT_IB12 -#define DISP_BITMASK_SAP0 DISP_BIT_IB11 -#define DISP_BITMASK_BT2 DISP_BIT_IB10 -#define DISP_BITMASK_BT1 DISP_BIT_IB09 -#define DISP_BITMASK_BT0 DISP_BIT_IB08 -#define DISP_BITMASK_DC2 DISP_BIT_IB07 -#define DISP_BITMASK_DC1 DISP_BIT_IB06 -#define DISP_BITMASK_DC0 DISP_BIT_IB05 -#define DISP_BITMASK_AP2 DISP_BIT_IB04 -#define DISP_BITMASK_AP1 DISP_BIT_IB03 -#define DISP_BITMASK_AP0 DISP_BIT_IB02 -/* DISP_POWER_CTL_3_ADDR Power Control (3) */ -#define DISP_BITMASK_VGL4 DISP_BIT_IB10 -#define DISP_BITMASK_VGL3 DISP_BIT_IB09 -#define DISP_BITMASK_VGL2 DISP_BIT_IB08 -#define DISP_BITMASK_VGL1 DISP_BIT_IB07 -#define DISP_BITMASK_VGL0 DISP_BIT_IB06 -#define DISP_BITMASK_VGH4 DISP_BIT_IB04 -#define DISP_BITMASK_VGH3 DISP_BIT_IB03 -#define DISP_BITMASK_VGH2 DISP_BIT_IB02 -#define DISP_BITMASK_VGH1 DISP_BIT_IB01 -#define DISP_BITMASK_VGH0 DISP_BIT_IB00 -/* DISP_POWER_CTL_4_ADDR Power Control (4) */ -#define DISP_BITMASK_VC2 DISP_BIT_IB02 -#define DISP_BITMASK_VC1 DISP_BIT_IB01 -#define DISP_BITMASK_VC0 DISP_BIT_IB00 -/* DISP_POWER_CTL_5_ADDR Power Control (5) */ -#define DISP_BITMASK_VRL3 DISP_BIT_IB11 -#define DISP_BITMASK_VRL2 DISP_BIT_IB10 -#define DISP_BITMASK_VRL1 DISP_BIT_IB09 -#define DISP_BITMASK_VRL0 DISP_BIT_IB08 -#define DISP_BITMASK_PON DISP_BIT_IB04 -#define DISP_BITMASK_VRH3 DISP_BIT_IB03 -#define DISP_BITMASK_VRH2 DISP_BIT_IB02 -#define DISP_BITMASK_VRH1 DISP_BIT_IB01 -#define DISP_BITMASK_VRH0 DISP_BIT_IB00 -/* DISP_POWER_CTL_6_ADDR Power Control (6) */ -#define DISP_BITMASK_VCOMG DISP_BIT_IB13 -#define DISP_BITMASK_VDV4 DISP_BIT_IB12 -#define DISP_BITMASK_VDV3 DISP_BIT_IB11 -#define DISP_BITMASK_VDV2 DISP_BIT_IB10 -#define DISP_BITMASK_VDV1 DISP_BIT_IB09 -#define DISP_BITMASK_VDV0 DISP_BIT_IB08 -#define DISP_BITMASK_VCM4 DISP_BIT_IB04 -#define DISP_BITMASK_VCM3 DISP_BIT_IB03 -#define DISP_BITMASK_VCM2 DISP_BIT_IB02 -#define DISP_BITMASK_VCM1 DISP_BIT_IB01 -#define DISP_BITMASK_VCM0 DISP_BIT_IB00 -/* RAM Access */ -/* DISP_RAM_ADDR_SET_1_ADDR RAM Address Set (1) */ -#define DISP_BITMASK_AD7 DISP_BIT_IB07 -#define DISP_BITMASK_AD6 DISP_BIT_IB06 -#define DISP_BITMASK_AD5 DISP_BIT_IB05 -#define DISP_BITMASK_AD4 DISP_BIT_IB04 -#define DISP_BITMASK_AD3 DISP_BIT_IB03 -#define DISP_BITMASK_AD2 DISP_BIT_IB02 -#define DISP_BITMASK_AD1 DISP_BIT_IB01 -#define DISP_BITMASK_AD0 DISP_BIT_IB00 -/* DISP_RAM_ADDR_SET_2_ADDR RAM Address Set (2) */ -#define DISP_BITMASK_AD16 DISP_BIT_IB08 -#define DISP_BITMASK_AD15 DISP_BIT_IB07 -#define DISP_BITMASK_AD14 DISP_BIT_IB06 -#define DISP_BITMASK_AD13 DISP_BIT_IB05 -#define DISP_BITMASK_AD12 DISP_BIT_IB04 -#define DISP_BITMASK_AD11 DISP_BIT_IB03 -#define DISP_BITMASK_AD10 DISP_BIT_IB02 -#define DISP_BITMASK_AD9 DISP_BIT_IB01 -#define DISP_BITMASK_AD8 DISP_BIT_IB00 -/* - * DISP_CMD_RAMWR RAM Data Read/Write - * Use Data Bit Configuration - */ -/* DISP_RAM_DATA_MASK_1_ADDR RAM Write Data Mask (1) */ -#define DISP_BITMASK_WM11 DISP_BIT_IB13 -#define DISP_BITMASK_WM10 DISP_BIT_IB12 -#define DISP_BITMASK_WM9 DISP_BIT_IB11 -#define DISP_BITMASK_WM8 DISP_BIT_IB10 -#define DISP_BITMASK_WM7 DISP_BIT_IB09 -#define DISP_BITMASK_WM6 DISP_BIT_IB08 -#define DISP_BITMASK_WM5 DISP_BIT_IB05 -#define DISP_BITMASK_WM4 DISP_BIT_IB04 -#define DISP_BITMASK_WM3 DISP_BIT_IB03 -#define DISP_BITMASK_WM2 DISP_BIT_IB02 -#define DISP_BITMASK_WM1 DISP_BIT_IB01 -#define DISP_BITMASK_WM0 DISP_BIT_IB00 -/* DISP_RAM_DATA_MASK_2_ADDR RAM Write Data Mask (2) */ -#define DISP_BITMASK_WM17 DISP_BIT_IB05 -#define DISP_BITMASK_WM16 DISP_BIT_IB04 -#define DISP_BITMASK_WM15 DISP_BIT_IB03 -#define DISP_BITMASK_WM14 DISP_BIT_IB02 -#define DISP_BITMASK_WM13 DISP_BIT_IB01 -#define DISP_BITMASK_WM12 DISP_BIT_IB00 -/*Gamma Control */ -/* DISP_GAMMA_CONTROL_1_ADDR Gamma Control (1) */ -#define DISP_BITMASK_PKP12 DISP_BIT_IB10 -#define DISP_BITMASK_PKP11 DISP_BIT_IB08 -#define DISP_BITMASK_PKP10 DISP_BIT_IB09 -#define DISP_BITMASK_PKP02 DISP_BIT_IB02 -#define DISP_BITMASK_PKP01 DISP_BIT_IB01 -#define DISP_BITMASK_PKP00 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_2_ADDR Gamma Control (2) */ -#define DISP_BITMASK_PKP32 DISP_BIT_IB10 -#define DISP_BITMASK_PKP31 DISP_BIT_IB09 -#define DISP_BITMASK_PKP30 DISP_BIT_IB08 -#define DISP_BITMASK_PKP22 DISP_BIT_IB02 -#define DISP_BITMASK_PKP21 DISP_BIT_IB01 -#define DISP_BITMASK_PKP20 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_3_ADDR Gamma Control (3) */ -#define DISP_BITMASK_PKP52 DISP_BIT_IB10 -#define DISP_BITMASK_PKP51 DISP_BIT_IB09 -#define DISP_BITMASK_PKP50 DISP_BIT_IB08 -#define DISP_BITMASK_PKP42 DISP_BIT_IB02 -#define DISP_BITMASK_PKP41 DISP_BIT_IB01 -#define DISP_BITMASK_PKP40 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_4_ADDR Gamma Control (4) */ -#define DISP_BITMASK_PRP12 DISP_BIT_IB10 -#define DISP_BITMASK_PRP11 DISP_BIT_IB08 -#define DISP_BITMASK_PRP10 DISP_BIT_IB09 -#define DISP_BITMASK_PRP02 DISP_BIT_IB02 -#define DISP_BITMASK_PRP01 DISP_BIT_IB01 -#define DISP_BITMASK_PRP00 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_5_ADDR Gamma Control (5) */ -#define DISP_BITMASK_VRP14 DISP_BIT_IB12 -#define DISP_BITMASK_VRP13 DISP_BIT_IB11 -#define DISP_BITMASK_VRP12 DISP_BIT_IB10 -#define DISP_BITMASK_VRP11 DISP_BIT_IB08 -#define DISP_BITMASK_VRP10 DISP_BIT_IB09 -#define DISP_BITMASK_VRP03 DISP_BIT_IB03 -#define DISP_BITMASK_VRP02 DISP_BIT_IB02 -#define DISP_BITMASK_VRP01 DISP_BIT_IB01 -#define DISP_BITMASK_VRP00 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_6_ADDR Gamma Control (6) */ -#define DISP_BITMASK_PKN12 DISP_BIT_IB10 -#define DISP_BITMASK_PKN11 DISP_BIT_IB08 -#define DISP_BITMASK_PKN10 DISP_BIT_IB09 -#define DISP_BITMASK_PKN02 DISP_BIT_IB02 -#define DISP_BITMASK_PKN01 DISP_BIT_IB01 -#define DISP_BITMASK_PKN00 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_7_ADDR Gamma Control (7) */ -#define DISP_BITMASK_PKN32 DISP_BIT_IB10 -#define DISP_BITMASK_PKN31 DISP_BIT_IB08 -#define DISP_BITMASK_PKN30 DISP_BIT_IB09 -#define DISP_BITMASK_PKN22 DISP_BIT_IB02 -#define DISP_BITMASK_PKN21 DISP_BIT_IB01 -#define DISP_BITMASK_PKN20 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_8_ADDR Gamma Control (8) */ -#define DISP_BITMASK_PKN52 DISP_BIT_IB10 -#define DISP_BITMASK_PKN51 DISP_BIT_IB08 -#define DISP_BITMASK_PKN50 DISP_BIT_IB09 -#define DISP_BITMASK_PKN42 DISP_BIT_IB02 -#define DISP_BITMASK_PKN41 DISP_BIT_IB01 -#define DISP_BITMASK_PKN40 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_9_ADDR Gamma Control (9) */ -#define DISP_BITMASK_PRN12 DISP_BIT_IB10 -#define DISP_BITMASK_PRN11 DISP_BIT_IB08 -#define DISP_BITMASK_PRN10 DISP_BIT_IB09 -#define DISP_BITMASK_PRN02 DISP_BIT_IB02 -#define DISP_BITMASK_PRN01 DISP_BIT_IB01 -#define DISP_BITMASK_PRN00 DISP_BIT_IB00 -/* DISP_GAMMA_CONTROL_10_ADDR Gamma Control (10) */ -#define DISP_BITMASK_VRN14 DISP_BIT_IB12 -#define DISP_BITMASK_VRN13 DISP_BIT_IB11 -#define DISP_BITMASK_VRN12 DISP_BIT_IB10 -#define DISP_BITMASK_VRN11 DISP_BIT_IB08 -#define DISP_BITMASK_VRN10 DISP_BIT_IB09 -#define DISP_BITMASK_VRN03 DISP_BIT_IB03 -#define DISP_BITMASK_VRN02 DISP_BIT_IB02 -#define DISP_BITMASK_VRN01 DISP_BIT_IB01 -#define DISP_BITMASK_VRN00 DISP_BIT_IB00 -/* Coordinate Control */ -/* DISP_VERT_SCROLL_CTL_1_ADDR Vertical Scroll Control (1) */ -#define DISP_BITMASK_VL18 DISP_BIT_IB08 -#define DISP_BITMASK_VL17 DISP_BIT_IB07 -#define DISP_BITMASK_VL16 DISP_BIT_IB06 -#define DISP_BITMASK_VL15 DISP_BIT_IB05 -#define DISP_BITMASK_VL14 DISP_BIT_IB04 -#define DISP_BITMASK_VL13 DISP_BIT_IB03 -#define DISP_BITMASK_VL12 DISP_BIT_IB02 -#define DISP_BITMASK_VL11 DISP_BIT_IB01 -#define DISP_BITMASK_VL10 DISP_BIT_IB00 -/* DISP_VERT_SCROLL_CTL_2_ADDR Vertical Scroll Control (2) */ -#define DISP_BITMASK_VL28 DISP_BIT_IB08 -#define DISP_BITMASK_VL27 DISP_BIT_IB07 -#define DISP_BITMASK_VL26 DISP_BIT_IB06 -#define DISP_BITMASK_VL25 DISP_BIT_IB05 -#define DISP_BITMASK_VL24 DISP_BIT_IB04 -#define DISP_BITMASK_VL23 DISP_BIT_IB03 -#define DISP_BITMASK_VL22 DISP_BIT_IB02 -#define DISP_BITMASK_VL21 DISP_BIT_IB01 -#define DISP_BITMASK_VL20 DISP_BIT_IB00 -/* DISP_SCREEN_1_DRV_POS_1_ADDR First Screen Driving Position (1) */ -#define DISP_BITMASK_SS18 DISP_BIT_IB08 -#define DISP_BITMASK_SS17 DISP_BIT_IB07 -#define DISP_BITMASK_SS16 DISP_BIT_IB06 -#define DISP_BITMASK_SS15 DISP_BIT_IB05 -#define DISP_BITMASK_SS14 DISP_BIT_IB04 -#define DISP_BITMASK_SS13 DISP_BIT_IB03 -#define DISP_BITMASK_SS12 DISP_BIT_IB02 -#define DISP_BITMASK_SS11 DISP_BIT_IB01 -#define DISP_BITMASK_SS10 DISP_BIT_IB00 -/* DISP_SCREEN_1_DRV_POS_2_ADDR First Screen Driving Position (2) */ -#define DISP_BITMASK_SE18 DISP_BIT_IB08 -#define DISP_BITMASK_SE17 DISP_BIT_IB07 -#define DISP_BITMASK_SE16 DISP_BIT_IB06 -#define DISP_BITMASK_SE15 DISP_BIT_IB05 -#define DISP_BITMASK_SE14 DISP_BIT_IB04 -#define DISP_BITMASK_SE13 DISP_BIT_IB03 -#define DISP_BITMASK_SE12 DISP_BIT_IB02 -#define DISP_BITMASK_SE11 DISP_BIT_IB01 -#define DISP_BITMASK_SE10 DISP_BIT_IB00 -/* DISP_SCREEN_2_DRV_POS_1_ADDR Second Screen Driving Position (1) */ -#define DISP_BITMASK_SS28 DISP_BIT_IB08 -#define DISP_BITMASK_SS27 DISP_BIT_IB07 -#define DISP_BITMASK_SS26 DISP_BIT_IB06 -#define DISP_BITMASK_SS25 DISP_BIT_IB05 -#define DISP_BITMASK_SS24 DISP_BIT_IB04 -#define DISP_BITMASK_SS23 DISP_BIT_IB03 -#define DISP_BITMASK_SS22 DISP_BIT_IB02 -#define DISP_BITMASK_SS21 DISP_BIT_IB01 -#define DISP_BITMASK_SS20 DISP_BIT_IB00 -/* DISP_SCREEN_3_DRV_POS_2_ADDR Second Screen Driving Position (2) */ -#define DISP_BITMASK_SE28 DISP_BIT_IB08 -#define DISP_BITMASK_SE27 DISP_BIT_IB07 -#define DISP_BITMASK_SE26 DISP_BIT_IB06 -#define DISP_BITMASK_SE25 DISP_BIT_IB05 -#define DISP_BITMASK_SE24 DISP_BIT_IB04 -#define DISP_BITMASK_SE23 DISP_BIT_IB03 -#define DISP_BITMASK_SE22 DISP_BIT_IB02 -#define DISP_BITMASK_SE21 DISP_BIT_IB01 -#define DISP_BITMASK_SE20 DISP_BIT_IB00 -/* DISP_HORZ_RAM_ADDR_POS_1_ADDR Horizontal RAM Address Position (1) */ -#define DISP_BITMASK_HSA7 DISP_BIT_IB07 -#define DISP_BITMASK_HSA6 DISP_BIT_IB06 -#define DISP_BITMASK_HSA5 DISP_BIT_IB05 -#define DISP_BITMASK_HSA4 DISP_BIT_IB04 -#define DISP_BITMASK_HSA3 DISP_BIT_IB03 -#define DISP_BITMASK_HSA2 DISP_BIT_IB02 -#define DISP_BITMASK_HSA1 DISP_BIT_IB01 -#define DISP_BITMASK_HSA0 DISP_BIT_IB00 -/* DISP_HORZ_RAM_ADDR_POS_2_ADDR Horizontal RAM Address Position (2) */ -#define DISP_BITMASK_HEA7 DISP_BIT_IB07 -#define DISP_BITMASK_HEA6 DISP_BIT_IB06 -#define DISP_BITMASK_HEA5 DISP_BIT_IB05 -#define DISP_BITMASK_HEA4 DISP_BIT_IB04 -#define DISP_BITMASK_HEA3 DISP_BIT_IB03 -#define DISP_BITMASK_HEA2 DISP_BIT_IB02 -#define DISP_BITMASK_HEA1 DISP_BIT_IB01 -#define DISP_BITMASK_HEA0 DISP_BIT_IB00 -/* DISP_VERT_RAM_ADDR_POS_1_ADDR Vertical RAM Address Position (1) */ -#define DISP_BITMASK_VSA8 DISP_BIT_IB08 -#define DISP_BITMASK_VSA7 DISP_BIT_IB07 -#define DISP_BITMASK_VSA6 DISP_BIT_IB06 -#define DISP_BITMASK_VSA5 DISP_BIT_IB05 -#define DISP_BITMASK_VSA4 DISP_BIT_IB04 -#define DISP_BITMASK_VSA3 DISP_BIT_IB03 -#define DISP_BITMASK_VSA2 DISP_BIT_IB02 -#define DISP_BITMASK_VSA1 DISP_BIT_IB01 -#define DISP_BITMASK_VSA0 DISP_BIT_IB00 -/* DISP_VERT_RAM_ADDR_POS_2_ADDR Vertical RAM Address Position (2) */ -#define DISP_BITMASK_VEA8 DISP_BIT_IB08 -#define DISP_BITMASK_VEA7 DISP_BIT_IB07 -#define DISP_BITMASK_VEA6 DISP_BIT_IB06 -#define DISP_BITMASK_VEA5 DISP_BIT_IB05 -#define DISP_BITMASK_VEA4 DISP_BIT_IB04 -#define DISP_BITMASK_VEA3 DISP_BIT_IB03 -#define DISP_BITMASK_VEA2 DISP_BIT_IB02 -#define DISP_BITMASK_VEA1 DISP_BIT_IB01 -#define DISP_BITMASK_VEA0 DISP_BIT_IB00 -static word disp_area_start_row; -static word disp_area_end_row; -static boolean disp_initialized = FALSE; -/* For some reason the contrast set at init time is not good. Need to do -* it again -*/ -static boolean display_on = FALSE; - -static uint32 tmd20qvga_lcd_rev; -uint16 tmd20qvga_panel_offset; - -#ifdef DISP_DEVICE_8BPP -static word convert_8_to_16_tbl[256] = { - 0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000, 0xE000, - 0x0100, 0x2100, 0x4100, 0x6100, 0x8100, 0xA100, 0xC100, 0xE100, - 0x0200, 0x2200, 0x4200, 0x6200, 0x8200, 0xA200, 0xC200, 0xE200, - 0x0300, 0x2300, 0x4300, 0x6300, 0x8300, 0xA300, 0xC300, 0xE300, - 0x0400, 0x2400, 0x4400, 0x6400, 0x8400, 0xA400, 0xC400, 0xE400, - 0x0500, 0x2500, 0x4500, 0x6500, 0x8500, 0xA500, 0xC500, 0xE500, - 0x0600, 0x2600, 0x4600, 0x6600, 0x8600, 0xA600, 0xC600, 0xE600, - 0x0700, 0x2700, 0x4700, 0x6700, 0x8700, 0xA700, 0xC700, 0xE700, - 0x0008, 0x2008, 0x4008, 0x6008, 0x8008, 0xA008, 0xC008, 0xE008, - 0x0108, 0x2108, 0x4108, 0x6108, 0x8108, 0xA108, 0xC108, 0xE108, - 0x0208, 0x2208, 0x4208, 0x6208, 0x8208, 0xA208, 0xC208, 0xE208, - 0x0308, 0x2308, 0x4308, 0x6308, 0x8308, 0xA308, 0xC308, 0xE308, - 0x0408, 0x2408, 0x4408, 0x6408, 0x8408, 0xA408, 0xC408, 0xE408, - 0x0508, 0x2508, 0x4508, 0x6508, 0x8508, 0xA508, 0xC508, 0xE508, - 0x0608, 0x2608, 0x4608, 0x6608, 0x8608, 0xA608, 0xC608, 0xE608, - 0x0708, 0x2708, 0x4708, 0x6708, 0x8708, 0xA708, 0xC708, 0xE708, - 0x0010, 0x2010, 0x4010, 0x6010, 0x8010, 0xA010, 0xC010, 0xE010, - 0x0110, 0x2110, 0x4110, 0x6110, 0x8110, 0xA110, 0xC110, 0xE110, - 0x0210, 0x2210, 0x4210, 0x6210, 0x8210, 0xA210, 0xC210, 0xE210, - 0x0310, 0x2310, 0x4310, 0x6310, 0x8310, 0xA310, 0xC310, 0xE310, - 0x0410, 0x2410, 0x4410, 0x6410, 0x8410, 0xA410, 0xC410, 0xE410, - 0x0510, 0x2510, 0x4510, 0x6510, 0x8510, 0xA510, 0xC510, 0xE510, - 0x0610, 0x2610, 0x4610, 0x6610, 0x8610, 0xA610, 0xC610, 0xE610, - 0x0710, 0x2710, 0x4710, 0x6710, 0x8710, 0xA710, 0xC710, 0xE710, - 0x0018, 0x2018, 0x4018, 0x6018, 0x8018, 0xA018, 0xC018, 0xE018, - 0x0118, 0x2118, 0x4118, 0x6118, 0x8118, 0xA118, 0xC118, 0xE118, - 0x0218, 0x2218, 0x4218, 0x6218, 0x8218, 0xA218, 0xC218, 0xE218, - 0x0318, 0x2318, 0x4318, 0x6318, 0x8318, 0xA318, 0xC318, 0xE318, - 0x0418, 0x2418, 0x4418, 0x6418, 0x8418, 0xA418, 0xC418, 0xE418, - 0x0518, 0x2518, 0x4518, 0x6518, 0x8518, 0xA518, 0xC518, 0xE518, - 0x0618, 0x2618, 0x4618, 0x6618, 0x8618, 0xA618, 0xC618, 0xE618, - 0x0718, 0x2718, 0x4718, 0x6718, 0x8718, 0xA718, 0xC718, 0xE718 -}; -#endif /* DISP_DEVICE_8BPP */ - -static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres); -static void tmd20qvga_disp_init(struct platform_device *pdev); -static void tmd20qvga_disp_set_contrast(void); -static void tmd20qvga_disp_set_display_area(word start_row, word end_row); -static int tmd20qvga_disp_off(struct platform_device *pdev); -static int tmd20qvga_disp_on(struct platform_device *pdev); -static void tmd20qvga_set_revId(int); - -/* future use */ -void tmd20qvga_disp_clear_screen_area(word start_row, word end_row, - word start_column, word end_column); - -static void tmd20qvga_set_revId(int id) -{ - - tmd20qvga_lcd_rev = id; - - if (tmd20qvga_lcd_rev == 1) - tmd20qvga_panel_offset = 0x10; - else - tmd20qvga_panel_offset = 0; -} - -static void tmd20qvga_disp_init(struct platform_device *pdev) -{ - struct msm_fb_data_type *mfd; - - if (disp_initialized) - return; - - mfd = platform_get_drvdata(pdev); - - DISP_CMD_PORT = mfd->cmd_port; - DISP_DATA_PORT = mfd->data_port; - -#ifdef TMD20QVGA_LCD_18BPP - tmd20qvga_set_revId(2); -#else - tmd20qvga_set_revId(1); -#endif - - disp_initialized = TRUE; - tmd20qvga_disp_set_contrast(); - tmd20qvga_disp_set_display_area(0, QVGA_HEIGHT - 1); -} - -static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres) -{ - if (!disp_initialized) - return; - - DISP_SET_RECT(y, y + yres - 1, x, x + xres - 1); - - DISP_CMD_OUT(DISP_CMD_RAMWR); -} - -static void tmd20qvga_disp_set_display_area(word start_row, word end_row) -{ - word start_driving = start_row; - word end_driving = end_row; - - if (!disp_initialized) - return; - - /* Range checking - */ - if (end_driving >= QVGA_HEIGHT) - end_driving = QVGA_HEIGHT - 1; - if (start_driving > end_driving) { - /* Probably Backwards Switch */ - start_driving = end_driving; - end_driving = start_row; /* Has not changed */ - if (end_driving >= QVGA_HEIGHT) - end_driving = QVGA_HEIGHT - 1; - } - - if ((start_driving == disp_area_start_row) - && (end_driving == disp_area_end_row)) - return; - - disp_area_start_row = start_driving; - disp_area_end_row = end_driving; - - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, - DISP_VAL_IF(start_driving & 0x100, - DISP_BITMASK_SS18) | - DISP_VAL_IF(start_driving & 0x080, - DISP_BITMASK_SS17) | - DISP_VAL_IF(start_driving & 0x040, - DISP_BITMASK_SS16) | - DISP_VAL_IF(start_driving & 0x020, - DISP_BITMASK_SS15) | - DISP_VAL_IF(start_driving & 0x010, - DISP_BITMASK_SS14) | - DISP_VAL_IF(start_driving & 0x008, - DISP_BITMASK_SS13) | - DISP_VAL_IF(start_driving & 0x004, - DISP_BITMASK_SS12) | - DISP_VAL_IF(start_driving & 0x002, - DISP_BITMASK_SS11) | - DISP_VAL_IF(start_driving & 0x001, DISP_BITMASK_SS10)); - - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, - DISP_VAL_IF(end_driving & 0x100, DISP_BITMASK_SE18) | - DISP_VAL_IF(end_driving & 0x080, DISP_BITMASK_SE17) | - DISP_VAL_IF(end_driving & 0x040, DISP_BITMASK_SE16) | - DISP_VAL_IF(end_driving & 0x020, DISP_BITMASK_SE15) | - DISP_VAL_IF(end_driving & 0x010, DISP_BITMASK_SE14) | - DISP_VAL_IF(end_driving & 0x008, DISP_BITMASK_SE13) | - DISP_VAL_IF(end_driving & 0x004, DISP_BITMASK_SE12) | - DISP_VAL_IF(end_driving & 0x002, DISP_BITMASK_SE11) | - DISP_VAL_IF(end_driving & 0x001, DISP_BITMASK_SE10)); -} - -static int tmd20qvga_disp_off(struct platform_device *pdev) -{ - if (!disp_initialized) - tmd20qvga_disp_init(pdev); - - if (display_on) { - if (tmd20qvga_lcd_rev == 2) { - DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000A); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFEE); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xF812); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xE811); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC011); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x4011); - WAIT_MSEC(20); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0010); - - } else { - DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000F); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFE); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BED); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(40); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x00CD); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(20); - DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0); - } - - DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0004); - DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0000); - - display_on = FALSE; - } - - return 0; -} - -static int tmd20qvga_disp_on(struct platform_device *pdev) -{ - if (!disp_initialized) - tmd20qvga_disp_init(pdev); - - if (!display_on) { - /* Deep Stand-by -> Stand-by */ - DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); - WAIT_MSEC(1); - DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); - WAIT_MSEC(1); - DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR); - WAIT_MSEC(1); - - /* OFF -> Deep Stan-By -> Stand-by */ - /* let's change the state from "Stand-by" to "Sleep" */ - DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0005); - WAIT_MSEC(1); - - /* Sleep -> Displaying */ - DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0001); - DISP_WRITE_OUT(DISP_DRIVER_OUTPUT_CTL_ADDR, 0x0127); - DISP_WRITE_OUT(DISP_LCD_DRIVING_SIG_ADDR, 0x200); - /* fast write mode */ - DISP_WRITE_OUT(DISP_ENTRY_MODE_ADDR, 0x0130); - if (tmd20qvga_lcd_rev == 2) - DISP_WRITE_OUT(DISP_TMD_700_ADDR, 0x0003); - /* back porch = 14 + front porch = 2 --> 16 lines */ - if (tmd20qvga_lcd_rev == 2) { -#ifdef TMD20QVGA_LCD_18BPP - /* 256k color */ - DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0000); -#else - /* 65k color */ - DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4000); -#endif - DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x0302); - } else { -#ifdef TMD20QVGA_LCD_18BPP - /* 256k color */ - DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0004); -#else - /* 65k color */ - DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4004); -#endif - DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x020E); - } - /* 16 bit one transfer */ - if (tmd20qvga_lcd_rev == 2) { - DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010); - DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0302); - DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0102); - DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_TMD_015_ADDR, 0x2000); - - DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0304); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0101); - DISP_WRITE_OUT(DISP_TMD_305_ADDR, 0); - - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F); - - DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x077D); - - DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0005); - DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0015); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC010); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x0001); - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFFE); - WAIT_MSEC(60); - } else { - DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0001); - DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010); - DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0301); - DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0001); - DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0507); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0405); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0607); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0502); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0301); - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F); - DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x0795); - - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0102); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0450); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0103); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0008); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0104); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0C00); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0105); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_7_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0106); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0801); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(1); - - DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x001F); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101); - WAIT_MSEC(60); - - DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x009F); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101); - WAIT_MSEC(10); - - DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, 0x0010); - DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, 0x00FF); - DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, 0x0000); - DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, 0x013F); - /* RAM starts at address 0x10 */ - DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, 0x0010); - DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, 0x0000); - - /* lcd controller uses internal clock, not ext. vsync */ - DISP_CMD_OUT(DISP_CMD_RAMWR); - - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0881); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(40); - - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BE1); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - WAIT_MSEC(40); - - DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFF); - DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100); - } - display_on = TRUE; - } - - return 0; -} - -static void tmd20qvga_disp_set_contrast(void) -{ -#if (defined(TMD20QVGA_LCD_18BPP)) - - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0302); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07); - -#else - int newcontrast = 0x46; - - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403); - - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, - DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP20) | - DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP21) | - DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP22) | - DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP30) | - DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP31) | - DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP32)); - - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, - DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP40) | - DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP41) | - DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP42) | - DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP50) | - DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP51) | - DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP52)); - - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303); - DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07); - -#endif /* defined(TMD20QVGA_LCD_18BPP) */ - -} /* End disp_set_contrast */ - -void tmd20qvga_disp_clear_screen_area - (word start_row, word end_row, word start_column, word end_column) { - int32 i; - - /* Clear the display screen */ - DISP_SET_RECT(start_row, end_row, start_column, end_column); - DISP_CMD_OUT(DISP_CMD_RAMWR); - i = (end_row - start_row + 1) * (end_column - start_column + 1); - for (; i > 0; i--) - DISP_DATA_OUT_16TO18BPP(0x0); -} - -static int __init tmd20qvga_probe(struct platform_device *pdev) -{ - msm_fb_add_device(pdev); - - return 0; -} - -static struct platform_driver this_driver = { - .probe = tmd20qvga_probe, - .driver = { - .name = "ebi2_tmd_qvga", - }, -}; - -static struct msm_fb_panel_data tmd20qvga_panel_data = { - .on = tmd20qvga_disp_on, - .off = tmd20qvga_disp_off, - .set_rect = tmd20qvga_disp_set_rect, -}; - -static struct platform_device this_device = { - .name = "ebi2_tmd_qvga", - .id = 0, - .dev = { - .platform_data = &tmd20qvga_panel_data, - } -}; - -static int __init tmd20qvga_init(void) -{ - int ret; - struct msm_panel_info *pinfo; - - ret = platform_driver_register(&this_driver); - if (!ret) { - pinfo = &tmd20qvga_panel_data.panel_info; - pinfo->xres = 240; - pinfo->yres = 320; - MSM_FB_SINGLE_MODE_PANEL(pinfo); - pinfo->type = EBI2_PANEL; - pinfo->pdest = DISPLAY_1; - pinfo->wait_cycle = 0x808000; -#ifdef TMD20QVGA_LCD_18BPP - pinfo->bpp = 18; -#else - pinfo->bpp = 16; -#endif - pinfo->fb_num = 2; - pinfo->lcd.vsync_enable = TRUE; - pinfo->lcd.refx100 = 6000; - pinfo->lcd.v_back_porch = 16; - pinfo->lcd.v_front_porch = 4; - pinfo->lcd.v_pulse_width = 0; - pinfo->lcd.hw_vsync_mode = FALSE; - pinfo->lcd.vsync_notifier_period = 0; - - ret = platform_device_register(&this_device); - if (ret) - platform_driver_unregister(&this_driver); - } - - return ret; -} - -module_init(tmd20qvga_init); - diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c deleted file mode 100644 index c6dce46d0..000000000 --- a/drivers/video/msm/external_common.c +++ /dev/null @@ -1,2452 +0,0 @@ -/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include - -/* #define DEBUG */ -#define DEV_DBG_PREFIX "EXT_COMMON: " - -/* The start of the data block collection within the CEA Extension Version 3 */ -#define DBC_START_OFFSET 4 - -#include "msm_fb.h" -#include "hdmi_msm.h" -#include "external_common.h" -#include "mhl_api.h" - -#include "mdp.h" - -struct external_common_state_type *external_common_state; -static int number_of_sad; - -EXPORT_SYMBOL(external_common_state); -DEFINE_MUTEX(external_common_state_hpd_mutex); -EXPORT_SYMBOL(external_common_state_hpd_mutex); - - -static int atoi(const char *name) -{ - int val = 0; - - for (;; name++) { - switch (*name) { - case '0' ... '9': - val = 10*val+(*name-'0'); - break; - default: - return val; - } - } -} - -#ifdef DEBUG_EDID -/* - * Block 0 - 1920x1080p, 1360x768p - * Block 1 - 1280x720p, 1920x540i, 720x480p - */ -const char edid_blk0[0x100] = { -0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x4C, 0x2D, 0x03, 0x05, 0x00, -0x00, 0x00, 0x00, 0x30, 0x12, 0x01, 0x03, 0x80, 0x10, 0x09, 0x78, 0x0A, 0xEE, -0x91, 0xA3, 0x54, 0x4C, 0x99, 0x26, 0x0F, 0x50, 0x54, 0xBD, 0xEF, 0x80, 0x71, -0x4F, 0x81, 0x00, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0x95, 0x0F, 0xB3, 0x00, -0xA9, 0x40, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, -0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x66, 0x21, 0x50, 0xB0, 0x51, 0x00, -0x1B, 0x30, 0x40, 0x70, 0x36, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x00, -0x00, 0x00, 0xFD, 0x00, 0x18, 0x4B, 0x1A, 0x51, 0x17, 0x00, 0x0A, 0x20, 0x20, -0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x53, 0x41, 0x4D, 0x53, -0x55, 0x4E, 0x47, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x8F}; - -const char edid_blk1[0x100] = { -0x02, 0x03, 0x1E, 0xF1, 0x46, 0x90, 0x04, 0x05, 0x03, 0x20, 0x22, 0x23, 0x09, -0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0xE2, 0x00, 0x0F, 0x67, 0x03, 0x0C, 0x00, -0x10, 0x00, 0xB8, 0x2D, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E, -0x28, 0x55, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x80, 0x18, -0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, -0x9E, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00, -0xA0, 0x5A, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDF}; -#endif /* DEBUG_EDID */ - -#define DMA_E_BASE 0xB0000 -void mdp_vid_quant_set(void) -{ - if ((external_common_state->video_resolution == \ - HDMI_VFRMT_720x480p60_4_3) || \ - (external_common_state->video_resolution == \ - HDMI_VFRMT_720x480p60_16_9)) { - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00EB0010); - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00EB0010); - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00EB0010); - } else { - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00FF0000); - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00FF0000); - MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00FF0000); - } -} - -const char *video_format_2string(uint32 format) -{ - switch (format) { -#if defined(CONFIG_FB_MSM_TVOUT) - case TVOUT_VFRMT_NTSC_M_720x480i: return "NTSC_M_720x480i"; - case TVOUT_VFRMT_NTSC_J_720x480i: return "NTSC_J_720x480i"; - case TVOUT_VFRMT_PAL_BDGHIN_720x576i: return "PAL_BDGHIN_720x576i"; - case TVOUT_VFRMT_PAL_M_720x480i: return "PAL_M_720x480i"; - case TVOUT_VFRMT_PAL_N_720x480i: return "PAL_N_720x480i"; -#endif - default: return "???"; - } -} -EXPORT_SYMBOL(video_format_2string); - -static ssize_t external_common_rda_video_mode_str(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n", - msm_hdmi_mode_2string(external_common_state->video_resolution)); - DEV_DBG("%s: '%s'\n", __func__, - msm_hdmi_mode_2string(external_common_state->video_resolution)); - return ret; -} - -#ifdef CONFIG_FB_MSM_HDMI_COMMON -struct msm_hdmi_mode_timing_info - hdmi_common_supported_video_mode_lut[HDMI_VFRMT_MAX]; -EXPORT_SYMBOL(hdmi_common_supported_video_mode_lut); - -struct msm_hdmi_mode_timing_info - hdmi_mhl_supported_video_mode_lut[HDMI_VFRMT_MAX] = { - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_UNKNOWN), - HDMI_VFRMT_640x480p60_4_3_TIMING, - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_16_9), - HDMI_VFRMT_1280x720p60_16_9_TIMING, - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p50_16_9), - HDMI_VFRMT_1920x1080p24_16_9_TIMING, - HDMI_VFRMT_1920x1080p25_16_9_TIMING, - HDMI_VFRMT_1920x1080p30_16_9_TIMING, - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1250i50_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i100_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p100_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i120_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p120_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_16_9), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_4_3), - VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_16_9), - HDMI_VFRMT_1280x1024p60_5_4_TIMING -}; -EXPORT_SYMBOL(hdmi_mhl_supported_video_mode_lut); - -static ssize_t hdmi_common_rda_edid_modes(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = 0; - int i; - - buf[0] = 0; - if (external_common_state->disp_mode_list.num_of_elements) { - uint32 *video_mode = external_common_state->disp_mode_list - .disp_mode_list; - for (i = 0; i < external_common_state->disp_mode_list - .num_of_elements; ++i) { - if (ret > 0) - ret += scnprintf(buf+ret, PAGE_SIZE-ret, ",%d", - *video_mode++); - else - ret += scnprintf(buf+ret, PAGE_SIZE-ret, "%d", - *video_mode++); - } - } else - ret += scnprintf(buf+ret, PAGE_SIZE-ret, "%d", - external_common_state->video_resolution+1); - - DEV_DBG("%s: '%s'\n", __func__, buf); - ret += scnprintf(buf+ret, PAGE_SIZE-ret, "\n"); - return ret; -} - -static ssize_t hdmi_common_rda_edid_physical_address(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = scnprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->physical_address); - - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->physical_address); - return ret; -} - - -static ssize_t hdmi_common_rda_edid_scan_info(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = scnprintf(buf, PAGE_SIZE, "%d, %d, %d\n", - external_common_state->pt_scan_info, - external_common_state->it_scan_info, - external_common_state->ce_scan_info); - DEV_DBG("%s: '%s'\n", __func__, buf); - return ret; -} - -static ssize_t hdmi_common_wta_vendor_name(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - uint8 *s = (uint8 *) buf; - uint8 *d = external_common_state->spd_vendor_name; - ssize_t sz; - ssize_t ret = strnlen(buf, PAGE_SIZE); - ret = (ret > 8) ? 8 : ret; - - sz = sizeof(external_common_state->spd_vendor_name); - memset(external_common_state->spd_vendor_name, 0, sz); - while (*s) { - if (*s & 0x60 && *s ^ 0x7f) { - *d = *s; - } else { - /* stop copying if control character found */ - break; - } - - if (++s > (uint8 *) (buf + ret)) - break; - - d++; - } - external_common_state->spd_vendor_name[sz - 1] = 0; - - DEV_DBG("%s: '%s'\n", __func__, - external_common_state->spd_vendor_name); - - return ret; -} - -static ssize_t hdmi_common_rda_vendor_name(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n", - external_common_state->spd_vendor_name); - DEV_DBG("%s: '%s'\n", __func__, - external_common_state->spd_vendor_name); - - return ret; -} - -static ssize_t hdmi_common_wta_product_description(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - uint8 *s = (uint8 *) buf; - uint8 *d = external_common_state->spd_product_description; - ssize_t ret = strnlen(buf, PAGE_SIZE); - ssize_t sz; - ret = (ret > 16) ? 16 : ret; - - sz = sizeof(external_common_state->spd_product_description); - memset(external_common_state->spd_product_description, 0, sz); - while (*s) { - if (*s & 0x60 && *s ^ 0x7f) { - *d = *s; - } else { - /* stop copying if control character found */ - break; - } - - if (++s > (uint8 *) (buf + ret)) - break; - - d++; - } - external_common_state->spd_product_description[sz - 1] = 0; - - DEV_DBG("%s: '%s'\n", __func__, - external_common_state->spd_product_description); - - return ret; -} - -static ssize_t hdmi_common_rda_product_description(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n", - external_common_state->spd_product_description); - DEV_DBG("%s: '%s'\n", __func__, - external_common_state->spd_product_description); - - return ret; -} - -static ssize_t hdmi_common_rda_edid_3d_modes(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = 0; - int i; - char buff_3d[128]; - - buf[0] = 0; - if (external_common_state->disp_mode_list.num_of_elements) { - uint32 *video_mode = external_common_state->disp_mode_list - .disp_mode_list; - uint32 *video_3d_mode = external_common_state->disp_mode_list - .disp_3d_mode_list; - for (i = 0; i < external_common_state->disp_mode_list - .num_of_elements; ++i) { - video_3d_format_2string(*video_3d_mode++, buff_3d, sizeof(buff_3d)); - if (ret > 0) - ret += scnprintf(buf+ret, PAGE_SIZE-ret, - ",%d=%s", - *video_mode++ + 1, buff_3d); - else - ret += scnprintf(buf+ret, PAGE_SIZE-ret, - "%d=%s", - *video_mode++ + 1, buff_3d); - } - } else - ret += scnprintf(buf+ret, PAGE_SIZE-ret, "%d", - external_common_state->video_resolution+1); - - DEV_DBG("%s: '%s'\n", __func__, buf); - ret += scnprintf(buf+ret, PAGE_SIZE-ret, "\n"); - return ret; -} - -static ssize_t hdmi_common_rda_hdcp(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->hdcp_active); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hdcp_active); - return ret; -} - -static ssize_t hdmi_common_rda_hpd(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret; - if (external_common_state->hpd_feature) { - ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->hpd_feature_on); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hpd_feature_on); - } else { - ret = snprintf(buf, PAGE_SIZE, "-1\n"); - DEV_DBG("%s: 'not supported'\n", __func__); - } - return ret; -} - -static ssize_t hdmi_common_wta_hpd(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - ssize_t ret = strnlen(buf, PAGE_SIZE); - int hpd; - if (hdmi_prim_display) - hpd = 1; - else - hpd = atoi(buf); - - if (external_common_state->hpd_feature) { - if (hpd == 0 && external_common_state->hpd_feature_on) { - external_common_state->hpd_feature(0); - external_common_state->hpd_feature_on = 0; - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hpd_feature_on); - } else if (hpd == 1 && !external_common_state->hpd_feature_on) { - external_common_state->hpd_feature(1); - external_common_state->hpd_feature_on = 1; - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hpd_feature_on); - } else { - DEV_DBG("%s: '%d' (unchanged)\n", __func__, - external_common_state->hpd_feature_on); - } - } else { - DEV_DBG("%s: 'not supported'\n", __func__); - } - - return ret; -} - -#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT -/* - * This interface for CEC feature is defined to suit - * the current requirements. However, the actual functionality is - * added to accommodate different interfaces - */ -static ssize_t hdmi_msm_rda_cec(struct device *dev, - struct device_attribute *attr, char *buf) -{ - /* 0x028C CEC_CTRL */ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - (HDMI_INP(0x028C) & BIT(0))); - return ret; -} - -static ssize_t hdmi_msm_wta_cec(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - ssize_t ret = strnlen(buf, PAGE_SIZE); - int cec = atoi(buf); - - if (cec != 0) { - mutex_lock(&hdmi_msm_state_mutex); - hdmi_msm_state->cec_enabled = true; - hdmi_msm_state->cec_logical_addr = 4; - - /* flush CEC queue */ - hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start; - hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start; - hdmi_msm_state->cec_queue_full = false; - memset(hdmi_msm_state->cec_queue_rd, 0, - sizeof(struct hdmi_msm_cec_msg)*CEC_QUEUE_SIZE); - - mutex_unlock(&hdmi_msm_state_mutex); - hdmi_msm_cec_init(); - hdmi_msm_cec_write_logical_addr( - hdmi_msm_state->cec_logical_addr); - DEV_DBG("CEC enabled\n"); - } else { - mutex_lock(&hdmi_msm_state_mutex); - hdmi_msm_state->cec_enabled = false; - hdmi_msm_state->cec_logical_addr = 15; - mutex_unlock(&hdmi_msm_state_mutex); - hdmi_msm_cec_write_logical_addr( - hdmi_msm_state->cec_logical_addr); - /* 0x028C CEC_CTRL */ - HDMI_OUTP(0x028C, 0); - DEV_DBG("CEC disabled\n"); - } - return ret; -} - -static ssize_t hdmi_msm_rda_cec_logical_addr(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret; - - mutex_lock(&hdmi_msm_state_mutex); - ret = snprintf(buf, PAGE_SIZE, "%d\n", - hdmi_msm_state->cec_logical_addr); - mutex_unlock(&hdmi_msm_state_mutex); - return ret; -} - -static ssize_t hdmi_msm_wta_cec_logical_addr(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - -#ifdef DRVR_ONLY_CECT_NO_DAEMON - /* - * Only for testing - */ - hdmi_msm_cec_one_touch_play(); - return 0; -#else - ssize_t ret = strnlen(buf, PAGE_SIZE); - int logical_addr = atoi(buf); - - if (logical_addr < 0 || logical_addr > 15) - return -EINVAL; - - mutex_lock(&hdmi_msm_state_mutex); - hdmi_msm_state->cec_logical_addr = logical_addr; - mutex_unlock(&hdmi_msm_state_mutex); - - hdmi_msm_cec_write_logical_addr(logical_addr); - - return ret; -#endif -} - -static ssize_t hdmi_msm_rda_cec_frame(struct device *dev, - struct device_attribute *attr, char *buf) -{ - mutex_lock(&hdmi_msm_state_mutex); - if (hdmi_msm_state->cec_queue_rd == hdmi_msm_state->cec_queue_wr - && !hdmi_msm_state->cec_queue_full) { - mutex_unlock(&hdmi_msm_state_mutex); - DEV_ERR("CEC message queue is empty\n"); - return -EBUSY; - } - memcpy(buf, hdmi_msm_state->cec_queue_rd++, - sizeof(struct hdmi_msm_cec_msg)); - hdmi_msm_state->cec_queue_full = false; - if (hdmi_msm_state->cec_queue_rd == CEC_QUEUE_END) - hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start; - mutex_unlock(&hdmi_msm_state_mutex); - - return sizeof(struct hdmi_msm_cec_msg); -} - -static ssize_t hdmi_msm_wta_cec_frame(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - int i; - struct hdmi_msm_cec_msg *msg; - int retry; - - msg = (struct hdmi_msm_cec_msg *) buf; - retry = msg->retransmit; - if (msg->frame_size > CEC_MAX_OPERAND_SIZE) { - pr_err("%s: cec msg too large\n", __func__); - return -EINVAL; - } - for (i = 0; i < RETRANSMIT_MAX_NUM; i++) { - hdmi_msm_cec_msg_send((struct hdmi_msm_cec_msg *) buf); - if (hdmi_msm_state->cec_frame_wr_status - & CEC_STATUS_WR_ERROR && retry--) { - mutex_lock(&hdmi_msm_state_mutex); - if (hdmi_msm_state->fsm_reset_done) - retry++; - mutex_unlock(&hdmi_msm_state_mutex); - msleep(20); - } else - break; - } - - if (hdmi_msm_state->cec_frame_wr_status & CEC_STATUS_WR_DONE) - return sizeof(struct hdmi_msm_cec_msg); - else - return -EINVAL; -} -#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */ - -static ssize_t hdmi_common_rda_3d_present(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->present_3d); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->present_3d); - return ret; -} - -static ssize_t hdmi_common_rda_hdcp_present(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->present_hdcp); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->present_hdcp); - return ret; -} -#endif - -#ifdef CONFIG_FB_MSM_HDMI_3D -static ssize_t hdmi_3d_rda_format_3d(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->format_3d); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->format_3d); - return ret; -} - -static ssize_t hdmi_3d_wta_format_3d(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - ssize_t ret = strnlen(buf, PAGE_SIZE); - int format_3d = atoi(buf); - - if (format_3d >= 0 && format_3d <= 2) { - if (format_3d != external_common_state->format_3d) { - external_common_state->format_3d = format_3d; - if (external_common_state->switch_3d) - external_common_state->switch_3d(format_3d); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->format_3d); - } else { - DEV_DBG("%s: '%d' (unchanged)\n", __func__, - external_common_state->format_3d); - } - } else { - DEV_DBG("%s: '%d' (unknown)\n", __func__, format_3d); - } - - return ret; -} -#endif - -#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT -static DEVICE_ATTR(cec, S_IRUGO | S_IWUSR, - hdmi_msm_rda_cec, - hdmi_msm_wta_cec); - -static DEVICE_ATTR(cec_logical_addr, S_IRUSR | S_IWUSR, - hdmi_msm_rda_cec_logical_addr, - hdmi_msm_wta_cec_logical_addr); - -static DEVICE_ATTR(cec_rd_frame, S_IRUGO, - hdmi_msm_rda_cec_frame, NULL); - -static DEVICE_ATTR(cec_wr_frame, S_IWUSR, - NULL, hdmi_msm_wta_cec_frame); -#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */ - - -static ssize_t external_common_rda_video_mode(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->video_resolution+1); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->video_resolution+1); - return ret; -} - -static ssize_t external_common_wta_video_mode(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - ssize_t ret = strnlen(buf, PAGE_SIZE); - uint32 video_mode; -#ifdef CONFIG_FB_MSM_HDMI_COMMON - const struct msm_hdmi_mode_timing_info *disp_mode; -#endif - mutex_lock(&external_common_state_hpd_mutex); - if (!external_common_state->hpd_state) { - mutex_unlock(&external_common_state_hpd_mutex); - DEV_INFO("%s: FAILED: display off or cable disconnected\n", - __func__); - return ret; - } - mutex_unlock(&external_common_state_hpd_mutex); - - video_mode = atoi(buf); - DEV_INFO("%s: video_mode is %d\n", __func__, video_mode); - kobject_uevent(external_common_state->uevent_kobj, KOBJ_OFFLINE); -#ifdef CONFIG_FB_MSM_HDMI_COMMON - disp_mode = hdmi_common_get_supported_mode(video_mode); - if (!disp_mode) { - DEV_INFO("%s: FAILED: mode not supported (%d)\n", - __func__, video_mode); - return ret; - } - external_common_state->disp_mode_list.num_of_elements = 1; - external_common_state->disp_mode_list.disp_mode_list[0] = video_mode; -#elif defined(CONFIG_FB_MSM_TVOUT) - external_common_state->video_resolution = video_mode; -#endif - DEV_DBG("%s: 'mode=%d %s' successful (sending OFF/ONLINE)\n", __func__, - video_mode, msm_hdmi_mode_2string(video_mode)); - kobject_uevent(external_common_state->uevent_kobj, KOBJ_ONLINE); - return ret; -} - -static ssize_t external_common_rda_connected(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret; - mutex_lock(&external_common_state_hpd_mutex); - ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->hpd_state); - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hpd_state); - mutex_unlock(&external_common_state_hpd_mutex); - return ret; -} - -static ssize_t external_common_rda_hdmi_mode(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret; - - ret = snprintf(buf, PAGE_SIZE, "%d\n", - external_common_state->hdmi_sink); - - DEV_DBG("%s: '%d'\n", __func__, - external_common_state->hdmi_sink); - - return ret; -} - -static ssize_t hdmi_common_rda_hdmi_primary(struct device *dev, - struct device_attribute *attr, char *buf) -{ - ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n", - hdmi_prim_display); - DEV_DBG("%s: '%d'\n", __func__, hdmi_prim_display); - return ret; -} - -static ssize_t hdmi_common_rda_audio_data_block(struct device *dev, - struct device_attribute *attr, char *buf) -{ - int adb_size = external_common_state->adb_size; - int adb_count = 1; - ssize_t ret = sizeof(adb_count) + sizeof(adb_size) + adb_size; - char *data = buf; - - if (ret > PAGE_SIZE) { - DEV_DBG("%s: Insufficient buffer size\n", __func__); - return 0; - } - - /* Currently only extracting one audio data block */ - memcpy(data, &adb_count, sizeof(adb_count)); - data += sizeof(adb_count); - memcpy(data, &adb_size, sizeof(adb_size)); - data += sizeof(adb_size); - memcpy(data, external_common_state->audio_data_block, - external_common_state->adb_size); - - print_hex_dump(KERN_DEBUG, "AUDIO DATA BLOCK: ", DUMP_PREFIX_NONE, - 32, 8, buf, ret, false); - - return ret; -} - -static ssize_t hdmi_common_rda_spkr_alloc_data_block(struct device *dev, - struct device_attribute *attr, char *buf) -{ - int sadb_size = external_common_state->sadb_size; - int sadb_count = 1; - ssize_t ret = sizeof(sadb_count) + sizeof(sadb_size) + sadb_size; - char *data = buf; - - if (ret > PAGE_SIZE) { - DEV_DBG("%s: Insufficient buffer size\n", __func__); - return 0; - } - - /* Currently only extracting one speaker allocation data block */ - memcpy(data, &sadb_count, sizeof(sadb_count)); - data += sizeof(sadb_count); - memcpy(data, &sadb_size, sizeof(sadb_size)); - data += sizeof(sadb_size); - memcpy(data, external_common_state->spkr_alloc_data_block, - external_common_state->sadb_size); - - print_hex_dump(KERN_DEBUG, "SPKR ALLOC DATA BLOCK: ", DUMP_PREFIX_NONE, - 32, 8, buf, ret, false); - - return ret; -} -static ssize_t hdmi_common_wta_audio_caps(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - ssize_t ret = strnlen(buf, PAGE_SIZE); - number_of_sad = atoi(buf); - return ret; -} - - -int hdmi_common_get_audio_capabilities( - uint8 *channels, uint8 *formats, - uint8 *freq, uint8 *bitrate, - uint8 *spkr_allocation) -{ - uint8 *adb = external_common_state->audio_data_block; - int count = external_common_state->adb_size/3; - - while (count--) { - *channels++ = (*adb & 0x07) + 1; - *formats++ = (*adb & 0x78) >> 3; - *freq++ = *(adb + 1) & 0xFF; - *bitrate++ = *(adb + 2) & 0xFF; - - adb += 3; - } - - *spkr_allocation = external_common_state->spkr_alloc_data_block[0]; - - return external_common_state->adb_size/3; -} - -static ssize_t hdmi_common_rda_audio_caps(struct device *dev, - struct device_attribute *attr, char *buf) -{ - uint8 channels[16]; - uint8 formats[16]; - uint8 frequency[16]; - uint8 bitrate[16]; - uint8 spkr_allocation; - int count, i; - char str[512]; - int str_size = 512; - boolean comma = FALSE; - - if (number_of_sad == 0) { - count = external_common_state->adb_size/3; - return snprintf(buf, sizeof(int)+1, "%d\n", count); - } - - count = hdmi_common_get_audio_capabilities(channels, formats, - frequency, bitrate, - &spkr_allocation); - - strlcpy(str, "\n", str_size); - i = number_of_sad - 1; - { - char t[3]; - snprintf(t, 3, "%d", i + 1); - - strlcat(str, "\tSHORT AUDIO DESCRIPTOR # ", str_size); - strlcat(str, t, str_size); - strlcat(str, "\n", str_size); - strlcat(str, "Number of channels \t= ", str_size); - - snprintf(t, 3, "%d", channels[i]); - strlcat(str, t, str_size); - - strlcat(str, "\n", str_size); - - strlcat(str, "Formats supported \t= ", str_size); - switch (formats[i]) { - case 1: - strlcat(str, "LPCM", str_size); - break; - case 2: - strlcat(str, "AC-3", str_size); - break; - case 3: - strlcat(str, "MPEG1 (Layers 1 & 2)", str_size); - break; - case 4: - strlcat(str, "MP3 (MPEG1 Layer 3)", str_size); - break; - case 5: - strlcat(str, "MPEG2 (multichannel)", str_size); - break; - case 6: - strlcat(str, "AAC", str_size); - break; - case 7: - strlcat(str, "DTS", str_size); - break; - case 8: - strlcat(str, "ATRAC", str_size); - break; - case 9: - strlcat(str, "One-bit audio aka SACD", str_size); - break; - case 10: - strlcat(str, "Dolby Digital +", str_size); - break; - case 11: - strlcat(str, "DTS-HD", str_size); - break; - case 12: - strlcat(str, "MAT (MLP)", str_size); - break; - case 13: - strlcat(str, "DST", str_size); - break; - case 14: - strlcat(str, "WMA Pro", str_size); - break; - default: - break; - } - - strlcat(str, "\n", str_size); - - strlcat(str, "Frequency supported \t= ", str_size); - comma = FALSE; - if (frequency[i] & BIT(0)) { - strlcat(str, "32kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(1)) { - if (comma) - strlcat(str, ", 44kHz", str_size); - else - strlcat(str, "44kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(2)) { - if (comma) - strlcat(str, ", 48kHz", str_size); - else - strlcat(str, "48kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(3)) { - if (comma) - strlcat(str, ", 88kHz", str_size); - else - strlcat(str, "88kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(4)) { - if (comma) - strlcat(str, ", 96kHz", str_size); - else - strlcat(str, "96kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(5)) { - if (comma) - strlcat(str, ", 176kHz", str_size); - else - strlcat(str, "176kHz", str_size); - comma = TRUE; - } - if (frequency[i] & BIT(6)) { - if (comma) - strlcat(str, ", 192kHz", str_size); - else - strlcat(str, "192kHz", str_size); - } - - strlcat(str, "\n", str_size); - - strlcat(str, "bitrate supported \t= ", str_size); - comma = FALSE; - if (formats[i] == 1) { - if (bitrate[i] & BIT(0)) { - strlcat(str, "16bit", str_size); - comma = TRUE; - } - if (bitrate[i] & BIT(1)) { - if (comma) - strlcat(str, ", 20bit", str_size); - else - strlcat(str, "20bit", str_size); - comma = TRUE; - } - if (bitrate[i] & BIT(2)) { - if (comma) - strlcat(str, ", 24bit", str_size); - else - strlcat(str, "24bit", str_size); - } - } else { - char t[20]; - snprintf(t, 20, "%d", bitrate[i] * 8); - strlcat(str, t, str_size); - strlcat(str, "Kbit/s", str_size); - } - - strlcat(str, "\n\n", str_size); - } - - strlcat(str, "Speaker Allocation \t= ", str_size); - comma = FALSE; - if (spkr_allocation & BIT(0)) { - strlcat(str, "FL/FR", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(1)) { - if (comma) - strlcat(str, ", LFE", str_size); - else - strlcat(str, "LFE", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(2)) { - if (comma) - strlcat(str, ", FC", str_size); - else - strlcat(str, "FC", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(3)) { - if (comma) - strlcat(str, ", RL/RR", str_size); - else - strlcat(str, "RL/RR", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(4)) { - if (comma) - strlcat(str, ", RC", str_size); - else - strlcat(str, "RC", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(5)) { - if (comma) - strlcat(str, ", FLC/FRC", str_size); - else - strlcat(str, "FLC/FRC", str_size); - comma = TRUE; - } - if (spkr_allocation & BIT(6)) { - if (comma) - strlcat(str, ", RLC/RRC", str_size); - else - strlcat(str, "RLC/RRC", str_size); - } - - return snprintf(buf, str_size, "%s\n", str); -} - -static DEVICE_ATTR(video_mode, S_IRUGO | S_IWUSR | S_IWGRP, - external_common_rda_video_mode, external_common_wta_video_mode); -static DEVICE_ATTR(video_mode_str, S_IRUGO, external_common_rda_video_mode_str, - NULL); -static DEVICE_ATTR(connected, S_IRUGO, external_common_rda_connected, NULL); -static DEVICE_ATTR(hdmi_mode, S_IRUGO, external_common_rda_hdmi_mode, NULL); -#ifdef CONFIG_FB_MSM_HDMI_COMMON -static DEVICE_ATTR(edid_modes, S_IRUGO, hdmi_common_rda_edid_modes, NULL); -static DEVICE_ATTR(hpd, S_IRUGO | S_IWUSR | S_IWGRP, hdmi_common_rda_hpd, - hdmi_common_wta_hpd); -static DEVICE_ATTR(hdcp, S_IRUGO, hdmi_common_rda_hdcp, NULL); -static DEVICE_ATTR(pa, S_IRUSR, - hdmi_common_rda_edid_physical_address, NULL); -static DEVICE_ATTR(scan_info, S_IRUGO, - hdmi_common_rda_edid_scan_info, NULL); -static DEVICE_ATTR(vendor_name, S_IRUGO | S_IWUSR, hdmi_common_rda_vendor_name, - hdmi_common_wta_vendor_name); -static DEVICE_ATTR(product_description, S_IRUGO | S_IWUSR, - hdmi_common_rda_product_description, - hdmi_common_wta_product_description); -static DEVICE_ATTR(edid_3d_modes, S_IRUGO, - hdmi_common_rda_edid_3d_modes, NULL); -static DEVICE_ATTR(3d_present, S_IRUGO, hdmi_common_rda_3d_present, NULL); -static DEVICE_ATTR(hdcp_present, S_IRUGO, hdmi_common_rda_hdcp_present, NULL); -#endif -#ifdef CONFIG_FB_MSM_HDMI_3D -static DEVICE_ATTR(format_3d, S_IRUGO | S_IWUSR | S_IWGRP, - hdmi_3d_rda_format_3d, hdmi_3d_wta_format_3d); -#endif -static DEVICE_ATTR(hdmi_primary, S_IRUGO, hdmi_common_rda_hdmi_primary, NULL); -static DEVICE_ATTR(audio_data_block, S_IRUGO, hdmi_common_rda_audio_data_block, - NULL); -static DEVICE_ATTR(spkr_alloc_data_block, S_IRUGO, - hdmi_common_rda_spkr_alloc_data_block, NULL); -static DEVICE_ATTR(audio_caps, S_IRUGO | S_IWOTH, hdmi_common_rda_audio_caps, - hdmi_common_wta_audio_caps); - -static struct attribute *external_common_fs_attrs[] = { - &dev_attr_video_mode.attr, - &dev_attr_video_mode_str.attr, - &dev_attr_connected.attr, - &dev_attr_hdmi_mode.attr, -#ifdef CONFIG_FB_MSM_HDMI_COMMON - &dev_attr_edid_modes.attr, - &dev_attr_hdcp.attr, - &dev_attr_hpd.attr, - &dev_attr_pa.attr, - &dev_attr_scan_info.attr, - &dev_attr_vendor_name.attr, - &dev_attr_product_description.attr, - &dev_attr_edid_3d_modes.attr, - &dev_attr_3d_present.attr, - &dev_attr_hdcp_present.attr, -#endif -#ifdef CONFIG_FB_MSM_HDMI_3D - &dev_attr_format_3d.attr, -#endif -#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT - &dev_attr_cec.attr, - &dev_attr_cec_logical_addr.attr, - &dev_attr_cec_rd_frame.attr, - &dev_attr_cec_wr_frame.attr, -#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */ - &dev_attr_hdmi_primary.attr, - &dev_attr_audio_data_block.attr, - &dev_attr_spkr_alloc_data_block.attr, - &dev_attr_audio_caps.attr, - NULL, -}; -static struct attribute_group external_common_fs_attr_group = { - .attrs = external_common_fs_attrs, -}; - -/* create external interface kobject and initialize */ -int external_common_state_create(struct platform_device *pdev) -{ - int rc; - struct msm_fb_data_type *mfd = platform_get_drvdata(pdev); - if (!mfd) { - DEV_ERR("%s: mfd not found\n", __func__); - return -ENODEV; - } - if (!mfd->fbi) { - DEV_ERR("%s: mfd->fbi not found\n", __func__); - return -ENODEV; - } - if (!mfd->fbi->dev) { - DEV_ERR("%s: mfd->fbi->dev not found\n", __func__); - return -ENODEV; - } - rc = sysfs_create_group(&mfd->fbi->dev->kobj, - &external_common_fs_attr_group); - if (rc) { - DEV_ERR("%s: sysfs group creation failed, rc=%d\n", __func__, - rc); - return rc; - } - external_common_state->uevent_kobj = &mfd->fbi->dev->kobj; - DEV_ERR("%s: sysfs group %p\n", __func__, - external_common_state->uevent_kobj); - - kobject_uevent(external_common_state->uevent_kobj, KOBJ_ADD); - DEV_DBG("%s: kobject_uevent(KOBJ_ADD)\n", __func__); - return 0; -} -EXPORT_SYMBOL(external_common_state_create); - -void external_common_state_remove(void) -{ - if (external_common_state->uevent_kobj) - sysfs_remove_group(external_common_state->uevent_kobj, - &external_common_fs_attr_group); - external_common_state->uevent_kobj = NULL; -} -EXPORT_SYMBOL(external_common_state_remove); - -#ifdef CONFIG_FB_MSM_HDMI_COMMON -/* The Logic ID for HDMI TX Core. Currently only support 1 HDMI TX Core. */ -struct hdmi_edid_video_mode_property_type { - uint32 video_code; - uint32 active_h; - uint32 active_v; - boolean interlaced; - uint32 total_h; - uint32 total_blank_h; - uint32 total_v; - uint32 total_blank_v; - /* Must divide by 1000 to get the frequency */ - uint32 freq_h; - /* Must divide by 1000 to get the frequency */ - uint32 freq_v; - /* Must divide by 1000 to get the frequency */ - uint32 pixel_freq; - /* Must divide by 1000 to get the frequency */ - uint32 refresh_rate; - boolean aspect_ratio_4_3; -}; - -/* LUT is sorted from lowest Active H to highest Active H - ease searching */ -static struct hdmi_edid_video_mode_property_type - hdmi_edid_disp_mode_lut[] = { - - /* All 640 H Active */ - {HDMI_VFRMT_640x480p60_4_3, 640, 480, FALSE, 800, 160, 525, 45, - 31465, 59940, 25175, 59940, TRUE}, - {HDMI_VFRMT_640x480p60_4_3, 640, 480, FALSE, 800, 160, 525, 45, - 31500, 60000, 25200, 60000, TRUE}, - - /* All 720 H Active */ - {HDMI_VFRMT_720x576p50_4_3, 720, 576, FALSE, 864, 144, 625, 49, - 31250, 50000, 27000, 50000, TRUE}, - {HDMI_VFRMT_720x480p60_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 31465, 59940, 27000, 59940, TRUE}, - {HDMI_VFRMT_720x480p60_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 31500, 60000, 27030, 60000, TRUE}, - {HDMI_VFRMT_720x576p100_4_3, 720, 576, FALSE, 864, 144, 625, 49, - 62500, 100000, 54000, 100000, TRUE}, - {HDMI_VFRMT_720x480p120_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 62937, 119880, 54000, 119880, TRUE}, - {HDMI_VFRMT_720x480p120_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 63000, 120000, 54054, 120000, TRUE}, - {HDMI_VFRMT_720x576p200_4_3, 720, 576, FALSE, 864, 144, 625, 49, - 125000, 200000, 108000, 200000, TRUE}, - {HDMI_VFRMT_720x480p240_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 125874, 239760, 108000, 239000, TRUE}, - {HDMI_VFRMT_720x480p240_4_3, 720, 480, FALSE, 858, 138, 525, 45, - 126000, 240000, 108108, 240000, TRUE}, - - /* All 1280 H Active */ - {HDMI_VFRMT_1280x720p50_16_9, 1280, 720, FALSE, 1980, 700, 750, 30, - 37500, 50000, 74250, 50000, FALSE}, - {HDMI_VFRMT_1280x720p60_16_9, 1280, 720, FALSE, 1650, 370, 750, 30, - 44955, 59940, 74176, 59940, FALSE}, - {HDMI_VFRMT_1280x720p60_16_9, 1280, 720, FALSE, 1650, 370, 750, 30, - 45000, 60000, 74250, 60000, FALSE}, - {HDMI_VFRMT_1280x720p100_16_9, 1280, 720, FALSE, 1980, 700, 750, 30, - 75000, 100000, 148500, 100000, FALSE}, - {HDMI_VFRMT_1280x720p120_16_9, 1280, 720, FALSE, 1650, 370, 750, 30, - 89909, 119880, 148352, 119880, FALSE}, - {HDMI_VFRMT_1280x720p120_16_9, 1280, 720, FALSE, 1650, 370, 750, 30, - 90000, 120000, 148500, 120000, FALSE}, - {HDMI_VFRMT_1280x1024p60_5_4, 1280, 1024, FALSE, 1688, 408, 1066, 42, - 63981, 60020, 108000, 60000, FALSE}, - - /* All 1440 H Active */ - {HDMI_VFRMT_1440x576i50_4_3, 1440, 576, TRUE, 1728, 288, 625, 24, - 15625, 50000, 27000, 50000, TRUE}, - {HDMI_VFRMT_720x288p50_4_3, 1440, 288, FALSE, 1728, 288, 312, 24, - 15625, 50080, 27000, 50000, TRUE}, - {HDMI_VFRMT_720x288p50_4_3, 1440, 288, FALSE, 1728, 288, 313, 25, - 15625, 49920, 27000, 50000, TRUE}, - {HDMI_VFRMT_720x288p50_4_3, 1440, 288, FALSE, 1728, 288, 314, 26, - 15625, 49761, 27000, 50000, TRUE}, - {HDMI_VFRMT_1440x576p50_4_3, 1440, 576, FALSE, 1728, 288, 625, 49, - 31250, 50000, 54000, 50000, TRUE}, - {HDMI_VFRMT_1440x480i60_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 15734, 59940, 27000, 59940, TRUE}, - {HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 262, 22, - 15734, 60054, 27000, 59940, TRUE}, - {HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 263, 23, - 15734, 59826, 27000, 59940, TRUE}, - {HDMI_VFRMT_1440x480p60_4_3, 1440, 480, FALSE, 1716, 276, 525, 45, - 31469, 59940, 54000, 59940, TRUE}, - {HDMI_VFRMT_1440x480i60_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 15750, 60000, 27027, 60000, TRUE}, - {HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 262, 22, - 15750, 60115, 27027, 60000, TRUE}, - {HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 263, 23, - 15750, 59886, 27027, 60000, TRUE}, - {HDMI_VFRMT_1440x480p60_4_3, 1440, 480, FALSE, 1716, 276, 525, 45, - 31500, 60000, 54054, 60000, TRUE}, - {HDMI_VFRMT_1440x576i100_4_3, 1440, 576, TRUE, 1728, 288, 625, 24, - 31250, 100000, 54000, 100000, TRUE}, - {HDMI_VFRMT_1440x480i120_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 31469, 119880, 54000, 119880, TRUE}, - {HDMI_VFRMT_1440x480i120_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 31500, 120000, 54054, 120000, TRUE}, - {HDMI_VFRMT_1440x576i200_4_3, 1440, 576, TRUE, 1728, 288, 625, 24, - 62500, 200000, 108000, 200000, TRUE}, - {HDMI_VFRMT_1440x480i240_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 62937, 239760, 108000, 239000, TRUE}, - {HDMI_VFRMT_1440x480i240_4_3, 1440, 480, TRUE, 1716, 276, 525, 22, - 63000, 240000, 108108, 240000, TRUE}, - - /* All 1920 H Active */ - {HDMI_VFRMT_1920x1080p60_16_9, 1920, 1080, FALSE, 2200, 280, 1125, - 45, 67433, 59940, 148352, 59940, FALSE}, - {HDMI_VFRMT_1920x1080p60_16_9, 1920, 1080, TRUE, 2200, 280, 1125, - 45, 67500, 60000, 148500, 60000, FALSE}, - {HDMI_VFRMT_1920x1080p50_16_9, 1920, 1080, FALSE, 2640, 720, 1125, - 45, 56250, 50000, 148500, 50000, FALSE}, - {HDMI_VFRMT_1920x1080p24_16_9, 1920, 1080, FALSE, 2750, 830, 1125, - 45, 26973, 23976, 74176, 24000, FALSE}, - {HDMI_VFRMT_1920x1080p24_16_9, 1920, 1080, FALSE, 2750, 830, 1125, - 45, 27000, 24000, 74250, 24000, FALSE}, - {HDMI_VFRMT_1920x1080p25_16_9, 1920, 1080, FALSE, 2640, 720, 1125, - 45, 28125, 25000, 74250, 25000, FALSE}, - {HDMI_VFRMT_1920x1080p30_16_9, 1920, 1080, FALSE, 2200, 280, 1125, - 45, 33716, 29970, 74176, 30000, FALSE}, - {HDMI_VFRMT_1920x1080p30_16_9, 1920, 1080, FALSE, 2200, 280, 1125, - 45, 33750, 30000, 74250, 30000, FALSE}, - {HDMI_VFRMT_1920x1080i50_16_9, 1920, 1080, TRUE, 2304, 384, 1250, - 85, 31250, 50000, 72000, 50000, FALSE}, - {HDMI_VFRMT_1920x1080i60_16_9, 1920, 1080, TRUE, 2200, 280, 1125, - 22, 33716, 59940, 74176, 59940, FALSE}, - {HDMI_VFRMT_1920x1080i60_16_9, 1920, 1080, TRUE, 2200, 280, 1125, - 22, 33750, 60000, 74250, 60000, FALSE}, - {HDMI_VFRMT_1920x1080i100_16_9, 1920, 1080, TRUE, 2640, 720, 1125, - 22, 56250, 100000, 148500, 100000, FALSE}, - {HDMI_VFRMT_1920x1080i120_16_9, 1920, 1080, TRUE, 2200, 280, 1125, - 22, 67432, 119880, 148352, 119980, FALSE}, - {HDMI_VFRMT_1920x1080i120_16_9, 1920, 1080, TRUE, 2200, 280, 1125, - 22, 67500, 120000, 148500, 120000, FALSE}, - - /* All 2880 H Active */ - {HDMI_VFRMT_2880x576i50_4_3, 2880, 576, TRUE, 3456, 576, 625, 24, - 15625, 50000, 54000, 50000, TRUE}, - {HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 312, 24, - 15625, 50080, 54000, 50000, TRUE}, - {HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 313, 25, - 15625, 49920, 54000, 50000, TRUE}, - {HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 314, 26, - 15625, 49761, 54000, 50000, TRUE}, - {HDMI_VFRMT_2880x576p50_4_3, 2880, 576, FALSE, 3456, 576, 625, 49, - 31250, 50000, 108000, 50000, TRUE}, - {HDMI_VFRMT_2880x480i60_4_3, 2880, 480, TRUE, 3432, 552, 525, 22, - 15734, 59940, 54000, 59940, TRUE}, - {HDMI_VFRMT_2880x240p60_4_3, 2880, 480, FALSE, 3432, 552, 262, 22, - 15734, 60054, 54000, 59940, TRUE}, - {HDMI_VFRMT_2880x240p60_4_3, 2880, 480, FALSE, 3432, 552, 263, 23, - 15734, 59940, 54000, 59940, TRUE}, - {HDMI_VFRMT_2880x480p60_4_3, 2880, 480, FALSE, 3432, 552, 525, 45, - 31469, 59940, 108000, 59940, TRUE}, - {HDMI_VFRMT_2880x480i60_4_3, 2880, 480, TRUE, 3432, 552, 525, 22, - 15750, 60000, 54054, 60000, TRUE}, - {HDMI_VFRMT_2880x240p60_4_3, 2880, 240, FALSE, 3432, 552, 262, 22, - 15750, 60115, 54054, 60000, TRUE}, - {HDMI_VFRMT_2880x240p60_4_3, 2880, 240, FALSE, 3432, 552, 262, 23, - 15750, 59886, 54054, 60000, TRUE}, - {HDMI_VFRMT_2880x480p60_4_3, 2880, 480, FALSE, 3432, 552, 525, 45, - 31500, 60000, 108108, 60000, TRUE}, -}; - -static const uint8 *hdmi_edid_find_block(const uint8 *in_buf, - uint32 start_offset, uint8 type, uint8 *len) -{ - /* the start of data block collection, start of Video Data Block */ - uint32 offset = start_offset; - uint32 end_dbc_offset = in_buf[2]; - - if(offset >= 128 || (end_dbc_offset >= (128-offset))) - return NULL; - *len = 0; - - /*edid buffer 1, byte 2 being 4 means no non-DTD/Data block collection - present. - edid buffer 1, byte 2 being 0 menas no non-DTD/DATA block collection - present and no DTD data present.*/ - if ((end_dbc_offset == 0) || (end_dbc_offset == 4)) { - DEV_WARN("EDID: no DTD or non-DTD data present\n"); - return NULL; - } - while (offset < end_dbc_offset) { - uint8 block_len = in_buf[offset] & 0x1F; - if ((block_len < end_dbc_offset - offset) && - (in_buf[offset] >> 5) == type) { - *len = block_len; - DEV_DBG("EDID: block=%d found @ %d with length=%d\n", - type, offset, block_len); - return in_buf+offset; - } - offset += 1 + block_len; - } - DEV_WARN("EDID: type=%d block not found in EDID block\n", type); - return NULL; -} - -static void hdmi_edid_extract_vendor_id(const uint8 *in_buf, - char *vendor_id) -{ - uint32 id_codes = ((uint32)in_buf[8] << 8) + in_buf[9]; - - vendor_id[0] = 'A' - 1 + ((id_codes >> 10) & 0x1F); - vendor_id[1] = 'A' - 1 + ((id_codes >> 5) & 0x1F); - vendor_id[2] = 'A' - 1 + (id_codes & 0x1F); - vendor_id[3] = 0; -} - -static uint32 hdmi_edid_extract_ieee_reg_id(const uint8 *in_buf) -{ - uint8 len; - const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3, - &len); - - if (vsd == NULL || len < 8) - return 0; - - DEV_DBG("EDID: VSD PhyAddr=%04x, MaxTMDS=%dMHz\n", - ((uint32)vsd[4] << 8) + (uint32)vsd[5], (uint32)vsd[7] * 5); - external_common_state->physical_address = - ((uint16)vsd[4] << 8) + (uint16)vsd[5]; - return ((uint32)vsd[3] << 16) + ((uint32)vsd[2] << 8) + (uint32)vsd[1]; -} - -#define HDMI_VSDB_3D_DATA_OFFSET(vsd) \ - (!((vsd)[8] & BIT(7)) ? 9 : (!((vsd)[8] & BIT(6)) ? 11 : 13)) - -static void hdmi_edid_extract_3d_present(const uint8 *in_buf) -{ - uint8 len, offset; - const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3, - &len); - - external_common_state->present_3d = 0; - if (vsd == NULL || len < 9) { - DEV_DBG("EDID[3D]: block-id 3 not found or not long enough\n"); - return; - } - - offset = HDMI_VSDB_3D_DATA_OFFSET(vsd); - DEV_DBG("EDID: 3D present @ %d = %02x\n", offset, vsd[offset]); - if (vsd[offset] >> 7) { /* 3D format indication present */ - DEV_INFO("EDID: 3D present, 3D-len=%d\n", vsd[offset+1] & 0x1F); - external_common_state->present_3d = 1; - } -} - - -static void hdmi_edid_extract_latency_fields(const uint8 *in_buf) -{ - uint8 len; - const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3, - &len); - - if (vsd == NULL || len < 12 || !(vsd[8] & BIT(7))) { - external_common_state->video_latency = (uint16)-1; - external_common_state->audio_latency = (uint16)-1; - DEV_DBG("EDID: No audio/video latency present\n"); - } else { - external_common_state->video_latency = vsd[9]; - external_common_state->audio_latency = vsd[10]; - DEV_DBG("EDID: video-latency=%04x, audio-latency=%04x\n", - external_common_state->video_latency, - external_common_state->audio_latency); - } -} - -static void hdmi_edid_extract_speaker_allocation_data(const uint8 *in_buf) -{ - uint8 len; - const uint8 *sadb = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 4, - &len); - - if (sadb == NULL) - return; - - if (len != MAX_SPKR_ALLOC_DATA_BLOCK_SIZE) - return; - - memcpy(external_common_state->spkr_alloc_data_block, sadb + 1, len); - external_common_state->sadb_size = len; -} - -static void hdmi_edid_extract_audio_data_blocks(const uint8 *in_buf) -{ - uint8 len; - const uint8 *adb = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 1, - &len); - - if (external_common_state->audio_data_block == NULL) - return; - - if (len > MAX_AUDIO_DATA_BLOCK_SIZE) - return; - - memcpy(external_common_state->audio_data_block, adb + 1, len); - external_common_state->adb_size = len; -} - -static void hdmi_edid_extract_extended_data_blocks(const uint8 *in_buf) -{ - uint8 len = 0; - uint32 start_offset = DBC_START_OFFSET; - - /* A Tage code of 7 identifies extended data blocks */ - uint8 const *etag = hdmi_edid_find_block(in_buf, start_offset, 7, &len); - - while (etag != NULL) { - /* The extended data block should at least be 2 bytes long */ - if (len < 2) { - DEV_DBG("EDID: Found an extended data block of length" - "less than 2 bytes. Ignoring ...\n"); - } else { - /* - * The second byte of the extended data block has the - * extended tag code - */ - switch (etag[1]) { - case 0: - /* Video Capability Data Block */ - DEV_DBG("EDID: VCDB=%02X %02X\n", etag[1], - etag[2]); - - /* - * Check if the sink specifies underscan - * support for: - * BIT 5: preferred video format - * BIT 3: IT video format - * BIT 1: CE video format - */ - external_common_state->pt_scan_info = (etag[2] & - (BIT(4) | BIT(5))) >> 4; - external_common_state->it_scan_info = (etag[2] & - (BIT(3) | BIT(2))) >> 2; - external_common_state->ce_scan_info = etag[2] & - (BIT(1) | BIT(0)); - DEV_DBG("EDID: Scan Information (pt|it|ce): " - "(%d|%d|%d)", - external_common_state->pt_scan_info, - external_common_state->it_scan_info, - external_common_state->ce_scan_info); - break; - default: - DEV_DBG("EDID: Extend Tag Code %d not" - "supported\n", etag[1]); - break; - } - } - - /* There could be more that one extended data block */ - start_offset = etag - in_buf + len + 1; - etag = hdmi_edid_find_block(in_buf, start_offset, 7, &len); - } -} - -static void hdmi_edid_detail_desc(const uint8 *data_buf, uint32 *disp_mode) -{ - boolean aspect_ratio_4_3 = FALSE; - boolean interlaced = FALSE; - uint32 active_h = 0; - uint32 active_v = 0; - uint32 blank_h = 0; - uint32 blank_v = 0; - uint32 ndx = 0; - uint32 max_num_of_elements = 0; - uint32 img_size_h = 0; - uint32 img_size_v = 0; - - /* See VESA Spec */ - /* EDID_TIMING_DESC_UPPER_H_NIBBLE[0x4]: Relative Offset to the EDID - * detailed timing descriptors - Upper 4 bit for each H active/blank - * field */ - /* EDID_TIMING_DESC_H_ACTIVE[0x2]: Relative Offset to the EDID detailed - * timing descriptors - H active */ - active_h = ((((uint32)data_buf[0x4] >> 0x4) & 0xF) << 8) - | data_buf[0x2]; - - /* EDID_TIMING_DESC_H_BLANK[0x3]: Relative Offset to the EDID detailed - * timing descriptors - H blank */ - blank_h = (((uint32)data_buf[0x4] & 0xF) << 8) - | data_buf[0x3]; - - /* EDID_TIMING_DESC_UPPER_V_NIBBLE[0x7]: Relative Offset to the EDID - * detailed timing descriptors - Upper 4 bit for each V active/blank - * field */ - /* EDID_TIMING_DESC_V_ACTIVE[0x5]: Relative Offset to the EDID detailed - * timing descriptors - V active */ - active_v = ((((uint32)data_buf[0x7] >> 0x4) & 0xF) << 8) - | data_buf[0x5]; - - /* EDID_TIMING_DESC_V_BLANK[0x6]: Relative Offset to the EDID detailed - * timing descriptors - V blank */ - blank_v = (((uint32)data_buf[0x7] & 0xF) << 8) - | data_buf[0x6]; - - /* EDID_TIMING_DESC_IMAGE_SIZE_UPPER_NIBBLE[0xE]: Relative Offset to the - * EDID detailed timing descriptors - Image Size upper nibble - * V and H */ - /* EDID_TIMING_DESC_H_IMAGE_SIZE[0xC]: Relative Offset to the EDID - * detailed timing descriptors - H image size */ - /* EDID_TIMING_DESC_V_IMAGE_SIZE[0xD]: Relative Offset to the EDID - * detailed timing descriptors - V image size */ - img_size_h = ((((uint32)data_buf[0xE] >> 0x4) & 0xF) << 8) - | data_buf[0xC]; - img_size_v = (((uint32)data_buf[0xE] & 0xF) << 8) - | data_buf[0xD]; - - /* - * aspect ratio as 4:3 if within specificed range , rathaer than being - * absolute value - */ - aspect_ratio_4_3 = (abs(img_size_h * 3 - img_size_v * 4) < 5) ? 1 : 0; - - max_num_of_elements = sizeof(hdmi_edid_disp_mode_lut) - / sizeof(*hdmi_edid_disp_mode_lut); - - /* EDID_TIMING_DESC_INTERLACE[0x11:7]: Relative Offset to the EDID - * detailed timing descriptors - Interlace flag */ - DEV_DBG("Interlaced mode byte data_buf[0x11]=[%x]\n", data_buf[0x11]); - /* - * CEA 861-D: interlaced bit is bit[7] of byte[0x11] - */ - interlaced = (data_buf[0x11] & 0x80) >> 7; - - DEV_DBG("%s: A[%ux%u] B[%ux%u] V[%ux%u] %s\n", __func__, - active_h, active_v, blank_h, blank_v, img_size_h, img_size_v, - interlaced ? "i" : "p"); - - *disp_mode = HDMI_VFRMT_FORCE_32BIT; - while (ndx < max_num_of_elements) { - const struct hdmi_edid_video_mode_property_type *edid = - hdmi_edid_disp_mode_lut+ndx; - - if ((interlaced == edid->interlaced) && - (active_h == edid->active_h) && - (blank_h == edid->total_blank_h) && - (blank_v == edid->total_blank_v) && - ((active_v == edid->active_v) || - (active_v == (edid->active_v + 1))) - ) { - if (edid->aspect_ratio_4_3 && !aspect_ratio_4_3) - /* Aspect ratio 16:9 */ - *disp_mode = edid->video_code + 1; - else - /* Aspect ratio 4:3 */ - *disp_mode = edid->video_code; - - DEV_DBG("%s: mode found:%d\n", __func__, *disp_mode); - break; - } - ++ndx; - } - if (ndx == max_num_of_elements) - DEV_INFO("%s: *no mode* found\n", __func__); -} - -static void limit_supported_video_format(uint32 *video_format) -{ - switch(sp_get_link_bw()){ - case 0x0a: - if((*video_format == HDMI_VFRMT_1920x1080p60_16_9) || - (*video_format == HDMI_VFRMT_2880x480p60_4_3)|| - (*video_format == HDMI_VFRMT_2880x480p60_16_9) || - (*video_format == HDMI_VFRMT_1280x720p120_16_9)) - - *video_format = HDMI_VFRMT_1280x720p60_16_9; - else if((*video_format == HDMI_VFRMT_1920x1080p50_16_9) || - (*video_format == HDMI_VFRMT_2880x576p50_4_3)|| - (*video_format == HDMI_VFRMT_2880x576p50_16_9) || - (*video_format == HDMI_VFRMT_1280x720p100_16_9)) - - *video_format = HDMI_VFRMT_1280x720p50_16_9; - else if (*video_format == HDMI_VFRMT_1920x1080i100_16_9) - *video_format = HDMI_VFRMT_1920x1080i50_16_9; - - else if (*video_format == HDMI_VFRMT_1920x1080i120_16_9) - *video_format = HDMI_VFRMT_1920x1080i60_16_9; - break; - case 0x06: - if(*video_format != HDMI_VFRMT_640x480p60_4_3) - *video_format = HDMI_VFRMT_640x480p60_4_3; - break; - case 0x14: - default: - break; - } -} - -static void add_supported_video_format( - struct hdmi_disp_mode_list_type *disp_mode_list, - uint32 video_format) -{ - const struct msm_hdmi_mode_timing_info *timing; - boolean supported = false; - boolean mhl_supported = true; - limit_supported_video_format(&video_format); - - if (video_format >= HDMI_VFRMT_MAX) - return; - - timing = hdmi_common_get_supported_mode(video_format); - supported = timing != NULL; - DEV_DBG("EDID: format: %d [%s], %s\n", - video_format, msm_hdmi_mode_2string(video_format), - supported ? "Supported" : "Not-Supported"); - - if (mhl_is_connected()) { - const struct msm_hdmi_mode_timing_info *mhl_timing = - hdmi_mhl_get_supported_mode(video_format); - mhl_supported = mhl_timing != NULL; - DEV_DBG("EDID: format: %d [%s], %s by MHL\n", - video_format, - msm_hdmi_mode_2string(video_format), - mhl_supported ? "Supported" : "Not-Supported"); - } - - if (supported && mhl_supported) { - disp_mode_list->disp_mode_list[ - disp_mode_list->num_of_elements++] = video_format; - if (video_format == external_common_state->video_resolution) { - DEV_DBG("%s: Default resolution %d [%s] supported\n", - __func__, video_format, - msm_hdmi_mode_2string(video_format)); - } - } -} - -const char *single_video_3d_format_2string(uint32 format) -{ - switch (format) { - case TOP_AND_BOTTOM: return "TAB"; - case FRAME_PACKING: return "FP"; - case SIDE_BY_SIDE_HALF: return "SSH"; - } - return ""; -} - -ssize_t video_3d_format_2string(uint32 format, char *buf, u32 size) -{ - ssize_t ret, len = 0; - ret = scnprintf(buf, size, "%s", - single_video_3d_format_2string(format & FRAME_PACKING)); - len += ret; - - if (len && (format & TOP_AND_BOTTOM)) - ret = scnprintf(buf + len, size - len, ":%s", - single_video_3d_format_2string( - format & TOP_AND_BOTTOM)); - else - ret = scnprintf(buf + len, size - len, "%s", - single_video_3d_format_2string( - format & TOP_AND_BOTTOM)); - len += ret; - - if (len && (format & SIDE_BY_SIDE_HALF)) - ret = scnprintf(buf + len, size - len, ":%s", - single_video_3d_format_2string( - format & SIDE_BY_SIDE_HALF)); - else - ret = scnprintf(buf + len, size - len, "%s", - single_video_3d_format_2string( - format & SIDE_BY_SIDE_HALF)); - len += ret; - - return len; -} - -static void add_supported_3d_format( - struct hdmi_disp_mode_list_type *disp_mode_list, - uint32 video_format, - uint32 video_3d_format) -{ - char string[128]; - boolean added = FALSE; - int i; - for (i = 0; i < disp_mode_list->num_of_elements; ++i) { - if (disp_mode_list->disp_mode_list[i] == video_format) { - disp_mode_list->disp_3d_mode_list[i] |= - video_3d_format; - added = TRUE; - break; - } - } - video_3d_format_2string(video_3d_format, string, sizeof(string)); - DEV_DBG("EDID[3D]: format: %d [%s], %s %s\n", - video_format, msm_hdmi_mode_2string(video_format), - string, added ? "added" : "NOT added"); -} - -static int hdmi_edid_get_display_vsd_3d_mode(const uint8 *data_buf, - struct hdmi_disp_mode_list_type *disp_mode_list, - uint32 num_og_cea_blocks) -{ - uint8 len, offset, present_multi_3d, hdmi_vic_len; - int hdmi_3d_len; - uint16 structure_all, structure_mask; - const uint8 *vsd = num_og_cea_blocks ? - hdmi_edid_find_block(data_buf+0x80, DBC_START_OFFSET, - 3, &len) : NULL; - int i; - - offset = HDMI_VSDB_3D_DATA_OFFSET(vsd); - if (offset >= len - 1) - return -ETOOSMALL; - present_multi_3d = (vsd[offset] & 0x60) >> 5; - - offset += 1; - hdmi_vic_len = (vsd[offset] >> 5) & 0x7; - hdmi_3d_len = vsd[offset] & 0x1F; - DEV_DBG("EDID[3D]: HDMI_VIC_LEN = %d, HDMI_3D_LEN = %d\n", - hdmi_vic_len, hdmi_3d_len); - - offset += (hdmi_vic_len + 1); - if (offset >= len - 1) - return -ETOOSMALL; - if (present_multi_3d == 1 || present_multi_3d == 2) { - DEV_DBG("EDID[3D]: multi 3D present (%d)\n", present_multi_3d); - /* 3d_structure_all */ - structure_all = (vsd[offset] << 8) | vsd[offset + 1]; - offset += 2; - if (offset >= len - 1) - return -ETOOSMALL; - hdmi_3d_len -= 2; - if (present_multi_3d == 2) { - /* 3d_structure_mask */ - structure_mask = (vsd[offset] << 8) | vsd[offset + 1]; - offset += 2; - hdmi_3d_len -= 2; - } else - structure_mask = 0xffff; - - i = 0; - while (i < 16) { - if (i >= disp_mode_list->disp_multi_3d_mode_list_cnt) - break; - - if (!(structure_mask & BIT(i))) { - ++i; - continue; - } - - /* BIT0: FRAME PACKING */ - if (structure_all & BIT(0)) - add_supported_3d_format(disp_mode_list, - disp_mode_list-> - disp_multi_3d_mode_list[i], - FRAME_PACKING); - - /* BIT6: TOP AND BOTTOM */ - if (structure_all & BIT(6)) - add_supported_3d_format(disp_mode_list, - disp_mode_list-> - disp_multi_3d_mode_list[i], - TOP_AND_BOTTOM); - - /* BIT8: SIDE BY SIDE HALF */ - if (structure_all & BIT(8)) - add_supported_3d_format(disp_mode_list, - disp_mode_list-> - disp_multi_3d_mode_list[i], - SIDE_BY_SIDE_HALF); - - ++i; - } - } - - i = 0; - while (hdmi_3d_len > 0) { - if (offset >= len - 1) - return -ETOOSMALL; - DEV_DBG("EDID[3D]: 3D_Structure_%d @ %d: %02x\n", - i + 1, offset, vsd[offset]); - - if ((vsd[offset] >> 4) >= - disp_mode_list->disp_multi_3d_mode_list_cnt) { - if ((vsd[offset] & 0x0F) >= 8) { - offset += 1; - hdmi_3d_len -= 1; - DEV_DBG("EDID[3D]: 3D_Detail_%d @ %d: %02x\n", - i + 1, offset, vsd[offset]); - } - i += 1; - offset += 1; - hdmi_3d_len -= 1; - continue; - } - - switch (vsd[offset] & 0x0F) { - case 0: - /* 0000b: FRAME PACKING */ - add_supported_3d_format(disp_mode_list, - disp_mode_list->disp_multi_3d_mode_list - [vsd[offset] >> 4], - FRAME_PACKING); - break; - case 6: - /* 0110b: TOP AND BOTTOM */ - add_supported_3d_format(disp_mode_list, - disp_mode_list->disp_multi_3d_mode_list - [vsd[offset] >> 4], - TOP_AND_BOTTOM); - break; - case 8: - /* 1000b: SIDE BY SIDE HALF */ - add_supported_3d_format(disp_mode_list, - disp_mode_list->disp_multi_3d_mode_list - [vsd[offset] >> 4], - SIDE_BY_SIDE_HALF); - break; - } - if ((vsd[offset] & 0x0F) >= 8) { - offset += 1; - hdmi_3d_len -= 1; - DEV_DBG("EDID[3D]: 3D_Detail_%d @ %d: %02x\n", - i + 1, offset, vsd[offset]); - } - i += 1; - offset += 1; - hdmi_3d_len -= 1; - } - return 0; -} - -static void hdmi_edid_get_display_mode(const uint8 *data_buf, - struct hdmi_disp_mode_list_type *disp_mode_list, - uint32 num_og_cea_blocks) -{ - uint8 i = 0, offset = 0, std_blk = 0; - uint32 video_format = HDMI_VFRMT_640x480p60_4_3; - boolean has480p = FALSE; - uint8 len; - int rc; - const uint8 *edid_blk0 = &data_buf[0x0]; - const uint8 *edid_blk1 = &data_buf[0x80]; - const uint8 *svd = num_og_cea_blocks ? - hdmi_edid_find_block(data_buf+0x80, DBC_START_OFFSET, - 2, &len) : NULL; - boolean has60hz_mode = FALSE; - boolean has50hz_mode = FALSE; - - - disp_mode_list->num_of_elements = 0; - disp_mode_list->disp_multi_3d_mode_list_cnt = 0; - if (svd != NULL) { - ++svd; - for (i = 0; i < len; ++i, ++svd) { - /* Subtract 1 because it is zero based in the driver, - * while the Video identification code is 1 based in the - * CEA_861D spec */ - video_format = (*svd & 0x7F); - add_supported_video_format(disp_mode_list, - video_format); - /* Make a note of the preferred video format */ - if (i == 0) { - external_common_state->preferred_video_format = - video_format; - } - if (i < 16) { - disp_mode_list->disp_multi_3d_mode_list[i] - = video_format; - disp_mode_list->disp_multi_3d_mode_list_cnt++; - } - - if (video_format <= HDMI_VFRMT_1920x1080p60_16_9 || - video_format == HDMI_VFRMT_2880x480p60_4_3 || - video_format == HDMI_VFRMT_2880x480p60_16_9) - has60hz_mode = TRUE; - - if ((video_format >= HDMI_VFRMT_720x576p50_4_3 && - video_format <= HDMI_VFRMT_1920x1080p50_16_9) || - video_format == HDMI_VFRMT_2880x576p50_4_3 || - video_format == HDMI_VFRMT_2880x576p50_16_9 || - video_format == HDMI_VFRMT_1920x1250i50_16_9) - has50hz_mode = TRUE; - if (video_format == HDMI_VFRMT_640x480p60_4_3) - has480p = TRUE; - } - } else if (!num_og_cea_blocks) { - /* Detailed timing descriptors */ - uint32 desc_offset = 0; - /* Maximum 4 timing descriptor in block 0 - No CEA - * extension in this case */ - /* EDID_FIRST_TIMING_DESC[0x36] - 1st detailed timing - * descriptor */ - /* EDID_DETAIL_TIMING_DESC_BLCK_SZ[0x12] - Each detailed timing - * descriptor has block size of 18 */ - while (4 > i && 0 != edid_blk0[0x36+desc_offset]) { - hdmi_edid_detail_desc(edid_blk0+0x36+desc_offset, - &video_format); - DEV_DBG("[%s:%d] Block-0 Adding vid fmt = [%s]\n", - __func__, __LINE__, - msm_hdmi_mode_2string(video_format)); - add_supported_video_format(disp_mode_list, - video_format); - if (video_format == HDMI_VFRMT_640x480p60_4_3) - has480p = TRUE; - /* Make a note of the preferred video format */ - if (i == 0) { - external_common_state->preferred_video_format = - video_format; - } - desc_offset += 0x12; - ++i; - } - } else if (1 == num_og_cea_blocks) { - uint32 desc_offset = 0; - - /* - * Read from both block 0 and block 1 - * Read EDID block[0] as above - */ - while (4 > i && 0 != edid_blk0[0x36+desc_offset]) { - hdmi_edid_detail_desc(edid_blk0+0x36+desc_offset, - &video_format); - DEV_DBG("[%s:%d] Block-0 Adding vid fmt = [%s]\n", - __func__, __LINE__, - msm_hdmi_mode_2string(video_format)); - add_supported_video_format(disp_mode_list, - video_format); - if (video_format == HDMI_VFRMT_640x480p60_4_3) - has480p = TRUE; - /* Make a note of the preferred video format */ - if (i == 0) { - external_common_state->preferred_video_format = - video_format; - } - desc_offset += 0x12; - ++i; - } - - /* Parse block 1 - CEA extension byte offset of first - * detailed timing generation - offset is relevant to - * the offset of block 1 */ - - /* EDID_CEA_EXTENSION_FIRST_DESC[0x82]: Offset to CEA - * extension first timing desc - indicate the offset of - * the first detailed timing descriptor */ - /* EDID_BLOCK_SIZE = 0x80 Each page size in the EDID ROM */ - desc_offset = edid_blk1[0x02]; - while (0 != edid_blk1[desc_offset]) { - hdmi_edid_detail_desc(edid_blk1+desc_offset, - &video_format); - DEV_DBG("[%s:%d] Block-1 Adding vid fmt = [%s]\n", - __func__, __LINE__, - msm_hdmi_mode_2string(video_format)); - add_supported_video_format(disp_mode_list, - video_format); - if (video_format == HDMI_VFRMT_640x480p60_4_3) - has480p = TRUE; - /* Make a note of the preferred video format */ - if (i == 0) { - external_common_state->preferred_video_format = - video_format; - } - desc_offset += 0x12; - ++i; - } - } - - - /* - * Check SD Timings if it contains 1280x1024@60Hz. - * SD Timing can be max 8 with 2 byte in size. - */ - std_blk = 0; - offset = 0; - while (std_blk < 8) { - if ((edid_blk0[0x26 + offset] == 0x81) && - (edid_blk0[0x26 + offset + 1] == 0x80)) { - add_supported_video_format(disp_mode_list, - HDMI_VFRMT_1280x1024p60_5_4); - break; - } else { - offset += 2; - } - std_blk++; - } - - /* check if the EDID revision is 4 (version 1.4) */ - if (edid_blk0[0x13] == 4) { - uint8 start = 0x36; - - i = 0; - - /* Check each of 4 - 18 bytes descriptors */ - while (i < 4) { - uint8 itrate = start; - uint32 header_1 = 0; - uint8 header_2 = 0; - - /* - * First 5 bytes are header. - * If they match 0x000000F700, it means its an - * established Timing III descriptor. - */ - header_1 = edid_blk0[itrate++]; - header_1 = header_1 << 8 | edid_blk0[itrate++]; - header_1 = header_1 << 8 | edid_blk0[itrate++]; - header_1 = header_1 << 8 | edid_blk0[itrate++]; - header_2 = edid_blk0[itrate]; - - if (header_1 == 0x000000F7 && - header_2 == 0x00) { - itrate++; /* VESA DMT Standard Version (0x0A)*/ - itrate++; /* First set of supported formats */ - itrate++; /* Second set of supported formats */ - /* BIT(1) indicates 1280x1024@60Hz */ - if (edid_blk0[itrate] & 0x02) { - add_supported_video_format( - disp_mode_list, - HDMI_VFRMT_1280x1024p60_5_4); - break; - } - } - i++; - start += 0x12; - } - } - - /* mandaroty 3d format */ - if (external_common_state->present_3d) { - if (has60hz_mode) { - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1920x1080p24_16_9, - FRAME_PACKING | TOP_AND_BOTTOM); - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1280x720p60_16_9, - FRAME_PACKING | TOP_AND_BOTTOM); - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1920x1080i60_16_9, - SIDE_BY_SIDE_HALF); - } - if (has50hz_mode) { - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1920x1080p24_16_9, - FRAME_PACKING | TOP_AND_BOTTOM); - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1280x720p50_16_9, - FRAME_PACKING | TOP_AND_BOTTOM); - add_supported_3d_format(disp_mode_list, - HDMI_VFRMT_1920x1080i50_16_9, - SIDE_BY_SIDE_HALF); - } - - /* 3d format described in Vendor Specific Data */ - rc = hdmi_edid_get_display_vsd_3d_mode(data_buf, disp_mode_list, - num_og_cea_blocks); - if (!rc) - pr_debug("%s: 3D formats in VSD\n", __func__); - } - - if (!has480p) - /* Need to add default 640 by 480 timings, in case not described - * in the EDID structure. - * All DTV sink devices should support this mode */ - add_supported_video_format(disp_mode_list, - HDMI_VFRMT_640x480p60_4_3); -} - -static int hdmi_common_read_edid_block(int block, uint8 *edid_buf) -{ - uint32 ndx, check_sum, print_len; -#ifdef DEBUG - const u8 *b = edid_buf; -#endif - int status = external_common_state->read_edid_block(block, edid_buf); - if (status) - goto error; - - /* Calculate checksum */ - check_sum = 0; - for (ndx = 0; ndx < 0x80; ++ndx) - check_sum += edid_buf[ndx]; - - if (check_sum & 0xFF) { - DEV_ERR("%s: failed CHECKSUM (read:%x, expected:%x)\n", - __func__, (uint8)edid_buf[0x7F], (uint8)check_sum); -#ifdef DEBUG - for (ndx = 0; ndx < 0x100; ndx += 16) - DEV_DBG("EDID[%02x-%02x] %02x %02x %02x %02x " - "%02x %02x %02x %02x %02x %02x %02x %02x " - "%02x %02x %02x %02x\n", ndx, ndx+15, - b[ndx+0], b[ndx+1], b[ndx+2], b[ndx+3], - b[ndx+4], b[ndx+5], b[ndx+6], b[ndx+7], - b[ndx+8], b[ndx+9], b[ndx+10], b[ndx+11], - b[ndx+12], b[ndx+13], b[ndx+14], b[ndx+15]); -#endif - status = -EPROTO; - goto error; - } - print_len = 0x80; - for (ndx = 0; ndx < print_len; ndx += 16) - DEV_DBG("EDID[%02x-%02x] %02x %02x %02x %02x " - "%02x %02x %02x %02x %02x %02x %02x %02x " - "%02x %02x %02x %02x\n", ndx, ndx+15, - b[ndx+0], b[ndx+1], b[ndx+2], b[ndx+3], - b[ndx+4], b[ndx+5], b[ndx+6], b[ndx+7], - b[ndx+8], b[ndx+9], b[ndx+10], b[ndx+11], - b[ndx+12], b[ndx+13], b[ndx+14], b[ndx+15]); - - -error: - return status; -} - -static boolean check_edid_header(const uint8 *edid_buf) -{ - return (edid_buf[0] == 0x00) && (edid_buf[1] == 0xff) - && (edid_buf[2] == 0xff) && (edid_buf[3] == 0xff) - && (edid_buf[4] == 0xff) && (edid_buf[5] == 0xff) - && (edid_buf[6] == 0xff) && (edid_buf[7] == 0x00); -} - -int hdmi_common_read_edid(void) -{ - int status = 0; - uint32 cea_extension_ver = 0; - uint32 num_og_cea_blocks = 0; - uint32 ieee_reg_id = 0; - uint32 i = 1; - char vendor_id[5]; - /* EDID_BLOCK_SIZE[0x80] Each page size in the EDID ROM */ - uint8 edid_buf[0x80 * 4]; - - external_common_state->pt_scan_info = 0; - external_common_state->it_scan_info = 0; - external_common_state->ce_scan_info = 0; - external_common_state->preferred_video_format = 0; - external_common_state->present_3d = 0; - memset(&external_common_state->disp_mode_list, 0, - sizeof(external_common_state->disp_mode_list)); - memset(edid_buf, 0, sizeof(edid_buf)); - memset(external_common_state->audio_data_block, 0, - sizeof(external_common_state->audio_data_block)); - memset(external_common_state->spkr_alloc_data_block, 0, - sizeof(external_common_state->spkr_alloc_data_block)); - external_common_state->adb_size = 0; - external_common_state->sadb_size = 0; - - status = hdmi_common_read_edid_block(0, edid_buf); - if (status || !check_edid_header(edid_buf)) { - if (!status) - status = -EPROTO; - DEV_ERR("%s: edid read block(0) failed: %d " - "[%02x%02x%02x%02x%02x%02x%02x%02x]\n", __func__, - status, - edid_buf[0], edid_buf[1], edid_buf[2], edid_buf[3], - edid_buf[4], edid_buf[5], edid_buf[6], edid_buf[7]); - goto error; - } - hdmi_edid_extract_vendor_id(edid_buf, vendor_id); - - /* EDID_CEA_EXTENSION_FLAG[0x7E] - CEC extension byte */ - num_og_cea_blocks = edid_buf[0x7E]; - - DEV_DBG("[JSR] (%s): No. of CEA blocks is [%u]\n", __func__, - num_og_cea_blocks); - /* Find out any CEA extension blocks following block 0 */ - switch (num_og_cea_blocks) { - case 0: /* No CEA extension */ - external_common_state->hdmi_sink = false; - DEV_DBG("HDMI DVI mode: %s\n", - external_common_state->hdmi_sink ? "no" : "yes"); - break; - case 1: /* Read block 1 */ - status = hdmi_common_read_edid_block(1, &edid_buf[0x80]); - if (status) { - DEV_ERR("%s: ddc read block(1) failed: %d\n", __func__, - status); - goto error; - } - if (edid_buf[0x80] != 2) - num_og_cea_blocks = 0; - if (num_og_cea_blocks) { - ieee_reg_id = - hdmi_edid_extract_ieee_reg_id(edid_buf+0x80); - if (ieee_reg_id == 0x0c03) - external_common_state->hdmi_sink = TRUE ; - else - external_common_state->hdmi_sink = FALSE ; - hdmi_edid_extract_latency_fields(edid_buf+0x80); - hdmi_edid_extract_speaker_allocation_data( - edid_buf+0x80); - hdmi_edid_extract_audio_data_blocks(edid_buf+0x80); - hdmi_edid_extract_3d_present(edid_buf+0x80); - hdmi_edid_extract_extended_data_blocks(edid_buf+0x80); - } - break; - case 2: - case 3: - case 4: - for (i = 1; i <= num_og_cea_blocks; i++) { - if (!(i % 2)) { - status = hdmi_common_read_edid_block(i, - edid_buf+0x00); - if (status) { - DEV_ERR("%s: ddc read block(%d)" - "failed: %d\n", __func__, i, - status); - goto error; - } - } else { - status = hdmi_common_read_edid_block(i, - edid_buf+0x80); - if (status) { - DEV_ERR("%s: ddc read block(%d)" - "failed:%d\n", __func__, i, - status); - goto error; - } - } - } - break; - default: - DEV_ERR("%s: ddc read failed, not supported multi-blocks: %d\n", - __func__, num_og_cea_blocks); - status = -EPROTO; - goto error; - } - - if (num_og_cea_blocks) { - /* EDID_CEA_EXTENSION_VERSION[0x81]: Offset to CEA extension - * version number - v1,v2,v3 (v1 is seldom, v2 is obsolete, - * v3 most common) */ - cea_extension_ver = edid_buf[0x81]; - } - - /* EDID_VERSION[0x12] - EDID Version */ - /* EDID_REVISION[0x13] - EDID Revision */ - DEV_INFO("EDID (V=%d.%d, #CEABlocks=%d[V%d], ID=%s, IEEE=%04x, " - "EDID-Ext=0x%02x)\n", edid_buf[0x12], edid_buf[0x13], - num_og_cea_blocks, cea_extension_ver, vendor_id, ieee_reg_id, - edid_buf[0x80]); - - hdmi_edid_get_display_mode(edid_buf, - &external_common_state->disp_mode_list, num_og_cea_blocks); - - return 0; - -error: - external_common_state->disp_mode_list.num_of_elements = 1; - external_common_state->disp_mode_list.disp_mode_list[0] = - external_common_state->video_resolution; - return status; -} -EXPORT_SYMBOL(hdmi_common_read_edid); - -bool hdmi_common_get_video_format_from_drv_data(struct msm_fb_data_type *mfd) -{ - uint32 format = external_common_state->video_resolution; - struct fb_var_screeninfo *var = &mfd->fbi->var; - bool changed = TRUE; - uint32_t userformat = 0; - userformat = var->reserved[3] >> 16; - - if (userformat) { - format = userformat; - DEV_DBG("reserved format is %d\n", format); - } else if (hdmi_prim_resolution) { - format = hdmi_prim_resolution; - } else { - DEV_DBG("detecting resolution from %dx%d use top 2 bytes of" - " var->reserved[3] to specify mode", mfd->var_xres, - mfd->var_yres); - switch (mfd->var_xres) { - default: - case 640: - format = HDMI_VFRMT_640x480p60_4_3; - break; - case 720: - format = (mfd->var_yres == 480) - ? HDMI_VFRMT_720x480p60_16_9 - : HDMI_VFRMT_720x576p50_16_9; - break; - case 1280: - if (mfd->var_yres == 1024) - format = HDMI_VFRMT_1280x1024p60_5_4; - else if (mfd->var_frame_rate == 50) - format = HDMI_VFRMT_1280x720p50_16_9; - else - format = HDMI_VFRMT_1280x720p60_16_9; - break; - case 1440: - format = (mfd->var_yres == 240) /* interlaced has half - of y res. - */ - ? HDMI_VFRMT_1440x480i60_16_9 - : HDMI_VFRMT_1440x576i50_16_9; - break; - case 1920: - if (mfd->var_yres == 540) {/* interlaced */ - format = HDMI_VFRMT_1920x1080i60_16_9; - } else if (mfd->var_yres == 1080) { - if (mfd->var_frame_rate == 50) - format = HDMI_VFRMT_1920x1080p50_16_9; - else if (mfd->var_frame_rate == 24) - format = HDMI_VFRMT_1920x1080p24_16_9; - else if (mfd->var_frame_rate == 25) - format = HDMI_VFRMT_1920x1080p25_16_9; - else if (mfd->var_frame_rate == 30) - format = HDMI_VFRMT_1920x1080p30_16_9; - else - format = HDMI_VFRMT_1920x1080p60_16_9; - } - break; - } - } - - changed = external_common_state->video_resolution != format; - if (external_common_state->video_resolution != format) - DEV_DBG("switching %s => %s", msm_hdmi_mode_2string( - external_common_state->video_resolution), - msm_hdmi_mode_2string(format)); - else - DEV_DBG("resolution %s", msm_hdmi_mode_2string( - external_common_state->video_resolution)); - external_common_state->video_resolution = format; - return changed; -} -EXPORT_SYMBOL(hdmi_common_get_video_format_from_drv_data); - -const struct msm_hdmi_mode_timing_info *hdmi_common_get_mode(uint32 mode) -{ - if (mode >= HDMI_VFRMT_MAX) - return NULL; - - return &hdmi_common_supported_video_mode_lut[mode]; -} -EXPORT_SYMBOL(hdmi_common_get_mode); - -const struct msm_hdmi_mode_timing_info *hdmi_common_get_supported_mode( - uint32 mode) -{ - const struct msm_hdmi_mode_timing_info *ret - = hdmi_common_get_mode(mode); - - if (ret == NULL || !ret->supported) - return NULL; - return ret; -} -EXPORT_SYMBOL(hdmi_common_get_supported_mode); - -const struct msm_hdmi_mode_timing_info *hdmi_mhl_get_mode(uint32 mode) -{ - if (mode >= HDMI_VFRMT_MAX) - return NULL; - - return &hdmi_mhl_supported_video_mode_lut[mode]; -} -EXPORT_SYMBOL(hdmi_mhl_get_mode); - -const struct msm_hdmi_mode_timing_info *hdmi_mhl_get_supported_mode( - uint32 mode) -{ - const struct msm_hdmi_mode_timing_info *ret - = hdmi_mhl_get_mode(mode); - - if (ret == NULL || !ret->supported) - return NULL; - return ret; -} -EXPORT_SYMBOL(hdmi_mhl_get_supported_mode); - -void hdmi_common_init_panel_info(struct msm_panel_info *pinfo) -{ - const struct msm_hdmi_mode_timing_info *timing = - hdmi_common_get_supported_mode( - external_common_state->video_resolution); - - if (timing == NULL) - return; - - pinfo->xres = timing->active_h; - pinfo->yres = timing->active_v; - pinfo->clk_rate = timing->pixel_freq*1000; - pinfo->frame_rate = timing->refresh_rate/1000; - - pinfo->lcdc.h_back_porch = timing->back_porch_h; - pinfo->lcdc.h_front_porch = timing->front_porch_h; - pinfo->lcdc.h_pulse_width = timing->pulse_width_h; - pinfo->lcdc.v_back_porch = timing->back_porch_v; - pinfo->lcdc.v_front_porch = timing->front_porch_v; - pinfo->lcdc.v_pulse_width = timing->pulse_width_v; - - pinfo->type = DTV_PANEL; - pinfo->pdest = DISPLAY_2; - pinfo->wait_cycle = 0; - pinfo->bpp = 24; - if (hdmi_prim_display) - pinfo->fb_num = 2; - else - pinfo->fb_num = 1; - - /* blk */ - pinfo->lcdc.border_clr = 0; - /* blue */ - pinfo->lcdc.underflow_clr = 0xff; - pinfo->lcdc.hsync_skew = 0; -} -EXPORT_SYMBOL(hdmi_common_init_panel_info); -#endif diff --git a/drivers/video/msm/external_common.h b/drivers/video/msm/external_common.h deleted file mode 100644 index b22f58bb6..000000000 --- a/drivers/video/msm/external_common.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef __EXTERNAL_COMMON_H__ -#define __EXTERNAL_COMMON_H__ -#include -#include