Bender.yml

# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

package:
  name: snitch_cluster
  authors:
    - Florian Zaruba <zarubaf@iis.ee.ethz.ch>
    - Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
    - Paul Scheffler <paulsc@iis.ee.ethz.ch>  # current maintainer
    - Thomas Benz <tbenz@iis.ee.ethz.ch>
    - Gianna Paulin <pauling@iis.ee.ethz.ch>
    - Tim Fischer <fischeti@iis.ee.ethz.ch>
    - Noah Huetter <huettern@ethz.ch>
    - Luca Colagrande <colluca@iis.ee.ethz.ch>
    - Samuel Riedel <sriedel@iis.ee.ethz.ch>
    - Nils Wistoff <nwistoff@iis.ee.ethz.ch>
    - Luca Bertaccini <lbertaccini@iis.ee.ethz.ch>
    - Matheus Cavalcante <matheusd@iis.ee.ethz.ch>

dependencies:
  axi:                { git: https://github.com/pulp-platform/axi,                rev:  4e54ac6766b160217a83a74d5a23af9bbf59e6ee  }
  axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0   }
  common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.35.0  }
  FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",        rev:      pulp-v0.1.3 }
  register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2   }
  tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11  }
  riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0   }
  cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, version:  0.1.0   }
  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__9cbcd30__snitch-tracing }

export_include_dirs:
  - hw/reqrsp_interface/include
  - hw/mem_interface/include
  - hw/tcdm_interface/include
  - hw/snitch/include
  - hw/snitch_ssr/include

sources:
  # reqrsp_interface
  - files:
      # Level 0
      - hw/reqrsp_interface/src/reqrsp_pkg.sv
      # Level 1
      - hw/reqrsp_interface/src/reqrsp_intf.sv
      # Level 2
      - hw/reqrsp_interface/src/axi_to_reqrsp.sv
      - hw/reqrsp_interface/src/reqrsp_cut.sv
      - hw/reqrsp_interface/src/reqrsp_demux.sv
      - hw/reqrsp_interface/src/reqrsp_iso.sv
      - hw/reqrsp_interface/src/reqrsp_mux.sv
      - hw/reqrsp_interface/src/reqrsp_to_axi.sv
  - target: simulation
    files:
      - hw/reqrsp_interface/src/reqrsp_test.sv
  - target: test
    files:
      - hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv
      - hw/reqrsp_interface/test/reqrsp_demux_tb.sv
      - hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv
      - hw/reqrsp_interface/test/reqrsp_mux_tb.sv
      - hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv

  # mem_interface
  - files:
      - hw/mem_interface/src/mem_wide_narrow_mux.sv
      - hw/mem_interface/src/mem_interface.sv
  - target: simulation
    files:
      - hw/mem_interface/src/mem_test.sv
  - target: test
    files:
      - hw/mem_interface/test/mem_wide_narrow_mux_tb.sv

  # tcdm_interface
  - files:
      # Level 0
      - hw/tcdm_interface/src/tcdm_interface.sv
      # Level 1
      - hw/tcdm_interface/src/axi_to_tcdm.sv
      - hw/tcdm_interface/src/reqrsp_to_tcdm.sv
      - hw/tcdm_interface/src/tcdm_mux.sv
  - target: simulation
    files:
      - hw/tcdm_interface/src/tcdm_test.sv
  - target: test
    files:
      - hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv
      - hw/tcdm_interface/test/tcdm_mux_tb.sv

  # snitch
  - files:
      # Level 0
      - hw/snitch/src/snitch_pma_pkg.sv
      - hw/snitch/src/riscv_instr.sv
      # Level 1
      - hw/snitch/src/snitch_pkg.sv
      # Level 2
      - hw/snitch/src/snitch_regfile_ff.sv
      - hw/snitch/src/snitch_lsu.sv
      - hw/snitch/src/snitch_l0_tlb.sv
  - target: not(disable_pmcs)
    defines:
      SNITCH_ENABLE_PERF:
    files:
      - hw/snitch/src/snitch.sv
  # Disable the performance monitoring counters to save area.
  - target: disable_pmcs
    files:
      - hw/snitch/src/snitch.sv
  - target: test
    files:
      - hw/snitch/test/snitch_l0_tlb_tb.sv

  # snitch_vm
  - files:
      - hw/snitch_vm/src/snitch_ptw.sv

  # snitch_ipu
  - files:
      # Level 0
      - hw/snitch_ipu/src/snitch_ipu_pkg.sv
      # Level 1
      - hw/snitch_ipu/src/snitch_ipu_alu.sv
      # Level 2
      - hw/snitch_ipu/src/snitch_int_ss.sv

  # snitch_ssr
  - files:
      # Level 0
      - hw/snitch_ssr/src/snitch_ssr_pkg.sv
      - hw/snitch_ssr/src/snitch_ssr_switch.sv
      - hw/snitch_ssr/src/snitch_ssr_credit_counter.sv
      # Level 1
      - hw/snitch_ssr/src/snitch_ssr_indirector.sv
      - hw/snitch_ssr/src/snitch_ssr_intersector.sv
      # Level 2
      - hw/snitch_ssr/src/snitch_ssr_addr_gen.sv
      # Level 3
      - hw/snitch_ssr/src/snitch_ssr.sv
      # Level 4
      - hw/snitch_ssr/src/snitch_ssr_streamer.sv
  - target: test
    files:
      # Level 0
      - hw/snitch_ssr/test/fixture_ssr.sv
      - hw/snitch_ssr/test/fixture_ssr_streamer.sv
      # Level 1
      - hw/snitch_ssr/test/tb_simple_ssr.sv
      - hw/snitch_ssr/test/tb_simple_ssr_streamer.sv

  # snitch_cluster
  - files:
      # Level 0
      - hw/snitch_cluster/src/snitch_amo_shim.sv
      - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
      - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv
      - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
      - hw/snitch_cluster/src/snitch_fpu.sv
      - hw/snitch_cluster/src/snitch_sequencer.sv
      - hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
      - target/snitch_cluster/test/snitch_bootrom.sv
      # Level 1
      - hw/snitch_cluster/src/snitch_barrier.sv
      - hw/snitch_cluster/src/snitch_fp_ss.sv
      - hw/snitch_cluster/src/snitch_shared_muldiv.sv
      # Level 2
      - hw/snitch_cluster/src/snitch_cc.sv
      - hw/snitch_cluster/src/snitch_clkdiv2.sv
      # Level 3
      - hw/snitch_cluster/src/snitch_hive.sv
      # Level 4
      - hw/snitch_cluster/src/snitch_cluster.sv
  - target: test
    files:
      - hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv

  # target/common
  - target: any(simulation, verilator)
    files:
      - target/common/test/tb_memory_regbus.sv
      - target/common/test/tb_memory_axi.sv
  - target: test
    files:
      - target/common/test/tb_bin.sv

  # target/snitch_cluster
  - target: snitch_cluster
    files:
      - target/snitch_cluster/generated/snitch_cluster_wrapper.sv
  - target: all(snitch_cluster, any(simulation, verilator))
    files:
      - target/snitch_cluster/test/vip_snitch_cluster.sv
      - target/snitch_cluster/test/testharness.sv