diff --git a/hw/ip/snitch_cluster/src/snitch_cluster.sv b/hw/ip/snitch_cluster/src/snitch_cluster.sv index a3825610c..b2bd6ea9e 100644 --- a/hw/ip/snitch_cluster/src/snitch_cluster.sv +++ b/hw/ip/snitch_cluster/src/snitch_cluster.sv @@ -1014,9 +1014,10 @@ module snitch_cluster reqrsp_req_t core_to_axi_req; reqrsp_rsp_t core_to_axi_rsp; - logic [$clog2(NrCores)-1:0] core_req_idx; - user_t core_user; - assign core_user = hart_base_id_i + core_req_idx + 1'b1; + user_t cluster_user; + // Atomic ID, needs to be unique ID of cluster + // cluster_id + HartIdOffset + 1 (because 0 is for non-atomic masters) + assign cluster_user = (hart_base_id_i / NrCores) + (hart_base_id_i % NrCores) + 1'b1; reqrsp_mux #( .NrPorts (NrCores), @@ -1032,7 +1033,7 @@ module snitch_cluster .slv_rsp_o (filtered_core_rsp), .mst_req_o (core_to_axi_req), .mst_rsp_i (core_to_axi_rsp), - .idx_o (core_req_idx) + .idx_o (/*unused*/) ); reqrsp_to_axi #( @@ -1045,7 +1046,7 @@ module snitch_cluster ) i_reqrsp_to_axi_core ( .clk_i, .rst_ni, - .user_i (core_user), + .user_i (cluster_user), .reqrsp_req_i (core_to_axi_req), .reqrsp_rsp_o (core_to_axi_rsp), .axi_req_o (narrow_axi_mst_req[CoreReq]), diff --git a/hw/system/occamy/src/occamy_cfg.hjson b/hw/system/occamy/src/occamy_cfg.hjson index 33c7efb99..df8b08683 100644 --- a/hw/system/occamy/src/occamy_cfg.hjson +++ b/hw/system/occamy/src/occamy_cfg.hjson @@ -84,7 +84,7 @@ rmq: 4, } narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 8, // clog2(total number of cores) + narrow_xbar_user_width: 5, // clog2(total number of clusters) nr_s1_quadrant: 6, s1_quadrant: { nr_clusters: 4, @@ -121,7 +121,7 @@ fall_through: false, }, narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 8, // clog2(total number of cores) + narrow_xbar_user_width: 5, // clog2(total number of clusters) cfg_base_addr: 184549376, // 0x0b000000 cfg_base_offset: 65536 // 0x10000 }, @@ -133,7 +133,7 @@ cluster_base_hartid: 1, addr_width: 48, data_width: 64, - user_width: 8, // clog2(total number of cores) + user_width: 5, // clog2(total number of clusters) tcdm: { size: 128, // 128 kiB banks: 32, diff --git a/hw/system/occamy/src/occamy_cluster_wrapper.sv b/hw/system/occamy/src/occamy_cluster_wrapper.sv index 2e6b41e86..b17bb56fb 100644 --- a/hw/system/occamy/src/occamy_cluster_wrapper.sv +++ b/hw/system/occamy/src/occamy_cluster_wrapper.sv @@ -31,7 +31,7 @@ package occamy_cluster_pkg; localparam int unsigned WideIdWidthIn = 1; localparam int unsigned WideIdWidthOut = $clog2(NrDmaMasters) + WideIdWidthIn; - localparam int unsigned NarrowUserWidth = 8; + localparam int unsigned NarrowUserWidth = 5; localparam int unsigned WideUserWidth = 1; localparam int unsigned ICacheLineWidth [NrHives] = '{ diff --git a/hw/system/occamy/src/occamy_cva6.sv b/hw/system/occamy/src/occamy_cva6.sv index fd6d44591..3e7b9bc40 100644 --- a/hw/system/occamy/src/occamy_cva6.sv +++ b/hw/system/occamy/src/occamy_cva6.sv @@ -15,26 +15,26 @@ module occamy_cva6 input logic ipi_i, input logic time_irq_i, input logic debug_req_i, - output axi_a48_d64_i4_u8_req_t axi_req_o, - input axi_a48_d64_i4_u8_resp_t axi_resp_i, + output axi_a48_d64_i4_u5_req_t axi_req_o, + input axi_a48_d64_i4_u5_resp_t axi_resp_i, input sram_cfg_cva6_t sram_cfg_i ); - axi_a48_d64_i4_u8_req_t cva6_axi_req; - axi_a48_d64_i4_u8_resp_t cva6_axi_rsp; + axi_a48_d64_i4_u5_req_t cva6_axi_req; + axi_a48_d64_i4_u5_resp_t cva6_axi_rsp; - axi_a48_d64_i4_u8_req_t cva6_axi_cut_req; - axi_a48_d64_i4_u8_resp_t cva6_axi_cut_rsp; + axi_a48_d64_i4_u5_req_t cva6_axi_cut_req; + axi_a48_d64_i4_u5_resp_t cva6_axi_cut_rsp; axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_cva6_axi_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -130,12 +130,12 @@ module occamy_cva6 .AxiAddrWidth(48), .AxiDataWidth(64), .AxiIdWidth(4), - .AxiUserWidth(8), - .axi_ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .axi_aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .axi_w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_rsp_t(axi_a48_d64_i4_u8_resp_t), + .AxiUserWidth(5), + .axi_ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .axi_aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .axi_w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_rsp_t(axi_a48_d64_i4_u5_resp_t), .sram_cfg_t(sram_cfg_t) ) i_cva6 ( .clk_i, diff --git a/hw/system/occamy/src/occamy_pkg.sv b/hw/system/occamy/src/occamy_pkg.sv index d5dbe7f2a..49fe4d87f 100644 --- a/hw/system/occamy/src/occamy_pkg.sv +++ b/hw/system/occamy/src/occamy_pkg.sv @@ -789,28 +789,28 @@ package occamy_pkg; NoAddrRules: 20 }; - // AXI bus with 48 bit address, 64 bit data, 4 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d64_i4_u8, logic [47:0], logic [3:0], logic [63:0], logic [7:0], - logic [7:0]) - - // AXI bus with 48 bit address, 64 bit data, 8 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d64_i8_u8, logic [47:0], logic [7:0], logic [63:0], logic [7:0], - logic [7:0]) - - typedef axi_a48_d64_i4_u8_req_t soc_narrow_xbar_in_req_t; - typedef axi_a48_d64_i8_u8_req_t soc_narrow_xbar_out_req_t; - typedef axi_a48_d64_i4_u8_resp_t soc_narrow_xbar_in_resp_t; - typedef axi_a48_d64_i8_u8_resp_t soc_narrow_xbar_out_resp_t; - typedef axi_a48_d64_i4_u8_aw_chan_t soc_narrow_xbar_in_aw_chan_t; - typedef axi_a48_d64_i8_u8_aw_chan_t soc_narrow_xbar_out_aw_chan_t; - typedef axi_a48_d64_i4_u8_w_chan_t soc_narrow_xbar_in_w_chan_t; - typedef axi_a48_d64_i8_u8_w_chan_t soc_narrow_xbar_out_w_chan_t; - typedef axi_a48_d64_i4_u8_b_chan_t soc_narrow_xbar_in_b_chan_t; - typedef axi_a48_d64_i8_u8_b_chan_t soc_narrow_xbar_out_b_chan_t; - typedef axi_a48_d64_i4_u8_ar_chan_t soc_narrow_xbar_in_ar_chan_t; - typedef axi_a48_d64_i8_u8_ar_chan_t soc_narrow_xbar_out_ar_chan_t; - typedef axi_a48_d64_i4_u8_r_chan_t soc_narrow_xbar_in_r_chan_t; - typedef axi_a48_d64_i8_u8_r_chan_t soc_narrow_xbar_out_r_chan_t; + // AXI bus with 48 bit address, 64 bit data, 4 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d64_i4_u5, logic [47:0], logic [3:0], logic [63:0], logic [7:0], + logic [4:0]) + + // AXI bus with 48 bit address, 64 bit data, 8 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d64_i8_u5, logic [47:0], logic [7:0], logic [63:0], logic [7:0], + logic [4:0]) + + typedef axi_a48_d64_i4_u5_req_t soc_narrow_xbar_in_req_t; + typedef axi_a48_d64_i8_u5_req_t soc_narrow_xbar_out_req_t; + typedef axi_a48_d64_i4_u5_resp_t soc_narrow_xbar_in_resp_t; + typedef axi_a48_d64_i8_u5_resp_t soc_narrow_xbar_out_resp_t; + typedef axi_a48_d64_i4_u5_aw_chan_t soc_narrow_xbar_in_aw_chan_t; + typedef axi_a48_d64_i8_u5_aw_chan_t soc_narrow_xbar_out_aw_chan_t; + typedef axi_a48_d64_i4_u5_w_chan_t soc_narrow_xbar_in_w_chan_t; + typedef axi_a48_d64_i8_u5_w_chan_t soc_narrow_xbar_out_w_chan_t; + typedef axi_a48_d64_i4_u5_b_chan_t soc_narrow_xbar_in_b_chan_t; + typedef axi_a48_d64_i8_u5_b_chan_t soc_narrow_xbar_out_b_chan_t; + typedef axi_a48_d64_i4_u5_ar_chan_t soc_narrow_xbar_in_ar_chan_t; + typedef axi_a48_d64_i8_u5_ar_chan_t soc_narrow_xbar_out_ar_chan_t; + typedef axi_a48_d64_i4_u5_r_chan_t soc_narrow_xbar_in_r_chan_t; + typedef axi_a48_d64_i8_u5_r_chan_t soc_narrow_xbar_out_r_chan_t; // verilog_lint: waive parameter-name-style localparam int SOC_NARROW_XBAR_IW_IN = 4; @@ -846,20 +846,20 @@ package occamy_pkg; NoAddrRules: 1 }; - typedef axi_a48_d64_i8_u8_req_t quadrant_s1_ctrl_soc_to_quad_xbar_in_req_t; - typedef axi_a48_d64_i8_u8_req_t quadrant_s1_ctrl_soc_to_quad_xbar_out_req_t; - typedef axi_a48_d64_i8_u8_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_in_resp_t; - typedef axi_a48_d64_i8_u8_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_out_resp_t; - typedef axi_a48_d64_i8_u8_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_aw_chan_t; - typedef axi_a48_d64_i8_u8_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_aw_chan_t; - typedef axi_a48_d64_i8_u8_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_w_chan_t; - typedef axi_a48_d64_i8_u8_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_w_chan_t; - typedef axi_a48_d64_i8_u8_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_b_chan_t; - typedef axi_a48_d64_i8_u8_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_b_chan_t; - typedef axi_a48_d64_i8_u8_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_ar_chan_t; - typedef axi_a48_d64_i8_u8_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_ar_chan_t; - typedef axi_a48_d64_i8_u8_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_r_chan_t; - typedef axi_a48_d64_i8_u8_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_r_chan_t; + typedef axi_a48_d64_i8_u5_req_t quadrant_s1_ctrl_soc_to_quad_xbar_in_req_t; + typedef axi_a48_d64_i8_u5_req_t quadrant_s1_ctrl_soc_to_quad_xbar_out_req_t; + typedef axi_a48_d64_i8_u5_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_in_resp_t; + typedef axi_a48_d64_i8_u5_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_out_resp_t; + typedef axi_a48_d64_i8_u5_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_aw_chan_t; + typedef axi_a48_d64_i8_u5_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_aw_chan_t; + typedef axi_a48_d64_i8_u5_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_w_chan_t; + typedef axi_a48_d64_i8_u5_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_w_chan_t; + typedef axi_a48_d64_i8_u5_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_b_chan_t; + typedef axi_a48_d64_i8_u5_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_b_chan_t; + typedef axi_a48_d64_i8_u5_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_ar_chan_t; + typedef axi_a48_d64_i8_u5_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_ar_chan_t; + typedef axi_a48_d64_i8_u5_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_r_chan_t; + typedef axi_a48_d64_i8_u5_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_r_chan_t; // verilog_lint: waive parameter-name-style localparam int QUADRANT_S1_CTRL_SOC_TO_QUAD_XBAR_IW_IN = 8; @@ -895,20 +895,20 @@ package occamy_pkg; NoAddrRules: 1 }; - typedef axi_a48_d64_i4_u8_req_t quadrant_s1_ctrl_quad_to_soc_xbar_in_req_t; - typedef axi_a48_d64_i4_u8_req_t quadrant_s1_ctrl_quad_to_soc_xbar_out_req_t; - typedef axi_a48_d64_i4_u8_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_in_resp_t; - typedef axi_a48_d64_i4_u8_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_out_resp_t; - typedef axi_a48_d64_i4_u8_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_aw_chan_t; - typedef axi_a48_d64_i4_u8_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_aw_chan_t; - typedef axi_a48_d64_i4_u8_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_w_chan_t; - typedef axi_a48_d64_i4_u8_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_w_chan_t; - typedef axi_a48_d64_i4_u8_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_b_chan_t; - typedef axi_a48_d64_i4_u8_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_b_chan_t; - typedef axi_a48_d64_i4_u8_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_ar_chan_t; - typedef axi_a48_d64_i4_u8_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_ar_chan_t; - typedef axi_a48_d64_i4_u8_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_r_chan_t; - typedef axi_a48_d64_i4_u8_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_r_chan_t; + typedef axi_a48_d64_i4_u5_req_t quadrant_s1_ctrl_quad_to_soc_xbar_in_req_t; + typedef axi_a48_d64_i4_u5_req_t quadrant_s1_ctrl_quad_to_soc_xbar_out_req_t; + typedef axi_a48_d64_i4_u5_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_in_resp_t; + typedef axi_a48_d64_i4_u5_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_out_resp_t; + typedef axi_a48_d64_i4_u5_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_aw_chan_t; + typedef axi_a48_d64_i4_u5_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_aw_chan_t; + typedef axi_a48_d64_i4_u5_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_w_chan_t; + typedef axi_a48_d64_i4_u5_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_w_chan_t; + typedef axi_a48_d64_i4_u5_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_b_chan_t; + typedef axi_a48_d64_i4_u5_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_b_chan_t; + typedef axi_a48_d64_i4_u5_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_ar_chan_t; + typedef axi_a48_d64_i4_u5_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_ar_chan_t; + typedef axi_a48_d64_i4_u5_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_r_chan_t; + typedef axi_a48_d64_i4_u5_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_r_chan_t; // verilog_lint: waive parameter-name-style localparam int QUADRANT_S1_CTRL_QUAD_TO_SOC_XBAR_IW_IN = 4; @@ -1057,24 +1057,24 @@ package occamy_pkg; NoAddrRules: 4 }; - // AXI bus with 48 bit address, 64 bit data, 7 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d64_i7_u8, logic [47:0], logic [6:0], logic [63:0], logic [7:0], - logic [7:0]) - - typedef axi_a48_d64_i4_u8_req_t narrow_xbar_quadrant_s1_in_req_t; - typedef axi_a48_d64_i7_u8_req_t narrow_xbar_quadrant_s1_out_req_t; - typedef axi_a48_d64_i4_u8_resp_t narrow_xbar_quadrant_s1_in_resp_t; - typedef axi_a48_d64_i7_u8_resp_t narrow_xbar_quadrant_s1_out_resp_t; - typedef axi_a48_d64_i4_u8_aw_chan_t narrow_xbar_quadrant_s1_in_aw_chan_t; - typedef axi_a48_d64_i7_u8_aw_chan_t narrow_xbar_quadrant_s1_out_aw_chan_t; - typedef axi_a48_d64_i4_u8_w_chan_t narrow_xbar_quadrant_s1_in_w_chan_t; - typedef axi_a48_d64_i7_u8_w_chan_t narrow_xbar_quadrant_s1_out_w_chan_t; - typedef axi_a48_d64_i4_u8_b_chan_t narrow_xbar_quadrant_s1_in_b_chan_t; - typedef axi_a48_d64_i7_u8_b_chan_t narrow_xbar_quadrant_s1_out_b_chan_t; - typedef axi_a48_d64_i4_u8_ar_chan_t narrow_xbar_quadrant_s1_in_ar_chan_t; - typedef axi_a48_d64_i7_u8_ar_chan_t narrow_xbar_quadrant_s1_out_ar_chan_t; - typedef axi_a48_d64_i4_u8_r_chan_t narrow_xbar_quadrant_s1_in_r_chan_t; - typedef axi_a48_d64_i7_u8_r_chan_t narrow_xbar_quadrant_s1_out_r_chan_t; + // AXI bus with 48 bit address, 64 bit data, 7 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d64_i7_u5, logic [47:0], logic [6:0], logic [63:0], logic [7:0], + logic [4:0]) + + typedef axi_a48_d64_i4_u5_req_t narrow_xbar_quadrant_s1_in_req_t; + typedef axi_a48_d64_i7_u5_req_t narrow_xbar_quadrant_s1_out_req_t; + typedef axi_a48_d64_i4_u5_resp_t narrow_xbar_quadrant_s1_in_resp_t; + typedef axi_a48_d64_i7_u5_resp_t narrow_xbar_quadrant_s1_out_resp_t; + typedef axi_a48_d64_i4_u5_aw_chan_t narrow_xbar_quadrant_s1_in_aw_chan_t; + typedef axi_a48_d64_i7_u5_aw_chan_t narrow_xbar_quadrant_s1_out_aw_chan_t; + typedef axi_a48_d64_i4_u5_w_chan_t narrow_xbar_quadrant_s1_in_w_chan_t; + typedef axi_a48_d64_i7_u5_w_chan_t narrow_xbar_quadrant_s1_out_w_chan_t; + typedef axi_a48_d64_i4_u5_b_chan_t narrow_xbar_quadrant_s1_in_b_chan_t; + typedef axi_a48_d64_i7_u5_b_chan_t narrow_xbar_quadrant_s1_out_b_chan_t; + typedef axi_a48_d64_i4_u5_ar_chan_t narrow_xbar_quadrant_s1_in_ar_chan_t; + typedef axi_a48_d64_i7_u5_ar_chan_t narrow_xbar_quadrant_s1_out_ar_chan_t; + typedef axi_a48_d64_i4_u5_r_chan_t narrow_xbar_quadrant_s1_in_r_chan_t; + typedef axi_a48_d64_i7_u5_r_chan_t narrow_xbar_quadrant_s1_out_r_chan_t; // verilog_lint: waive parameter-name-style localparam int NARROW_XBAR_QUADRANT_S1_IW_IN = 4; @@ -1085,9 +1085,9 @@ package occamy_pkg; `APB_TYPEDEF_REQ_T(apb_a48_d32_req_t, logic [47:0], logic [31:0], logic [3:0]) `APB_TYPEDEF_RESP_T(apb_a48_d32_rsp_t, logic [31:0]) - // AXI bus with 48 bit address, 32 bit data, 8 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d32_i8_u8, logic [47:0], logic [7:0], logic [31:0], logic [3:0], - logic [7:0]) + // AXI bus with 48 bit address, 32 bit data, 8 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d32_i8_u5, logic [47:0], logic [7:0], logic [31:0], logic [3:0], + logic [4:0]) // Register bus with 48 bit address and 64 bit data. `REG_BUS_TYPEDEF_ALL(reg_a48_d64, logic [47:0], logic [63:0], logic [7:0]) @@ -1096,21 +1096,21 @@ package occamy_pkg; `AXI_TYPEDEF_ALL(axi_a48_d64_i4_u0, logic [47:0], logic [3:0], logic [63:0], logic [7:0], logic [0:0]) - // AXI bus with 48 bit address, 512 bit data, 4 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d512_i4_u8, logic [47:0], logic [3:0], logic [511:0], logic [63:0], - logic [7:0]) + // AXI bus with 48 bit address, 512 bit data, 4 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d512_i4_u5, logic [47:0], logic [3:0], logic [511:0], logic [63:0], + logic [4:0]) - // AXI bus with 48 bit address, 64 bit data, 1 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d64_i1_u8, logic [47:0], logic [0:0], logic [63:0], logic [7:0], - logic [7:0]) + // AXI bus with 48 bit address, 64 bit data, 1 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d64_i1_u5, logic [47:0], logic [0:0], logic [63:0], logic [7:0], + logic [4:0]) - // AXI bus with 48 bit address, 32 bit data, 1 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d32_i1_u8, logic [47:0], logic [0:0], logic [31:0], logic [3:0], - logic [7:0]) + // AXI bus with 48 bit address, 32 bit data, 1 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d32_i1_u5, logic [47:0], logic [0:0], logic [31:0], logic [3:0], + logic [4:0]) - // AXI bus with 48 bit address, 64 bit data, 2 bit IDs, and 8 bit user data. - `AXI_TYPEDEF_ALL(axi_a48_d64_i2_u8, logic [47:0], logic [1:0], logic [63:0], logic [7:0], - logic [7:0]) + // AXI bus with 48 bit address, 64 bit data, 2 bit IDs, and 5 bit user data. + `AXI_TYPEDEF_ALL(axi_a48_d64_i2_u5, logic [47:0], logic [1:0], logic [63:0], logic [7:0], + logic [4:0]) // AXI bus with 48 bit address, 512 bit data, 1 bit IDs, and 0 bit user data. `AXI_TYPEDEF_ALL(axi_a48_d512_i1_u0, logic [47:0], logic [0:0], logic [511:0], logic [63:0], diff --git a/hw/system/occamy/src/occamy_quadrant_s1.sv b/hw/system/occamy/src/occamy_quadrant_s1.sv index dd18dc3cb..7e93c477f 100644 --- a/hw/system/occamy/src/occamy_quadrant_s1.sv +++ b/hw/system/occamy/src/occamy_quadrant_s1.sv @@ -22,10 +22,10 @@ module occamy_quadrant_s1 input logic [NrCoresS1Quadrant-1:0] mtip_i, input logic [NrCoresS1Quadrant-1:0] msip_i, // Next-Level - output axi_a48_d64_i4_u8_req_t quadrant_narrow_out_req_o, - input axi_a48_d64_i4_u8_resp_t quadrant_narrow_out_rsp_i, - input axi_a48_d64_i8_u8_req_t quadrant_narrow_in_req_i, - output axi_a48_d64_i8_u8_resp_t quadrant_narrow_in_rsp_o, + output axi_a48_d64_i4_u5_req_t quadrant_narrow_out_req_o, + input axi_a48_d64_i4_u5_resp_t quadrant_narrow_out_rsp_i, + input axi_a48_d64_i8_u5_req_t quadrant_narrow_in_req_i, + output axi_a48_d64_i8_u5_resp_t quadrant_narrow_in_rsp_o, output axi_a48_d512_i4_u0_req_t quadrant_wide_out_req_o, input axi_a48_d512_i4_u0_resp_t quadrant_wide_out_rsp_i, input axi_a48_d512_i7_u0_req_t quadrant_wide_in_req_i, @@ -121,19 +121,19 @@ module occamy_quadrant_s1 .Cfg (NarrowXbarQuadrantS1Cfg), .Connectivity (25'b0111110111110111110111110), .ATOPs (1), - .slv_aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .mst_aw_chan_t(axi_a48_d64_i7_u8_aw_chan_t), - .w_chan_t (axi_a48_d64_i4_u8_w_chan_t), - .slv_b_chan_t (axi_a48_d64_i4_u8_b_chan_t), - .mst_b_chan_t (axi_a48_d64_i7_u8_b_chan_t), - .slv_ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .mst_ar_chan_t(axi_a48_d64_i7_u8_ar_chan_t), - .slv_r_chan_t (axi_a48_d64_i4_u8_r_chan_t), - .mst_r_chan_t (axi_a48_d64_i7_u8_r_chan_t), - .slv_req_t (axi_a48_d64_i4_u8_req_t), - .slv_resp_t (axi_a48_d64_i4_u8_resp_t), - .mst_req_t (axi_a48_d64_i7_u8_req_t), - .mst_resp_t (axi_a48_d64_i7_u8_resp_t), + .slv_aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .mst_aw_chan_t(axi_a48_d64_i7_u5_aw_chan_t), + .w_chan_t (axi_a48_d64_i4_u5_w_chan_t), + .slv_b_chan_t (axi_a48_d64_i4_u5_b_chan_t), + .mst_b_chan_t (axi_a48_d64_i7_u5_b_chan_t), + .slv_ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .mst_ar_chan_t(axi_a48_d64_i7_u5_ar_chan_t), + .slv_r_chan_t (axi_a48_d64_i4_u5_r_chan_t), + .mst_r_chan_t (axi_a48_d64_i7_u5_r_chan_t), + .slv_req_t (axi_a48_d64_i4_u5_req_t), + .slv_resp_t (axi_a48_d64_i4_u5_resp_t), + .mst_req_t (axi_a48_d64_i7_u5_req_t), + .mst_resp_t (axi_a48_d64_i7_u5_resp_t), .rule_t (xbar_rule_48_t) ) i_narrow_xbar_quadrant_s1 ( .clk_i (clk_quadrant), @@ -152,21 +152,21 @@ module occamy_quadrant_s1 /////////////////////////////// // Narrow In + IW Converter // /////////////////////////////// - axi_a48_d64_i8_u8_req_t narrow_cluster_in_ctrl_req; - axi_a48_d64_i8_u8_resp_t narrow_cluster_in_ctrl_rsp; + axi_a48_d64_i8_u5_req_t narrow_cluster_in_ctrl_req; + axi_a48_d64_i8_u5_resp_t narrow_cluster_in_ctrl_rsp; - axi_a48_d64_i8_u8_req_t narrow_cluster_in_ctrl_cut_req; - axi_a48_d64_i8_u8_resp_t narrow_cluster_in_ctrl_cut_rsp; + axi_a48_d64_i8_u5_req_t narrow_cluster_in_ctrl_cut_req; + axi_a48_d64_i8_u5_resp_t narrow_cluster_in_ctrl_cut_rsp; axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_cluster_in_ctrl_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -175,8 +175,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_cluster_in_ctrl_cut_req), .mst_resp_i(narrow_cluster_in_ctrl_cut_rsp) ); - axi_a48_d64_i8_u8_req_t narrow_cluster_in_isolate_req; - axi_a48_d64_i8_u8_resp_t narrow_cluster_in_isolate_rsp; + axi_a48_d64_i8_u5_req_t narrow_cluster_in_isolate_req; + axi_a48_d64_i8_u5_resp_t narrow_cluster_in_isolate_rsp; axi_isolate #( .NumPending(32), @@ -185,9 +185,9 @@ module occamy_quadrant_s1 .AxiIdWidth(8), .AxiAddrWidth(48), .AxiDataWidth(64), - .AxiUserWidth(8), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .AxiUserWidth(5), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_cluster_in_isolate ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -204,10 +204,10 @@ module occamy_quadrant_s1 .AxiSlvPortMaxUniqIds(16), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(4), - .slv_req_t(axi_a48_d64_i8_u8_req_t), - .slv_resp_t(axi_a48_d64_i8_u8_resp_t), - .mst_req_t(axi_a48_d64_i4_u8_req_t), - .mst_resp_t(axi_a48_d64_i4_u8_resp_t) + .slv_req_t(axi_a48_d64_i8_u5_req_t), + .slv_resp_t(axi_a48_d64_i8_u5_resp_t), + .mst_req_t(axi_a48_d64_i4_u5_req_t), + .mst_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_cluster_in_iwc ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -221,21 +221,21 @@ module occamy_quadrant_s1 ///////////////////////////////////// // Narrow Out + TLB + IW Converter // ///////////////////////////////////// - axi_a48_d64_i7_u8_req_t narrow_cluster_out_tlb_req; - axi_a48_d64_i7_u8_resp_t narrow_cluster_out_tlb_rsp; + axi_a48_d64_i7_u5_req_t narrow_cluster_out_tlb_req; + axi_a48_d64_i7_u5_resp_t narrow_cluster_out_tlb_rsp; axi_tlb #( .AxiSlvPortAddrWidth(48), .AxiMstPortAddrWidth(48), .AxiDataWidth(64), .AxiIdWidth(7), - .AxiUserWidth(8), + .AxiUserWidth(5), .AxiSlvPortMaxTxns(32), .L1NumEntries(8), .L1CutAx(1'b1), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .mst_req_t(axi_a48_d64_i7_u8_req_t), - .axi_resp_t(axi_a48_d64_i7_u8_resp_t), + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .mst_req_t(axi_a48_d64_i7_u5_req_t), + .axi_resp_t(axi_a48_d64_i7_u5_resp_t), .entry_t(tlb_entry_t) ) i_narrow_cluster_out_tlb ( .clk_i(clk_quadrant), @@ -249,18 +249,18 @@ module occamy_quadrant_s1 .bypass_i(~narrow_tlb_enable) ); - axi_a48_d64_i4_u8_req_t narrow_cluster_out_iwc_req; - axi_a48_d64_i4_u8_resp_t narrow_cluster_out_iwc_rsp; + axi_a48_d64_i4_u5_req_t narrow_cluster_out_iwc_req; + axi_a48_d64_i4_u5_resp_t narrow_cluster_out_iwc_rsp; axi_id_remap #( .AxiSlvPortIdWidth(7), .AxiSlvPortMaxUniqIds(16), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(4), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .slv_resp_t(axi_a48_d64_i7_u8_resp_t), - .mst_req_t(axi_a48_d64_i4_u8_req_t), - .mst_resp_t(axi_a48_d64_i4_u8_resp_t) + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .slv_resp_t(axi_a48_d64_i7_u5_resp_t), + .mst_req_t(axi_a48_d64_i4_u5_req_t), + .mst_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_cluster_out_iwc ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -269,8 +269,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_cluster_out_iwc_req), .mst_resp_i(narrow_cluster_out_iwc_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_cluster_out_isolate_req; - axi_a48_d64_i4_u8_resp_t narrow_cluster_out_isolate_rsp; + axi_a48_d64_i4_u5_req_t narrow_cluster_out_isolate_req; + axi_a48_d64_i4_u5_resp_t narrow_cluster_out_isolate_rsp; axi_isolate #( .NumPending(32), @@ -279,9 +279,9 @@ module occamy_quadrant_s1 .AxiIdWidth(4), .AxiAddrWidth(48), .AxiDataWidth(64), - .AxiUserWidth(8), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .AxiUserWidth(5), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_cluster_out_isolate ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -293,18 +293,18 @@ module occamy_quadrant_s1 .isolated_o(isolated[1]) ); - axi_a48_d64_i4_u8_req_t narrow_cluster_out_ctrl_req; - axi_a48_d64_i4_u8_resp_t narrow_cluster_out_ctrl_rsp; + axi_a48_d64_i4_u5_req_t narrow_cluster_out_ctrl_req; + axi_a48_d64_i4_u5_resp_t narrow_cluster_out_ctrl_rsp; axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_cluster_out_ctrl ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -598,18 +598,18 @@ module occamy_quadrant_s1 /////////////// // Cluster 0 // /////////////// - axi_a48_d64_i2_u8_req_t narrow_in_iwc_0_req; - axi_a48_d64_i2_u8_resp_t narrow_in_iwc_0_rsp; + axi_a48_d64_i2_u5_req_t narrow_in_iwc_0_req; + axi_a48_d64_i2_u5_resp_t narrow_in_iwc_0_rsp; axi_id_remap #( .AxiSlvPortIdWidth(7), .AxiSlvPortMaxUniqIds(4), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(2), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .slv_resp_t(axi_a48_d64_i7_u8_resp_t), - .mst_req_t(axi_a48_d64_i2_u8_req_t), - .mst_resp_t(axi_a48_d64_i2_u8_resp_t) + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .slv_resp_t(axi_a48_d64_i7_u5_resp_t), + .mst_req_t(axi_a48_d64_i2_u5_req_t), + .mst_resp_t(axi_a48_d64_i2_u5_resp_t) ) i_narrow_in_iwc_0 ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -618,8 +618,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_in_iwc_0_req), .mst_resp_i(narrow_in_iwc_0_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_0_req; - axi_a48_d64_i4_u8_resp_t narrow_out_0_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_0_req; + axi_a48_d64_i4_u5_resp_t narrow_out_0_rsp; assign narrow_xbar_quadrant_s1_in_req[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_0] = narrow_out_0_req; assign narrow_out_0_rsp = narrow_xbar_quadrant_s1_in_rsp[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_0]; @@ -677,18 +677,18 @@ module occamy_quadrant_s1 /////////////// // Cluster 1 // /////////////// - axi_a48_d64_i2_u8_req_t narrow_in_iwc_1_req; - axi_a48_d64_i2_u8_resp_t narrow_in_iwc_1_rsp; + axi_a48_d64_i2_u5_req_t narrow_in_iwc_1_req; + axi_a48_d64_i2_u5_resp_t narrow_in_iwc_1_rsp; axi_id_remap #( .AxiSlvPortIdWidth(7), .AxiSlvPortMaxUniqIds(4), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(2), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .slv_resp_t(axi_a48_d64_i7_u8_resp_t), - .mst_req_t(axi_a48_d64_i2_u8_req_t), - .mst_resp_t(axi_a48_d64_i2_u8_resp_t) + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .slv_resp_t(axi_a48_d64_i7_u5_resp_t), + .mst_req_t(axi_a48_d64_i2_u5_req_t), + .mst_resp_t(axi_a48_d64_i2_u5_resp_t) ) i_narrow_in_iwc_1 ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -697,8 +697,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_in_iwc_1_req), .mst_resp_i(narrow_in_iwc_1_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_1_req; - axi_a48_d64_i4_u8_resp_t narrow_out_1_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_1_req; + axi_a48_d64_i4_u5_resp_t narrow_out_1_rsp; assign narrow_xbar_quadrant_s1_in_req[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_1] = narrow_out_1_req; assign narrow_out_1_rsp = narrow_xbar_quadrant_s1_in_rsp[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_1]; @@ -756,18 +756,18 @@ module occamy_quadrant_s1 /////////////// // Cluster 2 // /////////////// - axi_a48_d64_i2_u8_req_t narrow_in_iwc_2_req; - axi_a48_d64_i2_u8_resp_t narrow_in_iwc_2_rsp; + axi_a48_d64_i2_u5_req_t narrow_in_iwc_2_req; + axi_a48_d64_i2_u5_resp_t narrow_in_iwc_2_rsp; axi_id_remap #( .AxiSlvPortIdWidth(7), .AxiSlvPortMaxUniqIds(4), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(2), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .slv_resp_t(axi_a48_d64_i7_u8_resp_t), - .mst_req_t(axi_a48_d64_i2_u8_req_t), - .mst_resp_t(axi_a48_d64_i2_u8_resp_t) + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .slv_resp_t(axi_a48_d64_i7_u5_resp_t), + .mst_req_t(axi_a48_d64_i2_u5_req_t), + .mst_resp_t(axi_a48_d64_i2_u5_resp_t) ) i_narrow_in_iwc_2 ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -776,8 +776,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_in_iwc_2_req), .mst_resp_i(narrow_in_iwc_2_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_2_req; - axi_a48_d64_i4_u8_resp_t narrow_out_2_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_2_req; + axi_a48_d64_i4_u5_resp_t narrow_out_2_rsp; assign narrow_xbar_quadrant_s1_in_req[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_2] = narrow_out_2_req; assign narrow_out_2_rsp = narrow_xbar_quadrant_s1_in_rsp[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_2]; @@ -835,18 +835,18 @@ module occamy_quadrant_s1 /////////////// // Cluster 3 // /////////////// - axi_a48_d64_i2_u8_req_t narrow_in_iwc_3_req; - axi_a48_d64_i2_u8_resp_t narrow_in_iwc_3_rsp; + axi_a48_d64_i2_u5_req_t narrow_in_iwc_3_req; + axi_a48_d64_i2_u5_resp_t narrow_in_iwc_3_rsp; axi_id_remap #( .AxiSlvPortIdWidth(7), .AxiSlvPortMaxUniqIds(4), .AxiMaxTxnsPerId(4), .AxiMstPortIdWidth(2), - .slv_req_t(axi_a48_d64_i7_u8_req_t), - .slv_resp_t(axi_a48_d64_i7_u8_resp_t), - .mst_req_t(axi_a48_d64_i2_u8_req_t), - .mst_resp_t(axi_a48_d64_i2_u8_resp_t) + .slv_req_t(axi_a48_d64_i7_u5_req_t), + .slv_resp_t(axi_a48_d64_i7_u5_resp_t), + .mst_req_t(axi_a48_d64_i2_u5_req_t), + .mst_resp_t(axi_a48_d64_i2_u5_resp_t) ) i_narrow_in_iwc_3 ( .clk_i(clk_quadrant), .rst_ni(rst_quadrant_n), @@ -855,8 +855,8 @@ module occamy_quadrant_s1 .mst_req_o(narrow_in_iwc_3_req), .mst_resp_i(narrow_in_iwc_3_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_3_req; - axi_a48_d64_i4_u8_resp_t narrow_out_3_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_3_req; + axi_a48_d64_i4_u5_resp_t narrow_out_3_rsp; assign narrow_xbar_quadrant_s1_in_req[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_3] = narrow_out_3_req; assign narrow_out_3_rsp = narrow_xbar_quadrant_s1_in_rsp[NARROW_XBAR_QUADRANT_S1_IN_CLUSTER_3]; diff --git a/hw/system/occamy/src/occamy_quadrant_s1_ctrl.sv b/hw/system/occamy/src/occamy_quadrant_s1_ctrl.sv index 222bad767..b46942f3a 100644 --- a/hw/system/occamy/src/occamy_quadrant_s1_ctrl.sv +++ b/hw/system/occamy/src/occamy_quadrant_s1_ctrl.sv @@ -37,10 +37,10 @@ module occamy_quadrant_s1_ctrl output logic [3:0][47:0] ro_end_addr_o, // Upward (SoC) narrow ports - output axi_a48_d64_i4_u8_req_t soc_out_req_o, - input axi_a48_d64_i4_u8_resp_t soc_out_rsp_i, - input axi_a48_d64_i8_u8_req_t soc_in_req_i, - output axi_a48_d64_i8_u8_resp_t soc_in_rsp_o, + output axi_a48_d64_i4_u5_req_t soc_out_req_o, + input axi_a48_d64_i4_u5_resp_t soc_out_rsp_i, + input axi_a48_d64_i8_u5_req_t soc_in_req_i, + output axi_a48_d64_i8_u5_resp_t soc_in_rsp_o, // TLB narrow and wide configuration ports output tlb_entry_t [7:0] narrow_tlb_entries_o, @@ -49,10 +49,10 @@ module occamy_quadrant_s1_ctrl output logic wide_tlb_enable_o, // Quadrant narrow ports - output axi_a48_d64_i8_u8_req_t quadrant_out_req_o, - input axi_a48_d64_i8_u8_resp_t quadrant_out_rsp_i, - input axi_a48_d64_i4_u8_req_t quadrant_in_req_i, - output axi_a48_d64_i4_u8_resp_t quadrant_in_rsp_o + output axi_a48_d64_i8_u5_req_t quadrant_out_req_o, + input axi_a48_d64_i8_u5_resp_t quadrant_out_rsp_i, + input axi_a48_d64_i4_u5_req_t quadrant_in_req_i, + output axi_a48_d64_i4_u5_resp_t quadrant_in_rsp_o ); // Upper half of quadrant space reserved for internal use (same size as for all clusters) @@ -76,19 +76,19 @@ axi_xbar #( .Cfg ( QuadrantS1CtrlSocToQuadXbarCfg ), .Connectivity ( 2'b11 ), .ATOPs ( 1 ), - .slv_aw_chan_t ( axi_a48_d64_i8_u8_aw_chan_t ), - .mst_aw_chan_t ( axi_a48_d64_i8_u8_aw_chan_t ), - .w_chan_t ( axi_a48_d64_i8_u8_w_chan_t ), - .slv_b_chan_t ( axi_a48_d64_i8_u8_b_chan_t ), - .mst_b_chan_t ( axi_a48_d64_i8_u8_b_chan_t ), - .slv_ar_chan_t ( axi_a48_d64_i8_u8_ar_chan_t ), - .mst_ar_chan_t ( axi_a48_d64_i8_u8_ar_chan_t ), - .slv_r_chan_t ( axi_a48_d64_i8_u8_r_chan_t ), - .mst_r_chan_t ( axi_a48_d64_i8_u8_r_chan_t ), - .slv_req_t ( axi_a48_d64_i8_u8_req_t ), - .slv_resp_t ( axi_a48_d64_i8_u8_resp_t ), - .mst_req_t ( axi_a48_d64_i8_u8_req_t ), - .mst_resp_t ( axi_a48_d64_i8_u8_resp_t ), + .slv_aw_chan_t ( axi_a48_d64_i8_u5_aw_chan_t ), + .mst_aw_chan_t ( axi_a48_d64_i8_u5_aw_chan_t ), + .w_chan_t ( axi_a48_d64_i8_u5_w_chan_t ), + .slv_b_chan_t ( axi_a48_d64_i8_u5_b_chan_t ), + .mst_b_chan_t ( axi_a48_d64_i8_u5_b_chan_t ), + .slv_ar_chan_t ( axi_a48_d64_i8_u5_ar_chan_t ), + .mst_ar_chan_t ( axi_a48_d64_i8_u5_ar_chan_t ), + .slv_r_chan_t ( axi_a48_d64_i8_u5_r_chan_t ), + .mst_r_chan_t ( axi_a48_d64_i8_u5_r_chan_t ), + .slv_req_t ( axi_a48_d64_i8_u5_req_t ), + .slv_resp_t ( axi_a48_d64_i8_u5_resp_t ), + .mst_req_t ( axi_a48_d64_i8_u5_req_t ), + .mst_resp_t ( axi_a48_d64_i8_u5_resp_t ), .rule_t ( xbar_rule_48_t ) ) i_quadrant_s1_ctrl_soc_to_quad_xbar ( .clk_i ( clk_i ), @@ -118,19 +118,19 @@ axi_xbar #( .Cfg ( QuadrantS1CtrlQuadToSocXbarCfg ), .Connectivity ( 2'b11 ), .ATOPs ( 1 ), - .slv_aw_chan_t ( axi_a48_d64_i4_u8_aw_chan_t ), - .mst_aw_chan_t ( axi_a48_d64_i4_u8_aw_chan_t ), - .w_chan_t ( axi_a48_d64_i4_u8_w_chan_t ), - .slv_b_chan_t ( axi_a48_d64_i4_u8_b_chan_t ), - .mst_b_chan_t ( axi_a48_d64_i4_u8_b_chan_t ), - .slv_ar_chan_t ( axi_a48_d64_i4_u8_ar_chan_t ), - .mst_ar_chan_t ( axi_a48_d64_i4_u8_ar_chan_t ), - .slv_r_chan_t ( axi_a48_d64_i4_u8_r_chan_t ), - .mst_r_chan_t ( axi_a48_d64_i4_u8_r_chan_t ), - .slv_req_t ( axi_a48_d64_i4_u8_req_t ), - .slv_resp_t ( axi_a48_d64_i4_u8_resp_t ), - .mst_req_t ( axi_a48_d64_i4_u8_req_t ), - .mst_resp_t ( axi_a48_d64_i4_u8_resp_t ), + .slv_aw_chan_t ( axi_a48_d64_i4_u5_aw_chan_t ), + .mst_aw_chan_t ( axi_a48_d64_i4_u5_aw_chan_t ), + .w_chan_t ( axi_a48_d64_i4_u5_w_chan_t ), + .slv_b_chan_t ( axi_a48_d64_i4_u5_b_chan_t ), + .mst_b_chan_t ( axi_a48_d64_i4_u5_b_chan_t ), + .slv_ar_chan_t ( axi_a48_d64_i4_u5_ar_chan_t ), + .mst_ar_chan_t ( axi_a48_d64_i4_u5_ar_chan_t ), + .slv_r_chan_t ( axi_a48_d64_i4_u5_r_chan_t ), + .mst_r_chan_t ( axi_a48_d64_i4_u5_r_chan_t ), + .slv_req_t ( axi_a48_d64_i4_u5_req_t ), + .slv_resp_t ( axi_a48_d64_i4_u5_resp_t ), + .mst_req_t ( axi_a48_d64_i4_u5_req_t ), + .mst_resp_t ( axi_a48_d64_i4_u5_resp_t ), .rule_t ( xbar_rule_48_t ) ) i_quadrant_s1_ctrl_quad_to_soc_xbar ( .clk_i ( clk_i ), @@ -194,8 +194,8 @@ axi_lite_xbar #( assign quadrant_in_rsp_o = quadrant_s1_ctrl_quad_to_soc_xbar_in_rsp[QUADRANT_S1_CTRL_QUAD_TO_SOC_XBAR_IN_IN]; // Convert both internal ports to AXI lite, since only registers for now - axi_a48_d64_i1_u8_req_t soc_to_quad_internal_ser_req; - axi_a48_d64_i1_u8_resp_t soc_to_quad_internal_ser_rsp; + axi_a48_d64_i1_u5_req_t soc_to_quad_internal_ser_req; + axi_a48_d64_i1_u5_resp_t soc_to_quad_internal_ser_rsp; axi_id_serialize #( .AtopSupport (1), @@ -206,11 +206,11 @@ axi_lite_xbar #( .AxiMstPortMaxTxnsPerId (2), .AxiAddrWidth (48), .AxiDataWidth (64), - .AxiUserWidth (8), - .slv_req_t (axi_a48_d64_i8_u8_req_t), - .slv_resp_t (axi_a48_d64_i8_u8_resp_t), - .mst_req_t (axi_a48_d64_i1_u8_req_t), - .mst_resp_t (axi_a48_d64_i1_u8_resp_t) + .AxiUserWidth (5), + .slv_req_t (axi_a48_d64_i8_u5_req_t), + .slv_resp_t (axi_a48_d64_i8_u5_resp_t), + .mst_req_t (axi_a48_d64_i1_u5_req_t), + .mst_resp_t (axi_a48_d64_i1_u5_resp_t) ) i_soc_to_quad_internal_ser ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -219,25 +219,25 @@ axi_lite_xbar #( .mst_req_o ( soc_to_quad_internal_ser_req ), .mst_resp_i ( soc_to_quad_internal_ser_rsp ) ); - axi_a48_d32_i1_u8_req_t axi_to_axi_lite_dw_req; - axi_a48_d32_i1_u8_resp_t axi_to_axi_lite_dw_rsp; + axi_a48_d32_i1_u5_req_t axi_to_axi_lite_dw_req; + axi_a48_d32_i1_u5_resp_t axi_to_axi_lite_dw_rsp; axi_dw_converter #( .AxiSlvPortDataWidth ( 64 ), .AxiMstPortDataWidth ( 32 ), .AxiAddrWidth ( 48 ), .AxiIdWidth ( 1 ), - .aw_chan_t ( axi_a48_d32_i1_u8_aw_chan_t ), - .mst_w_chan_t ( axi_a48_d32_i1_u8_w_chan_t ), - .slv_w_chan_t ( axi_a48_d64_i1_u8_w_chan_t ), - .b_chan_t ( axi_a48_d32_i1_u8_b_chan_t ), - .ar_chan_t ( axi_a48_d32_i1_u8_ar_chan_t ), - .mst_r_chan_t ( axi_a48_d32_i1_u8_r_chan_t ), - .slv_r_chan_t ( axi_a48_d64_i1_u8_r_chan_t ), - .axi_mst_req_t ( axi_a48_d32_i1_u8_req_t ), - .axi_mst_resp_t ( axi_a48_d32_i1_u8_resp_t ), - .axi_slv_req_t ( axi_a48_d64_i1_u8_req_t ), - .axi_slv_resp_t ( axi_a48_d64_i1_u8_resp_t ) + .aw_chan_t ( axi_a48_d32_i1_u5_aw_chan_t ), + .mst_w_chan_t ( axi_a48_d32_i1_u5_w_chan_t ), + .slv_w_chan_t ( axi_a48_d64_i1_u5_w_chan_t ), + .b_chan_t ( axi_a48_d32_i1_u5_b_chan_t ), + .ar_chan_t ( axi_a48_d32_i1_u5_ar_chan_t ), + .mst_r_chan_t ( axi_a48_d32_i1_u5_r_chan_t ), + .slv_r_chan_t ( axi_a48_d64_i1_u5_r_chan_t ), + .axi_mst_req_t ( axi_a48_d32_i1_u5_req_t ), + .axi_mst_resp_t ( axi_a48_d32_i1_u5_resp_t ), + .axi_slv_req_t ( axi_a48_d64_i1_u5_req_t ), + .axi_slv_resp_t ( axi_a48_d64_i1_u5_resp_t ) ) i_axi_to_axi_lite_dw ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -251,12 +251,12 @@ axi_lite_xbar #( .AxiAddrWidth ( 48 ), .AxiDataWidth ( 32 ), .AxiIdWidth ( 1 ), - .AxiUserWidth ( 8 ), + .AxiUserWidth ( 5 ), .AxiMaxWriteTxns ( 4 ), .AxiMaxReadTxns ( 4 ), .FallThrough ( 0 ), - .full_req_t ( axi_a48_d32_i1_u8_req_t ), - .full_resp_t ( axi_a48_d32_i1_u8_resp_t ), + .full_req_t ( axi_a48_d32_i1_u5_req_t ), + .full_resp_t ( axi_a48_d32_i1_u5_resp_t ), .lite_req_t ( axi_lite_a48_d32_req_t ), .lite_resp_t ( axi_lite_a48_d32_rsp_t ) ) i_quad_to_soc_internal_ser_pc ( @@ -269,8 +269,8 @@ axi_lite_xbar #( .mst_resp_i (quadrant_s1_ctrl_mux_in_rsp[QUADRANT_S1_CTRL_MUX_IN_SOC]) ); - axi_a48_d64_i1_u8_req_t soc_internal_serialize_req; - axi_a48_d64_i1_u8_resp_t soc_internal_serialize_rsp; + axi_a48_d64_i1_u5_req_t soc_internal_serialize_req; + axi_a48_d64_i1_u5_resp_t soc_internal_serialize_rsp; axi_id_serialize #( .AtopSupport (1), @@ -281,11 +281,11 @@ axi_lite_xbar #( .AxiMstPortMaxTxnsPerId (2), .AxiAddrWidth (48), .AxiDataWidth (64), - .AxiUserWidth (8), - .slv_req_t (axi_a48_d64_i4_u8_req_t), - .slv_resp_t (axi_a48_d64_i4_u8_resp_t), - .mst_req_t (axi_a48_d64_i1_u8_req_t), - .mst_resp_t (axi_a48_d64_i1_u8_resp_t) + .AxiUserWidth (5), + .slv_req_t (axi_a48_d64_i4_u5_req_t), + .slv_resp_t (axi_a48_d64_i4_u5_resp_t), + .mst_req_t (axi_a48_d64_i1_u5_req_t), + .mst_resp_t (axi_a48_d64_i1_u5_resp_t) ) i_soc_internal_serialize ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -294,25 +294,25 @@ axi_lite_xbar #( .mst_req_o ( soc_internal_serialize_req ), .mst_resp_i ( soc_internal_serialize_rsp ) ); - axi_a48_d32_i1_u8_req_t soc_internal_change_dw_req; - axi_a48_d32_i1_u8_resp_t soc_internal_change_dw_rsp; + axi_a48_d32_i1_u5_req_t soc_internal_change_dw_req; + axi_a48_d32_i1_u5_resp_t soc_internal_change_dw_rsp; axi_dw_converter #( .AxiSlvPortDataWidth ( 64 ), .AxiMstPortDataWidth ( 32 ), .AxiAddrWidth ( 48 ), .AxiIdWidth ( 1 ), - .aw_chan_t ( axi_a48_d32_i1_u8_aw_chan_t ), - .mst_w_chan_t ( axi_a48_d32_i1_u8_w_chan_t ), - .slv_w_chan_t ( axi_a48_d64_i1_u8_w_chan_t ), - .b_chan_t ( axi_a48_d32_i1_u8_b_chan_t ), - .ar_chan_t ( axi_a48_d32_i1_u8_ar_chan_t ), - .mst_r_chan_t ( axi_a48_d32_i1_u8_r_chan_t ), - .slv_r_chan_t ( axi_a48_d64_i1_u8_r_chan_t ), - .axi_mst_req_t ( axi_a48_d32_i1_u8_req_t ), - .axi_mst_resp_t ( axi_a48_d32_i1_u8_resp_t ), - .axi_slv_req_t ( axi_a48_d64_i1_u8_req_t ), - .axi_slv_resp_t ( axi_a48_d64_i1_u8_resp_t ) + .aw_chan_t ( axi_a48_d32_i1_u5_aw_chan_t ), + .mst_w_chan_t ( axi_a48_d32_i1_u5_w_chan_t ), + .slv_w_chan_t ( axi_a48_d64_i1_u5_w_chan_t ), + .b_chan_t ( axi_a48_d32_i1_u5_b_chan_t ), + .ar_chan_t ( axi_a48_d32_i1_u5_ar_chan_t ), + .mst_r_chan_t ( axi_a48_d32_i1_u5_r_chan_t ), + .slv_r_chan_t ( axi_a48_d64_i1_u5_r_chan_t ), + .axi_mst_req_t ( axi_a48_d32_i1_u5_req_t ), + .axi_mst_resp_t ( axi_a48_d32_i1_u5_resp_t ), + .axi_slv_req_t ( axi_a48_d64_i1_u5_req_t ), + .axi_slv_resp_t ( axi_a48_d64_i1_u5_resp_t ) ) i_soc_internal_change_dw ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -326,12 +326,12 @@ axi_lite_xbar #( .AxiAddrWidth ( 48 ), .AxiDataWidth ( 32 ), .AxiIdWidth ( 1 ), - .AxiUserWidth ( 8 ), + .AxiUserWidth ( 5 ), .AxiMaxWriteTxns ( 4 ), .AxiMaxReadTxns ( 4 ), .FallThrough ( 0 ), - .full_req_t ( axi_a48_d32_i1_u8_req_t ), - .full_resp_t ( axi_a48_d32_i1_u8_resp_t ), + .full_req_t ( axi_a48_d32_i1_u5_req_t ), + .full_resp_t ( axi_a48_d32_i1_u5_resp_t ), .lite_req_t ( axi_lite_a48_d32_req_t ), .lite_resp_t ( axi_lite_a48_d32_rsp_t ) ) i_soc_internal_to_axi_lite_pc ( diff --git a/hw/system/occamy/src/occamy_soc.sv b/hw/system/occamy/src/occamy_soc.sv index 2858ed2b1..908ee5db0 100644 --- a/hw/system/occamy/src/occamy_soc.sv +++ b/hw/system/occamy/src/occamy_soc.sv @@ -44,29 +44,29 @@ module occamy_soc output axi_a48_d512_i6_u0_req_t hbi_wide_req_o, input axi_a48_d512_i6_u0_resp_t hbi_wide_rsp_i, - input axi_a48_d64_i4_u8_req_t hbi_narrow_req_i, - output axi_a48_d64_i4_u8_resp_t hbi_narrow_rsp_o, - output axi_a48_d64_i8_u8_req_t hbi_narrow_req_o, - input axi_a48_d64_i8_u8_resp_t hbi_narrow_rsp_i, + input axi_a48_d64_i4_u5_req_t hbi_narrow_req_i, + output axi_a48_d64_i4_u5_resp_t hbi_narrow_rsp_o, + output axi_a48_d64_i8_u5_req_t hbi_narrow_req_o, + input axi_a48_d64_i8_u5_resp_t hbi_narrow_rsp_i, /// PCIe Ports - output axi_a48_d64_i8_u8_req_t pcie_axi_req_o, - input axi_a48_d64_i8_u8_resp_t pcie_axi_rsp_i, + output axi_a48_d64_i8_u5_req_t pcie_axi_req_o, + input axi_a48_d64_i8_u5_resp_t pcie_axi_rsp_i, - input axi_a48_d64_i4_u8_req_t pcie_axi_req_i, - output axi_a48_d64_i4_u8_resp_t pcie_axi_rsp_o, + input axi_a48_d64_i4_u5_req_t pcie_axi_req_i, + output axi_a48_d64_i4_u5_resp_t pcie_axi_rsp_o, // Peripheral Ports (to AXI-lite Xbar) - output axi_a48_d64_i8_u8_req_t periph_axi_lite_req_o, - input axi_a48_d64_i8_u8_resp_t periph_axi_lite_rsp_i, + output axi_a48_d64_i8_u5_req_t periph_axi_lite_req_o, + input axi_a48_d64_i8_u5_resp_t periph_axi_lite_rsp_i, - input axi_a48_d64_i4_u8_req_t periph_axi_lite_req_i, - output axi_a48_d64_i4_u8_resp_t periph_axi_lite_rsp_o, + input axi_a48_d64_i4_u5_req_t periph_axi_lite_req_i, + output axi_a48_d64_i4_u5_resp_t periph_axi_lite_rsp_o, // Peripheral Ports (to Regbus Xbar) - output axi_a48_d64_i8_u8_req_t periph_axi_lite_narrow_req_o, - input axi_a48_d64_i8_u8_resp_t periph_axi_lite_narrow_rsp_i, + output axi_a48_d64_i8_u5_req_t periph_axi_lite_narrow_req_o, + input axi_a48_d64_i8_u5_resp_t periph_axi_lite_narrow_rsp_i, // SoC control register IO output logic [1:0] spm_narrow_rerror_o, @@ -571,19 +571,19 @@ module occamy_soc .Cfg(SocNarrowXbarCfg), .Connectivity ( 143'b11111011111110111111111111111101111111111111101111111111111111111111111101111111111111011111111111110111111111111101111111111111011111111111110 ), .ATOPs(1), - .slv_aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .mst_aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .slv_b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .mst_b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .slv_ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .mst_ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .slv_r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .mst_r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .slv_req_t(axi_a48_d64_i4_u8_req_t), - .slv_resp_t(axi_a48_d64_i4_u8_resp_t), - .mst_req_t(axi_a48_d64_i8_u8_req_t), - .mst_resp_t(axi_a48_d64_i8_u8_resp_t), + .slv_aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .mst_aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .slv_b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .mst_b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .slv_ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .mst_ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .slv_r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .mst_r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .slv_req_t(axi_a48_d64_i4_u5_req_t), + .slv_resp_t(axi_a48_d64_i4_u5_resp_t), + .mst_req_t(axi_a48_d64_i8_u5_req_t), + .mst_resp_t(axi_a48_d64_i8_u5_resp_t), .rule_t(xbar_rule_48_t) ) i_soc_narrow_xbar ( .clk_i (clk_i), @@ -713,18 +713,18 @@ module occamy_soc .mst_req_o(hbm_xbar_in_req[HBM_XBAR_IN_WIDE_XBAR]), .mst_resp_i(hbm_xbar_in_rsp[HBM_XBAR_IN_WIDE_XBAR]) ); - axi_a48_d64_i8_u8_req_t soc_narrow_wide_amo_adapter_req; - axi_a48_d64_i8_u8_resp_t soc_narrow_wide_amo_adapter_rsp; + axi_a48_d64_i8_u5_req_t soc_narrow_wide_amo_adapter_req; + axi_a48_d64_i8_u5_resp_t soc_narrow_wide_amo_adapter_rsp; axi_riscv_atomics #( .AXI_ADDR_WIDTH(48), .AXI_DATA_WIDTH(64), .AXI_ID_WIDTH(8), - .AXI_USER_WIDTH(8), + .AXI_USER_WIDTH(5), .AXI_MAX_READ_TXNS(8), .AXI_MAX_WRITE_TXNS(8), .AXI_USER_AS_ID(1), - .AXI_USER_ID_MSB(7), + .AXI_USER_ID_MSB(4), .AXI_USER_ID_LSB(0), .RISCV_WORD_WIDTH(64), .N_AXI_CUT(1) @@ -824,18 +824,18 @@ module occamy_soc .mst_b_valid_i(soc_narrow_wide_amo_adapter_rsp.b_valid) ); - axi_a48_d64_i8_u8_req_t soc_narrow_wide_amo_adapter_cut_req; - axi_a48_d64_i8_u8_resp_t soc_narrow_wide_amo_adapter_cut_rsp; + axi_a48_d64_i8_u5_req_t soc_narrow_wide_amo_adapter_cut_req; + axi_a48_d64_i8_u5_resp_t soc_narrow_wide_amo_adapter_cut_rsp; axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_soc_narrow_wide_amo_adapter_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -844,18 +844,18 @@ module occamy_soc .mst_req_o(soc_narrow_wide_amo_adapter_cut_req), .mst_resp_i(soc_narrow_wide_amo_adapter_cut_rsp) ); - axi_a48_d64_i4_u8_req_t soc_narrow_wide_iwc_req; - axi_a48_d64_i4_u8_resp_t soc_narrow_wide_iwc_rsp; + axi_a48_d64_i4_u5_req_t soc_narrow_wide_iwc_req; + axi_a48_d64_i4_u5_resp_t soc_narrow_wide_iwc_rsp; axi_id_remap #( .AxiSlvPortIdWidth(8), .AxiSlvPortMaxUniqIds(16), .AxiMaxTxnsPerId(16), .AxiMstPortIdWidth(4), - .slv_req_t(axi_a48_d64_i8_u8_req_t), - .slv_resp_t(axi_a48_d64_i8_u8_resp_t), - .mst_req_t(axi_a48_d64_i4_u8_req_t), - .mst_resp_t(axi_a48_d64_i4_u8_resp_t) + .slv_req_t(axi_a48_d64_i8_u5_req_t), + .slv_resp_t(axi_a48_d64_i8_u5_resp_t), + .mst_req_t(axi_a48_d64_i4_u5_req_t), + .mst_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_soc_narrow_wide_iwc ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -915,31 +915,31 @@ module occamy_soc .mst_req_o(soc_wide_narrow_iwc_req), .mst_resp_i(soc_wide_narrow_iwc_rsp) ); - axi_a48_d512_i4_u8_req_t soc_wide_narrow_uwc_req; - axi_a48_d512_i4_u8_resp_t soc_wide_narrow_uwc_rsp; + axi_a48_d512_i4_u5_req_t soc_wide_narrow_uwc_req; + axi_a48_d512_i4_u5_resp_t soc_wide_narrow_uwc_rsp; // Change UW `AXI_ASSIGN_REQ_STRUCT(soc_wide_narrow_uwc_req, soc_wide_narrow_iwc_req) `AXI_ASSIGN_RESP_STRUCT(soc_wide_narrow_iwc_rsp, soc_wide_narrow_uwc_rsp) - axi_a48_d64_i4_u8_req_t soc_wide_narrow_dw_req; - axi_a48_d64_i4_u8_resp_t soc_wide_narrow_dw_rsp; + axi_a48_d64_i4_u5_req_t soc_wide_narrow_dw_req; + axi_a48_d64_i4_u5_resp_t soc_wide_narrow_dw_rsp; axi_dw_converter #( .AxiSlvPortDataWidth(512), .AxiMstPortDataWidth(64), .AxiAddrWidth(48), .AxiIdWidth(4), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .mst_w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .slv_w_chan_t(axi_a48_d512_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .mst_r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .slv_r_chan_t(axi_a48_d512_i4_u8_r_chan_t), - .axi_mst_req_t(axi_a48_d64_i4_u8_req_t), - .axi_mst_resp_t(axi_a48_d64_i4_u8_resp_t), - .axi_slv_req_t(axi_a48_d512_i4_u8_req_t), - .axi_slv_resp_t(axi_a48_d512_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .mst_w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .slv_w_chan_t(axi_a48_d512_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .mst_r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .slv_r_chan_t(axi_a48_d512_i4_u5_r_chan_t), + .axi_mst_req_t(axi_a48_d64_i4_u5_req_t), + .axi_mst_resp_t(axi_a48_d64_i4_u5_resp_t), + .axi_slv_req_t(axi_a48_d512_i4_u5_req_t), + .axi_slv_resp_t(axi_a48_d512_i4_u5_resp_t) ) i_soc_wide_narrow_dw ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -951,13 +951,13 @@ module occamy_soc axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_soc_wide_narrow_dw_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -970,14 +970,14 @@ module occamy_soc ////////// // PCIe // ////////// - axi_a48_d64_i8_u8_req_t pcie_out_noatop_req; - axi_a48_d64_i8_u8_resp_t pcie_out_noatop_rsp; + axi_a48_d64_i8_u5_req_t pcie_out_noatop_req; + axi_a48_d64_i8_u5_resp_t pcie_out_noatop_rsp; axi_atop_filter #( .AxiIdWidth(8), .AxiMaxWriteTxns(32), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_pcie_out_atop_filter ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -987,18 +987,18 @@ module occamy_soc .mst_resp_i(pcie_out_noatop_rsp) ); - axi_a48_d64_i8_u8_req_t pcie_out_req; - axi_a48_d64_i8_u8_resp_t pcie_out_rsp; + axi_a48_d64_i8_u5_req_t pcie_out_req; + axi_a48_d64_i8_u5_resp_t pcie_out_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_pcie_out_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1007,18 +1007,18 @@ module occamy_soc .mst_req_o(pcie_out_req), .mst_resp_i(pcie_out_rsp) ); - axi_a48_d64_i4_u8_req_t pcie_in_req; - axi_a48_d64_i4_u8_resp_t pcie_in_rsp; + axi_a48_d64_i4_u5_req_t pcie_in_req; + axi_a48_d64_i4_u5_resp_t pcie_in_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_pcie_in_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1036,18 +1036,18 @@ module occamy_soc ////////// // CVA6 // ////////// - axi_a48_d64_i4_u8_req_t cva6_mst_req; - axi_a48_d64_i4_u8_resp_t cva6_mst_rsp; + axi_a48_d64_i4_u5_req_t cva6_mst_req; + axi_a48_d64_i4_u5_resp_t cva6_mst_rsp; axi_multicut #( .NoCuts(2), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_cva6_mst_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1072,18 +1072,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 0 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_0_req; - axi_a48_d64_i8_u8_resp_t narrow_in_0_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_0_req; + axi_a48_d64_i8_u5_resp_t narrow_in_0_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_0 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1092,18 +1092,18 @@ module occamy_soc .mst_req_o(narrow_in_0_req), .mst_resp_i(narrow_in_0_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_0_req; - axi_a48_d64_i4_u8_resp_t narrow_out_0_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_0_req; + axi_a48_d64_i4_u5_resp_t narrow_out_0_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_0 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1209,18 +1209,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 1 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_1_req; - axi_a48_d64_i8_u8_resp_t narrow_in_1_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_1_req; + axi_a48_d64_i8_u5_resp_t narrow_in_1_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_1 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1229,18 +1229,18 @@ module occamy_soc .mst_req_o(narrow_in_1_req), .mst_resp_i(narrow_in_1_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_1_req; - axi_a48_d64_i4_u8_resp_t narrow_out_1_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_1_req; + axi_a48_d64_i4_u5_resp_t narrow_out_1_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_1 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1346,18 +1346,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 2 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_2_req; - axi_a48_d64_i8_u8_resp_t narrow_in_2_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_2_req; + axi_a48_d64_i8_u5_resp_t narrow_in_2_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_2 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1366,18 +1366,18 @@ module occamy_soc .mst_req_o(narrow_in_2_req), .mst_resp_i(narrow_in_2_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_2_req; - axi_a48_d64_i4_u8_resp_t narrow_out_2_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_2_req; + axi_a48_d64_i4_u5_resp_t narrow_out_2_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_2 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1483,18 +1483,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 3 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_3_req; - axi_a48_d64_i8_u8_resp_t narrow_in_3_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_3_req; + axi_a48_d64_i8_u5_resp_t narrow_in_3_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_3 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1503,18 +1503,18 @@ module occamy_soc .mst_req_o(narrow_in_3_req), .mst_resp_i(narrow_in_3_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_3_req; - axi_a48_d64_i4_u8_resp_t narrow_out_3_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_3_req; + axi_a48_d64_i4_u5_resp_t narrow_out_3_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_3 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1620,18 +1620,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 4 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_4_req; - axi_a48_d64_i8_u8_resp_t narrow_in_4_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_4_req; + axi_a48_d64_i8_u5_resp_t narrow_in_4_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_4 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1640,18 +1640,18 @@ module occamy_soc .mst_req_o(narrow_in_4_req), .mst_resp_i(narrow_in_4_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_4_req; - axi_a48_d64_i4_u8_resp_t narrow_out_4_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_4_req; + axi_a48_d64_i4_u5_resp_t narrow_out_4_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_4 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1757,18 +1757,18 @@ module occamy_soc ////////////////////// // S1 Quadrant 5 // ////////////////////// - axi_a48_d64_i8_u8_req_t narrow_in_5_req; - axi_a48_d64_i8_u8_resp_t narrow_in_5_rsp; + axi_a48_d64_i8_u5_req_t narrow_in_5_req; + axi_a48_d64_i8_u5_resp_t narrow_in_5_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_in_5 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1777,18 +1777,18 @@ module occamy_soc .mst_req_o(narrow_in_5_req), .mst_resp_i(narrow_in_5_rsp) ); - axi_a48_d64_i4_u8_req_t narrow_out_5_req; - axi_a48_d64_i4_u8_resp_t narrow_out_5_rsp; + axi_a48_d64_i4_u5_req_t narrow_out_5_req; + axi_a48_d64_i4_u5_resp_t narrow_out_5_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_narrow_out_cut_5 ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1895,18 +1895,18 @@ module occamy_soc //////////////// // SPM NARROW // //////////////// - axi_a48_d64_i8_u8_req_t soc_narrow_xbar_out_cut_req; - axi_a48_d64_i8_u8_resp_t soc_narrow_xbar_out_cut_rsp; + axi_a48_d64_i8_u5_req_t soc_narrow_xbar_out_cut_req; + axi_a48_d64_i8_u5_resp_t soc_narrow_xbar_out_cut_rsp; axi_multicut #( .NoCuts(2), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_soc_narrow_xbar_out_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -1915,18 +1915,18 @@ module occamy_soc .mst_req_o(soc_narrow_xbar_out_cut_req), .mst_resp_i(soc_narrow_xbar_out_cut_rsp) ); - axi_a48_d64_i8_u8_req_t spm_narrow_amo_adapter_req; - axi_a48_d64_i8_u8_resp_t spm_narrow_amo_adapter_rsp; + axi_a48_d64_i8_u5_req_t spm_narrow_amo_adapter_req; + axi_a48_d64_i8_u5_resp_t spm_narrow_amo_adapter_rsp; axi_riscv_atomics #( .AXI_ADDR_WIDTH(48), .AXI_DATA_WIDTH(64), .AXI_ID_WIDTH(8), - .AXI_USER_WIDTH(8), + .AXI_USER_WIDTH(5), .AXI_MAX_READ_TXNS(8), .AXI_MAX_WRITE_TXNS(8), .AXI_USER_AS_ID(1), - .AXI_USER_ID_MSB(7), + .AXI_USER_ID_MSB(4), .AXI_USER_ID_LSB(0), .RISCV_WORD_WIDTH(64), .N_AXI_CUT(1) @@ -2026,18 +2026,18 @@ module occamy_soc .mst_b_valid_i(spm_narrow_amo_adapter_rsp.b_valid) ); - axi_a48_d64_i8_u8_req_t spm_narrow_amo_adapter_cut_req; - axi_a48_d64_i8_u8_resp_t spm_narrow_amo_adapter_cut_rsp; + axi_a48_d64_i8_u5_req_t spm_narrow_amo_adapter_cut_req; + axi_a48_d64_i8_u5_resp_t spm_narrow_amo_adapter_cut_rsp; axi_multicut #( .NoCuts(1), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_spm_narrow_amo_adapter_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -2058,8 +2058,8 @@ module occamy_soc mem_narrow_strb_t spm_narrow_strb; axi_to_mem_interleaved #( - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t), .AddrWidth(19), .DataWidth(64), .IdWidth(8), @@ -2210,14 +2210,14 @@ module occamy_soc // SYS iDMA // ////////////// - axi_a48_d64_i8_u8_req_t out_sys_idma_cfg_noatop_req; - axi_a48_d64_i8_u8_resp_t out_sys_idma_cfg_noatop_rsp; + axi_a48_d64_i8_u5_req_t out_sys_idma_cfg_noatop_req; + axi_a48_d64_i8_u5_resp_t out_sys_idma_cfg_noatop_rsp; axi_atop_filter #( .AxiIdWidth(8), .AxiMaxWriteTxns(4), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_out_sys_idma_cfg_atop_filter ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2258,9 +2258,9 @@ module occamy_soc .ADDR_WIDTH(48), .DATA_WIDTH(64), .ID_WIDTH (8), - .USER_WIDTH(8), - .axi_req_t (axi_a48_d64_i8_u8_req_t), - .axi_rsp_t (axi_a48_d64_i8_u8_resp_t), + .USER_WIDTH(5), + .axi_req_t (axi_a48_d64_i8_u5_req_t), + .axi_rsp_t (axi_a48_d64_i8_u5_resp_t), .reg_req_t (idma_cfg_reg_a48_d64_req_t), .reg_rsp_t (idma_cfg_reg_a48_d64_rsp_t) ) i_axi_to_reg_sys_idma_cfg ( @@ -2589,18 +2589,18 @@ module occamy_soc .mst_req_o(wide_to_hbi_cut_req), .mst_resp_i(wide_to_hbi_cut_rsp) ); - axi_a48_d64_i4_u8_req_t hbi_in_narrow_soc_req; - axi_a48_d64_i4_u8_resp_t hbi_in_narrow_soc_rsp; + axi_a48_d64_i4_u5_req_t hbi_in_narrow_soc_req; + axi_a48_d64_i4_u5_resp_t hbi_in_narrow_soc_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_hbi_to_narrow_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -2609,14 +2609,14 @@ module occamy_soc .mst_req_o(soc_narrow_xbar_in_req[SOC_NARROW_XBAR_IN_HBI]), .mst_resp_i(soc_narrow_xbar_in_rsp[SOC_NARROW_XBAR_IN_HBI]) ); - axi_a48_d64_i8_u8_req_t narrow_to_hbi_trunc_req; - axi_a48_d64_i8_u8_resp_t narrow_to_hbi_trunc_rsp; + axi_a48_d64_i8_u5_req_t narrow_to_hbi_trunc_req; + axi_a48_d64_i8_u5_resp_t narrow_to_hbi_trunc_rsp; axi_modify_address #( - .slv_req_t (axi_a48_d64_i8_u8_req_t), + .slv_req_t (axi_a48_d64_i8_u5_req_t), .mst_addr_t(logic [47:0]), - .mst_req_t (axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .mst_req_t (axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_to_hbi_trunc ( .slv_req_i(soc_narrow_xbar_out_req[SOC_NARROW_XBAR_OUT_HBI]), .slv_resp_o(soc_narrow_xbar_out_rsp[SOC_NARROW_XBAR_OUT_HBI]), @@ -2626,18 +2626,18 @@ module occamy_soc .mst_resp_i(narrow_to_hbi_trunc_rsp) ); - axi_a48_d64_i8_u8_req_t narrow_to_hbi_cut_req; - axi_a48_d64_i8_u8_resp_t narrow_to_hbi_cut_rsp; + axi_a48_d64_i8_u5_req_t narrow_to_hbi_cut_req; + axi_a48_d64_i8_u5_resp_t narrow_to_hbi_cut_rsp; axi_multicut #( .NoCuts(3), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_narrow_to_hbi_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -2661,14 +2661,14 @@ module occamy_soc ///////////////// // Peripherals // ///////////////// - axi_a48_d64_i8_u8_req_t periph_axi_lite_narrow_out_noatop_req; - axi_a48_d64_i8_u8_resp_t periph_axi_lite_narrow_out_noatop_rsp; + axi_a48_d64_i8_u5_req_t periph_axi_lite_narrow_out_noatop_req; + axi_a48_d64_i8_u5_resp_t periph_axi_lite_narrow_out_noatop_rsp; axi_atop_filter #( .AxiIdWidth(8), .AxiMaxWriteTxns(4), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_periph_axi_lite_narrow_out_atop_filter ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2678,18 +2678,18 @@ module occamy_soc .mst_resp_i(periph_axi_lite_narrow_out_noatop_rsp) ); - axi_a48_d64_i8_u8_req_t periph_axi_lite_narrow_out_req; - axi_a48_d64_i8_u8_resp_t periph_axi_lite_narrow_out_rsp; + axi_a48_d64_i8_u5_req_t periph_axi_lite_narrow_out_req; + axi_a48_d64_i8_u5_resp_t periph_axi_lite_narrow_out_rsp; axi_multicut #( .NoCuts(2), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_periph_axi_lite_narrow_out_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -2698,14 +2698,14 @@ module occamy_soc .mst_req_o(periph_axi_lite_narrow_out_req), .mst_resp_i(periph_axi_lite_narrow_out_rsp) ); - axi_a48_d64_i8_u8_req_t periph_axi_lite_out_noatop_req; - axi_a48_d64_i8_u8_resp_t periph_axi_lite_out_noatop_rsp; + axi_a48_d64_i8_u5_req_t periph_axi_lite_out_noatop_req; + axi_a48_d64_i8_u5_resp_t periph_axi_lite_out_noatop_rsp; axi_atop_filter #( .AxiIdWidth(8), .AxiMaxWriteTxns(4), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_periph_axi_lite_out_atop_filter ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -2715,18 +2715,18 @@ module occamy_soc .mst_resp_i(periph_axi_lite_out_noatop_rsp) ); - axi_a48_d64_i8_u8_req_t periph_axi_lite_out_req; - axi_a48_d64_i8_u8_resp_t periph_axi_lite_out_rsp; + axi_a48_d64_i8_u5_req_t periph_axi_lite_out_req; + axi_a48_d64_i8_u5_resp_t periph_axi_lite_out_rsp; axi_multicut #( .NoCuts(2), - .aw_chan_t(axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_periph_axi_lite_out_cut ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -2735,18 +2735,18 @@ module occamy_soc .mst_req_o(periph_axi_lite_out_req), .mst_resp_i(periph_axi_lite_out_rsp) ); - axi_a48_d64_i4_u8_req_t periph_axi_lite_in_req; - axi_a48_d64_i4_u8_resp_t periph_axi_lite_in_rsp; + axi_a48_d64_i4_u5_req_t periph_axi_lite_in_req; + axi_a48_d64_i4_u5_resp_t periph_axi_lite_in_rsp; axi_multicut #( .NoCuts(2), - .aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t), - .w_chan_t(axi_a48_d64_i4_u8_w_chan_t), - .b_chan_t(axi_a48_d64_i4_u8_b_chan_t), - .ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t), - .r_chan_t(axi_a48_d64_i4_u8_r_chan_t), - .axi_req_t(axi_a48_d64_i4_u8_req_t), - .axi_resp_t(axi_a48_d64_i4_u8_resp_t) + .aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t), + .w_chan_t(axi_a48_d64_i4_u5_w_chan_t), + .b_chan_t(axi_a48_d64_i4_u5_b_chan_t), + .ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t), + .r_chan_t(axi_a48_d64_i4_u5_r_chan_t), + .axi_req_t(axi_a48_d64_i4_u5_req_t), + .axi_resp_t(axi_a48_d64_i4_u5_resp_t) ) i_periph_axi_lite_in_cut ( .clk_i(clk_i), .rst_ni(rst_ni), diff --git a/hw/system/occamy/src/occamy_top.sv b/hw/system/occamy/src/occamy_top.sv index d3bbe0d27..00cd0ae0d 100644 --- a/hw/system/occamy/src/occamy_top.sv +++ b/hw/system/occamy/src/occamy_top.sv @@ -104,17 +104,17 @@ module occamy_top output axi_a48_d512_i6_u0_req_t hbi_wide_req_o, input axi_a48_d512_i6_u0_resp_t hbi_wide_rsp_i, - input axi_a48_d64_i4_u8_req_t hbi_narrow_req_i, - output axi_a48_d64_i4_u8_resp_t hbi_narrow_rsp_o, - output axi_a48_d64_i8_u8_req_t hbi_narrow_req_o, - input axi_a48_d64_i8_u8_resp_t hbi_narrow_rsp_i, + input axi_a48_d64_i4_u5_req_t hbi_narrow_req_i, + output axi_a48_d64_i4_u5_resp_t hbi_narrow_rsp_o, + output axi_a48_d64_i8_u5_req_t hbi_narrow_req_o, + input axi_a48_d64_i8_u5_resp_t hbi_narrow_rsp_i, /// PCIe Ports - output axi_a48_d64_i8_u8_req_t pcie_axi_req_o, - input axi_a48_d64_i8_u8_resp_t pcie_axi_rsp_i, + output axi_a48_d64_i8_u5_req_t pcie_axi_req_o, + input axi_a48_d64_i8_u5_resp_t pcie_axi_rsp_i, - input axi_a48_d64_i4_u8_req_t pcie_axi_req_i, - output axi_a48_d64_i4_u8_resp_t pcie_axi_rsp_o, + input axi_a48_d64_i4_u5_req_t pcie_axi_req_i, + output axi_a48_d64_i4_u5_resp_t pcie_axi_rsp_o, /// SRAM configuration @@ -323,14 +323,14 @@ module occamy_top /////////////////////////////// // Peripheral Xbar connections - axi_a48_d64_i8_u8_req_t periph_axi_lite_soc2per_req; - axi_a48_d64_i8_u8_resp_t periph_axi_lite_soc2per_rsp; + axi_a48_d64_i8_u5_req_t periph_axi_lite_soc2per_req; + axi_a48_d64_i8_u5_resp_t periph_axi_lite_soc2per_rsp; - axi_a48_d64_i4_u8_req_t periph_axi_lite_per2soc_req; - axi_a48_d64_i4_u8_resp_t periph_axi_lite_per2soc_rsp; + axi_a48_d64_i4_u5_req_t periph_axi_lite_per2soc_req; + axi_a48_d64_i4_u5_resp_t periph_axi_lite_per2soc_rsp; - axi_a48_d64_i8_u8_req_t periph_regbus_soc2per_req; - axi_a48_d64_i8_u8_resp_t periph_regbus_soc2per_rsp; + axi_a48_d64_i8_u5_req_t periph_regbus_soc2per_req; + axi_a48_d64_i8_u5_resp_t periph_regbus_soc2per_rsp; occamy_soc i_occamy_soc ( .clk_i, @@ -381,17 +381,17 @@ module occamy_top ); // Connect AXI-lite master - axi_a48_d64_i8_u8_req_t axi_lite_from_soc_cdc_req; - axi_a48_d64_i8_u8_resp_t axi_lite_from_soc_cdc_rsp; + axi_a48_d64_i8_u5_req_t axi_lite_from_soc_cdc_req; + axi_a48_d64_i8_u5_resp_t axi_lite_from_soc_cdc_rsp; axi_cdc #( - .aw_chan_t (axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t (axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t (axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t (axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t (axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t (axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t), + .aw_chan_t (axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t (axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t (axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t (axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t (axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t (axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t), .LogDepth (2) ) i_axi_lite_from_soc_cdc ( .src_clk_i (clk_i), @@ -408,12 +408,12 @@ module occamy_top .AxiAddrWidth(48), .AxiDataWidth(64), .AxiIdWidth(8), - .AxiUserWidth(8), + .AxiUserWidth(5), .AxiMaxWriteTxns(4), .AxiMaxReadTxns(4), .FallThrough(0), - .full_req_t(axi_a48_d64_i8_u8_req_t), - .full_resp_t(axi_a48_d64_i8_u8_resp_t), + .full_req_t(axi_a48_d64_i8_u5_req_t), + .full_resp_t(axi_a48_d64_i8_u5_resp_t), .lite_req_t(axi_lite_a48_d64_req_t), .lite_resp_t(axi_lite_a48_d64_rsp_t) ) i_axi_to_axi_lite_periph_pc ( @@ -454,8 +454,8 @@ module occamy_top .AxiDataWidth(64), .req_lite_t (axi_lite_a48_d64_req_t), .resp_lite_t (axi_lite_a48_d64_rsp_t), - .axi_req_t (axi_a48_d64_i4_u8_req_t), - .axi_resp_t (axi_a48_d64_i4_u8_resp_t) + .axi_req_t (axi_a48_d64_i4_u5_req_t), + .axi_resp_t (axi_a48_d64_i4_u5_resp_t) ) i_axi_lite_to_axi_periph_pc ( .slv_req_lite_i (axi_lite_to_soc_cdc_req), .slv_resp_lite_o(axi_lite_to_soc_cdc_rsp), @@ -466,17 +466,17 @@ module occamy_top ); - axi_a48_d64_i8_u8_req_t periph_cdc_req; - axi_a48_d64_i8_u8_resp_t periph_cdc_rsp; + axi_a48_d64_i8_u5_req_t periph_cdc_req; + axi_a48_d64_i8_u5_resp_t periph_cdc_rsp; axi_cdc #( - .aw_chan_t (axi_a48_d64_i8_u8_aw_chan_t), - .w_chan_t (axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t (axi_a48_d64_i8_u8_b_chan_t), - .ar_chan_t (axi_a48_d64_i8_u8_ar_chan_t), - .r_chan_t (axi_a48_d64_i8_u8_r_chan_t), - .axi_req_t (axi_a48_d64_i8_u8_req_t), - .axi_resp_t(axi_a48_d64_i8_u8_resp_t), + .aw_chan_t (axi_a48_d64_i8_u5_aw_chan_t), + .w_chan_t (axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t (axi_a48_d64_i8_u5_b_chan_t), + .ar_chan_t (axi_a48_d64_i8_u5_ar_chan_t), + .r_chan_t (axi_a48_d64_i8_u5_r_chan_t), + .axi_req_t (axi_a48_d64_i8_u5_req_t), + .axi_resp_t(axi_a48_d64_i8_u5_resp_t), .LogDepth (2) ) i_periph_cdc ( .src_clk_i (clk_i), @@ -489,25 +489,25 @@ module occamy_top .dst_resp_i(periph_cdc_rsp) ); - axi_a48_d32_i8_u8_req_t axi_to_axi_lite_dw_req; - axi_a48_d32_i8_u8_resp_t axi_to_axi_lite_dw_rsp; + axi_a48_d32_i8_u5_req_t axi_to_axi_lite_dw_req; + axi_a48_d32_i8_u5_resp_t axi_to_axi_lite_dw_rsp; axi_dw_converter #( .AxiSlvPortDataWidth(64), .AxiMstPortDataWidth(32), .AxiAddrWidth(48), .AxiIdWidth(8), - .aw_chan_t(axi_a48_d32_i8_u8_aw_chan_t), - .mst_w_chan_t(axi_a48_d32_i8_u8_w_chan_t), - .slv_w_chan_t(axi_a48_d64_i8_u8_w_chan_t), - .b_chan_t(axi_a48_d32_i8_u8_b_chan_t), - .ar_chan_t(axi_a48_d32_i8_u8_ar_chan_t), - .mst_r_chan_t(axi_a48_d32_i8_u8_r_chan_t), - .slv_r_chan_t(axi_a48_d64_i8_u8_r_chan_t), - .axi_mst_req_t(axi_a48_d32_i8_u8_req_t), - .axi_mst_resp_t(axi_a48_d32_i8_u8_resp_t), - .axi_slv_req_t(axi_a48_d64_i8_u8_req_t), - .axi_slv_resp_t(axi_a48_d64_i8_u8_resp_t) + .aw_chan_t(axi_a48_d32_i8_u5_aw_chan_t), + .mst_w_chan_t(axi_a48_d32_i8_u5_w_chan_t), + .slv_w_chan_t(axi_a48_d64_i8_u5_w_chan_t), + .b_chan_t(axi_a48_d32_i8_u5_b_chan_t), + .ar_chan_t(axi_a48_d32_i8_u5_ar_chan_t), + .mst_r_chan_t(axi_a48_d32_i8_u5_r_chan_t), + .slv_r_chan_t(axi_a48_d64_i8_u5_r_chan_t), + .axi_mst_req_t(axi_a48_d32_i8_u5_req_t), + .axi_mst_resp_t(axi_a48_d32_i8_u5_resp_t), + .axi_slv_req_t(axi_a48_d64_i8_u5_req_t), + .axi_slv_resp_t(axi_a48_d64_i8_u5_resp_t) ) i_axi_to_axi_lite_dw ( .clk_i(clk_periph_i), .rst_ni(rst_periph_ni), @@ -521,12 +521,12 @@ module occamy_top .AxiAddrWidth(48), .AxiDataWidth(32), .AxiIdWidth(8), - .AxiUserWidth(8), + .AxiUserWidth(5), .AxiMaxWriteTxns(4), .AxiMaxReadTxns(4), .FallThrough(0), - .full_req_t(axi_a48_d32_i8_u8_req_t), - .full_resp_t(axi_a48_d32_i8_u8_resp_t), + .full_req_t(axi_a48_d32_i8_u5_req_t), + .full_resp_t(axi_a48_d32_i8_u5_resp_t), .lite_req_t(axi_lite_a48_d32_req_t), .lite_resp_t(axi_lite_a48_d32_rsp_t) ) i_axi_to_axi_lite_regbus_periph_pc ( diff --git a/hw/system/occamy/src/occamy_xilinx.sv b/hw/system/occamy/src/occamy_xilinx.sv index d8114581b..61af9dcfc 100644 --- a/hw/system/occamy/src/occamy_xilinx.sv +++ b/hw/system/occamy/src/occamy_xilinx.sv @@ -432,13 +432,13 @@ module occamy_xilinx output axi_pkg::prot_t m_axi_pcie_awprot, output axi_pkg::qos_t m_axi_pcie_awqos, output axi_pkg::region_t m_axi_pcie_awregion, - output logic [ 7:0] m_axi_pcie_awuser, + output logic [ 4:0] m_axi_pcie_awuser, input logic m_axi_pcie_wready, output logic m_axi_pcie_wvalid, output logic [63:0] m_axi_pcie_wdata, output logic [ 7:0] m_axi_pcie_wstrb, output logic m_axi_pcie_wlast, - output logic [ 7:0] m_axi_pcie_wuser, + output logic [ 4:0] m_axi_pcie_wuser, input logic m_axi_pcie_arready, output logic m_axi_pcie_arvalid, output logic [ 7:0] m_axi_pcie_arid, @@ -451,19 +451,19 @@ module occamy_xilinx output axi_pkg::prot_t m_axi_pcie_arprot, output axi_pkg::qos_t m_axi_pcie_arqos, output axi_pkg::region_t m_axi_pcie_arregion, - output logic [ 7:0] m_axi_pcie_aruser, + output logic [ 4:0] m_axi_pcie_aruser, output logic m_axi_pcie_rready, input logic m_axi_pcie_rvalid, input logic [ 7:0] m_axi_pcie_rid, input logic [63:0] m_axi_pcie_rdata, input axi_pkg::resp_t m_axi_pcie_rresp, input logic m_axi_pcie_rlast, - input logic [ 7:0] m_axi_pcie_ruser, + input logic [ 4:0] m_axi_pcie_ruser, output logic m_axi_pcie_bready, input logic m_axi_pcie_bvalid, input logic [ 7:0] m_axi_pcie_bid, input axi_pkg::resp_t m_axi_pcie_bresp, - input logic [ 7:0] m_axi_pcie_buser, + input logic [ 4:0] m_axi_pcie_buser, output logic s_axi_pcie_awready, input logic s_axi_pcie_awvalid, input logic [ 3:0] s_axi_pcie_awid, @@ -476,13 +476,13 @@ module occamy_xilinx input axi_pkg::prot_t s_axi_pcie_awprot, input axi_pkg::qos_t s_axi_pcie_awqos, input axi_pkg::region_t s_axi_pcie_awregion, - input logic [ 7:0] s_axi_pcie_awuser, + input logic [ 4:0] s_axi_pcie_awuser, output logic s_axi_pcie_wready, input logic s_axi_pcie_wvalid, input logic [63:0] s_axi_pcie_wdata, input logic [ 7:0] s_axi_pcie_wstrb, input logic s_axi_pcie_wlast, - input logic [ 7:0] s_axi_pcie_wuser, + input logic [ 4:0] s_axi_pcie_wuser, output logic s_axi_pcie_arready, input logic s_axi_pcie_arvalid, input logic [ 3:0] s_axi_pcie_arid, @@ -495,19 +495,19 @@ module occamy_xilinx input axi_pkg::prot_t s_axi_pcie_arprot, input axi_pkg::qos_t s_axi_pcie_arqos, input axi_pkg::region_t s_axi_pcie_arregion, - input logic [ 7:0] s_axi_pcie_aruser, + input logic [ 4:0] s_axi_pcie_aruser, input logic s_axi_pcie_rready, output logic s_axi_pcie_rvalid, output logic [ 3:0] s_axi_pcie_rid, output logic [63:0] s_axi_pcie_rdata, output axi_pkg::resp_t s_axi_pcie_rresp, output logic s_axi_pcie_rlast, - output logic [ 7:0] s_axi_pcie_ruser, + output logic [ 4:0] s_axi_pcie_ruser, input logic s_axi_pcie_bready, output logic s_axi_pcie_bvalid, output logic [ 3:0] s_axi_pcie_bid, output axi_pkg::resp_t s_axi_pcie_bresp, - output logic [ 7:0] s_axi_pcie_buser + output logic [ 4:0] s_axi_pcie_buser /// HBI Ports ); @@ -515,11 +515,11 @@ module occamy_xilinx ////////// // PCIe // ////////// - axi_a48_d64_i8_u8_req_t pcie_axi_req_o; - axi_a48_d64_i8_u8_resp_t pcie_axi_rsp_i; + axi_a48_d64_i8_u5_req_t pcie_axi_req_o; + axi_a48_d64_i8_u5_resp_t pcie_axi_rsp_i; - axi_a48_d64_i4_u8_req_t pcie_axi_req_i; - axi_a48_d64_i4_u8_resp_t pcie_axi_rsp_o; + axi_a48_d64_i4_u5_req_t pcie_axi_req_i; + axi_a48_d64_i4_u5_resp_t pcie_axi_rsp_o; // Assign structs to flattened ports `AXI_FLATTEN_MASTER(pcie, pcie_axi_req_o, pcie_axi_rsp_i) diff --git a/hw/system/occamy/test/testharness.sv b/hw/system/occamy/test/testharness.sv index 75e0b4576..6413eb302 100644 --- a/hw/system/occamy/test/testharness.sv +++ b/hw/system/occamy/test/testharness.sv @@ -277,17 +277,17 @@ module testharness import occamy_pkg::*; ( - axi_a48_d64_i8_u8_req_t pcie_axi_req; - axi_a48_d64_i8_u8_resp_t pcie_axi_rsp; + axi_a48_d64_i8_u5_req_t pcie_axi_req; + axi_a48_d64_i8_u5_resp_t pcie_axi_rsp; tb_memory_axi #( .AxiAddrWidth (48), .AxiDataWidth (64), .AxiIdWidth (8), - .AxiUserWidth (9), + .AxiUserWidth (6), .ATOPSupport (0), - .req_t (axi_a48_d64_i8_u8_req_t), - .rsp_t (axi_a48_d64_i8_u8_resp_t) + .req_t (axi_a48_d64_i8_u5_req_t), + .rsp_t (axi_a48_d64_i8_u5_resp_t) ) i_pcie_axi_channel ( .clk_i, .rst_ni,