diff --git a/.gitignore b/.gitignore index 0a6a3b21..6551a7a6 100644 --- a/.gitignore +++ b/.gitignore @@ -1,10 +1,8 @@ -.bender -scripts/compile.tcl - +.bender/ +work/ modelsim.ini -work transcript - -regression-tests -pulp-runtime -nonfree +scripts/compile.tcl +regression_tests/ +pulp-runtime/ +fault_injection_sim/ diff --git a/Bender.lock b/Bender.lock index 5fe7ce1d..0a7f2ea2 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,7 +1,14 @@ packages: + apb: + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 + source: + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells axi: - revision: fccffb5953ec8564218ba05e20adbedec845e014 - version: 0.39.1 + revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d + version: 0.39.5 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -9,7 +16,7 @@ packages: - common_verification - tech_cells_generic axi2mem: - revision: 6973e0434d26ba578cdb4aa69c26c1facd1a3f15 + revision: b0e963433b2f6a61262b1448031e74eaec57c203 version: null source: Git: https://github.com/pulp-platform/axi2mem.git @@ -17,8 +24,8 @@ packages: - axi_slice - common_cells axi2per: - revision: a99ef2fac9f3b087671109a27c766f25e8e0f115 - version: 1.0.1 + revision: 4932bd2b88a1c7b5f0bf95411fc512905ed32439 + version: null source: Git: https://github.com/pulp-platform/axi2per.git dependencies: @@ -30,23 +37,34 @@ packages: Git: https://github.com/pulp-platform/axi_slice.git dependencies: - common_cells + cluster_icache: + revision: dd0e8f3497903a9ca99fc9f349d5a4f688ceb3ae + version: null + source: + Git: https://github.com/pulp-platform/cluster_icache.git + dependencies: + - axi + - common_cells + - register_interface + - scm + - tech_cells_generic cluster_interconnect: - revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27 - version: 1.2.1 + revision: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 + version: null source: Git: https://github.com/pulp-platform/cluster_interconnect.git dependencies: - common_cells cluster_peripherals: - revision: d388a790d9e1129e3ec57b2e0075ee21e454c3b1 - version: 2.1.0 + revision: 0b8e8ab9e6be3a5030a18256bb7e75cf6b6f6cac + version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git dependencies: - hci common_cells: - revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f - version: 1.32.0 + revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb + version: 1.37.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -59,25 +77,26 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40p: - revision: 8d58109ab61e1fb6c9dcbafefb8f3a56ee596427 + revision: e863f576699815b38cc9d80dbdede8ed5efd5991 version: null source: Git: https://github.com/pulp-platform/cv32e40p.git dependencies: + - common_cells - fpnew - tech_cells_generic event_unit_flex: - revision: 53fb3a1093aaaedfe883739fd8a3155d601210bc + revision: 28e0499374117c7b0ef4c6ad81b60d7526af886f version: null source: Git: https://github.com/pulp-platform/event_unit_flex.git dependencies: - common_cells fpnew: - revision: 8dc44406b1ccbc4487121710c1883e805f893965 - version: 0.6.6 + revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 + version: null source: - Git: https://github.com/pulp-platform/fpnew.git + Git: https://github.com/pulp-platform/cvfpu.git dependencies: - common_cells - fpu_div_sqrt_mvp @@ -89,24 +108,27 @@ packages: dependencies: - common_cells fpu_interco: - revision: 66b4084117546d5b748c30b5500769805f489d2f + revision: b5f7a315929308823cacd81e1e4898f1eeecfc64 version: null source: Git: https://github.com/pulp-platform/fpu_interco.git dependencies: - - cv32e40p - fpnew + - riscv hci: - revision: 8fb848e8f6722c1c21b44533535f430960c31b0b - version: 1.0.8 + revision: 38fc2a7eea7978df52434e66ee04a40788fd86b7 + version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect + - common_cells - hwpe-stream - l2_tcdm_hybrid_interco + - redundancy_cells + - register_interface hier-icache: - revision: fc231dfc9559c6715c3577049eae3d1887282cb0 + revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c version: null source: Git: https://github.com/pulp-platform/hier-icache.git @@ -118,33 +140,24 @@ packages: - scm - tech_cells_generic hwpe-ctrl: - revision: 1916c72f024175f1fe351acc3db3c6e9925a117d - version: 1.7.3 + revision: a5966201aeeb988d607accdc55da933a53c6a56e + version: null source: Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: - tech_cells_generic - hwpe-datamover-example: - revision: 47e7fe8a38331b123d763ecab11be4058d425021 - version: 1.0.1 - source: - Git: https://github.com/pulp-platform/hwpe-datamover-example.git - dependencies: - - hci - - hwpe-ctrl - - hwpe-stream hwpe-stream: - revision: 389bd7fb1975d2df1546910c5f220c668122e646 - version: 1.6.5 + revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 + version: 1.8.0 source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: - tech_cells_generic ibex: - revision: 95b85ddd1c995ace9f89ee42530f9e24820c1051 + revision: b18f7ef178ed07f5085051f96042c670a919fd5c version: null source: - Git: https://github.com/lowRISC/ibex.git + Git: https://github.com/pulp-platform/ibex.git dependencies: - tech_cells_generic icache-intc: @@ -153,6 +166,16 @@ packages: source: Git: https://github.com/pulp-platform/icache-intc.git dependencies: [] + idma: + revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 + version: null + source: + Git: https://github.com/pulp-platform/iDMA.git + dependencies: + - axi + - common_cells + - common_verification + - register_interface l2_tcdm_hybrid_interco: revision: fa55e72859dcfb117a2788a77352193bef94ff2b version: 1.0.0 @@ -160,25 +183,91 @@ packages: Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git dependencies: [] mchan: - revision: a9c71f2d9845a4ca05cf2c6ad089b4753f76fc2e - version: 1.2.3 + revision: 7f064f205a3e0203e959b14773c4afecf56681ab + version: null source: Git: https://github.com/pulp-platform/mchan.git dependencies: - common_cells + neureka: + revision: 94528df2bc6d5eedc0439bd403c2ad005f0a7519 + version: null + source: + Git: https://github.com/pulp-platform/neureka.git + dependencies: + - hci + - hwpe-ctrl + - hwpe-stream + - register_interface + - zeroriscy per2axi: - revision: 892fcad60b6374fe558cbde76f4a529d473ba5ca - version: 1.0.4 + revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 + version: null source: Git: https://github.com/pulp-platform/per2axi.git dependencies: - axi_slice + redmule: + revision: 9223ccc932e21d0667e9c2d30831db41eec9299e + version: null + source: + Git: https://github.com/pulp-platform/redmule.git + dependencies: + - common_cells + - cv32e40p + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - register_interface + - tech_cells_generic + redundancy_cells: + revision: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc + version: null + source: + Git: https://github.com/pulp-platform/redundancy_cells.git + dependencies: + - common_cells + - common_verification + - register_interface + - tech_cells_generic + register_interface: + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 + source: + Git: https://github.com/pulp-platform/register_interface.git + dependencies: + - apb + - axi + - common_cells + - common_verification + riscv: + revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac + version: null + source: + Git: https://github.com/AlSaqr-platform/riscv_nn.git + dependencies: + - fpnew + - tech_cells_generic scm: - revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60 - version: 1.1.1 + revision: 74426dee36f28ae1c02f7635cf844a0156145320 + version: null source: Git: https://github.com/pulp-platform/scm.git - dependencies: [] + dependencies: + - tech_cells_generic + softex: + revision: 23faeccaf204817bc9e6649e469072e5726be561 + version: 1.0.0 + source: + Git: https://github.com/belanoa/softex.git + dependencies: + - common_cells + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - ibex tech_cells_generic: revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf version: 0.2.13 @@ -192,3 +281,9 @@ packages: source: Git: https://github.com/pulp-platform/timer_unit.git dependencies: [] + zeroriscy: + revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 + version: null + source: + Git: https://github.com/yvantor/ibex.git + dependencies: [] diff --git a/Bender.yml b/Bender.yml index 12353bcf..557c89f5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -4,7 +4,7 @@ package: name: pulp_cluster - authors: + authors: - "Pirmin Vogel " - "Angelo Garofalo " - "Francesco Conti " @@ -12,25 +12,34 @@ package: - "Michael Rogenmoser " dependencies: - axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "6973e0434d26ba578cdb4aa69c26c1facd1a3f15" } # deprecated, replace with axi_to_mem in axi repo - axi2per: { git: "https://github.com/pulp-platform/axi2per.git", version: 1.0.1 } - per2axi: { git: "https://github.com/pulp-platform/per2axi.git", version: 1.0.4 } - cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 } - event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } - mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fc231dfc9559c6715c3577049eae3d1887282cb0" } - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "66b4084117546d5b748c30b5500769805f489d2f" } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } - axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) + axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "b0e963433b2f6a61262b1448031e74eaec57c203" } # branch: yt/astral + axi2per: { git: "https://github.com/pulp-platform/axi2per.git", rev: "4932bd2b88a1c7b5f0bf95411fc512905ed32439" } # branch: yt/astral + per2axi: { git: "https://github.com/pulp-platform/per2axi.git", rev: "95bf23119b47fc171d9ed3734c431f71cffd9350" } # branch: yt/astral + cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 } # branch: michaero/hci-fix + event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr + mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization + idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "dd0e8f3497903a9ca99fc9f349d5a4f688ceb3ae" } # branch: michaero/astral_reliability + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "b5f7a315929308823cacd81e1e4898f1eeecfc64" } # branch: astral + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "pulpissimo-v3.4.0-rev4"} - ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } - scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0} - hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } - hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } + riscv: { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 } + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch + ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } + scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 38fc2a7 } # branch: lg/ecc_rebase_v2.1.1 + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 9223ccc } # branch: astral-hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 94528df } # branch: fc/astral-v1.0-rebased + softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } + +export_include_dirs: + - include sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this @@ -44,7 +53,13 @@ sources: - rtl/cluster_clock_gate.sv - rtl/cluster_event_map.sv - rtl/cluster_timer_wrap.sv - - rtl/dmac_wrap.sv + - rtl/obi_pulp_adapter.sv + - target: mchan + files: + - rtl/mchan_wrap.sv + - target: not(mchan) + files: + - rtl/idma_wrap.sv - rtl/hwpe_subsystem.sv - rtl/instr_width_converter.sv - rtl/per2axi_wrap.sv @@ -56,19 +71,16 @@ sources: # Level 1 - rtl/cluster_interconnect_wrap.sv - rtl/cluster_peripherals.sv - - rtl/core_demux.sv - # Level 2 - - target: rtl + - rtl/data_periph_demux.sv + - rtl/core_demux_wrap.sv + - rtl/core_region.sv + - target: simulation + files: defines: TRACE_EXECUTION: ~ - files: - - rtl/core_region.sv - - target: not(rtl) - files: - - rtl/core_region.sv # Level 3 - rtl/pulp_cluster.sv - + - target: test files: - tb/mock_uart.sv @@ -78,4 +90,4 @@ sources: - target: cluster_standalone files: - include/pulp_interfaces.sv - + diff --git a/Makefile b/Makefile index 9990ecb9..c0272924 100644 --- a/Makefile +++ b/Makefile @@ -2,28 +2,42 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) +ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -GIT ?= git +QUESTA ?= BENDER ?= bender -VSIM ?= vsim -VLIB ?= vlib -VOPT ?= vopt + +VSIM ?= $(QUESTA) vsim +VOPT ?= $(QUESTA) vopt +VLIB ?= $(QUESTA) vlib top_level ?= pulp_cluster_tb library ?= work elf-bin ?= stimuli.riscv bwruntest = $(ROOT_DIR)/pulp-runtime/scripts/bwruntests.py -CFLAGS ?= -I$(QUESTASIM_HOME)/include \ - -I$(RISCV)/include/ \ - -I/include -std=c++11 -I../tb/dpi -O3 +REGRESSIONS := $(ROOT_DIR)/regression_tests VLOG_ARGS += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale \"1 ns / 1 ps\" \"+incdir+$(shell pwd)/include\" -XVLOG_ARGS += -64bit -compile -vtimescale 1ns/1ns -quiet + +bender_defs += -D FEATURE_ICACHE_STAT +bender_defs += -D PRIVATE_ICACHE +bender_defs += -D HIERARCHY_ICACHE_32BIT +bender_defs += -D ICAHE_USE_FF +bender_defs += -D TRACE_EXECUTION +bender_defs += -D CLUSTER_ALIAS +bender_defs += -D USE_PULP_PARAMETERS +bender_defs += -D SNITCH_ICACHE + +bender_targs += -t rtl +bender_targs += -t test +bender_targs += -t mchan +bender_targs += -t cluster_standalone +bender_targs += -t scm_use_fpga_scm +bender_targs += -t cv32e40p_use_ff_regfile define generate_vsim echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1 - bender script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 + $(BENDER) script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 echo >> $1 endef @@ -32,7 +46,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= ff679262d78198a3ff54ff91811d7395e83998db +NONFREE_COMMIT ?= 67079fe nonfree-init: git clone $(NONFREE_REMOTE) nonfree @@ -42,70 +56,94 @@ nonfree-init: # Dependencies # ################ +.PHONY: init + +init: checkout + .PHONY: checkout ## Checkout/update dependencies using Bender checkout: - bender checkout + $(BENDER) checkout touch Bender.lock make scripts/compile.tcl Bender.lock: - bender checkout + $(BENDER) checkout touch Bender.lock + ###### # SW # ###### +.PHONY: sw-init sw-clean + +sw-init: pulp-runtime fault_injection_sim regression_tests +sw-clean: + @rm -rf pulp-runtime fault_injection_sim regression_test + ## Clone pulp-runtime as SW stack +PULP_RUNTIME_REMOTE ?= https://github.com/pulp-platform/pulp-runtime.git +PULP_RUNTIME_COMMIT ?= a5bc02e # branch: upstream-features + pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git $@ - cd $@; git checkout 38ae6be6e28ff39f79218d333c41632a935bd584; cd .. + git clone $(PULP_RUNTIME_REMOTE) $@ + cd $@ && git checkout $(PULP_RUNTIME_COMMIT) -## Clone regression tests for bare-metal verification -regression-tests: - git clone https://github.com/pulp-platform/regression_tests.git $@ - cd $@; git checkout 7343d39bb9d1137b6eb3f2561777df546cd1e421; cd .. +## Clone fault injection scripts +FAULT_SIM_REMOTE ?= https://github.com/pulp-platform/InjectaFault.git +FAULT_SIM_COMMIT ?= 84ddcff # branch: rt/rename-var + +fault_injection_sim: + git clone $(FAULT_SIM_REMOTE) $@ + cd $@ && git checkout $(FAULT_SIM_COMMIT) + +## Clone regression tests +REGRESSION_TESTS_REMOTE ?= https://github.com/pulp-platform/regression_tests.git +REGRESSION_TESTS_COMMIT ?= 799c996 # branch: upstream-features + +regression_tests: + git clone $(REGRESSION_TESTS_REMOTE) $@ + cd $@ && git checkout $(REGRESSION_TESTS_COMMIT) + cd $@ && git submodule update --init --recursive ######################## # Build and simulation # ######################## +.PHONY: sim_clean compile build run + +$(BENDER): + curl --proto '=https' \ + --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.24.0 + mv bender $(BENDER) + sim_clean: rm -rf scripts/compile.tcl rm -rf work scripts/compile.tcl: | Bender.lock - $(call generate_vsim, $@, -t rtl -t test -t cluster_standalone,..) + $(call generate_vsim, $@, $(bender_defs) $(bender_targs),..) echo 'vlog "$(realpath $(ROOT_DIR))/tb/dpi/elfloader.cpp" -ccflags "-std=c++11"' >> $@ + echo 'vopt +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES $(top_level) -o $(top_level)_optimized' >> $@ $(library): - $(VLIB) $(library) + $(QUESTA) vlib $(library) -compile: $(library) scripts/compile.tcl +compile: $(library) @test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; } @test -f scripts/compile.tcl || { echo "ERROR: scripts/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; } - $(VSIM) -c -do 'source scripts/compile.tcl; quit' + $(VSIM) -c -do 'quit -code [source scripts/compile.tcl]' build: compile - $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized -debug - + $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc run: - $(VSIM) +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ + $(VSIM) +permissive $(questa-flags) $(uvm-flags) $(QUESTASIM_FLAGS) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log -.PHONY: test-rt-par-bare -## Run only parallel tests on pulp-runtime -test-rt-par-bare: pulp-runtime regression-tests - cd regression-tests && $(bwruntest) --proc-verbose -v \ - -t 3600 --yaml --max-procs 2 \ - -o runtime-parallel.xml parallel-bare-tests.yaml - +#################### +# Regression tests # +#################### -.PHONY: test-rt-mchan -## Run mchan tests on pulp-runtime -test-rt-mchan: pulp-runtime regression-tests - cd regression-tests && $(bwruntest) --proc-verbose -v \ - -t 3600 --yaml --max-procs 2 \ - -o runtime-mchan.xml pulp_cluster-mchan-tests.yaml +include regression.mk diff --git a/README.md b/README.md index 57f97422..42e29b31 100644 --- a/README.md +++ b/README.md @@ -28,26 +28,31 @@ Warning: requires QuestaSim 2022.3 or newer. RISCV GCC toolchain](https://github.com/pulp-platform/pulp-riscv-gcc) to use a pre-built release. (At IIS, this is set up by the env script in step 4.) -2. Compile the hw: +2. We need RV64 toolchain to compile DPI libraries. To this purpose, export the + RV64 toolchain to a `RISCV` env variable and also export your questa + installation path to a `QUESTASIM_HOME` env variable. Please refer to [RISC-V + GNU toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain/) to use a + pre-built RV64 toolchain release. + +3. Compile the hw: ``` make checkout make scripts/compile.tcl make build ``` -3. Download the sw stack and bare-metal tests: +4. Download the sw stack and bare-metal tests: ``` make pulp-runtime - make regression-tests + make regression_tests ``` -4. Source the environment: +5. Source the environment: ``` source env/env.sh ``` - (At IIS, this sets up a proper QuestaSim environment, and links the toolchain.) -5. Run the tests. Choose any test among the `parallel_bare_tests` and the +6. Run the tests. Choose any test among the `parallel_bare_tests` and the `mchan_tests`, move into the related folder and do: ``` diff --git a/env/astral-env.sh b/env/astral-env.sh new file mode 100644 index 00000000..582fef0c --- /dev/null +++ b/env/astral-env.sh @@ -0,0 +1,23 @@ +# Copyright 2023 ETH Zurich and University of Bologna +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# set up environment variables for rtl simulation, pulp-runtime and freertos +ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) + +# If at IIS, set up appropriate questa version. +if test -f /etc/iis.version; then + export QUESTA=questa-2023.4-zr +fi + +export QUESTA=questa-2023.4-zr +export VLOG="$QUESTA vlog" +export VLIB="$QUESTA vlib" +export VMAP="$QUESTA vmap" +export VCOM="$QUESTA vcom" +export VOPT="$QUESTA vopt" +export VSIM="$QUESTA vsim" +export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 + +source "$ROOTD/pulp-runtime/configs/astral-cluster.sh" +source "$ROOTD/scripts/vsim.sh" diff --git a/env/carfield-env.sh b/env/carfield-env.sh new file mode 100644 index 00000000..77db3c93 --- /dev/null +++ b/env/carfield-env.sh @@ -0,0 +1,23 @@ +# Copyright 2023 ETH Zurich and University of Bologna +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# set up environment variables for rtl simulation, pulp-runtime and freertos +ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) + +# If at IIS, set up appropriate questa version. +if test -f /etc/iis.version; then + export QUESTA=questa-2023.4-zr +fi + +export QUESTA=questa-2023.4-zr +export VLOG="$QUESTA vlog" +export VLIB="$QUESTA vlib" +export VMAP="$QUESTA vmap" +export VCOM="$QUESTA vcom" +export VOPT="$QUESTA vopt" +export VSIM="$QUESTA vsim" +export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 + +source "$ROOTD/pulp-runtime/configs/carfield-cluster.sh" +source "$ROOTD/scripts/vsim.sh" diff --git a/env/env.sh b/env/env.sh index 28c3ce75..5407d4ec 100644 --- a/env/env.sh +++ b/env/env.sh @@ -8,16 +8,15 @@ ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) # If at IIS, set up appropriate questa version. if test -f /etc/iis.version; then export QUESTA=questa-2023.4-zr - export VLOG="$QUESTA vlog" - export VLIB="$QUESTA vlib" - export VMAP="$QUESTA vmap" - export VCOM="$QUESTA vcom" - export VOPT="$QUESTA vopt" - export VSIM="$QUESTA vsim" - export QUESTA_HOME=/usr/pack/${QUESTA}/questasim - export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim - export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 fi +export VLOG="$QUESTA vlog" +export VLIB="$QUESTA vlib" +export VMAP="$QUESTA vmap" +export VCOM="$QUESTA vcom" +export VOPT="$QUESTA vopt" +export VSIM="$QUESTA vsim" +export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 + source "$ROOTD/pulp-runtime/configs/pulp_cluster.sh" source "$ROOTD/scripts/vsim.sh" diff --git a/include/cluster_bus_defines.sv b/include/cluster_bus_defines.sv index 9306c090..487e2629 100644 --- a/include/cluster_bus_defines.sv +++ b/include/cluster_bus_defines.sv @@ -26,7 +26,7 @@ `define MASTER_1_START_ADDR 32'h1020_0000 `define MASTER_1_END_ADDR 32'h103F_FFFF -`define TCDM_ASSIGN_MASTER(lhs, rhs) \ +`define TCDM_ASSIGN_MASTER(lhs, rhs) \ assign lhs.req = rhs.req; \ assign lhs.add = rhs.add; \ assign lhs.wen = rhs.wen; \ diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 49d9ad3d..965fef4a 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -22,7 +22,6 @@ `define CLUSTER_ALIAS `define PRIVATE_ICACHE `define HIERARCHY_ICACHE_32BIT -`define SHARED_FPU_CLUSTER `define FEATURE_ICACHE_STAT `define FC_FPU 1 @@ -34,6 +33,11 @@ `define CLUST_FP_DIVSQRT 0 `define CLUST_SHARED_FP 0 `define CLUST_SHARED_FP_DIVSQRT 0 +`elsif NO_FPU + `define CLUST_FPU 0 + `define CLUST_FP_DIVSQRT 0 + `define CLUST_SHARED_FP 0 + `define CLUST_SHARED_FP_DIVSQRT 0 `else `define CLUST_FPU 1 `define CLUST_FP_DIVSQRT 1 @@ -46,4 +50,4 @@ `define NB_CORES 8 `define NB_DMAS 4 `define NB_MPERIPHS 1 -`define NB_SPERIPHS 10 +`define NB_SPERIPHS 12 diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 685a3bda..689148e8 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -15,45 +15,275 @@ */ package pulp_cluster_package; - - typedef struct packed { - logic [31:0] idx; - logic [31:0] start_addr; - logic [31:0] end_addr; - } addr_map_rule_t; + import rapid_recovery_pkg::*; + + typedef bit [ 7:0] byte_t; + typedef bit [12:0] alias_t; + typedef bit [31:0] word_t; + typedef bit [63:0] doub_t; + + // Core type + typedef enum logic[1:0] { + CV32, + RISCY, + IBEX + } core_type_e; + + // HWPE type + typedef enum byte_t { + REDMULE, + NEUREKA, + SOFTEX + } hwpe_type_e; + + localparam int unsigned MAX_NUM_HWPES = 8; - parameter NB_SPERIPH_PLUGS_EU = 2; + typedef struct packed { + hwpe_type_e [MAX_NUM_HWPES-1:0] HwpeList; + byte_t NumHwpes; + } hwpe_subsystem_cfg_t; + + // PULP cluster configuration + typedef struct packed { + // Type of core in the cluster + core_type_e CoreType; + // Number of cores in the cluster + byte_t NumCores; + // Number of DMA TCDM plugs + byte_t DmaNumPlugs; + // Number of DMA outstanding transactions + byte_t DmaNumOutstandingBursts; + // DMA burst length in bits + word_t DmaBurstLength; + // Number of masters in crossbar peripherals + byte_t NumMstPeriphs; + // Number of slaves in crossbar peripherals + byte_t NumSlvPeriphs; + // Enable cluster aliasing + bit ClusterAlias; + // Base of the cluster alias + alias_t ClusterAliasBase; + // Number of internal synchronization stages + byte_t NumSyncStages; + // Enable HCI + bit UseHci; + // Size of the TCDM in bytes (power of two) + word_t TcdmSize; + // Number of TCDM banks (power of two) + byte_t TcdmNumBank; + // Enable HWPEs + bit HwpePresent; + // HWPEs selection and ID map + hwpe_subsystem_cfg_t HwpeCfg; + // Number of memory ports available for HWPEs + byte_t HwpeNumPorts; + // Enable the HMR Unit + bit HMRPresent; + // Enable triple modular redundancy + bit HMRTmrEnabled; + // Enable ECC + bit EnableECC; + // Enable ECC on the hci interconnect + bit ECCInterco; + // Number if I$ banks + byte_t iCacheNumBanks; + // Number of I$ lines + byte_t iCacheNumLines; + // Number of I$ ways + byte_t iCacheNumWays; // default is 4 + // Shared I$ size in bytes + word_t iCacheSharedSize; // default is 4096 + // Private I$ size in bytes + word_t iCachePrivateSize; // default is 521 + // Private I$ data width + byte_t iCachePrivateDataWidth; + // Enable reduced tag + bit EnableReducedTag; + // L2 size + word_t L2Size; + // Debug module base address + doub_t DmBaseAddr; + // BootROM base address + doub_t BootRomBaseAddr; + // Cores boot address + doub_t BootAddr; + // Enable private FPU + bit EnablePrivateFpu; + // Enable private FP division/sqrt + bit EnablePrivateFpDivSqrt; + // Enable shared FPUs + bit EnableSharedFpu; + // Enable shared FP division/sqrt + bit EnableSharedFpDivSqrt; + // Number of shared FPUs + byte_t NumSharedFpu; + // Number of AXI crossbar subordinate ports + byte_t NumAxiIn; + // Number of AXI crossbar manager ports + byte_t NumAxiOut; + // AXI ID width of crossbar subordinate ports + byte_t AxiIdInWidth; + // AXI ID width of crossbar manager ports + byte_t AxiIdOutWidth; + // AXI address width + byte_t AxiAddrWidth; + // AXI data width from external to cluster + byte_t AxiDataInWidth; + // AXI data width from cluster to external + byte_t AxiDataOutWidth; + // AXI user width + byte_t AxiUserWidth; + // AXI maximum subordinate transaction per ID + byte_t AxiMaxInTrans; + // AXI maximum manager transaction per ID + byte_t AxiMaxOutTrans; + // Log depth of AXI CDC FIFOs + byte_t AxiCdcLogDepth; // old LOG_DEPTH + // Sinchronization stages of AXI CDC FIFOs + byte_t AxiCdcSyncStages; + // Input synchronization stages + byte_t SyncStages; + // Cluster base address + doub_t ClusterBaseAddr; + // Cluster peripherals offset + doub_t ClusterPeriphOffs; + // Cluster base external offset + doub_t ClusterExternalOffs; + // Address remap for virtualization + bit EnableRemapAddress; + } pulp_cluster_cfg_t; + localparam int unsigned NB_SPERIPH_PLUGS_EU = 2; // number of master and slave cluster periphs - parameter NB_MPERIPHS = 1; - parameter NB_SPERIPHS = 10; + localparam int unsigned NB_MPERIPHS = 1; + localparam int unsigned NB_SPERIPHS = 12; // position of peripherals on slave port of periph interconnect - parameter SPER_EOC_ID = 0; - parameter SPER_TIMER_ID = 1; - parameter SPER_EVENT_U_ID = 2; - // 3 also used for Event Unit - parameter SPER_HWPE_ID = 4; - parameter SPER_ICACHE_CTRL = 5; - parameter SPER_DMA_CL_ID = 6; - parameter SPER_DMA_FC_ID = 7; - parameter SPER_DECOMP_ID = 8; // Currently unused / grounded, available for specific designs - parameter SPER_EXT_ID = 9; - parameter SPER_ERROR_ID = 10; - - // if set to 1, then instantiate APU in the cluster - // parameter APU_CLUSTER = 0; - - // // if set to 1, the 0x0000_0000 to 0x0040_0000 is the alias of the current cluster address space (eg cluster 0 is from 0x1000_0000 to 0x1040_0000) - // parameter CLUSTER_ALIAS = 1; - - // // if set to 1, the DEMUX peripherals (EU, MCHAN) are placed right before the test and set region. - // // This will steal 16KB from the 1MB TCDM reegion. - // // EU is mapped from 0x10100000 - 0x400 - // // MCHAN regs are mapped from 0x10100000 - 0x800 - // // remember to change the defines in the pulp.h as well to be coherent with this approach - // parameter DEM_PER_BEFORE_TCDM_TS = 0; + localparam int unsigned SPER_EOC_ID = 0; // 0x0000 - 0x0400 + localparam int unsigned SPER_TIMER_ID = 1; // 0x0400 - 0x0800 + localparam int unsigned SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000 + // 3 also used for Event Unit + localparam int unsigned SPER_HWPE_ID = 4; // 0x1000 - 0x1400 + localparam int unsigned SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800 + localparam int unsigned SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00 + localparam int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 + localparam int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 + localparam int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800 + localparam int unsigned SPER_HWPE_HCI_ECC_ID = 10; // 0x2800 - 0x3200 + localparam int unsigned SPER_EXT_ID = 11; // -> unmapped, directed to error + localparam int unsigned SPER_ERROR_ID = 12; // -> unmapped, directed to error + + // The following parameters refer to the cluster AXI crossbar + localparam byte_t NumAxiSubordinatePorts = 4; + localparam byte_t NumAxiManagerPorts = 3; + localparam byte_t AxiSubordinateIdwidth = 4; + localparam byte_t AxiManagerIdwidth = AxiSubordinateIdwidth + $clog2(NumAxiSubordinatePorts); + + localparam pulp_cluster_cfg_t PulpClusterDefaultCfg = '{ + CoreType: CV32, + NumCores: 8, + DmaNumPlugs: 4, + DmaNumOutstandingBursts: 8, + DmaBurstLength: 256, + NumMstPeriphs: NB_MPERIPHS, + NumSlvPeriphs: NB_SPERIPHS, + ClusterAlias: 1, + ClusterAliasBase: 'h0, + NumSyncStages: 3, + UseHci: 1, + TcdmSize: 64*1024, + TcdmNumBank: 16, + HwpePresent: 0, + HwpeCfg: '0, + HwpeNumPorts: 0, + HMRPresent: 0, + HMRTmrEnabled: 0, + EnableECC: 0, + ECCInterco: 0, + iCacheNumBanks: 2, + iCacheNumLines: 1, + iCacheNumWays: 4, + iCacheSharedSize: 4*1024, + iCachePrivateSize: 512, + iCachePrivateDataWidth: 32, + EnableReducedTag: 1, + L2Size: 1000*1024, + DmBaseAddr: 'h1A110000, + BootRomBaseAddr: 'h1A000000, + BootAddr: 'h1C000000, + EnablePrivateFpu: 1, + EnablePrivateFpDivSqrt: 0, + EnableSharedFpu: 0, + EnableSharedFpDivSqrt: 0, + NumSharedFpu: 0, + NumAxiIn: NumAxiSubordinatePorts, + NumAxiOut: NumAxiManagerPorts, + AxiIdInWidth: AxiSubordinateIdwidth, + AxiIdOutWidth:AxiManagerIdwidth, + AxiAddrWidth: 32, + AxiDataInWidth: 32, + AxiDataOutWidth: 32, + AxiUserWidth: 10, + AxiMaxInTrans: 64, + AxiMaxOutTrans: 64, + AxiCdcLogDepth: 3, + AxiCdcSyncStages: 3, + ClusterBaseAddr: 'h10000000, + ClusterPeriphOffs: 'h00200000, + ClusterExternalOffs: 'h00400000, + EnableRemapAddress: 0, + default: '0 + }; + + typedef struct packed { + logic gnt; + logic [31:0] r_data; + logic r_valid; + } core_data_rsp_t; + + typedef struct packed { + logic req; + logic [31:0] add; + logic we; + logic [31:0] data; + logic [3:0] be; + } core_data_req_t; + + typedef struct packed { + logic clock_en; + logic [31:0] boot_addr; + logic [3:0] core_id; + logic [5:0] cluster_id; + logic instr_gnt; + logic instr_rvalid; + logic [31:0] instr_rdata; + logic data_gnt; + logic data_rvalid; + logic [31:0] data_rdata; + logic irq_req; + logic [4:0] irq_id; + } core_inputs_t; + + typedef struct packed { + logic instr_req; + logic [31:0] instr_addr; + logic data_req; + logic data_we; + logic [3:0] data_be; + logic [31:0] data_add; + logic [31:0] data_wdata; + logic irq_ack; + logic [4:0] irq_ack_id; + logic debug_halted; + logic core_busy; + } core_outputs_t; + + typedef struct packed { + rapid_recovery_pkg::regfile_write_t regfile_backup; + rapid_recovery_pkg::csrs_intf_t csr_backup; + rapid_recovery_pkg::pc_intf_t pc_backup; + } core_backup_t; endpackage diff --git a/regression.mk b/regression.mk new file mode 100644 index 00000000..051e34f4 --- /dev/null +++ b/regression.mk @@ -0,0 +1,23 @@ +## Clone regression tests for bare-metal verification +TARGET ?= pulp_cluster + +.PHONY: test-rt-par-bare +## Run only parallel tests on pulp-runtime +test-rt-par-bare: pulp-runtime regression_tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 3600 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/$(TARGET)/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml + +.PHONY: test-rt-mchan +## Run mchan tests on pulp-runtime +test-rt-mchan: pulp-runtime regression_tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 7200 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/$(TARGET)/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml + +.PHONY: test-rt-$(TARGET) +## Run Carfield tests on pulp-runtime +test-rt-$(TARGET): pulp-runtime regression_tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 3600 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/$(TARGET)/runtime-mchan.xml $(REGRESSIONS)/$(TARGET).yaml diff --git a/rtl/axi2mem_wrap.sv b/rtl/axi2mem_wrap.sv index 1984f171..562b6500 100644 --- a/rtl/axi2mem_wrap.sv +++ b/rtl/axi2mem_wrap.sv @@ -27,13 +27,13 @@ module axi2mem_wrap parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - input axi_req_t axi_slave_req_i, - output axi_resp_t axi_slave_resp_o, - hci_core_intf.master tcdm_master[NB_DMAS-1:0], - output logic busy_o + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input axi_req_t axi_slave_req_i, + output axi_resp_t axi_slave_resp_o, + hci_core_intf.initiator tcdm_master[0:NB_DMAS-1], + output logic busy_o ); logic [NB_DMAS-1:0][31:0] s_tcdm_bus_wdata; @@ -52,8 +52,12 @@ module axi2mem_wrap assign tcdm_master[i].data = s_tcdm_bus_wdata[i]; assign tcdm_master[i].wen = s_tcdm_bus_wen[i]; assign tcdm_master[i].be = s_tcdm_bus_be[i]; - assign tcdm_master[i].boffs = '0; - assign tcdm_master[i].lrdy = '1; + assign tcdm_master[i].r_ready = '1; + assign tcdm_master[i].user = '0; + assign tcdm_master[i].ecc = '0; + assign tcdm_master[i].id = '0; + assign tcdm_master[i].ereq = '0; + assign tcdm_master[i].r_eready = '1; assign s_tcdm_bus_gnt[i] = tcdm_master[i].gnt; assign s_tcdm_bus_r_valid[i] = tcdm_master[i].r_valid; @@ -69,17 +73,16 @@ module axi2mem_wrap ) axi2mem_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - //.slave ( axi_slave ), - .tcdm_master_req_o ( s_tcdm_bus_req ), - .tcdm_master_add_o ( s_tcdm_bus_add ), - .tcdm_master_type_o ( s_tcdm_bus_wen ), - .tcdm_master_data_o ( s_tcdm_bus_wdata ), - .tcdm_master_be_o ( s_tcdm_bus_be ), + .tcdm_master_req_o ( s_tcdm_bus_req ), + .tcdm_master_add_o ( s_tcdm_bus_add ), + .tcdm_master_type_o ( s_tcdm_bus_wen ), + .tcdm_master_data_o ( s_tcdm_bus_wdata ), + .tcdm_master_be_o ( s_tcdm_bus_be ), .tcdm_master_gnt_i ( s_tcdm_bus_gnt ), .tcdm_master_r_valid_i ( s_tcdm_bus_r_valid ), - .tcdm_master_r_data_i ( s_tcdm_bus_r_rdata ), + .tcdm_master_r_data_i ( s_tcdm_bus_r_rdata ), .busy_o ( busy_o ), .test_en_i ( test_en_i ), diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 11f3d816..9c1d1245 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -17,36 +17,38 @@ */ -`include "cluster_bus_defines.sv" `include "axi/assign.svh" `include "axi/typedef.svh" - module cluster_bus_wrap import axi_pkg::xbar_cfg_t; - import pulp_cluster_package::addr_map_rule_t; #( - parameter int unsigned NB_CORES = 4 , - parameter int unsigned AXI_ADDR_WIDTH = 32, - parameter int unsigned AXI_DATA_WIDTH = 64, - parameter int unsigned AXI_ID_IN_WIDTH = 4 , - parameter int unsigned AXI_ID_OUT_WIDTH = 6 , - parameter int unsigned AXI_USER_WIDTH = 6 , - parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , - parameter int unsigned TCDM_SIZE = 0, - parameter type slave_req_t = logic, - parameter type slave_resp_t = logic, - parameter type master_req_t = logic, - parameter type master_resp_t = logic, - parameter type slave_aw_chan_t = logic, - parameter type master_aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type slave_b_chan_t = logic, - parameter type master_b_chan_t = logic, - parameter type slave_ar_chan_t = logic, - parameter type master_ar_chan_t = logic, - parameter type slave_r_chan_t = logic, - parameter type master_r_chan_t = logic + parameter int unsigned NB_MASTER = 3 , + parameter int unsigned NB_SLAVE = 4 , + parameter int unsigned NB_CORES = 4 , + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_ID_IN_WIDTH = 4 , + parameter int unsigned AXI_ID_OUT_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 6 , + parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , + parameter int unsigned TCDM_SIZE = 0, + parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, + parameter type slave_req_t = logic, + parameter type slave_resp_t = logic, + parameter type master_req_t = logic, + parameter type master_resp_t = logic, + parameter type slave_aw_chan_t = logic, + parameter type master_aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type slave_b_chan_t = logic, + parameter type master_b_chan_t = logic, + parameter type slave_ar_chan_t = logic, + parameter type master_ar_chan_t = logic, + parameter type slave_r_chan_t = logic, + parameter type master_r_chan_t = logic ) ( input logic clk_i, @@ -70,24 +72,17 @@ module cluster_bus_wrap input master_resp_t ext_master_resp_i ); - - localparam NB_MASTER = `NB_MASTER; - localparam NB_SLAVE = `NB_SLAVE; - - //Ensure that AXI_ID out width has the correct size with an elaboration system task if (AXI_ID_OUT_WIDTH < AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) $error("ID width of AXI output ports is to small. The output id width must be input ID width + clog2() which is %d but it was %d", AXI_ID_IN_WIDTH + $clog2(NB_SLAVE), AXI_ID_OUT_WIDTH); else if (AXI_ID_OUT_WIDTH > AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) $warning("ID width of the AXI output port has the wrong length. It is larger than the required value. Trim it to the right length to get rid of this warning."); - if (AXI_ADDR_WIDTH != 32) - $fatal(1,"Address map is only defined for 32-bit addresses!"); if (TCDM_SIZE == 0) $fatal(1,"TCDM size must be non-zero!"); - if (TCDM_SIZE >128*1024) + if (TCDM_SIZE >2048*1024) // Periph start address is at offset 0x0020_0000, which actually allows for up to 2 MiB of TCDM, + // do not know why to trigger te assertion for more than 128 KiB TCDM size... $fatal(1,"TCDM size exceeds available address space in cluster bus!"); - // Crossbar slave_req_t [NB_SLAVE-1:0] axi_slave_reqs; @@ -114,12 +109,18 @@ module cluster_bus_wrap `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, axi_master_reqs[2]) `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[2], ext_master_resp_i) - // address map - logic [31:0] cluster_base_addr; - assign cluster_base_addr = 32'h1000_0000 + ( cluster_id_i << 22); - localparam int unsigned N_RULES = 3; - pulp_cluster_package::addr_map_rule_t [N_RULES-1:0] addr_map; + // Address Map Rule + typedef struct packed { + logic [AXI_ADDR_WIDTH-1:0] idx ; + logic [AXI_ADDR_WIDTH-1:0] start_addr; + logic [AXI_ADDR_WIDTH-1:0] end_addr ; + } addr_map_rule_t; + // address map + logic [AXI_ADDR_WIDTH-1:0] cluster_base_addr; + assign cluster_base_addr = BaseAddr + ( cluster_id_i << 22); + localparam int unsigned N_RULES = 4; + addr_map_rule_t [N_RULES-1:0] addr_map; assign addr_map[0] = '{ // TCDM idx: 0, @@ -128,19 +129,23 @@ module cluster_bus_wrap }; assign addr_map[1] = '{ // Peripherals idx: 1, - start_addr: cluster_base_addr + 32'h0020_0000, - end_addr: cluster_base_addr + 32'h0040_0000 + start_addr: cluster_base_addr + ClusterPeripheralsOffs, + end_addr: cluster_base_addr + ClusterExternalOffs }; assign addr_map[2] = '{ // everything above cluster to ext_slave idx: 2, - start_addr: cluster_base_addr + 32'h0040_0000, + start_addr: cluster_base_addr + ClusterExternalOffs, end_addr: 32'hFFFF_FFFF }; + assign addr_map[3] = '{ // everything below cluster + idx: 2, + start_addr: 'h0, + end_addr: cluster_base_addr + }; localparam int unsigned MAX_TXNS_PER_SLV_PORT = (DMA_NB_OUTSND_BURSTS > NB_CORES) ? DMA_NB_OUTSND_BURSTS : NB_CORES; - localparam xbar_cfg_t AXI_XBAR_CFG = '{ NoSlvPorts: NB_SLAVE, NoMstPorts: NB_MASTER, diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index d8921b39..51b5dd15 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -13,46 +13,56 @@ * (http://www.pulp-platform.org), under the copyright of ETH Zurich and the * University of Bologna. */ - -`include "pulp_soc_defines.sv" + +`include "hci_helpers.svh" import hci_package::*; module cluster_interconnect_wrap #( - parameter int unsigned NB_CORES = 8, - parameter int unsigned HWPE_PRESENT = 1, - parameter int unsigned NB_HWPE_PORTS = 4, - parameter int unsigned NB_DMAS = 4, - parameter int unsigned NB_MPERIPHS = 1, - parameter int unsigned NB_TCDM_BANKS = 16, - parameter int unsigned NB_SPERIPHS = 8, //differ - - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned ADDR_WIDTH = 32, - parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter int unsigned NB_CORES = 8, + parameter int unsigned HWPE_PRESENT = 1, + parameter int unsigned NB_HWPE_PORTS = 9, + parameter int unsigned NB_DMAS = 4, + parameter int unsigned NB_MPERIPHS = 1, + parameter int unsigned NB_TCDM_BANKS = 16, + parameter int unsigned NB_SPERIPHS = 10, //differ + + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, //TCDM PARAMETERS - parameter int unsigned TEST_SET_BIT = 20, - parameter int unsigned ADDR_MEM_WIDTH = 11, - parameter int unsigned LOG_CLUSTER = 5, - parameter int unsigned PE_ROUTING_LSB = 16, - parameter int unsigned PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ - parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, - - parameter bit USE_HETEROGENEOUS_INTERCONNECT = 1 + parameter int unsigned TEST_SET_BIT = 20, + parameter int unsigned ADDR_MEM_WIDTH = 11, + parameter int unsigned LOG_CLUSTER = 5, + parameter int unsigned PE_ROUTING_LSB = 10, + parameter int unsigned PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ + parameter int unsigned CLUSTER_ALIAS = 1, + parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000, + + parameter int unsigned USE_HETEROGENEOUS_INTERCONNECT = 1, + parameter int unsigned USE_ECC_INTERCONNECT = 0, + parameter hci_package::hci_size_parameter_t HCI_CORE_SIZE = '0, + parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0, + parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0 ) ( input logic clk_i, input logic rst_ni, - hci_core_intf.slave core_tcdm_slave [NB_CORES-1:0], - hci_core_intf.slave hwpe_tcdm_slave [0:0], - XBAR_PERIPH_BUS.Slave core_periph_slave[NB_CORES-1:0], - hci_core_intf.slave ext_slave [3:0], - hci_core_intf.slave dma_slave [NB_DMAS-1:0], //FIXME IGOR --> check NB_CORES depend ASK DAVIDE - XBAR_TCDM_BUS.Slave mperiph_slave[NB_MPERIPHS-1:0], - hci_mem_intf.master tcdm_sram_master[NB_TCDM_BANKS-1:0], - XBAR_PERIPH_BUS.Master speriph_master[NB_SPERIPHS-1:0], + input logic [5:0] cluster_id_i, + XBAR_PERIPH_BUS.Slave hci_ecc_periph_slave, + hci_core_intf.target core_tcdm_slave [0 : NB_CORES-1 ], + hci_core_intf.target hwpe_tcdm_slave [0 : 0 ], + XBAR_PERIPH_BUS.Slave core_periph_slave [NB_CORES-1 : 0 ], + hci_core_intf.target ext_slave [0 : 3 ], + hci_core_intf.target dma_slave [0 : NB_DMAS-1 ], + XBAR_TCDM_BUS.Slave mperiph_slave [NB_MPERIPHS-1 : 0 ], + hci_core_intf.initiator tcdm_sram_master [0 : NB_TCDM_BANKS-1], + XBAR_PERIPH_BUS.Master speriph_master [NB_SPERIPHS-1 : 0 ], input hci_interconnect_ctrl_t hci_ctrl_i, input logic [1:0] TCDM_arb_policy_i ); @@ -66,67 +76,108 @@ module cluster_interconnect_wrap // Wraps the Logarithmic Interconnect + a HWPE Interconnect generate if( USE_HETEROGENEOUS_INTERCONNECT || !HWPE_PRESENT ) begin : hci_gen + if (USE_ECC_INTERCONNECT) begin : gen_ecc_interco + hci_ecc_interconnect #( + .N_HWPE ( HWPE_PRESENT ), + .N_CORE ( NB_CORES ), + .N_DMA ( NB_DMAS ), + .N_EXT ( 4 ), + .N_MEM ( NB_TCDM_BANKS ), + .IW ( TCDM_ID_WIDTH ), + .TS_BIT ( TEST_SET_BIT ), + //For an explanation of these macros refer to https://github.com/pulp-platform/hci/blob/v2.1.1/rtl/common/hci_helpers.svh + .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ), + .`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ), + .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) + `ifndef SYNTHESIS + , + .WAIVE_RQ3_ASSERT ( 1'b1 ), + .WAIVE_RQ4_ASSERT ( 1'b1 ), + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) + `endif + ) i_hci_interconnect ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( 1'b0 ), + .ctrl_i ( hci_ctrl_i ), + .periph_hci_ecc ( hci_ecc_periph_slave ), + .cores ( core_tcdm_slave ), + .hwpe ( hwpe_tcdm_slave [0] ), + .dma ( dma_slave ), + .ext ( ext_slave ), + .mems ( tcdm_sram_master ) + ); + end else begin : gen_standard_interco + hci_interconnect #( + .N_HWPE ( HWPE_PRESENT ), + .N_CORE ( NB_CORES ), + .N_DMA ( NB_DMAS ), + .N_EXT ( 4 ), + .N_MEM ( NB_TCDM_BANKS ), + .IW ( TCDM_ID_WIDTH ), + .TS_BIT ( TEST_SET_BIT ), + .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ), + .`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ), + .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) + `ifndef SYNTHESIS + , + .WAIVE_RQ3_ASSERT ( 1'b1 ), + .WAIVE_RQ4_ASSERT ( 1'b1 ), + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) + `endif + ) i_hci_interconnect ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( 1'b0 ), + .ctrl_i ( hci_ctrl_i ), + .cores ( core_tcdm_slave ), + .hwpe ( hwpe_tcdm_slave [0] ), + .dma ( dma_slave ), + .ext ( ext_slave ), + .mems ( tcdm_sram_master ) + ); - hci_interconnect #( - .N_HWPE ( HWPE_PRESENT ), - .N_CORE ( NB_CORES ), - .N_DMA ( NB_DMAS ), - .N_EXT ( 4 ), - .N_MEM ( NB_TCDM_BANKS ), - .IW ( TCDM_ID_WIDTH ), - .AWC ( ADDR_WIDTH ), - .DW_LIC ( DATA_WIDTH ), - .DW_SIC ( NB_HWPE_PORTS*DATA_WIDTH ), - .TS_BIT ( TEST_SET_BIT ), - .AWH ( ADDR_WIDTH ), - .DWH ( NB_HWPE_PORTS*DATA_WIDTH ), - .OWH ( 1 ), - .AWM ( ADDR_MEM_WIDTH+2 ) - ) i_hci_interconnect ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i( 1'b0 ), - .ctrl_i ( hci_ctrl_i ), - .cores ( core_tcdm_slave ), - .hwpe ( hwpe_tcdm_slave [0] ), - .dma ( dma_slave ), - .ext ( ext_slave ), - .mems ( tcdm_sram_master ) - ); + assign hci_ecc_periph_slave.gnt = '0; + assign hci_ecc_periph_slave.r_rdata = '0; + assign hci_ecc_periph_slave.r_opc = '0; + assign hci_ecc_periph_slave.r_id = '0; + assign hci_ecc_periph_slave.r_valid = '0; + end end else begin : no_hci_gen hci_core_intf #( .DW ( 32 ), - .AW ( 32 ), - .OW ( 1 ) - ) core_hwpe_tcdm_slave [NB_CORES+NB_HWPE_PORTS-1:0] ( + .AW ( 32 ) + ) core_hwpe_tcdm_slave [0:NB_CORES+NB_HWPE_PORTS-1] ( .clk ( clk_i ) ); hci_core_intf #( .DW ( NB_HWPE_PORTS*32 ), - .AW ( 32 ), - .OW ( 1 ) + .AW ( 32 ) ) null_hwpe_tcdm_slave ( .clk ( clk_i ) ); hci_core_split #( - .DW ( NB_HWPE_PORTS*32 ), - .NB_OUT_CHAN ( NB_HWPE_PORTS ) + .DW ( NB_HWPE_PORTS*32 ), + .NB_OUT_CHAN ( NB_HWPE_PORTS ), + .`HCI_SIZE_PARAM(tcdm_target) ( HCI_HWPE_SIZE ) ) i_hwpe_tcdm_splitter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear_i ), - .tcdm_slave ( hwpe_tcdm_slave[0] ), - .tcdm_master ( core_hwpe_tcdm_slave[NB_CORES+NB_HWPE_PORTS-1:NB_CORES] ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .tcdm_target ( hwpe_tcdm_slave[0] ), + .tcdm_initiator ( core_hwpe_tcdm_slave[NB_CORES:NB_CORES+NB_HWPE_PORTS-1] ) ); for(genvar ii=0; ii */ -import pulp_cluster_package::*; +`include "register_interface/typedef.svh" -`include "pulp_soc_defines.sv" - -module cluster_peripherals +module cluster_peripherals + import pulp_cluster_package::*; #( - parameter int unsigned NB_CORES = 8, - parameter int unsigned NB_MPERIPHS = 1, - parameter int unsigned NB_CACHE_BANKS = 4, - parameter int unsigned NB_SPERIPHS = 8, - parameter int unsigned NB_TCDM_BANKS = 8, - parameter bit [31:0] ROM_BOOT_ADDR = 32'h1A000000, - parameter bit [31:0] BOOT_ADDR = 32'h1C000000, - parameter int unsigned EVNT_WIDTH = 8, - parameter int unsigned FEATURE_DEMUX_MAPPED = 1, - parameter int unsigned NB_L1_CUTS = 16, - parameter int unsigned RW_MARGIN_WIDTH = 4 + parameter int unsigned NB_CORES = 8, + parameter int unsigned NB_HWPES = 8, + parameter int unsigned NB_MPERIPHS = 1, + parameter int unsigned NB_CACHE_BANKS = 4, + parameter int unsigned NB_SPERIPHS = 8, + parameter int unsigned NB_TCDM_BANKS = 8, + parameter int unsigned ROM_BOOT_ADDR = 32'h1A000000, + parameter int unsigned BOOT_ADDR = 32'h1C000000, + parameter int unsigned EVNT_WIDTH = 8, + parameter int unsigned FEATURE_DEMUX_MAPPED = 1, + parameter int unsigned NB_L1_CUTS = 16, + parameter int unsigned RW_MARGIN_WIDTH = 4, + parameter int unsigned NB_BARRIERS = NB_CORES ) ( input logic clk_i, @@ -52,23 +53,23 @@ module cluster_peripherals output logic busy_o, - XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], // SPER_EXT_ID NOT PLUGGED HERE + XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], // SPER_EXT_ID NOT PLUGGED HERE XBAR_PERIPH_BUS.Slave core_eu_direct_link[NB_CORES-1:0], input logic [NB_CORES-1:0] dma_event_i, input logic [NB_CORES-1:0] dma_irq_i, + input logic mbox_irq_i, XBAR_PERIPH_BUS.Master dma_cfg_master[1:0], input logic dma_cl_event_i, input logic dma_cl_irq_i, - input logic dma_fc_event_i, input logic dma_fc_irq_i, - + output logic soc_periph_evt_ready_o, input logic soc_periph_evt_valid_i, input logic [EVNT_WIDTH-1:0] soc_periph_evt_data_i, - + input logic [NB_CORES-1:0] dbg_core_halted_i, output logic [NB_CORES-1:0] dbg_core_halt_o, @@ -84,34 +85,46 @@ module cluster_peripherals input logic [NB_CORES-1:0] dbg_req_i, output logic [NB_CORES-1:0] dbg_req_o, + output logic [NB_BARRIERS-1:0] barrier_matched_o, + + // HMR synch requests + input logic [NB_CORES-1:0] hmr_sw_resynch_req_i, + input logic [NB_CORES-1:0] hmr_sw_synch_req_i, // SRAM SPEED REGULATION --> TCDM output logic [1:0] TCDM_arb_policy_o, - + XBAR_PERIPH_BUS.Master hwpe_cfg_master, + XBAR_PERIPH_BUS.Master hmr_cfg_master, + XBAR_PERIPH_BUS.Master tcdm_scrubber_cfg_master, + XBAR_PERIPH_BUS.Master hwpe_hci_ecc_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, + output logic [$clog2(NB_HWPES)-1:0] hwpe_sel_o, output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports - SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS], - PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES], - output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o + SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0], + PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], + output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o, + output logic [NB_CORES-1:0] flush_valid_o, + input logic [NB_CORES-1:0] flush_ready_i, + input snitch_icache_pkg::icache_l1_events_t l1_events_i ); - + logic s_timer_out_lo_event; logic s_timer_out_hi_event; logic s_timer_in_lo_event; logic s_timer_in_hi_event; - + logic [NB_CORES-1:0][31:0] s_cluster_events; logic [NB_CORES-1:0][3:0] s_acc_events; logic [NB_CORES-1:0][1:0] s_timer_events; logic [NB_CORES-1:0][1:0] s_dma_events; - + logic [NB_CORES-1:0] s_fetch_en_cc; - MESSAGE_BUS eu_message_master(); + MESSAGE_BUS eu_message_master(); logic [NB_SPERIPH_PLUGS_EU-1:0] eu_speriph_plug_req; logic [NB_SPERIPH_PLUGS_EU-1:0][31:0] eu_speriph_plug_add; @@ -122,7 +135,7 @@ module cluster_peripherals logic soc_periph_evt_valid, soc_periph_evt_ready; logic [7:0] soc_periph_evt_data; - + // internal speriph bus to combine multiple plugs to new event unit XBAR_PERIPH_BUS speriph_slave_eu_comb(); @@ -131,18 +144,21 @@ module cluster_peripherals `else localparam bit FEATURE_STAT = 1'b0; `endif - + // decide between common or core-specific event sources generate for (genvar I=0; I target +assign tcdm_bus_mst_o.req = tcdm_bus_mst_req; +assign tcdm_bus_mst_o.add = tcdm_bus_mst_add; +assign tcdm_bus_mst_o.wen = tcdm_bus_mst_wen; +assign tcdm_bus_mst_o.data = tcdm_bus_mst_wdata; +assign tcdm_bus_mst_o.be = tcdm_bus_mst_be; +// bidings target -> initiator +assign tcdm_bus_mst_gnt = tcdm_bus_mst_o.gnt; +assign tcdm_bus_mst_r_valid = tcdm_bus_mst_o.r_valid; +assign tcdm_bus_mst_r_rdata = tcdm_bus_mst_o.r_data; + +// ties initiator -> target +assign tcdm_bus_mst_o.r_ready = '1; +assign tcdm_bus_mst_o.user = '0; +assign tcdm_bus_mst_o.id = '0; +assign tcdm_bus_mst_o.ecc = '0; +assign tcdm_bus_mst_o.ereq = '0; +assign tcdm_bus_mst_o.r_eready = '1; + +data_periph_demux #( + .ADDR_WIDTH ( AddrWidth ), + .DATA_WIDTH ( DataWidth ), + .BYTE_ENABLE_BIT ( ByteEnable ), + .REMAP_ADDRESS ( RemapAddress ), + .CLUSTER_ALIAS ( ClustAlias ), + .CLUSTER_ALIAS_BASE ( ClustAliasBase ) +) data_periph_demux_i ( + .clk ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + .base_addr_i ( base_addr_i ), + .data_req_i ( core_data_req_i.req ), + .data_add_i ( core_data_req_i.add ), + .data_wen_i ( ~core_data_req_i.we ), //inverted when using OR10N + .data_wdata_i ( core_data_req_i.data ), + .data_be_i ( core_data_req_i.be ), + .data_gnt_o ( core_data_rsp_o.gnt ), + .data_r_valid_o ( core_data_rsp_o.r_valid ), + .data_r_opc_o ( /* ucnconnected */ ), + .data_r_rdata_o ( core_data_rsp_o.r_data ), + + .data_req_o_SH ( tcdm_bus_mst_req ), + .data_add_o_SH ( tcdm_bus_mst_add ), + .data_wen_o_SH ( tcdm_bus_mst_wen ), + .data_wdata_o_SH ( tcdm_bus_mst_wdata ), + .data_be_o_SH ( tcdm_bus_mst_be ), + .data_gnt_i_SH ( tcdm_bus_mst_gnt ), + .data_r_valid_i_SH ( tcdm_bus_mst_r_valid ), + .data_r_rdata_i_SH ( tcdm_bus_mst_r_rdata ), + + .data_req_o_EXT ( periph_demux_bus.req ), + .data_add_o_EXT ( periph_demux_bus.add ), + .data_wen_o_EXT ( periph_demux_bus.wen ), + .data_wdata_o_EXT ( periph_demux_bus.wdata ), + .data_be_o_EXT ( periph_demux_bus.be ), + .data_gnt_i_EXT ( periph_demux_bus.gnt ), + .data_r_valid_i_EXT ( periph_demux_bus.r_valid ), + .data_r_rdata_i_EXT ( periph_demux_bus.r_rdata ), + .data_r_opc_i_EXT ( periph_demux_bus.r_opc ), + + .data_req_o_PE ( peripheral_bus_mst_o.req ), + .data_add_o_PE ( peripheral_bus_mst_o.add ), + .data_wen_o_PE ( peripheral_bus_mst_o.wen ), + .data_wdata_o_PE ( peripheral_bus_mst_o.wdata ), + .data_be_o_PE ( peripheral_bus_mst_o.be ), + .data_gnt_i_PE ( peripheral_bus_mst_o.gnt ), + .data_r_valid_i_PE ( peripheral_bus_mst_o.r_valid ), + .data_r_rdata_i_PE ( peripheral_bus_mst_o.r_rdata ), + .data_r_opc_i_PE ( peripheral_bus_mst_o.r_opc ), + + .perf_l2_ld_o ( ext_perf_o [0] ), + .perf_l2_st_o ( ext_perf_o [1] ), + .perf_l2_ld_cyc_o ( ext_perf_o [2] ), + .perf_l2_st_cyc_o ( ext_perf_o [3] ), + .CLUSTER_ID ( cluster_id_i ) +); + +assign ext_perf_o[4] = '0; + +assign periph_demux_bus.id = '0; + +assign dma_ctrl_mst_o.r_ready = '1; +assign dma_ctrl_mst_o.user = '0; +assign dma_ctrl_mst_o.id = '0; +assign dma_ctrl_mst_o.ecc = '0; +assign dma_ctrl_mst_o.ereq = '0; +assign dma_ctrl_mst_o.r_eready = '1; + +periph_demux +periph_demux_i ( + .clk ( clk_i ), + .rst_ni ( rst_ni ), + + .data_req_i ( periph_demux_bus.req ), + .data_add_i ( periph_demux_bus.add ), + .data_wen_i ( periph_demux_bus.wen ), + .data_wdata_i ( periph_demux_bus.wdata ), + .data_be_i ( periph_demux_bus.be ), + .data_gnt_o ( periph_demux_bus.gnt ), + .data_r_valid_o ( periph_demux_bus.r_valid ), + .data_r_opc_o ( periph_demux_bus.r_opc ), + .data_r_rdata_o ( periph_demux_bus.r_rdata ), + + .data_req_o_MH ( dma_ctrl_mst_o.req ), + .data_add_o_MH ( dma_ctrl_mst_o.add ), + .data_wen_o_MH ( dma_ctrl_mst_o.wen ), + .data_wdata_o_MH ( dma_ctrl_mst_o.data ), + .data_be_o_MH ( dma_ctrl_mst_o.be ), + .data_gnt_i_MH ( dma_ctrl_mst_o.gnt ), + .data_r_valid_i_MH ( dma_ctrl_mst_o.r_valid ), + .data_r_rdata_i_MH ( dma_ctrl_mst_o.r_data ), + .data_r_opc_i_MH ( dma_ctrl_mst_o.r_opc ), + + .data_req_o_EU ( eventunit_bus_mst_o.req ), + .data_add_o_EU ( eventunit_bus_mst_o.add ), + .data_wen_o_EU ( eventunit_bus_mst_o.wen ), + .data_wdata_o_EU ( eventunit_bus_mst_o.wdata ), + .data_be_o_EU ( eventunit_bus_mst_o.be ), + .data_gnt_i_EU ( eventunit_bus_mst_o.gnt ), + .data_r_valid_i_EU ( eventunit_bus_mst_o.r_valid ), + .data_r_rdata_i_EU ( eventunit_bus_mst_o.r_rdata ), + .data_r_opc_i_EU ( eventunit_bus_mst_o.r_opc ) +); + +endmodule: core_demux_wrap diff --git a/rtl/core_region.sv b/rtl/core_region.sv index dce0b22f..b7ba08b8 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -16,10 +16,6 @@ * Francesco Conti */ -`include "pulp_soc_defines.sv" -`include "periph_bus_defines.sv" - - // USER DEFINED MACROS to improve self-testing capabilities `ifndef PULP_FPGA_SIM `define DEBUG_FETCH_INTERFACE @@ -28,42 +24,44 @@ //`define DUMP_INSTR_FETCH module core_region +import rapid_recovery_pkg::*; #( // CORE PARAMETERS - parameter int unsigned CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - // parameter bit USE_FPU = 1, - // parameter bit USE_HWPE = 1, - parameter int unsigned N_EXT_PERF_COUNTERS = 1, - parameter int unsigned CORE_ID = 0, - parameter int unsigned ADDR_WIDTH = 32, - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned INSTR_RDATA_WIDTH = 32, - parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, - parameter int unsigned REMAP_ADDRESS = 0, - - parameter int unsigned APU_NARGS_CPU = 2, - parameter int unsigned APU_WOP_CPU = 1, - parameter int unsigned WAPUTYPE = 3, - parameter int unsigned APU_NDSFLAGS_CPU = 3, - parameter int unsigned APU_NUSFLAGS_CPU = 5, - - parameter int unsigned FPU = 0, - parameter int unsigned FP_DIVSQRT = 0, - parameter int unsigned SHARED_FP = 0, - parameter int unsigned SHARED_FP_DIVSQRT = 0, - - parameter bit [31:0] DEBUG_START_ADDR = `DEBUG_START_ADDR, - - parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", - parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" + parameter int unsigned CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC + parameter int unsigned N_EXT_PERF_COUNTERS = 1, + parameter int unsigned NUM_INTERRUPTS = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned INSTR_RDATA_WIDTH = 32, + parameter int unsigned CLUSTER_ALIAS = 1, + parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000, + parameter int unsigned REMAP_ADDRESS = 0, + + parameter int unsigned APU_NARGS_CPU = 2, + parameter int unsigned APU_WOP_CPU = 1, + parameter int unsigned WAPUTYPE = 3, + parameter int unsigned APU_NDSFLAGS_CPU = 3, + parameter int unsigned APU_NUSFLAGS_CPU = 5, + + parameter int unsigned FPU = 0, + parameter int unsigned FP_DIVSQRT = 0, + parameter int unsigned SHARED_FP = 0, + parameter int unsigned SHARED_FP_DIVSQRT = 0, + + parameter int unsigned DEBUG_START_ADDR = 32'h1A110000, + + parameter type core_data_req_t = logic, + parameter type core_data_rsp_t = logic, + + parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", + parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" ) ( input logic clk_i, input logic rst_ni, - input logic init_ni, - - input logic [3:0] base_addr_i, // FOR CLUSTER VIRTUALIZATION + input logic setback_i, + input logic [3:0] core_id_i, input logic [5:0] cluster_id_i, input logic irq_req_i, @@ -73,7 +71,6 @@ module core_region input logic clock_en_i, input logic fetch_en_i, - input logic fregfile_disable_i, input logic [31:0] boot_addr_i, @@ -89,22 +86,20 @@ module core_region input logic instr_r_valid_i, input logic debug_req_i, - - //XBAR_TCDM_BUS.Slave debug_bus, - //output logic debug_core_halted_o, - //input logic debug_core_halt_i, - //input logic debug_core_resume_i, - - // Interface for DEMUX to TCDM INTERCONNECT ,PERIPHERAL INTERCONNECT and DMA CONTROLLER - hci_core_intf.master tcdm_data_master, - XBAR_TCDM_BUS.Master dma_ctrl_master, - XBAR_PERIPH_BUS.Master eu_ctrl_master, - XBAR_PERIPH_BUS.Master periph_data_master - - // new interface signals - `ifdef SHARED_FPU_CLUSTER - // TODO: Ensure disable if CORE_TYPE_CL != 0 - , + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + // Recovery bus + input rapid_recovery_pkg::rapid_recovery_t recovery_bus_i, + // Backup bus + output rapid_recovery_pkg::regfile_write_t regfile_backup_o, + output rapid_recovery_pkg::pc_intf_t pc_backup_o, + output rapid_recovery_pkg::csrs_intf_t csr_backup_o, + + input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_i, + + output core_data_req_t core_data_req_o, + input core_data_rsp_t core_data_rsp_i, output logic apu_master_req_o, input logic apu_master_gnt_i, // request channel @@ -117,29 +112,8 @@ module core_region input logic apu_master_valid_i, input logic [31:0] apu_master_result_i, input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i -`endif - -`ifdef APU_CLUSTER - // TODO: Ensure disable if CORE_TYPE_CL != 0 - , - output logic apu_master_req_o, - input logic apu_master_gnt_i, - // request channel - output logic [WAPUTYPE-1:0] apu_master_type_o, - output logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o, - output logic [APU_WOP_CPU-1:0] apu_master_op_o, - output logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o, - // response channel - output logic apu_master_ready_o, - input logic apu_master_valid_i, - input logic [31:0] apu_master_result_i, - input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i -`endif - - ); - localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; localparam USE_IBEX = CORE_TYPE_CL == 1 || CORE_TYPE_CL == 2; localparam IBEX_RV32M = CORE_TYPE_CL == 1 ? ibex_pkg::RV32MSingleCycle : ibex_pkg::RV32MNone; localparam IBEX_RV32E = CORE_TYPE_CL == 2; @@ -155,16 +129,10 @@ module core_region //******************************************************** //***************** SIGNALS DECLARATION ****************** //******************************************************** - - XBAR_DEMUX_BUS s_core_bus(); // Internal interface between CORE <--> DEMUX - XBAR_PERIPH_BUS periph_demux_bus(); // Internal interface between CORE_DEMUX <--> PERIPHERAL DEMUX - - logic [N_EXT_PERF_COUNTERS_ACTUAL-1:0] perf_counters; - logic clk_int; - logic [31:0] hart_id; - logic core_sleep; - logic [31:0] boot_addr; - logic [31:0] core_irq_x; + logic [31:0] hart_id; + logic core_sleep; + logic [31:0] boot_addr; + logic [NUM_INTERRUPTS-1:0] core_irq_x; logic core_instr_req; logic core_instr_gnt; @@ -174,117 +142,215 @@ module core_region logic core_mem_req; - // clock gate of the core_region less the core itself - cluster_clock_gating clock_gate_i ( - .clk_i ( clk_i ), - .en_i ( clock_en_i ), - .test_en_i ( test_mode_i ), - .clk_o ( clk_int ) - ); - - assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, CORE_ID[3:0]}; - -`ifndef APU_CLUSTER - `ifndef SHARED_FPU_CLUSTER - // TODO: Disable if CORE_TYPE_CL != 0 - logic apu_master_req_o; - logic apu_master_gnt_i; - // request channel - logic [WAPUTYPE-1:0] apu_master_type_o; - logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o; - logic [APU_WOP_CPU-1:0] apu_master_op_o; - logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o; - // response channel - logic apu_master_ready_o; - logic apu_master_valid_i; - logic [31:0] apu_master_result_i; - logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i; - - assign apu_master_gnt_i = '1; - assign apu_master_valid_i = '0; - assign apu_master_result_i = '0; - assign apu_master_flags_i = '0; - `endif -`endif + logic core_data_req_we ; + + assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i}; //******************************************************** //***************** PROCESSOR **************************** //******************************************************** generate - if ( CORE_TYPE_CL == 0 ) begin: CL_CORE + if ( CORE_TYPE_CL == 0 ) begin: CV32_CORE + assign boot_addr = boot_addr_i; + cv32e40p_wrapper #( + .PULP_XPULP ( 1 ), // For now this is a no + .PULP_CLUSTER ( 1 ), + .FPU ( FPU ), + .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS ), + .NUM_INTERRUPTS ( NUM_INTERRUPTS ), + .PULP_ZFINX ( 0 ) + ) CV32_CORE ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .setback_i ( '0 ), + // Control Interface + .pulp_clock_en_i ( clock_en_i ), + .scan_cg_en_i ( test_mode_i ), + .boot_addr_i ( boot_addr ), + .mtvec_addr_i ( '0 ), + .mtvt_addr_i ( '0 ), + .dm_halt_addr_i ( DEBUG_START_ADDR + 16'h0800 ), + .hart_id_i ( hart_id ), + .dm_exception_addr_i ( DEBUG_START_ADDR + 16'h080C ), // From Control PULP, to be checked + // Instruction Interface + .instr_req_o ( instr_req_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_r_valid_i ), + .instr_addr_o ( instr_addr_o ), + .instr_rdata_i ( instr_r_rdata_i ), + // Data Interface + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_o.we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), + // Shadow Memory Interface + .shadow_req_o ( /* Unconnected */ ), + .shadow_gnt_i ( '0 ), + .shadow_rvalid_i ( '0 ), + .shadow_we_o ( /* Unconnected */ ), + .shadow_be_o ( /* Unconnected */ ), + .shadow_addr_o ( /* Unconnected */ ), + .shadow_wdata_o ( /* Unconnected */ ), + .shadow_rdata_i ( '0 ), + // Atomic operation + .data_atop_o ( /* Unconnected */ ), + // apu-interconnect + // Handshake + .apu_req_o ( apu_master_req_o ), + .apu_gnt_i ( apu_master_gnt_i ), + // Request Bus + .apu_operands_o ( apu_master_operands_o ), + .apu_op_o ( apu_master_op_o ), + .apu_type_o ( apu_master_type_o ), + .apu_flags_o ( apu_master_flags_o ), + // Response Bus + .apu_rvalid_i ( apu_master_valid_i ), + .apu_result_i ( apu_master_result_i ), + .apu_flags_i ( apu_master_flags_i ), + // IRQ Interface + .irq_i ( core_irq_x ), + .irq_level_i ( '0 ), // CLIC interrupt level + .irq_shv_i ( '0 ), // CLIC selective hardware vectoring + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_ack_id_o ), + // Debug Interface + .debug_req_i ( debug_req_i ), + .debug_havereset_o ( debug_havereset_o ), + .debug_running_o ( debug_running_o ), + .debug_halted_o ( debug_halted_o ), + // Yet other control signals + .fetch_enable_i ( fetch_en_i ), + .core_sleep_o ( core_sleep ), + // External performance monitoring signals + .external_perf_i ( ext_perf_i ) + ); + assign core_busy_o = ~core_sleep; + end else if ( CORE_TYPE_CL == 1 ) begin: RI5CY_CORE assign boot_addr = boot_addr_i; riscv_core #( - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), - .PULP_SECURE ( 0 ), - .FPU ( FPU ), - .FP_DIVSQRT ( FP_DIVSQRT ), - .SHARED_FP ( SHARED_FP ), - .SHARED_DSP_MULT ( 0 ), - .SHARED_INT_DIV ( 0 ), - .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), - .WAPUTYPE ( WAPUTYPE ), + .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), + .PULP_CLUSTER ( 1 ), + .FPU ( FPU | SHARED_FP ), + .FP_DIVSQRT ( FP_DIVSQRT ), + .SHARED_FP ( SHARED_FP ), + .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), + .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS ), + .Zfinx ( FPU ), + .WAPUTYPE ( WAPUTYPE ), .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) - - ) RISCV_CORE ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .clock_en_i ( clock_en_i ), - .test_en_i ( test_mode_i ), - - .boot_addr_i ( boot_addr ), - .core_id_i ( CORE_ID[3:0] ), - .cluster_id_i ( cluster_id_i ), - - .instr_addr_o ( instr_addr_o ), - .instr_req_o ( instr_req_o ), - .instr_rdata_i ( instr_r_rdata_i ), - .instr_gnt_i ( instr_gnt_i ), - .instr_rvalid_i ( instr_r_valid_i ), - - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_we_o ( s_core_bus.we ), - .data_req_o ( s_core_bus.req ), - .data_be_o ( s_core_bus.be ), - .data_rdata_i ( s_core_bus.r_rdata ), - .data_gnt_i ( s_core_bus.gnt ), - .data_rvalid_i ( s_core_bus.r_valid ), - - .irq_i ( irq_req_i ), - .irq_id_i ( irq_id_i ), - .irq_id_o ( irq_ack_id_o ), - .irq_ack_o ( irq_ack_o ), - - .sec_lvl_o ( ), - .irq_sec_i ( 1'b0 ), - - .debug_req_i ( debug_req_i ), - - .fetch_enable_i ( fetch_en_i ), - .core_busy_o ( core_busy_o ), - - - // apu-interconnect - .apu_master_req_o ( apu_master_req_o ), - .apu_master_gnt_i ( apu_master_gnt_i ), - .apu_master_type_o ( apu_master_type_o ), - .apu_master_operands_o ( apu_master_operands_o ), - .apu_master_op_o ( apu_master_op_o ), - .apu_master_flags_o ( apu_master_flags_o ), - - .apu_master_valid_i ( apu_master_valid_i ), - .apu_master_ready_o ( apu_master_ready_o ), - .apu_master_result_i ( apu_master_result_i ), - .apu_master_flags_i ( apu_master_flags_i ), - - .ext_perf_counters_i ( perf_counters ), - .fregfile_disable_i ( 1'b1 ) //disable FP regfile - ); - end else begin: CL_CORE + ) RI5CY_CORE ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .setback_i ( setback_i ), + .clock_en_i ( clock_en_i ), + .test_en_i ( test_mode_i ), + // Control Interface + .fregfile_disable_i ( '1 ), + .boot_addr_i ( boot_addr ), + .core_id_i ( hart_id ), + .cluster_id_i ( cluster_id_i ), + // Instruction Interface + .instr_req_o ( instr_req_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_r_valid_i ), + .instr_addr_o ( instr_addr_o ), + .instr_rdata_i ( instr_r_rdata_i ), + // Data Interface + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_o.we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), + .data_unaligned_o ( /* Unused */ ), + // apu-interconnect + // Handshake + .apu_master_req_o ( apu_master_req_o ), + .apu_master_ready_o ( apu_master_ready_o ), + .apu_master_gnt_i ( apu_master_gnt_i ), + // Request Bus + .apu_master_operands_o ( apu_master_operands_o ), + .apu_master_op_o ( apu_master_op_o ), + .apu_master_type_o ( apu_master_type_o ), + .apu_master_flags_o ( apu_master_flags_o ), + // Response Bus + .apu_master_valid_i ( apu_master_valid_i ), + .apu_master_result_i ( apu_master_result_i ), + .apu_master_flags_i ( apu_master_flags_i ), + // IRQ Interface + .irq_i ( irq_req_i ), + .irq_id_i ( irq_id_i ), + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_ack_id_o ), + .irq_sec_i ( '0 ), + .sec_lvl_o ( ), + // Debug Interface + .debug_req_i ( debug_req_i | + recovery_bus_i.debug_req ), + .debug_resume_i ( recovery_bus_i.debug_resume ), + .debug_mode_o ( debug_halted_o ), + // Yet other control signals + .fetch_enable_i ( fetch_en_i ), + .core_busy_o ( core_busy_o ), + // External performance monitoring signals + .ext_perf_counters_i ( ext_perf_i ), + // RF recovery ports + .recover_i ( recovery_bus_i.rf_recovery_en ), + // Write port A + .regfile_waddr_a_i ( recovery_bus_i.rf_recovery_wdata.waddr_a ), + .regfile_wdata_a_i ( recovery_bus_i.rf_recovery_rdata.rdata_a ), + .regfile_we_a_i ( recovery_bus_i.rf_recovery_wdata.we_a ), + // Write port B + .regfile_waddr_b_i ( recovery_bus_i.rf_recovery_wdata.waddr_b ), + .regfile_wdata_b_i ( recovery_bus_i.rf_recovery_rdata.rdata_b ), + .regfile_we_b_i ( recovery_bus_i.rf_recovery_wdata.we_b ), + // Outputs from RF + // Port A + .regfile_we_a_o ( regfile_backup_o.we_a ), + .regfile_waddr_a_o ( regfile_backup_o.waddr_a ), + .regfile_wdata_a_o ( regfile_backup_o.wdata_a ), + // Port B + .regfile_we_b_o ( regfile_backup_o.we_b ), + .regfile_waddr_b_o ( regfile_backup_o.waddr_b ), + .regfile_wdata_b_o ( regfile_backup_o.wdata_b ), + // Program Counter Backup + .backup_program_counter_o ( pc_backup_o.program_counter ), + .backup_program_counter_if_o ( pc_backup_o.program_counter_if ), + .backup_branch_o ( pc_backup_o.is_branch ), + .backup_branch_addr_o ( pc_backup_o.branch_addr ), + // Program Counter Recovery + .pc_recover_i ( recovery_bus_i.pc_recovery_en ), + .recovery_program_counter_i ( recovery_bus_i.pc_recovery.program_counter ), + .recovery_branch_i ( recovery_bus_i.pc_recovery.is_branch ), + .recovery_branch_addr_i ( recovery_bus_i.pc_recovery.branch_addr ), + // CSRs Backup + .backup_mstatus_o ( csr_backup_o.csr_mstatus ), + .backup_mtvec_o ( csr_backup_o.csr_mtvec ), + .backup_mscratch_o ( csr_backup_o.csr_mscratch ), + .backup_mepc_o ( csr_backup_o.csr_mepc ), + .backup_mcause_o ( csr_backup_o.csr_mcause ), + // CSRs Recovery + .recovery_mstatus_i ( recovery_bus_i.csr_recovery.csr_mstatus ), + .recovery_mtvec_i ( recovery_bus_i.csr_recovery.csr_mtvec ), + .recovery_mscratch_i ( recovery_bus_i.csr_recovery.csr_mscratch ), + .recovery_mepc_i ( recovery_bus_i.csr_recovery.csr_mepc ), + .recovery_mcause_i ( recovery_bus_i.csr_recovery.csr_mcause ) + ); + assign debug_havereset_o = '0; + assign debug_running_o = '0; + assign csr_backup_o.csr_mie = '0; + assign csr_backup_o.csr_mip = '0; + end else begin: IBEX_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) + // Core busy + assign core_busy_o = ~core_sleep; if (INSTR_RDATA_WIDTH == 128) begin instr_width_converter ibex_width_converter ( @@ -322,9 +388,9 @@ module core_region .clk_i (clk_i ), .rst_ni (rst_ni ), .core_req_i (core_mem_req ), - .mem_req_o (s_core_bus.req ), - .mem_gnt_i (s_core_bus.gnt ), - .mem_rvalid_i(s_core_bus.r_valid) + .mem_req_o (core_data_req_o.req ), + .mem_gnt_i (core_data_rsp_i.gnt ), + .mem_rvalid_i(core_data_rsp_i.r_valid) ); `ifdef VERILATOR @@ -371,14 +437,14 @@ module core_region .instr_err_i ( 1'b0 ), // Data memory interface: - .data_req_o ( core_mem_req ), - .data_gnt_i ( s_core_bus.gnt ), - .data_rvalid_i ( s_core_bus.r_valid ), - .data_we_o ( s_core_bus.we ), - .data_be_o ( s_core_bus.be ), - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_rdata_i ( s_core_bus.r_rdata ), + .data_req_o ( core_mem_req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_o.we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.wdata ), + .data_rdata_i ( core_data_rsp_i.r_rdata ), .data_err_i ( 1'b0 ), .irq_software_i ( 1'b0 ), @@ -391,7 +457,7 @@ module core_region .irq_x_ack_o ( irq_ack_o ), .irq_x_ack_id_o ( irq_ack_id_o ), - .external_perf_i ( {{{16- N_EXT_PERF_COUNTERS_ACTUAL}{'0}}, perf_counters} ), + .external_perf_i ( {{{16- N_EXT_PERF_COUNTERS}{'0}}, ext_perf_i} ), .debug_req_i ( debug_req_i ), @@ -400,135 +466,16 @@ module core_region .alert_major_o (), .core_sleep_o ( core_sleep ) ); - assign core_busy_o = ~core_sleep; - // Ibex supports 32 additional fast interrupts and reads the interrupt lines directly. - // Convert ID back to interrupt lines - always_comb begin : gen_core_irq_x - core_irq_x = '0; - if (irq_req_i) begin - core_irq_x[irq_id_i] = 1'b1; - end - end end endgenerate - //assign debug_bus.r_opc = 1'b0; - - // Bind to 0 Unused Signals in CORE interface - assign s_core_bus.r_gnt = 1'b0; - assign s_core_bus.barrier = 1'b0; - assign s_core_bus.exec_cancel = 1'b0; - assign s_core_bus.exec_stall = 1'b0; - - // Performance Counters - assign perf_counters[4] = tcdm_data_master.req & (~tcdm_data_master.gnt); // Cycles lost due to contention - - - //******************************************************** - //****** DEMUX TO TCDM AND PERIPHERAL INTERCONNECT ******* - //******************************************************** - - // demuxes to TCDM & memory hierarchy - core_demux #( - .ADDR_WIDTH ( 32 ), - .DATA_WIDTH ( 32 ), - .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ), - .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) - ) core_demux_i ( - .clk ( clk_int ), - .rst_ni ( rst_ni ), - .test_en_i ( test_mode_i ), - `ifdef REMAP_ADDRESS - .base_addr_i ( base_addr_i ), -`endif - .data_req_i ( s_core_bus.req ), - .data_add_i ( s_core_bus.add ), - .data_wen_i ( ~s_core_bus.we ), //inverted when using OR10N - .data_wdata_i ( s_core_bus.wdata ), - .data_be_i ( s_core_bus.be ), - .data_gnt_o ( s_core_bus.gnt ), - .data_r_gnt_i ( s_core_bus.r_gnt ), - .data_r_valid_o ( s_core_bus.r_valid ), - .data_r_opc_o ( ), - .data_r_rdata_o ( s_core_bus.r_rdata ), - - .data_req_o_SH ( tcdm_data_master.req ), - .data_add_o_SH ( tcdm_data_master.add ), - .data_wen_o_SH ( tcdm_data_master.wen ), - .data_wdata_o_SH ( tcdm_data_master.data ), - .data_be_o_SH ( tcdm_data_master.be ), - .data_gnt_i_SH ( tcdm_data_master.gnt ), - .data_r_valid_i_SH ( tcdm_data_master.r_valid ), - .data_r_rdata_i_SH ( tcdm_data_master.r_data ), - - .data_req_o_EXT ( periph_demux_bus.req ), - .data_add_o_EXT ( periph_demux_bus.add ), - .data_wen_o_EXT ( periph_demux_bus.wen ), - .data_wdata_o_EXT ( periph_demux_bus.wdata ), - .data_be_o_EXT ( periph_demux_bus.be ), - .data_gnt_i_EXT ( periph_demux_bus.gnt ), - .data_r_valid_i_EXT ( periph_demux_bus.r_valid ), - .data_r_rdata_i_EXT ( periph_demux_bus.r_rdata ), - .data_r_opc_i_EXT ( periph_demux_bus.r_opc ), - - .data_req_o_PE ( periph_data_master.req ), - .data_add_o_PE ( periph_data_master.add ), - .data_wen_o_PE ( periph_data_master.wen ), - .data_wdata_o_PE ( periph_data_master.wdata ), - .data_be_o_PE ( periph_data_master.be ), - .data_gnt_i_PE ( periph_data_master.gnt ), - .data_r_valid_i_PE ( periph_data_master.r_valid ), - .data_r_rdata_i_PE ( periph_data_master.r_rdata ), - .data_r_opc_i_PE ( periph_data_master.r_opc ), - - .perf_l2_ld_o ( perf_counters[0] ), - .perf_l2_st_o ( perf_counters[1] ), - .perf_l2_ld_cyc_o ( perf_counters[2] ), - .perf_l2_st_cyc_o ( perf_counters[3] ), - .CLUSTER_ID ( cluster_id_i ) - ); - - assign tcdm_data_master.boffs = '0; - assign tcdm_data_master.lrdy = '1; - - periph_demux periph_demux_i ( - .clk ( clk_int ), - .rst_ni ( rst_ni ), - - .data_req_i ( periph_demux_bus.req ), - .data_add_i ( periph_demux_bus.add ), - .data_wen_i ( periph_demux_bus.wen ), - .data_wdata_i ( periph_demux_bus.wdata ), - .data_be_i ( periph_demux_bus.be ), - .data_gnt_o ( periph_demux_bus.gnt ), - - .data_r_valid_o ( periph_demux_bus.r_valid ), - .data_r_opc_o ( periph_demux_bus.r_opc ), - .data_r_rdata_o ( periph_demux_bus.r_rdata ), - - .data_req_o_MH ( dma_ctrl_master.req ), - .data_add_o_MH ( dma_ctrl_master.add ), - .data_wen_o_MH ( dma_ctrl_master.wen ), - .data_wdata_o_MH ( dma_ctrl_master.wdata ), - .data_be_o_MH ( dma_ctrl_master.be ), - .data_gnt_i_MH ( dma_ctrl_master.gnt ), - - .data_r_valid_i_MH ( dma_ctrl_master.r_valid ), - .data_r_rdata_i_MH ( dma_ctrl_master.r_rdata ), - .data_r_opc_i_MH ( dma_ctrl_master.r_opc ), - - .data_req_o_EU ( eu_ctrl_master.req ), - .data_add_o_EU ( eu_ctrl_master.add ), - .data_wen_o_EU ( eu_ctrl_master.wen ), - .data_wdata_o_EU ( eu_ctrl_master.wdata ), - .data_be_o_EU ( eu_ctrl_master.be ), - .data_gnt_i_EU ( eu_ctrl_master.gnt ), - - .data_r_valid_i_EU ( eu_ctrl_master.r_valid ), - .data_r_rdata_i_EU ( eu_ctrl_master.r_rdata ), - .data_r_opc_i_EU ( eu_ctrl_master.r_opc ) - ); + always_comb begin : gen_core_irq_x + core_irq_x = '0; + if (irq_req_i) begin + core_irq_x[irq_id_i] = 1'b1; + end + end /* debug stuff */ //synopsys translate_off @@ -537,12 +484,12 @@ module core_region always @(posedge clk_i) begin : CHECK_ASSERTIONS `ifndef CLUSTER_ALIAS - if ((s_core_bus.req == 1'b1) && (s_core_bus.add < 32'h1000_0000)) begin - $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,s_core_bus.add, $time()/1000 ); + if ((core_data_req_o.req == 1'b1) && (core_data_req_o.add < 32'h1000_0000)) begin + $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_data_req_o.add, $time()/1000 ); $finish(); end - if ((s_core_bus.req == 1'b1) && (s_core_bus.add >= 32'h1040_0000) && ((s_core_bus.add < 32'h1A00_0000))) begin - $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,s_core_bus.add, $time()/1000 ); + if ((core_data_req_o.req == 1'b1) && (core_data_req_o.add >= 32'h1040_0000) && ((core_data_req_o.add < 32'h1A00_0000))) begin + $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_data_req_o.add, $time()/1000 ); $finish(); end `endif @@ -564,7 +511,7 @@ module core_region initial begin - FILE_ID.itoa(CORE_ID); + FILE_ID.itoa(core_id_i); FILENAME = {"FETCH_CORE_", FILE_ID, ".log" }; FILE=$fopen(FILENAME,"w"); end diff --git a/rtl/core_demux.sv b/rtl/data_periph_demux.sv similarity index 97% rename from rtl/core_demux.sv rename to rtl/data_periph_demux.sv index 6b575732..0328d0c9 100644 --- a/rtl/core_demux.sv +++ b/rtl/data_periph_demux.sv @@ -13,24 +13,22 @@ * (http://www.pulp-platform.org), under the copyright of ETH Zurich and the * University of Bologna. */ - -`include "pulp_soc_defines.sv" -//`define PERF_CNT -module core_demux + +module data_periph_demux #( parameter int unsigned ADDR_WIDTH = 32, parameter int unsigned DATA_WIDTH = 32, parameter int unsigned BYTE_ENABLE_BIT = DATA_WIDTH/8, - parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000 + parameter int unsigned REMAP_ADDRESS = 0, + parameter int unsigned CLUSTER_ALIAS = 1, + parameter int unsigned CLUSTER_ALIAS_BASE = 12'h000 ) ( input logic clk, input logic rst_ni, input logic test_en_i, -`ifdef REMAP_ADDRESS input logic [3:0] base_addr_i, -`endif // CORE SIDE input logic data_req_i, @@ -40,7 +38,6 @@ module core_demux input logic [BYTE_ENABLE_BIT - 1:0] data_be_i, output logic data_gnt_o, - input logic data_r_gnt_i, // Data Response Grant (For LOAD/STORE commands) output logic data_r_valid_o, // Data Response Valid (For LOAD/STORE commands) output logic [DATA_WIDTH - 1:0] data_r_rdata_o, // Data Response DATA (For LOAD commands) output logic data_r_opc_o, // Data Response Error @@ -138,9 +135,9 @@ module core_demux always_comb begin - TCDM_RW = 12'h100 + (CLUSTER_ID << 2) + 0; - TCDM_TS = 12'h100 + (CLUSTER_ID << 2) + 1; - DEM_PER = 12'h100 + (CLUSTER_ID << 2) + 2; + TCDM_RW = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 0; + TCDM_TS = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 1; + DEM_PER = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 2; end @@ -153,7 +150,7 @@ module core_demux assign data_add_int[27:0] = data_add_i[27:0]; -`ifdef REMAP_ADDRESS +if (REMAP_ADDRESS == 1) begin always_comb begin if(data_add_i[31:28] == base_addr_i) @@ -169,9 +166,9 @@ module core_demux data_add_int[31:28] = data_add_i[31:28]; end end -`else +end else begin assign data_add_int[31:28] = data_add_i[31:28]; -`endif +end //******************************************************** //************** LEVEL 1 REQUEST ARBITER ***************** @@ -637,4 +634,4 @@ logic clear_regs, enable_regs; end `endif -endmodule +endmodule: data_periph_demux diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 069a4d2e..c37a8608 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -13,79 +13,237 @@ * Francesco Conti */ -import hci_package::*; +`include "hci_helpers.svh" module hwpe_subsystem + import hci_package::*; + import pulp_cluster_package::*; #( - parameter int unsigned N_CORES = 8, - parameter int unsigned N_MASTER_PORT = 9, - parameter int unsigned ID_WIDTH = 8, - parameter bit USE_RBE = 0 + parameter hwpe_subsystem_cfg_t HWPE_CFG = '0, + parameter int unsigned N_CORES = 8, + parameter int unsigned N_MASTER_PORT = 9, + parameter int unsigned ID_WIDTH = 8, + parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0 ) ( - input logic clk, - input logic rst_n, - input logic test_mode, - - hci_core_intf.master hwpe_xbar_master, - XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, - - output logic [N_CORES-1:0][1:0] evt_o, - output logic busy_o + input logic clk, + input logic rst_n, + input logic test_mode, + input logic hwpe_en_i, + input logic [$clog2(MAX_NUM_HWPES)-1:0] hwpe_sel_i, + + hci_core_intf.initiator hwpe_xbar_master, + XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, + + output logic [N_CORES-1:0][1:0] evt_o, + output logic busy_o ); + localparam int unsigned DW = HCI_HWPE_SIZE.DW; + localparam int unsigned AW = HCI_HWPE_SIZE.AW; + localparam int unsigned EW = HCI_HWPE_SIZE.EW; + localparam int unsigned EHW = HCI_HWPE_SIZE.EHW; + + // TEMP: localparam used by softex since it doesn't support yet ECC-HCI interface + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_softex) = '{ + DW: DW, + AW: AW, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW + }; + `HCI_INTF(tcdm_softex, clk); + + localparam int unsigned N_HWPES = HWPE_CFG.NumHwpes; + + logic [N_HWPES-1:0] busy; + logic [N_HWPES-1:0][N_CORES-1:0][1:0] evt; + + logic [N_HWPES-1:0] hwpe_clk; + logic [N_HWPES-1:0] hwpe_en_int; + + logic [$clog2(N_HWPES)-1:0] hwpe_sel_int; + + assign hwpe_sel_int = hwpe_sel_i[0+:$clog2(N_HWPES)]; + hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) - ) periph ( - .clk ( clk ) - ); - - generate - if(USE_RBE) begin : rbe_gen - rbe_top #( - .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ), - .BW ( N_MASTER_PORT*32 ) - ) hwpe_top_wrap_i ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - .evt_o ( evt_o ), - .tcdm ( hwpe_xbar_master ), - .hci_ctrl_o ( ), - .periph ( periph ) + ) periph [N_HWPES-1:0] (.clk(clk)); + + hci_core_intf #( + .DW ( DW ), + .AW ( AW ), + .EW ( EW ), + .EHW ( EHW ) + ) tcdm [0:N_HWPES-1] (.clk(clk)); + + for (genvar i = 0; i < N_HWPES; i++) begin : gen_hwpe + + // HWPE specific enable + assign hwpe_en_int[i] = hwpe_en_i && (hwpe_sel_int == i); + + // Clock gating cell + tc_clk_gating i_hwpe_clock_gate ( + .clk_i ( clk ), + .en_i ( hwpe_en_int[i] ), + .test_en_i ( test_mode ), + .clk_o ( hwpe_clk[i] ) + ); + + // Generate desired HWPEs + if (HWPE_CFG.HwpeList[i] == REDMULE) begin : gen_redmule + + ///////////// + // REDMULE // + ///////////// + + redmule_top #( + .ID_WIDTH ( ID_WIDTH ), + .N_CORES ( N_CORES ), + .DW ( N_MASTER_PORT*32 ), + .`HCI_SIZE_PARAM(tcdm) ( HCI_HWPE_SIZE ) + ) i_redmule ( + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + .busy_o ( busy[i] ), + .evt_o ( evt[i] ), + .tcdm ( tcdm[i] ), + .periph ( periph[i] ) ); - assign busy_o = 1'b1; - end - else begin : datamover_gen - datamover_top #( - .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ), - .BW ( N_MASTER_PORT*32 ) - ) hwpe_top_wrap_i ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - .evt_o ( evt_o ), - .tcdm ( hwpe_xbar_master ), - .periph ( periph ) + + end else if (HWPE_CFG.HwpeList[i] == NEUREKA) begin : gen_neureka + + ///////////// + // NEUREKA // + ///////////// + + neureka_top #( + .PE_H ( 4 ), + .PE_W ( 4 ), + .ID ( ID_WIDTH ), + .N_CORES ( N_CORES ), + .`HCI_SIZE_PARAM(tcdm) ( HCI_HWPE_SIZE ) + ) i_neureka ( + // global signals + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + // events + .evt_o ( evt[i] ), + .busy_o ( busy[i] ), + // tcdm master ports + .tcdm ( tcdm[i] ), + // periph slave port + .periph ( periph[i] ) ); - assign busy_o = 1'b1; + + end else if (HWPE_CFG.HwpeList[i] == SOFTEX) begin : gen_softex + + //////////// + // SOFTEX // + //////////// + + softex_top #( + .N_CORES ( N_CORES ), + .`HCI_SIZE_PARAM(Tcdm) ( `HCI_SIZE_PARAM(tcdm_softex) ) + ) i_softex ( + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .busy_o ( busy[i] ), + .evt_o ( evt[i] ), + .tcdm ( tcdm_softex ), + .periph ( periph[i] ) + ); + + // TEMP: softex doesn't yet support ECC-HCI internally + hci_ecc_enc #( + .`HCI_SIZE_PARAM(tcdm_target) ( `HCI_SIZE_PARAM(tcdm_softex) ), + .`HCI_SIZE_PARAM(tcdm_initiator) ( HCI_HWPE_SIZE ) + ) i_ecc_softex_enc ( + .r_data_single_err_o ( ), + .r_data_multi_err_o ( ), + .r_meta_single_err_o ( ), + .r_meta_multi_err_o ( ), + .tcdm_target ( tcdm_softex ), + .tcdm_initiator ( tcdm[i] ) + ); + + end + end + + ////////////////// + // HWPE CFG BUS // + ////////////////// + + // Target signals muxed according to `hwpe_sel_int` + logic [N_HWPES-1:0] periph_gnt; + logic [N_HWPES-1:0][31:0] periph_r_rdata; + logic [N_HWPES-1:0] periph_r_valid; + logic [N_HWPES-1:0][ID_WIDTH-1:0] periph_r_id; + + for (genvar i = 0; i < N_HWPES; i++) begin + always_comb begin + // Initiator signals decoded according to `hwpe_sel_int` + periph[i].req = (hwpe_sel_int == i) ? hwpe_cfg_slave.req : '0; + // No muxing needed + periph[i].add = hwpe_cfg_slave.add; + periph[i].wen = hwpe_cfg_slave.wen; + periph[i].be = hwpe_cfg_slave.be; + periph[i].data = hwpe_cfg_slave.wdata; + periph[i].id = hwpe_cfg_slave.id; + // Split interface signals into packed vectors + periph_gnt [i] = periph[i].gnt; + periph_r_rdata [i] = periph[i].r_data; + periph_r_valid [i] = periph[i].r_valid; + periph_r_id [i] = periph[i].r_id; end - endgenerate - - always_comb - begin - periph.req = hwpe_cfg_slave.req; - periph.add = hwpe_cfg_slave.add; - periph.wen = hwpe_cfg_slave.wen; - periph.be = hwpe_cfg_slave.be; - periph.data = hwpe_cfg_slave.wdata; - periph.id = hwpe_cfg_slave.id; end - assign hwpe_cfg_slave.gnt = periph.gnt; - assign hwpe_cfg_slave.r_rdata = periph.r_data; - assign hwpe_cfg_slave.r_valid = periph.r_valid; - assign hwpe_cfg_slave.r_id = periph.r_id; + + always_comb begin + // Config bus + hwpe_cfg_slave.gnt = periph_gnt [0]; + hwpe_cfg_slave.r_rdata = periph_r_rdata [0]; + hwpe_cfg_slave.r_valid = periph_r_valid [0]; + hwpe_cfg_slave.r_id = periph_r_id [0]; + // evt and busy + evt_o = evt[0]; + busy_o = busy[0]; + for (int i = 1; i < N_HWPES; i++) begin + if (hwpe_sel_int == i) begin + // Config bus + hwpe_cfg_slave.gnt = periph_gnt [i]; + hwpe_cfg_slave.r_rdata = periph_r_rdata [i]; + hwpe_cfg_slave.r_valid = periph_r_valid [i]; + hwpe_cfg_slave.r_id = periph_r_id [i]; + // evt and busy + evt_o = evt[i]; + busy_o = busy[i]; + end + end + end + + ////////////////////// + // HWPE XBAR MASTER // + ////////////////////// + + hci_core_mux_static #( + .NB_CHAN ( N_HWPES ), + .`HCI_SIZE_PARAM(in) ( HCI_HWPE_SIZE ) + ) i_hwpe_hci_mux ( + + /* Internally unused */ + .clk_i ( clk ), + .rst_ni ( rst_n ), + .clear_i ( '0 ), + /*********************/ + + .sel_i ( hwpe_sel_int ), + + .in ( tcdm ), + .out ( hwpe_xbar_master ) +); endmodule diff --git a/rtl/idma_wrap.sv b/rtl/idma_wrap.sv new file mode 100644 index 00000000..ab4954b0 --- /dev/null +++ b/rtl/idma_wrap.sv @@ -0,0 +1,461 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/* + * dmac_wrap.sv + * Thomas Benz + * Michael Rogenmoser + */ + +// DMA Core wrapper + +`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "idma/typedef.svh" +`include "register_interface/typedef.svh" + +module dmac_wrap #( + parameter int unsigned NB_CORES = 4, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 4, + parameter int unsigned PE_ID_WIDTH = 1, + parameter int unsigned NB_PE_PORTS = 1, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter int unsigned NUM_STREAMS = 1, // Only 1 for now + parameter int unsigned TCDM_SIZE = 0, + parameter int unsigned TwoDMidend = 1, // Leave this on for now + parameter int unsigned NB_OUTSND_BURSTS = 8, + parameter int unsigned GLOBAL_QUEUE_DEPTH = 16, + parameter int unsigned BACKEND_QUEUE_DEPTH = 16, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0], + hci_core_intf.target ctrl_slave[0:NB_CORES-1], + hci_core_intf.initiator tcdm_master[0:3], + output axi_req_t ext_master_req_o, + input axi_resp_t ext_master_resp_i, + output logic [NB_CORES-1:0] term_event_o, + output logic [NB_CORES-1:0] term_irq_o, + output logic [NB_PE_PORTS-1:0] term_event_pe_o, + output logic [NB_PE_PORTS-1:0] term_irq_pe_o, + output logic busy_o +); + + localparam int unsigned NumRegs = NB_CORES+NB_PE_PORTS; + localparam int unsigned MstIdxWidth = AXI_ID_WIDTH; + localparam int unsigned SlvIdxWidth = AXI_ID_WIDTH - $clog2(NUM_STREAMS); + + // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS + logic [NumRegs-1:0][DATA_WIDTH-1:0] config_wdata; + logic [NumRegs-1:0][ADDR_WIDTH-1:0] config_add; + logic [NumRegs-1:0] config_req; + logic [NumRegs-1:0] config_wen; + logic [NumRegs-1:0][BE_WIDTH-1:0] config_be; + logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_id; + logic [NumRegs-1:0] config_gnt; + logic [NumRegs-1:0][DATA_WIDTH-1:0] config_r_rdata; + logic [NumRegs-1:0] config_r_valid; + logic [NumRegs-1:0] config_r_opc; + logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_r_id; + + // tie-off pe control ports + for (genvar i = 0; i < NB_CORES; i++) begin : gen_ctrl_registers + assign config_add[i] = ctrl_slave[i].add; + assign config_req[i] = ctrl_slave[i].req; + assign config_wdata[i] = ctrl_slave[i].data; + assign config_wen[i] = ctrl_slave[i].wen; + assign config_be[i] = ctrl_slave[i].be; + assign config_id[i] = '0; + assign ctrl_slave[i].gnt = config_gnt[i]; + assign ctrl_slave[i].r_opc = config_r_opc[i]; + assign ctrl_slave[i].r_valid = config_r_valid[i]; + assign ctrl_slave[i].r_data = config_r_rdata[i]; + end + + for (genvar i = 0; i < NB_PE_PORTS; i++) begin : gen_pe_ctrl_registers + assign config_add[NB_CORES+i] = pe_ctrl_slave[i].add; + assign config_req[NB_CORES+i] = pe_ctrl_slave[i].req; + assign config_wdata[NB_CORES+i] = pe_ctrl_slave[i].wdata; + assign config_wen[NB_CORES+i] = pe_ctrl_slave[i].wen; + assign config_be[NB_CORES+i] = pe_ctrl_slave[i].be; + assign config_id[NB_CORES+i] = pe_ctrl_slave[i].id; + assign pe_ctrl_slave[i].gnt = config_gnt[NB_CORES+i]; + assign pe_ctrl_slave[i].r_opc = config_r_opc[NB_CORES+i]; + assign pe_ctrl_slave[i].r_valid = config_r_valid[NB_CORES+i]; + assign pe_ctrl_slave[i].r_rdata = config_r_rdata[NB_CORES+i]; + assign pe_ctrl_slave[i].r_id = config_r_id[NB_CORES+i]; + end + + // AXI4+ATOP types + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [ADDR_WIDTH-1:0] mem_addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [SlvIdxWidth-1:0] slv_id_t; + typedef logic [MstIdxWidth-1:0] mst_id_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + // AXI4+ATOP channels typedefs + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mem_aw_chan_t, mem_addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mem_ar_chan_t, mem_addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mem_req_t, mem_aw_chan_t, w_chan_t, mem_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + // BUS definitions + mst_req_t tcdm_req, soc_req; + mem_req_t tcdm_mem_req; + mst_resp_t soc_rsp; + mst_resp_t tcdm_rsp; + slv_req_t [NUM_STREAMS-1:0] dma_req; + slv_resp_t [NUM_STREAMS-1:0] dma_rsp; + // interface to structs + //`AXI_ASSIGN_FROM_REQ(ext_master_req_o, soc_req) + //`AXI_ASSIGN_TO_RESP(soc_rsp, ext_master_resp_i) + + `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, soc_req) + `AXI_ASSIGN_RESP_STRUCT(soc_rsp, ext_master_resp_i) + + // Register BUS definitions + `REG_BUS_TYPEDEF_ALL(dma_regs, logic[9:0], logic[31:0], logic[3:0]) + dma_regs_req_t [NumRegs-1:0] dma_regs_req; + dma_regs_rsp_t [NumRegs-1:0] dma_regs_rsp; + + // iDMA struct definitions + localparam int unsigned TFLenWidth = AXI_ADDR_WIDTH; + localparam int unsigned NumDim = 2; // Support 2D midend for 2D transfers + localparam int unsigned RepWidth = 32; + localparam int unsigned StrideWidth = 32; + typedef logic [TFLenWidth-1:0] tf_len_t; + typedef logic [RepWidth-1:0] reps_t; + typedef logic [StrideWidth-1:0] strides_t; + + // iDMA request / response types + `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, slv_id_t, addr_t, tf_len_t) + `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) + + // iDMA ND request + `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) + + idma_nd_req_t twod_req, twod_req_queue; + idma_req_t burst_req; + idma_rsp_t idma_rsp; + + logic fe_valid, twod_queue_valid, be_valid, be_rsp_valid; + logic fe_ready, twod_queue_ready, be_ready, be_rsp_ready; + logic trans_complete, midend_busy; + idma_pkg::idma_busy_t idma_busy; + + // ------------------------------------------------------ + // FRONTEND + // ------------------------------------------------------ + + for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs + periph_to_reg #( + .AW ( 10 ), + .DW ( 32 ), + .BW ( 8 ), + .IW ( PE_ID_WIDTH ), + .req_t ( dma_regs_req_t ), + .rsp_t ( dma_regs_rsp_t ) + ) i_pe_translate ( + .clk_i, + .rst_ni, + .req_i ( config_req [i] ), + .add_i ( config_add [i][9:0] ), + .wen_i ( config_wen [i] ), + .wdata_i ( config_wdata [i] ), + .be_i ( config_be [i] ), + .id_i ( config_id [i] ), + .gnt_o ( config_gnt [i] ), + .r_rdata_o ( config_r_rdata [i] ), + .r_opc_o ( config_r_opc [i] ), + .r_id_o ( config_r_id [i] ), + .r_valid_o ( config_r_valid [i] ), + .reg_req_o ( dma_regs_req [i] ), + .reg_rsp_i ( dma_regs_rsp [i] ) + ); + end + + idma_reg32_2d_frontend #( + .NumRegs ( NumRegs ), + .IdCounterWidth ( 28 ), + .dma_regs_req_t ( dma_regs_req_t ), + .dma_regs_rsp_t ( dma_regs_rsp_t ), + .burst_req_t ( idma_nd_req_t ) + ) i_idma_reg32_2d_frontend ( + .clk_i, + .rst_ni, + .dma_ctrl_req_i ( dma_regs_req ), + .dma_ctrl_rsp_o ( dma_regs_rsp ), + .burst_req_o ( twod_req ), + .valid_o ( fe_valid ), + .ready_i ( fe_ready ), + .backend_idle_i ( ~busy_o ), + .trans_complete_i ( trans_complete ) + ); + + // interrupts and events (currently broadcast tx_cplt event only) + assign term_event_pe_o = |trans_complete ? '1 : '0; + assign term_irq_pe_o = '0; + assign term_event_o = |trans_complete ? '1 : '0; + assign term_irq_o = '0; + + assign busy_o = midend_busy | |idma_busy; + + // ------------------------------------------------------ + // MIDEND + // ------------------------------------------------------ + + // global (2D) request FIFO + stream_fifo #( + .DEPTH ( GLOBAL_QUEUE_DEPTH ), + .T (idma_nd_req_t ) + ) i_2D_request_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( test_mode_i ), + .usage_o (/*NOT CONNECTED*/), + + .data_i ( twod_req ), + .valid_i ( fe_valid ), + .ready_o ( fe_ready ), + + .data_o ( twod_req_queue ), + .valid_o ( twod_queue_valid ), + .ready_i ( twod_queue_ready ) + ); + + localparam logic [1:0][31:0] RepWidths = '{default: 32'd32}; + + idma_nd_midend #( + .NumDim ( NumDim ), + .addr_t ( addr_t ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_nd_req_t( idma_nd_req_t ), + .RepWidths ( RepWidths ) + ) i_idma_2D_midend ( + .clk_i, + .rst_ni, + + .nd_req_i ( twod_req_queue ), + .nd_req_valid_i ( twod_queue_valid ), + .nd_req_ready_o ( twod_queue_ready ), + + .nd_rsp_o (/*NOT CONNECTED*/ ), + .nd_rsp_valid_o ( trans_complete ), + .nd_rsp_ready_i ( 1'b1 ), // Always ready to accept completed transfers + + .burst_req_o ( burst_req ), + .burst_req_valid_o( be_valid ), + .burst_req_ready_i( be_ready ), + + .burst_rsp_i ( idma_rsp ), + .burst_rsp_valid_i( be_rsp_valid ), + .burst_rsp_ready_o( be_rsp_ready ), + + .busy_o ( midend_busy ) + ); + + // ------------------------------------------------------ + // BACKEND + // ------------------------------------------------------ + + idma_backend #( + .DataWidth ( AXI_DATA_WIDTH ), + .AddrWidth ( AXI_ADDR_WIDTH ), + .UserWidth ( AXI_USER_WIDTH ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .NumAxInFlight ( NB_OUTSND_BURSTS ), + .BufferDepth ( 3 ), + .TFLenWidth ( TFLenWidth ), + .RAWCouplingAvail ( 1'b1 ), + .MemSysDepth ( 32'd0 ), + .MaskInvalidData ( 1'b1 ), + .HardwareLegalizer ( 1'b1 ), + .RejectZeroTransfers ( 1'b1 ), + .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), + .idma_busy_t ( idma_pkg::idma_busy_t ), + .protocol_req_t ( slv_req_t ), + .protocol_rsp_t ( slv_resp_t ), + .aw_chan_t ( slv_aw_chan_t ), + .ar_chan_t ( slv_ar_chan_t ) + ) i_idma_backend ( + .clk_i, + .rst_ni, + .testmode_i ( test_mode_i ), + + .idma_req_i ( burst_req ), + .req_valid_i ( be_valid ), + .req_ready_o ( be_ready ), + + .idma_rsp_o ( idma_rsp ), + .rsp_valid_o ( be_rsp_valid ), + .rsp_ready_i ( be_rsp_ready ), + + .idma_eh_req_i ( '0 ), // No error handling + .eh_req_valid_i ( 1'b1 ), + .eh_req_ready_o (/*NOT CONNECTED*/), + + .protocol_req_o ( dma_req ), + .protocol_rsp_i ( dma_rsp ), + .busy_o ( idma_busy ) + ); + + // ------------------------------------------------------ + // AXI connection to EXT/TCDM + // ------------------------------------------------------ + + // xbar + localparam int unsigned NumRules = 3; + typedef struct packed { + int unsigned idx; + logic [AXI_ADDR_WIDTH-1:0] start_addr; + logic [AXI_ADDR_WIDTH-1:0] end_addr; + } xbar_rule_t; + xbar_rule_t [NumRules-1:0] addr_map; + logic [AXI_ADDR_WIDTH-1:0] cluster_base_addr; + assign cluster_base_addr = ClusterBaseAddr; /* + (cluster_id_i << 22);*/ + assign addr_map = '{ + '{ // SoC low + start_addr: '0, + end_addr: cluster_base_addr, + idx: 0 + }, + '{ // TCDM + start_addr: cluster_base_addr, + end_addr: cluster_base_addr + TCDM_SIZE, + idx: 1 + }, + '{ // SoC high + start_addr: cluster_base_addr + TCDM_SIZE, + end_addr: '1, + idx: 0 + } + }; + localparam int unsigned NumMstPorts = 2; + localparam int unsigned NumSlvPorts = NUM_STREAMS; + + /* verilator lint_off WIDTHCONCAT */ + localparam axi_pkg::xbar_cfg_t XbarCfg = '{ + NoSlvPorts: NumSlvPorts, + NoMstPorts: NumMstPorts, + MaxMstTrans: NB_OUTSND_BURSTS, + MaxSlvTrans: NB_OUTSND_BURSTS, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + PipelineStages: 0, + AxiIdWidthSlvPorts: SlvIdxWidth, + AxiIdUsedSlvPorts: SlvIdxWidth, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: NumRules + }; + /* verilator lint_on WIDTHCONCAT */ + + axi_xbar #( + .Cfg ( XbarCfg ), + .slv_aw_chan_t( slv_aw_chan_t ), + .mst_aw_chan_t( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t( slv_ar_chan_t ), + .mst_ar_chan_t( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( xbar_rule_t ) + ) i_dma_axi_xbar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( test_mode_i ), + .slv_ports_req_i ( dma_req ), + .slv_ports_resp_o ( dma_rsp ), + .mst_ports_req_o ( { tcdm_req, soc_req } ), + .mst_ports_resp_i ( { tcdm_rsp, soc_rsp } ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); + + localparam int unsigned TcdmFifoDepth = 1; + `AXI_ASSIGN_REQ_STRUCT(tcdm_mem_req, tcdm_req) + + axi_to_mem_split #( + .axi_req_t ( mem_req_t ), + .axi_resp_t ( mst_resp_t ), + .AddrWidth ( ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .IdWidth ( MstIdxWidth ), + .MemDataWidth ( DATA_WIDTH ), + .BufDepth ( TcdmFifoDepth ), + .HideStrb ( 1'b1 ) + ) i_axi_to_mem ( + .clk_i, + .rst_ni, + .busy_o (), + .axi_req_i ( tcdm_mem_req ), + .axi_resp_o ( tcdm_rsp ), + .mem_req_o ( { tcdm_master[0].req, tcdm_master[1].req, + tcdm_master[2].req, tcdm_master[3].req } ), + .mem_gnt_i ( { tcdm_master[0].gnt, tcdm_master[1].gnt, + tcdm_master[2].gnt, tcdm_master[3].gnt } ), + .mem_addr_o ( { tcdm_master[0].add, tcdm_master[1].add, + tcdm_master[2].add, tcdm_master[3].add } ), + .mem_wdata_o ( { tcdm_master[0].data, tcdm_master[1].data, + tcdm_master[2].data, tcdm_master[3].data } ), + .mem_strb_o ( { tcdm_master[0].be, tcdm_master[1].be, + tcdm_master[2].be, tcdm_master[3].be } ), + .mem_atop_o ( ), + .mem_we_o ( { tcdm_master_we_0, tcdm_master_we_1, + tcdm_master_we_2, tcdm_master_we_3 } ), + .mem_rvalid_i ( { tcdm_master[0].r_valid, tcdm_master[1].r_valid, + tcdm_master[2].r_valid, tcdm_master[3].r_valid } ), + .mem_rdata_i ( { tcdm_master[0].r_data, tcdm_master[1].r_data, + tcdm_master[2].r_data, tcdm_master[3].r_data } ) + ); + + // flip we polarity + assign tcdm_master[0].wen = !tcdm_master_we_0; + assign tcdm_master[1].wen = !tcdm_master_we_1; + assign tcdm_master[2].wen = !tcdm_master_we_2; + assign tcdm_master[3].wen = !tcdm_master_we_3; + + for (genvar ii=0; ii<4; ii++) begin : gen_tie_unused_tcdm_master + assign tcdm_master[ii].user = '0; + assign tcdm_master[ii].ecc = '0; + assign tcdm_master[ii].id = '0; + assign tcdm_master[ii].ereq = '0; + assign tcdm_master[ii].r_eready = '1; + end + +endmodule : dmac_wrap diff --git a/rtl/dmac_wrap.sv b/rtl/mchan_wrap.sv similarity index 82% rename from rtl/dmac_wrap.sv rename to rtl/mchan_wrap.sv index 939dad36..b79ab71b 100644 --- a/rtl/dmac_wrap.sv +++ b/rtl/mchan_wrap.sv @@ -34,16 +34,16 @@ module dmac_wrap parameter type axi_req_t = logic, parameter type axi_resp_t = logic ) -( +( input logic clk_i, input logic rst_ni, input logic test_mode_i, - - XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0], + + hci_core_intf.target ctrl_slave[0:NB_CORES-1], XBAR_PERIPH_BUS.Slave cl_ctrl_slave, XBAR_PERIPH_BUS.Slave fc_ctrl_slave, - hci_core_intf.master tcdm_master[3:0], + hci_core_intf.initiator tcdm_master[3:0], output axi_req_t ext_master_req_o, input axi_resp_t ext_master_resp_i, output logic term_event_cl_o, @@ -54,7 +54,7 @@ module dmac_wrap output logic [NB_CORES-1:0] term_irq_o, output logic busy_o ); - + // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS logic [NB_CTRLS-1:0][DATA_WIDTH-1:0] s_ctrl_bus_wdata; logic [NB_CTRLS-1:0][ADDR_WIDTH-1:0] s_ctrl_bus_add; @@ -85,16 +85,16 @@ module dmac_wrap assign s_ctrl_bus_add[i] = ctrl_slave[i].add; assign s_ctrl_bus_req[i] = ctrl_slave[i].req; - assign s_ctrl_bus_wdata[i] = ctrl_slave[i].wdata; + assign s_ctrl_bus_wdata[i] = ctrl_slave[i].data; assign s_ctrl_bus_wen[i] = ctrl_slave[i].wen; assign s_ctrl_bus_be[i] = ctrl_slave[i].be; assign s_ctrl_bus_id[i] = i; - + assign ctrl_slave[i].gnt = s_ctrl_bus_gnt[i]; assign ctrl_slave[i].r_opc = s_ctrl_bus_r_opc[i]; assign ctrl_slave[i].r_valid = s_ctrl_bus_r_valid[i]; - assign ctrl_slave[i].r_rdata = s_ctrl_bus_r_rdata[i]; + assign ctrl_slave[i].r_data = s_ctrl_bus_r_rdata[i]; end // for (genvar i=0; i */ -`include "pulp_soc_defines.sv" module periph_demux #( diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index ee990c74..20e5f9a3 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -17,130 +17,103 @@ * Angelo Garofalo */ -import pulp_cluster_package::*; -import hci_package::*; - -`include "pulp_soc_defines.sv" -`include "cluster_bus_defines.sv" `include "axi/typedef.svh" `include "axi/assign.svh" - +`include "cluster_bus_defines.sv" +`include "pulp_interfaces.sv" +`include "register_interface/typedef.svh" module pulp_cluster + import pulp_cluster_package::*; + import hci_package::*; + import rapid_recovery_pkg::*; + import fpnew_pkg::*; #( - // cluster parameters - parameter int unsigned CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - parameter int unsigned NB_CORES = 8, - parameter int unsigned NB_HWPE_PORTS = 9, - // number of DMA TCDM plugs, NOT number of DMA slave peripherals! - // Everything will go to hell if you change this! - parameter int unsigned NB_DMAS = 4, - parameter int unsigned NB_MPERIPHS = NB_MPERIPHS, - parameter int unsigned NB_SPERIPHS = NB_SPERIPHS, - - parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, - - parameter int unsigned TCDM_SIZE = 64*1024, // [B], must be 2**N - parameter int unsigned NB_TCDM_BANKS = 16, // must be 2**N - parameter int unsigned TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] - parameter int unsigned TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] - parameter bit HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster - parameter bit USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC - - // I$ parameters - parameter int unsigned SET_ASSOCIATIVE = 4, - parameter int unsigned NB_CACHE_BANKS = 2, - parameter int unsigned CACHE_LINE = 1, - parameter int unsigned CACHE_SIZE = 4096, - parameter int unsigned ICACHE_DATA_WIDTH = 128, - parameter L0_BUFFER_FEATURE = "DISABLED", - parameter MULTICAST_FEATURE = "DISABLED", - parameter SHARED_ICACHE = "ENABLED", - parameter DIRECT_MAPPED_FEATURE = "DISABLED", - parameter int unsigned L2_SIZE = 512*1024, - parameter USE_REDUCED_TAG = "TRUE", - - // core parameters - parameter bit [31:0] ROM_BOOT_ADDR = 32'h1A000000, - parameter bit [31:0] BOOT_ADDR = 32'h1C000000, - parameter int unsigned INSTR_RDATA_WIDTH = 32, - - parameter int unsigned CLUST_FPU = 1, - parameter int unsigned CLUST_FP_DIVSQRT = 1, - parameter int unsigned CLUST_SHARED_FP = 2, - parameter int unsigned CLUST_SHARED_FP_DIVSQRT = 2, - - // AXI parameters - parameter int unsigned AXI_ADDR_WIDTH = 32, - parameter int unsigned AXI_DATA_C2S_WIDTH = 64, - parameter int unsigned AXI_DATA_S2C_WIDTH = 32, - parameter int unsigned AXI_USER_WIDTH = 6, - parameter int unsigned AXI_ID_IN_WIDTH = 5, - parameter int unsigned AXI_ID_OUT_WIDTH = 7, - parameter int unsigned AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, - parameter int unsigned AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, - parameter int unsigned DC_SLICE_BUFFER_WIDTH = 8, - parameter int unsigned LOG_DEPTH = 3, - // CLUSTER TO SOC CDC AXI PARAMETER - localparam int unsigned S2C_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam int unsigned S2C_W_WIDTH = axi_pkg::w_width(AXI_DATA_S2C_WIDTH,AXI_USER_WIDTH), - localparam int unsigned S2C_R_WIDTH = axi_pkg::r_width(AXI_DATA_S2C_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam int unsigned S2C_B_WIDTH = axi_pkg::b_width(AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam int unsigned S2C_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - // CLUSTER TO SOC CDC AXI PARAMETERS - localparam int unsigned C2S_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam int unsigned C2S_W_WIDTH = axi_pkg::w_width(AXI_DATA_C2S_WIDTH,AXI_USER_WIDTH), - localparam int unsigned C2S_R_WIDTH = axi_pkg::r_width(AXI_DATA_C2S_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam int unsigned C2S_B_WIDTH = axi_pkg::b_width(AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam int unsigned C2S_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - - localparam int unsigned ASYNC_C2S_AW_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AW_WIDTH, - localparam int unsigned ASYNC_C2S_W_DATA_WIDTH = (2**LOG_DEPTH)*C2S_W_WIDTH, - localparam int unsigned ASYNC_C2S_B_DATA_WIDTH = (2**LOG_DEPTH)*C2S_B_WIDTH, - localparam int unsigned ASYNC_C2S_AR_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AR_WIDTH, - localparam int unsigned ASYNC_C2S_R_DATA_WIDTH = (2**LOG_DEPTH)*C2S_R_WIDTH, - - localparam int unsigned ASYNC_S2C_AW_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AW_WIDTH, - localparam int unsigned ASYNC_S2C_W_DATA_WIDTH = (2**LOG_DEPTH)*S2C_W_WIDTH, - localparam int unsigned ASYNC_S2C_B_DATA_WIDTH = (2**LOG_DEPTH)*S2C_B_WIDTH, - localparam int unsigned ASYNC_S2C_AR_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AR_WIDTH, - localparam int unsigned ASYNC_S2C_R_DATA_WIDTH = (2**LOG_DEPTH)*S2C_R_WIDTH, - - // TCDM and log interconnect parameters - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned ADDR_WIDTH = 32, - parameter int unsigned BE_WIDTH = DATA_WIDTH/8, - parameter int unsigned TEST_SET_BIT = 20, // bit used to indicate a test-and-set operation during a load in TCDM - parameter int unsigned ADDR_MEM_WIDTH = $clog2(TCDM_BANK_SIZE/4), // WORD address width per TCDM bank (the word width is 32 bits) - - // DMA parameters - parameter int unsigned TCDM_ADD_WIDTH = ADDR_MEM_WIDTH + $clog2(NB_TCDM_BANKS) + 2, // BYTE address width TCDM - parameter int unsigned NB_OUTSND_BURSTS = 8, - parameter int unsigned MCHAN_BURST_LENGTH = 256, - - - // peripheral and periph interconnect parameters - parameter int unsigned LOG_CLUSTER = 5, // unused - parameter int unsigned PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco - // parameter PE_ROUTING_MSB = 13, // MSB used as routing BIT in periph interco - parameter int unsigned EVNT_WIDTH = 8, // size of the event bus - parameter int unsigned REMAP_ADDRESS = 1, // for cluster virtualization - - localparam int unsigned ASYNC_EVENT_DATA_WIDTH = (2**LOG_DEPTH)*EVNT_WIDTH, - // FPU PARAMETERS - parameter int unsigned APU_NARGS_CPU = 3, - parameter int unsigned APU_WOP_CPU = 6, - parameter int unsigned WAPUTYPE = 3, - parameter int unsigned APU_NDSFLAGS_CPU = 15, - parameter int unsigned APU_NUSFLAGS_CPU = 5 -) -( + parameter pulp_cluster_package::pulp_cluster_cfg_t Cfg = pulp_cluster_package::PulpClusterDefaultCfg, + localparam int unsigned TcdmBankSize = Cfg.TcdmSize/Cfg.TcdmNumBank, + localparam int unsigned TcdmNumRows = TcdmBankSize/4, + localparam int unsigned MaxUniqId = 1, + localparam int unsigned AxiIdInWidth = pulp_cluster_package::AxiSubordinateIdwidth, + localparam int unsigned AxiIdOutWidth = pulp_cluster_package::AxiManagerIdwidth, + // CDC AXI parameters (external to cluster) + localparam int unsigned AwInWidth = axi_pkg::aw_width(Cfg.AxiAddrWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned WInWidth = axi_pkg::w_width(Cfg.AxiDataInWidth, + Cfg.AxiUserWidth), + localparam int unsigned BInWidth = axi_pkg::b_width(Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned ArInWidth = axi_pkg::ar_width(Cfg.AxiAddrWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned RInWidth = axi_pkg::r_width(Cfg.AxiDataInWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned AsyncInAwDatawidth = (2**Cfg.AxiCdcLogDepth)*AwInWidth, + localparam int unsigned AsyncInWDatawidth = (2**Cfg.AxiCdcLogDepth)*WInWidth, + localparam int unsigned AsyncInBDataWidth = (2**Cfg.AxiCdcLogDepth)*BInWidth, + localparam int unsigned AsyncInArDatawidth = (2**Cfg.AxiCdcLogDepth)*ArInWidth, + localparam int unsigned AsyncInRDataWidth = (2**Cfg.AxiCdcLogDepth)*RInWidth, + // CDC AXI parameters (cluster to external) + localparam int unsigned AwOutWidth = axi_pkg::aw_width(Cfg.AxiAddrWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned WOutWidth = axi_pkg::w_width(Cfg.AxiDataOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned BOutWidth = axi_pkg::b_width(Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned ArOutWidth = axi_pkg::ar_width(Cfg.AxiAddrWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned ROutWidth = axi_pkg::r_width(Cfg.AxiDataOutWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned AsyncOutAwDataWidth = (2**Cfg.AxiCdcLogDepth)*AwOutWidth, + localparam int unsigned AsyncOutWDataWidth = (2**Cfg.AxiCdcLogDepth)*WOutWidth, + localparam int unsigned AsyncOutBDataWidth = (2**Cfg.AxiCdcLogDepth)*BOutWidth, + localparam int unsigned AsyncOutArDataWidth = (2**Cfg.AxiCdcLogDepth)*ArOutWidth, + localparam int unsigned AsyncOutRDataWidth = (2**Cfg.AxiCdcLogDepth)*ROutWidth, + // Internal bus parameters + // TCDM data bus width (never changes) + localparam int unsigned DataWidth = 32, + // TCDM address bus width (never changes) + localparam int unsigned AddrWidth = 32, + // TCDM bank enable width (never changes) + localparam int unsigned BeWidth = DataWidth/8, + // Indicates a test-and-set operation during a load in TCDM + localparam int unsigned TestSetBit = 20, + // Word address width per TCDM bank + localparam int unsigned AddrMemWidth= $clog2(TcdmNumRows), + // Byte address width of TCDM + localparam int unsigned TcdmAddrWidth = AddrMemWidth + $clog2(Cfg.TcdmNumBank) + 2, + // Synchronous event bus size + localparam int unsigned EventWidth = 8, + // Asynchronous event bus size + localparam int unsigned AsyncEventDataWidth = (2**Cfg.AxiCdcLogDepth)*EventWidth, + // LSB used as routing BIT in periph interco + localparam int unsigned PeRoutingLsb = 10, + // FPU bus parameters + localparam int unsigned FpuNumArgs = 3, + localparam int unsigned FpuOpCodeWidth = 6, + localparam int unsigned FpuTypeWidth = 3, + localparam int unsigned FpuInFlagsWidth = 15, + localparam int unsigned FpuOutFlagsWidth = 5, + // Number of parity bits for ECC in memory banks + localparam int unsigned ParityWidth = 7, + // Number of parity bits for metadata in ECC-extended HCI + localparam int unsigned MetaParityWidth = $clog2( AddrMemWidth+2 + BeWidth +1 ) + 2, + // TCDM banks data width extended with parity for ECCs + localparam int unsigned ProtectedTcdmWidth = DataWidth + ParityWidth, + // Number of parity bits for ECC-extended HCI HWPE branch + localparam int unsigned HWPEParityWidth = ($clog2(DataWidth)+2)*Cfg.HwpeNumPorts + ($clog2(AddrWidth+(Cfg.HwpeNumPorts*DataWidth)/8+1)+2) +)( input logic clk_i, input logic rst_ni, input logic ref_clk_i, + input logic pwr_on_rst_ni, input logic pmu_mem_pwdn_i, - + input logic [3:0] base_addr_i, input logic test_mode_i, @@ -150,86 +123,89 @@ module pulp_cluster input logic [5:0] cluster_id_i, input logic fetch_en_i, - + output logic eoc_o, - + output logic busy_o, - - + + input logic axi_isolate_i, + output logic axi_isolated_o, + input logic dma_pe_evt_ack_i, output logic dma_pe_evt_valid_o, input logic dma_pe_irq_ack_i, output logic dma_pe_irq_valid_o, - + input logic pf_evt_ack_i, output logic pf_evt_valid_o, - input logic [NB_CORES-1:0] dbg_irq_valid_i, + input logic [Cfg.NumCores-1:0] dbg_irq_valid_i, + + input logic mbox_irq_i, + + input logic [Cfg.AxiCdcLogDepth:0] async_cluster_events_wptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_cluster_events_rptr_o, + input logic [AsyncEventDataWidth-1:0] async_cluster_events_data_i, - input logic [LOG_DEPTH:0] async_cluster_events_wptr_i, - output logic [LOG_DEPTH:0] async_cluster_events_rptr_o, - input logic [ASYNC_EVENT_DATA_WIDTH-1:0] async_cluster_events_data_i, - // AXI4 SLAVE //*************************************** // WRITE ADDRESS CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_aw_wptr_i, - input logic [ASYNC_S2C_AW_DATA_WIDTH-1:0] async_data_slave_aw_data_i, - output logic [LOG_DEPTH:0] async_data_slave_aw_rptr_o, - - // READ ADDRESS CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_ar_wptr_i, - input logic [ASYNC_S2C_AR_DATA_WIDTH-1:0] async_data_slave_ar_data_i, - output logic [LOG_DEPTH:0] async_data_slave_ar_rptr_o, - - // WRITE DATA CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_w_wptr_i, - input logic [ASYNC_S2C_W_DATA_WIDTH-1:0] async_data_slave_w_data_i, - output logic [LOG_DEPTH:0] async_data_slave_w_rptr_o, - - // READ DATA CHANNEL - output logic [LOG_DEPTH:0] async_data_slave_r_wptr_o, - output logic [ASYNC_S2C_R_DATA_WIDTH-1:0] async_data_slave_r_data_o, - input logic [LOG_DEPTH:0] async_data_slave_r_rptr_i, - - // WRITE RESPONSE CHANNEL - output logic [LOG_DEPTH:0] async_data_slave_b_wptr_o, - output logic [ASYNC_S2C_B_DATA_WIDTH-1:0] async_data_slave_b_data_o, - input logic [LOG_DEPTH:0] async_data_slave_b_rptr_i, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_aw_wptr_i, + input logic [AsyncInAwDatawidth-1:0] async_data_slave_aw_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_aw_rptr_o, + + // READ ADDRESS CHANNEL + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_ar_wptr_i, + input logic [AsyncInArDatawidth-1:0] async_data_slave_ar_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_ar_rptr_o, + + // WRITE DATA CHANNEL + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_w_wptr_i, + input logic [AsyncInWDatawidth-1:0] async_data_slave_w_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_w_rptr_o, + + // READ DATA CHANNEL + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_r_wptr_o, + output logic [AsyncInRDataWidth-1:0] async_data_slave_r_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_r_rptr_i, + + // WRITE RESPONSE CHANNEL + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_b_wptr_o, + output logic [AsyncInBDataWidth-1:0] async_data_slave_b_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_b_rptr_i, // AXI4 MASTER //*************************************** // WRITE ADDRESS CHANNEL - output logic [LOG_DEPTH:0] async_data_master_aw_wptr_o, - output logic [ASYNC_C2S_AW_DATA_WIDTH-1:0] async_data_master_aw_data_o, - input logic [LOG_DEPTH:0] async_data_master_aw_rptr_i, - - // READ ADDRESS CHANNEL - output logic [LOG_DEPTH:0] async_data_master_ar_wptr_o, - output logic [ASYNC_C2S_AR_DATA_WIDTH-1:0] async_data_master_ar_data_o, - input logic [LOG_DEPTH:0] async_data_master_ar_rptr_i, - - // WRITE DATA CHANNEL - output logic [LOG_DEPTH:0] async_data_master_w_wptr_o, - output logic [ASYNC_C2S_W_DATA_WIDTH-1:0] async_data_master_w_data_o, - input logic [LOG_DEPTH:0] async_data_master_w_rptr_i, - - // READ DATA CHANNEL - input logic [LOG_DEPTH:0] async_data_master_r_wptr_i, - input logic [ASYNC_C2S_R_DATA_WIDTH-1:0] async_data_master_r_data_i, - output logic [LOG_DEPTH:0] async_data_master_r_rptr_o, - - // WRITE RESPONSE CHANNEL - input logic [LOG_DEPTH:0] async_data_master_b_wptr_i, - input logic [ASYNC_C2S_B_DATA_WIDTH-1:0] async_data_master_b_data_i, - output logic [LOG_DEPTH:0] async_data_master_b_rptr_o - + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_aw_wptr_o, + output logic [AsyncOutAwDataWidth-1:0] async_data_master_aw_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_aw_rptr_i, + + // READ ADDRESS CHANNEL + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_ar_wptr_o, + output logic [AsyncOutArDataWidth-1:0] async_data_master_ar_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_ar_rptr_i, + + // WRITE DATA CHANNEL + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_w_wptr_o, + output logic [AsyncOutWDataWidth-1:0] async_data_master_w_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_w_rptr_i, + + // READ DATA CHANNEL + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_r_wptr_i, + input logic [AsyncOutRDataWidth-1:0] async_data_master_r_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_r_rptr_o, + + // WRITE RESPONSE CHANNEL + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_b_wptr_i, + input logic [AsyncOutBDataWidth-1:0] async_data_master_b_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_b_rptr_o ); //Ensure that the input AXI ID width is big enough to accomodate the accomodate the IDs of internal wiring -if (AXI_ID_IN_WIDTH < 1 + $clog2(NB_CACHE_BANKS)) - $error("AXI input ID width must be larger than 1+$clog2(NB_CACHE_BANKS) which is %d but was %d", 1 + $clog2(NB_CACHE_BANKS), AXI_ID_IN_WIDTH); +if (Cfg.AxiIdInWidth < 1 + $clog2(Cfg.iCacheNumBanks)) + $info("AXI input ID width must be larger than 1+$clog2(Cfg.iCacheNumBanks) which is %d but was %d", 1 + $clog2(Cfg.iCacheNumBanks), Cfg.AxiIdInWidth); localparam int unsigned NB_L1_CUTS = 16; localparam int unsigned RW_MARGIN_WIDTH = 4; @@ -239,228 +215,265 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; localparam bit FEATURE_STAT = 1'b0; `endif +//******************************************************** +//***************** SIGNALS DECLARATION ****************** +//******************************************************** + +logic [Cfg.NumCores-1:0] fetch_enable_reg_int; +logic [Cfg.NumCores-1:0] fetch_en_int; +logic [Cfg.NumCores-1:0][AddrWidth-1:0] boot_addr; +logic [Cfg.NumCores-1:0] dbg_core_halt; +logic [Cfg.NumCores-1:0] dbg_core_resume; +logic [Cfg.NumCores-1:0] dbg_core_halted; +logic [Cfg.NumCores-1:0] dbg_core_havereset; +logic [Cfg.NumCores-1:0] dbg_core_running; +logic [Cfg.NumCores-1:0] s_dbg_irq; +logic s_hwpe_en; +logic [$clog2(MAX_NUM_HWPES)-1:0] s_hwpe_sel; + +logic fetch_en_synch; +logic en_sa_boot_synch; +logic axi_isolate_synch; +logic eoc_synch; + +logic s_cluster_periphs_busy; +logic s_axi2mem_busy; +logic s_per2axi_busy; +logic s_axi2per_busy; +logic s_dmac_busy; +logic s_cluster_cg_en; +logic [Cfg.NumCores-1:0] s_dma_event; +logic [Cfg.NumCores-1:0] s_dma_irq; +logic [Cfg.NumCores-1:0][3:0] s_hwpe_remap_evt; +logic [Cfg.NumCores-1:0][1:0] s_hwpe_evt; +logic s_hwpe_busy; +hci_package::hci_interconnect_ctrl_t s_hci_ctrl; + +logic [Cfg.NumCores-1:0] clk_core_en; + +// CLK reset, and other control signals + +logic s_cluster_int_busy; +logic s_fregfile_disable; + +logic [Cfg.NumCores-1:0] core_busy; + +logic s_incoming_req; +logic s_isolate_cluster; +logic s_events_async; + +logic s_events_valid; +logic s_events_ready; +logic [EventWidth-1:0] s_events_data; + +// Signals Between CORE_ISLAND and INSTRUCTION CACHES +logic [Cfg.NumCores-1:0] instr_req; +logic [Cfg.NumCores-1:0][AddrWidth-1:0] instr_addr; +logic [Cfg.NumCores-1:0] instr_gnt; +logic [Cfg.NumCores-1:0] instr_r_valid; +logic [Cfg.NumCores-1:0][Cfg.iCachePrivateDataWidth-1:0] instr_r_rdata; + +logic [1:0] s_TCDM_arb_policy; +logic tcdm_sleep; + +logic[Cfg.NumCores-1:0][4:0] irq_id; +logic[Cfg.NumCores-1:0][4:0] irq_ack_id; +logic[Cfg.NumCores-1:0] irq_req; +logic[Cfg.NumCores-1:0] irq_ack; + +logic [Cfg.NumCores-1:0] s_core_dbg_irq; + + +logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] s_rw_margin_L1; + +logic s_dma_cl_event; +logic s_dma_cl_irq; +logic s_dma_fc_event; +logic s_dma_fc_irq; + +logic [Cfg.NumCores-1:0] hmr_barrier_matched; +logic [Cfg.NumCores-1:0] hmr_dmr_sw_resynch_req, hmr_tmr_sw_resynch_req; +logic [Cfg.NumCores-1:0] hmr_dmr_sw_synch_req, hmr_tmr_sw_synch_req; + +localparam hci_package::hci_size_parameter_t HciCoreSizeParam = '{ + DW: DataWidth, + AW: AddrWidth, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW +}; +localparam hci_package::hci_size_parameter_t HciHwpeSizeParam = '{ + DW: Cfg.HwpeNumPorts * DataWidth, + AW: AddrWidth, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: HWPEParityWidth, + EHW: DEFAULT_EHW +}; +/* logarithmic and peripheral interconnect interfaces */ +// ext -> log interconnect +hci_core_intf #( + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) +) s_hci_ext[0:Cfg.DmaNumPlugs-1] ( + .clk ( clk_i ) +); - //******************************************************** - //***************** SIGNALS DECLARATION ****************** - //******************************************************** - - - logic [NB_CORES-1:0] fetch_enable_reg_int; - logic [NB_CORES-1:0] fetch_en_int; - logic s_rst_n; - logic s_init_n; - logic [NB_CORES-1:0][31:0] boot_addr; - logic [NB_CORES-1:0] dbg_core_halt; - logic [NB_CORES-1:0] dbg_core_resume; - logic [NB_CORES-1:0] dbg_core_halted; - logic [NB_CORES-1:0] s_dbg_irq; - logic s_hwpe_en; - - logic s_cluster_periphs_busy; - logic s_axi2mem_busy; - logic s_per2axi_busy; - logic s_axi2per_busy; - logic s_dmac_busy; - logic s_cluster_cg_en; - logic [NB_CORES-1:0] s_dma_event; - logic [NB_CORES-1:0] s_dma_irq; - logic [NB_CORES-1:0][3:0] s_hwpe_remap_evt; - logic [NB_CORES-1:0][1:0] s_hwpe_evt; - logic s_hwpe_busy; - hci_package::hci_interconnect_ctrl_t s_hci_ctrl; - - logic [NB_CORES-1:0] clk_core_en; - logic clk_cluster; - - // CLK reset, and other control signals - - logic s_cluster_int_busy; - logic s_fregfile_disable; - - logic [NB_CORES-1:0] core_busy; - - logic s_incoming_req; - logic s_isolate_cluster; - logic s_events_async; - - logic s_events_valid; - logic s_events_ready; - logic [EVNT_WIDTH-1:0] s_events_data; - - // Signals Between CORE_ISLAND and INSTRUCTION CACHES - logic [NB_CORES-1:0] instr_req; - logic [NB_CORES-1:0][31:0] instr_addr; - logic [NB_CORES-1:0] instr_gnt; - logic [NB_CORES-1:0] instr_r_valid; - logic [NB_CORES-1:0][INSTR_RDATA_WIDTH-1:0] instr_r_rdata; - - logic [1:0] s_TCDM_arb_policy; - logic tcdm_sleep; - - logic s_dma_pe_event; - logic s_dma_pe_irq; - logic s_pf_event; - - logic[NB_CORES-1:0][4:0] irq_id; - logic[NB_CORES-1:0][4:0] irq_ack_id; - logic[NB_CORES-1:0] irq_req; - logic[NB_CORES-1:0] irq_ack; - - logic [NB_CORES-1:0] s_core_dbg_irq; - - - logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] s_rw_margin_L1; - - logic s_dma_cl_event; - logic s_dma_cl_irq; - logic s_dma_fc_event; - logic s_dma_fc_irq; - - - logic s_dma_decompr_event; - logic s_dma_decompr_irq; - - logic s_decompr_done_evt; - - assign s_dma_fc_irq = s_decompr_done_evt; - - - - /* logarithmic and peripheral interconnect interfaces */ - // ext -> log interconnect - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_ext[NB_DMAS-1:0] ( - .clk ( clk_cluster ) - ); +// periph interconnect -> slave peripherals +XBAR_PERIPH_BUS s_xbar_speriph_bus[Cfg.NumSlvPeriphs-1:0](); + +// periph interconnect -> HWPE subsystem +XBAR_PERIPH_BUS s_hwpe_cfg_bus(); - // periph interconnect -> slave peripherals - XBAR_PERIPH_BUS s_xbar_speriph_bus[NB_SPERIPHS-1:0](); +// DMA -> log interconnect +hci_core_intf #( + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) +) s_hci_dma[0:Cfg.DmaNumPlugs-1] ( + .clk ( clk_i ) +); +XBAR_TCDM_BUS s_dma_plugin_xbar_bus[Cfg.DmaNumPlugs-1:0](); + +// ext -> xbar periphs FIXME +XBAR_TCDM_BUS s_mperiph_xbar_bus[Cfg.NumMstPeriphs-1:0](); + +// periph demux +XBAR_TCDM_BUS s_mperiph_bus(); + +// cores & accelerators -> log interconnect +hci_core_intf #( + .DW ( HciHwpeSizeParam.DW ), + .AW ( HciHwpeSizeParam.AW ), + .EW ( HciHwpeSizeParam.EW ), + .EHW ( HciHwpeSizeParam.EHW ) +) s_hci_hwpe [0:0] ( + .clk ( clk_i ) +); +hci_core_intf #( + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) +) s_hci_core [0:Cfg.NumCores-1] ( + .clk ( clk_i ) +); - // periph interconnect -> HWPE subsystem - XBAR_PERIPH_BUS s_hwpe_cfg_bus(); +// cores -> periph interconnect +XBAR_PERIPH_BUS s_core_periph_bus[Cfg.NumCores-1:0](); - // DMA -> log interconnect - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_dma[NB_DMAS-1:0] ( - .clk ( clk_cluster ) - ); - XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); - - // ext -> xbar periphs FIXME - XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); - - // periph demux - XBAR_TCDM_BUS s_mperiph_bus(); - XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); - - // cores & accelerators -> log interconnect - hci_core_intf #( - .DW ( NB_HWPE_PORTS*DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_hwpe [0:0] ( - .clk ( clk_cluster ) - ); - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_core [NB_CORES-1:0] ( - .clk ( clk_cluster ) - ); +// periph interconnect -> DMA +XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); + +// periph interconnect -> HMR unit +XBAR_PERIPH_BUS s_periph_hmr_bus (); + +// periph interconnect -> TCDM scrubber +XBAR_PERIPH_BUS s_periph_tcdm_scrubber_bus (); - // cores -> periph interconnect - XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); - - // periph interconnect -> DMA - XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); - - // debug - XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); - - /* other interfaces */ - // cores -> DMA ctrl - XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); - - // cores -> event unit ctrl - XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); - - -`ifdef SHARED_FPU_CLUSTER - // apu-interconnect - // handshake signals - logic [NB_CORES-1:0] s_apu_master_req; - logic [NB_CORES-1:0] s_apu_master_gnt; - // request channel - logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; - logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; - logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; - logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; - // response channel - logic [NB_CORES-1:0] s_apu_master_rready; - logic [NB_CORES-1:0] s_apu_master_rvalid; - logic [NB_CORES-1:0][31:0] s_apu_master_rdata; - logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; +// periph interconnect -> HCI with ECC +XBAR_PERIPH_BUS s_periph_hwpe_hci_ecc_bus (); + +// debug +XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); + +/* other interfaces */ +// cores -> DMA ctrl +// FIXME: iDMA +hci_core_intf #( + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) +) s_core_dmactrl_bus [0:Cfg.NumCores-1] ( + .clk ( clk_i ) +); + +// cores -> event unit ctrl +XBAR_PERIPH_BUS s_core_euctrl_bus[Cfg.NumCores-1:0](); + +// apu-interconnect +// handshake signals +logic [Cfg.NumCores-1:0] s_apu_master_req; +logic [Cfg.NumCores-1:0] s_apu_master_gnt; +// request channel +logic [Cfg.NumCores-1:0][FpuNumArgs-1:0][31:0] s_apu_master_operands; +logic [Cfg.NumCores-1:0][FpuOpCodeWidth-1:0] s_apu_master_op; +logic [Cfg.NumCores-1:0][FpuTypeWidth-1:0] s_apu_master_type; +logic [Cfg.NumCores-1:0][FpuInFlagsWidth-1:0] s_apu_master_flags; +// response channel +logic [Cfg.NumCores-1:0] s_apu_master_rready; +logic [Cfg.NumCores-1:0] s_apu_master_rvalid; +logic [Cfg.NumCores-1:0][31:0] s_apu_master_rdata; +logic [Cfg.NumCores-1:0][FpuOutFlagsWidth-1:0] s_apu_master_rflags; + +//----------------------------------------------------------------------// +// Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // +// // +SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[Cfg.iCacheNumBanks](); +PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[Cfg.NumCores]();; +logic [Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; +logic [Cfg.NumCores-1:0] s_icache_flush_valid, s_icache_flush_ready; +snitch_icache_pkg::icache_l0_events_t [Cfg.NumCores-1:0] s_icache_l0_events; +snitch_icache_pkg::icache_l1_events_t s_icache_l1_events; +//----------------------------------------------------------------------// + +localparam TCDM_ID_WIDTH = Cfg.NumCores + Cfg.DmaNumPlugs + 4 + Cfg.HwpeNumPorts; +localparam hci_package::hci_size_parameter_t HciMemSizeParam = '{ + DW: DataWidth, + AW: AddrMemWidth+2, + BW: 8, + UW: DEFAULT_UW, + IW: TCDM_ID_WIDTH, + EW: ParityWidth+MetaParityWidth, + EHW: DEFAULT_EHW +}; + +// log interconnect -> TCDM memory banks (SRAM) +hci_core_intf #( + .AW ( AddrMemWidth+2 ), // AddrMemWidth is word-wise, +2 for byte-wise + .DW ( DataWidth ), + .BW ( 8 ), + .IW ( TCDM_ID_WIDTH ), + .EW ( ParityWidth+MetaParityWidth ) +`ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) `endif +) s_tcdm_bus_sram[0:Cfg.TcdmNumBank-1] ( + .clk ( clk_i ) +); - //----------------------------------------------------------------------// - // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // - // // - SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[NB_CACHE_BANKS](); - PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[NB_CORES](); - logic s_special_core_icache_cfg; - logic[NB_CORES-1:0] s_enable_l1_l15_prefetch; - //----------------------------------------------------------------------// - - localparam TCDM_ID_WIDTH = NB_CORES+NB_DMAS+4+NB_HWPE_PORTS; - - // log interconnect -> TCDM memory banks (SRAM) - hci_mem_intf #( - .AW (ADDR_WIDTH ), - .DW ( DATA_WIDTH ), - .BW ( 8 ), - .IW ( TCDM_ID_WIDTH ) - ) s_tcdm_bus_sram[NB_TCDM_BANKS-1:0] ( - .clk ( clk_cluster ) - ); + // SOC TO CLUSTER + `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) - //*************************************************** - /* synchronous AXI interfaces at CLUSTER/SOC interface */ - //*************************************************** - - `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_DATA_C2S_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - - `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_DATA_S2C_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) + `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) + + // CLUSTER TO SOC + `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiDataOutWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + + `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) + `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) typedef s2c_aw_chan_t c2s_in_aw_chan_t; typedef c2s_w_chan_t c2s_in_w_chan_t; typedef s2c_b_chan_t c2s_in_b_chan_t; - typedef s2c_ar_chan_t c2s_in_ar_chan_t; - `AXI_TYPEDEF_R_CHAN_T(c2s_in_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - + typedef s2c_ar_chan_t c2s_in_ar_chan_t; + + `AXI_TYPEDEF_R_CHAN_T(c2s_in_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) - `AXI_TYPEDEF_REQ_T(c2s_req_t, c2s_aw_chan_t, c2s_w_chan_t, c2s_ar_chan_t) - `AXI_TYPEDEF_RESP_T(c2s_resp_t, c2s_b_chan_t, c2s_r_chan_t) `AXI_TYPEDEF_REQ_T(c2s_in_req_t, c2s_in_aw_chan_t, c2s_in_w_chan_t, c2s_in_ar_chan_t) `AXI_TYPEDEF_RESP_T(c2s_in_resp_t, c2s_in_b_chan_t, c2s_in_r_chan_t) - `AXI_TYPEDEF_REQ_T(s2c_req_t, s2c_aw_chan_t, s2c_w_chan_t, s2c_ar_chan_t) - `AXI_TYPEDEF_RESP_T(s2c_resp_t, s2c_b_chan_t, s2c_r_chan_t) c2s_in_req_t s_data_slave_64_req; c2s_in_resp_t s_data_slave_64_resp; @@ -471,8 +484,8 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; c2s_req_t s_data_master_req; c2s_resp_t s_data_master_resp; - c2s_in_req_t s_core_instr_bus_req; - c2s_in_resp_t s_core_instr_bus_resp; + c2s_in_req_t s_core_instr_bus_req; + c2s_in_resp_t s_core_instr_bus_resp; // ***********************************************************************************************+ // ***********************************************************************************************+ @@ -509,212 +522,211 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .rst_no ( s_rst_n ), .init_no ( s_init_n ) ); - - /* fetch & busy genertion */ - assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi2mem_busy | s_dmac_busy | s_hwpe_busy; - assign busy_o = s_cluster_int_busy | (|core_busy); - assign fetch_en_int = fetch_enable_reg_int; - - /* cluster bus and attached peripherals */ - cluster_bus_wrap #( - .NB_CORES ( NB_CORES ), - .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .TCDM_SIZE ( TCDM_SIZE ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), - .slave_req_t ( c2s_in_req_t ), - .slave_resp_t ( c2s_in_resp_t ), - .master_req_t ( c2s_req_t ), - .master_resp_t ( c2s_resp_t ), - .slave_aw_chan_t ( c2s_in_aw_chan_t ), - .master_aw_chan_t ( c2s_aw_chan_t ), - .w_chan_t ( c2s_w_chan_t ), - .slave_b_chan_t ( c2s_in_b_chan_t ), - .master_b_chan_t ( c2s_b_chan_t ), - .slave_ar_chan_t ( c2s_in_ar_chan_t ), - .master_ar_chan_t ( c2s_ar_chan_t ), - .slave_r_chan_t ( c2s_in_r_chan_t ), - .master_r_chan_t ( c2s_r_chan_t ) - ) cluster_bus_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .cluster_id_i ( cluster_id_i ), - .data_slave_req_i ( s_core_ext_bus_req ), - .data_slave_resp_o ( s_core_ext_bus_resp ), - .instr_slave_req_i ( s_core_instr_bus_req ), - .instr_slave_resp_o ( s_core_instr_bus_resp ), - .dma_slave_req_i ( s_dma_ext_bus_req ), - .dma_slave_resp_o ( s_dma_ext_bus_resp ), - .ext_slave_req_i ( s_data_slave_64_req ), - .ext_slave_resp_o ( s_data_slave_64_resp ), - .tcdm_master_req_o ( s_ext_tcdm_bus_req ), - .tcdm_master_resp_i ( s_ext_tcdm_bus_resp ), - .periph_master_req_o ( s_ext_mperiph_bus_req ), - .periph_master_resp_i( s_ext_mperiph_bus_resp), - .ext_master_req_o ( s_data_master_req ), - .ext_master_resp_i ( s_data_master_resp ) - ); - axi2mem_wrap #( - .NB_DMAS ( NB_DMAS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .axi_req_t ( c2s_req_t ), - .axi_resp_t ( c2s_resp_t ) - ) axi2mem_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave_req_i ( s_ext_tcdm_bus_req ), - .axi_slave_resp_o ( s_ext_tcdm_bus_resp ), - .tcdm_master ( s_hci_ext ), - .busy_o ( s_axi2mem_busy ) - ); +/* fetch & busy genertion */ +assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi2mem_busy | s_dmac_busy | s_hwpe_busy; +assign busy_o = s_cluster_int_busy | (|core_busy); +assign fetch_en_int = fetch_enable_reg_int; + +/* cluster bus and attached peripherals */ +cluster_bus_wrap #( + .NB_MASTER ( Cfg.NumAxiOut ), + .NB_SLAVE ( Cfg.NumAxiIn ), + .NB_CORES ( Cfg.NumCores ), + .DMA_NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .TCDM_SIZE ( Cfg.TcdmSize ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_IN_WIDTH ( AxiIdInWidth ), + .AXI_ID_OUT_WIDTH ( AxiIdOutWidth ), + .BaseAddr ( Cfg.ClusterBaseAddr ), + .ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ), + .ClusterExternalOffs ( Cfg.ClusterExternalOffs ), + .slave_req_t ( c2s_in_req_t ), + .slave_resp_t ( c2s_in_resp_t ), + .master_req_t ( c2s_req_t ), + .master_resp_t ( c2s_resp_t ), + .slave_aw_chan_t ( c2s_in_aw_chan_t ), + .master_aw_chan_t ( c2s_aw_chan_t ), + .w_chan_t ( c2s_w_chan_t ), + .slave_b_chan_t ( c2s_in_b_chan_t ), + .master_b_chan_t ( c2s_b_chan_t ), + .slave_ar_chan_t ( c2s_in_ar_chan_t ), + .master_ar_chan_t ( c2s_ar_chan_t ), + .slave_r_chan_t ( c2s_in_r_chan_t ), + .master_r_chan_t ( c2s_r_chan_t ) +) cluster_bus_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .cluster_id_i ( cluster_id_i ), + .data_slave_req_i ( s_core_ext_bus_req ), + .data_slave_resp_o ( s_core_ext_bus_resp ), + .instr_slave_req_i ( s_core_instr_bus_req ), + .instr_slave_resp_o ( s_core_instr_bus_resp ), + .dma_slave_req_i ( s_dma_ext_bus_req ), + .dma_slave_resp_o ( s_dma_ext_bus_resp ), + .ext_slave_req_i ( s_data_slave_64_req ), + .ext_slave_resp_o ( s_data_slave_64_resp ), + .tcdm_master_req_o ( s_ext_tcdm_bus_req ), + .tcdm_master_resp_i ( s_ext_tcdm_bus_resp ), + .periph_master_req_o ( s_ext_mperiph_bus_req ), + .periph_master_resp_i( s_ext_mperiph_bus_resp), + .ext_master_req_o ( s_data_master_req ), + .ext_master_resp_i ( s_data_master_resp ) +); - axi2per_wrap #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .axi_req_t ( c2s_req_t ), - .axi_resp_t ( c2s_resp_t ) - ) axi2per_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave_req_i ( s_ext_mperiph_bus_req ), - .axi_slave_resp_o ( s_ext_mperiph_bus_resp ), - .periph_master ( s_mperiph_bus ), - .busy_o ( s_axi2per_busy ) - ); +axi2mem_wrap #( + .NB_DMAS ( Cfg.DmaNumPlugs ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) +) axi2mem_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_tcdm_bus_req ), + .axi_slave_resp_o ( s_ext_tcdm_bus_resp ), + .tcdm_master ( s_hci_ext ), + .busy_o ( s_axi2mem_busy ) +); +axi2per_wrap #( + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) +) axi2per_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_mperiph_bus_req ), + .axi_slave_resp_o ( s_ext_mperiph_bus_resp ), + .periph_master ( s_mperiph_bus ), + .busy_o ( s_axi2per_busy ) +); + +if (Cfg.NumMstPeriphs > 1) begin + XBAR_TCDM_BUS s_mperiph_demux_bus[Cfg.NumMstPeriphs-1:0](); per_demux_wrap #( - .NB_MASTERS ( 2 ), - .ADDR_OFFSET ( 20 ) + .NB_MASTERS ( Cfg.NumMstPeriphs ), + .ADDR_OFFSET ( 20 ) ) per_demux_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .slave ( s_mperiph_bus ), .masters ( s_mperiph_demux_bus ) ); - `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[`NB_MPERIPHS-1], s_mperiph_demux_bus[0]) - - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].req = s_mperiph_demux_bus[0].req; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].add = s_mperiph_demux_bus[0].add; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wen = s_mperiph_demux_bus[0].wen; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wdata = s_mperiph_demux_bus[0].wdata; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].be = s_mperiph_demux_bus[0].be; - - // assign s_mperiph_demux_bus[0].gnt = s_mperiph_xbar_bus[NB_MPERIPHS-1].gnt; - // assign s_mperiph_demux_bus[0].r_valid = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_valid; - // assign s_mperiph_demux_bus[0].r_opc = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_opc; - // assign s_mperiph_demux_bus[0].r_rdata = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_rdata; - -/* not used in vega - per_demux_wrap #( - .NB_MASTERS ( NB_CORES ), - .ADDR_OFFSET ( 15 ) - ) debug_interconect_i ( - .clk_i ( clk_cluster ), - .rst_ni ( rst_ni ), - .slave ( s_mperiph_demux_bus[1] ), - .masters ( s_debug_bus ) - ); - */ - per2axi_wrap #( - .NB_CORES ( NB_CORES ), - .PER_ADDR_WIDTH ( 32 ), - .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .axi_req_t ( c2s_in_req_t ), - .axi_resp_t ( c2s_in_resp_t ) - ) per2axi_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), - .axi_master_req_o ( s_core_ext_bus_req ), - .axi_master_resp_i ( s_core_ext_bus_resp ), - .busy_o ( s_per2axi_busy ) - ); - + for (genvar i = 0; i < Cfg.NumMstPeriphs; i++) begin + `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[i], s_mperiph_demux_bus[i]) + end +end else begin + `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[0], s_mperiph_bus) +end + +per2axi_wrap #( + .NB_CORES ( Cfg.NumCores ), + .PER_ADDR_WIDTH ( AddrWidth ), + .PER_ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) +) per2axi_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), + .axi_master_req_o ( s_core_ext_bus_req ), + .axi_master_resp_i ( s_core_ext_bus_resp ), + .busy_o ( s_per2axi_busy ) +); - //*************************************************** - /* cluster (log + periph) interconnect and attached peripherals */ - //*************************************************** - - cluster_interconnect_wrap #( - .NB_CORES ( NB_CORES ), - .HWPE_PRESENT ( HWPE_PRESENT ), - .NB_HWPE_PORTS ( NB_HWPE_PORTS ), - .NB_DMAS ( NB_DMAS ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - - .TEST_SET_BIT ( TEST_SET_BIT ), - .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), - - .LOG_CLUSTER ( LOG_CLUSTER ), - .PE_ROUTING_LSB ( PE_ROUTING_LSB ), - .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) - - ) cluster_interconnect_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - - .core_tcdm_slave ( s_hci_core ), - .hwpe_tcdm_slave ( s_hci_hwpe ), - .ext_slave ( s_hci_ext ), - .dma_slave ( s_hci_dma ), - - .tcdm_sram_master ( s_tcdm_bus_sram ), - - .core_periph_slave ( s_core_periph_bus ), - .mperiph_slave ( s_mperiph_xbar_bus[NB_MPERIPHS-1:0] ), - .speriph_master ( s_xbar_speriph_bus ), - - .hci_ctrl_i ( s_hci_ctrl ), - .TCDM_arb_policy_i ( s_TCDM_arb_policy ) - ); +//*************************************************** +/* cluster (log + periph) interconnect and attached peripherals */ +//*************************************************** + +cluster_interconnect_wrap #( + .NB_CORES ( Cfg.NumCores ), + .HWPE_PRESENT ( Cfg.HwpePresent ), + .NB_HWPE_PORTS ( Cfg.HwpeNumPorts ), + .NB_DMAS ( Cfg.DmaNumPlugs ), + .NB_MPERIPHS ( Cfg.NumMstPeriphs ), + .NB_TCDM_BANKS ( Cfg.TcdmNumBank ), + .NB_SPERIPHS ( Cfg.NumSlvPeriphs ), + + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BeWidth ), + .ClusterBaseAddr ( Cfg.ClusterBaseAddr ), + .ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ), + .ClusterExternalOffs ( Cfg.ClusterExternalOffs ), + + .TEST_SET_BIT ( TestSetBit ), + .ADDR_MEM_WIDTH ( AddrMemWidth ), + + .PE_ROUTING_LSB ( PeRoutingLsb ), + .CLUSTER_ALIAS ( Cfg.ClusterAlias ), + .USE_HETEROGENEOUS_INTERCONNECT ( Cfg.UseHci ), + .USE_ECC_INTERCONNECT ( Cfg.EnableECC && Cfg.ECCInterco ), + .HCI_CORE_SIZE ( HciCoreSizeParam ), + .HCI_HWPE_SIZE ( HciHwpeSizeParam ), + .HCI_MEM_SIZE ( HciMemSizeParam ) + +) cluster_interconnect_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .cluster_id_i ( '0 ), + + .hci_ecc_periph_slave ( s_periph_hwpe_hci_ecc_bus ), + + .core_tcdm_slave ( s_hci_core ), + .hwpe_tcdm_slave ( s_hci_hwpe ), + .ext_slave ( s_hci_ext ), + .dma_slave ( s_hci_dma ), + + .tcdm_sram_master ( s_tcdm_bus_sram ), + + .core_periph_slave ( s_core_periph_bus ), + .mperiph_slave ( s_mperiph_xbar_bus[Cfg.NumMstPeriphs-1:0] ), + .speriph_master ( s_xbar_speriph_bus ), + + .hci_ctrl_i ( s_hci_ctrl ), + .TCDM_arb_policy_i ( s_TCDM_arb_policy ) +); - //*************************************************** - //*********************DMAC WRAP********************* - //*************************************************** - +//*************************************************** +//*********************DMAC WRAP********************* +//*************************************************** +`ifdef TARGET_MCHAN dmac_wrap #( - .NB_CTRLS ( 10 ), - .NB_CORES ( NB_CORES ), - .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .MCHAN_BURST_LENGTH ( MCHAN_BURST_LENGTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .PE_ID_WIDTH ( NB_CORES + 1 ), - .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .axi_req_t ( c2s_in_req_t ), - .axi_resp_t ( c2s_in_resp_t ) - ) dmac_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .NB_CTRLS ( Cfg.NumCores + 2 ), + .NB_CORES ( Cfg.NumCores ), + .NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .PE_ID_WIDTH ( Cfg.NumCores + 1 ), + .TCDM_ADD_WIDTH ( TcdmAddrWidth ), + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BeWidth ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) + ) dmac_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_mode_i ( test_mode_i ), .ctrl_slave ( s_core_dmactrl_bus ), .cl_ctrl_slave ( s_periph_dma_bus[0]), @@ -725,360 +737,687 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .term_event_cl_o ( s_dma_cl_event ), .term_irq_cl_o ( s_dma_cl_irq ), .term_event_pe_o ( s_dma_fc_event ), - .term_irq_pe_o ( s_dma_pe_irq ), + .term_irq_pe_o ( s_dma_fc_irq ), .term_event_o ( s_dma_event ), .term_irq_o ( s_dma_irq ), .busy_o ( s_dmac_busy ) ); - - //*************************************************** - //**************CLUSTER PERIPHERALS****************** - //*************************************************** - - cluster_peripherals #( - .NB_CORES ( NB_CORES ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_CACHE_BANKS ( NB_CACHE_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), - .BOOT_ADDR ( BOOT_ADDR ), - .EVNT_WIDTH ( EVNT_WIDTH ), - - .NB_L1_CUTS ( NB_L1_CUTS ), - .RW_MARGIN_WIDTH ( RW_MARGIN_WIDTH ) - - ) cluster_peripherals_i ( - - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .ref_clk_i ( ref_clk_i ), - .test_mode_i ( test_mode_i ), - .busy_o ( s_cluster_periphs_busy ), - - .en_sa_boot_i ( en_sa_boot_i ), - .fetch_en_i ( fetch_en_i ), - .boot_addr_o ( boot_addr ), - .core_busy_i ( core_busy ), - .core_clk_en_o ( clk_core_en ), - - .speriph_slave ( s_xbar_speriph_bus[NB_SPERIPHS-2:0]), - .core_eu_direct_link ( s_core_euctrl_bus ), - - .dma_cfg_master ( s_periph_dma_bus ), - - .dma_cl_event_i ( s_dma_cl_event ), - .dma_cl_irq_i ( s_dma_cl_irq ), - .dma_event_i ( s_dma_event ), - .dma_irq_i ( s_dma_irq ), - - // NEW_SIGNALS .decompr_done_evt_i ( s_decompr_done_evt ), - - .dma_fc_event_i ( s_dma_fc_event ), - .dma_fc_irq_i ( ), - - .soc_periph_evt_ready_o ( s_events_ready ), - .soc_periph_evt_valid_i ( s_events_valid ), - .soc_periph_evt_data_i ( s_events_data ), - - .dbg_core_halt_o ( dbg_core_halt ), - .dbg_core_halted_i ( dbg_core_halted ), - .dbg_core_resume_o ( dbg_core_resume ), - - .eoc_o ( eoc_o ), - .cluster_cg_en_o ( s_cluster_cg_en ), - .fetch_enable_reg_o ( fetch_enable_reg_int ), - .irq_id_o ( irq_id ), - .irq_ack_id_i ( irq_ack_id ), - .irq_req_o ( irq_req ), - .irq_ack_i ( irq_ack ), - .dbg_req_i ( s_dbg_irq ), - .dbg_req_o ( s_core_dbg_irq ), - - .fregfile_disable_o ( s_fregfile_disable ), - - .TCDM_arb_policy_o ( s_TCDM_arb_policy ), - - .hwpe_cfg_master ( s_hwpe_cfg_bus ), - .hwpe_events_i ( s_hwpe_remap_evt ), - .hwpe_en_o ( s_hwpe_en ), - .hci_ctrl_o ( s_hci_ctrl ), - .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), - .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ) +`else + dmac_wrap #( + .NB_CORES ( Cfg.NumCores ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), + .PE_ID_WIDTH ( Cfg.NumCores + 1 ), + .NB_PE_PORTS ( 2 ), + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BeWidth ), + .NUM_STREAMS ( 4 ), + .TCDM_SIZE ( Cfg.TcdmSize ), + .NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .ClusterBaseAddr ( Cfg.ClusterBaseAddr ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) + ) dmac_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .pe_ctrl_slave ( s_periph_dma_bus[1:0] ), + .ctrl_slave ( s_core_dmactrl_bus ), + .tcdm_master ( s_hci_dma ), + + .ext_master_req_o ( s_dma_ext_bus_req ), + .ext_master_resp_i ( s_dma_ext_bus_resp ), + + .term_event_o ( s_dma_event ), + .term_irq_o ( s_dma_irq ), + .term_event_pe_o ( {s_dma_fc_event, s_dma_cl_event} ), + .term_irq_pe_o ( {s_dma_fc_irq, s_dma_cl_irq} ), + .busy_o ( s_dmac_busy ) ); +`endif +//*************************************************** +//**************CLUSTER PERIPHERALS****************** +//*************************************************** +cluster_peripherals #( + .NB_CORES ( Cfg.NumCores ), + .NB_HWPES ( MAX_NUM_HWPES ), + .NB_MPERIPHS ( Cfg.NumMstPeriphs ), + .NB_CACHE_BANKS ( Cfg.iCacheNumBanks), + .NB_SPERIPHS ( Cfg.NumSlvPeriphs ), + .NB_TCDM_BANKS ( Cfg.TcdmNumBank ), + .ROM_BOOT_ADDR ( Cfg.BootRomBaseAddr), + .BOOT_ADDR ( Cfg.BootAddr ), + .EVNT_WIDTH ( EventWidth ), + + .NB_L1_CUTS ( NB_L1_CUTS ), + .RW_MARGIN_WIDTH ( RW_MARGIN_WIDTH ) + +) cluster_peripherals_i ( + + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .ref_clk_i ( ref_clk_i ), + .test_mode_i ( test_mode_i ), + .busy_o ( s_cluster_periphs_busy ), + + .en_sa_boot_i ( en_sa_boot_synch ), + .fetch_en_i ( fetch_en_synch ), + .boot_addr_o ( boot_addr ), + .core_busy_i ( core_busy ), + .core_clk_en_o ( clk_core_en ), + + .speriph_slave ( s_xbar_speriph_bus[Cfg.NumSlvPeriphs-2:0] ), + .core_eu_direct_link ( s_core_euctrl_bus ), + + .dma_cfg_master ( s_periph_dma_bus ), + .hmr_cfg_master ( s_periph_hmr_bus ), + .tcdm_scrubber_cfg_master ( s_periph_tcdm_scrubber_bus ), + .hwpe_hci_ecc_cfg_master ( s_periph_hwpe_hci_ecc_bus ), + + .dma_cl_event_i ( s_dma_cl_event ), + .dma_cl_irq_i ( s_dma_cl_irq ), + .dma_event_i ( s_dma_event ), + .dma_irq_i ( s_dma_irq ), + .mbox_irq_i ( mbox_irq_synch ), + + // NEW_SIGNALS .decompr_done_evt_i ( s_decompr_done_evt ), + + .dma_fc_event_i ( s_dma_fc_event ), + .dma_fc_irq_i ( '0 ), + + .soc_periph_evt_ready_o ( s_events_ready ), + .soc_periph_evt_valid_i ( s_events_valid ), + .soc_periph_evt_data_i ( s_events_data ), + + .dbg_core_halt_o ( dbg_core_halt ), + .dbg_core_halted_i ( dbg_core_halted ), + .dbg_core_resume_o ( dbg_core_resume ), + + .eoc_o ( eoc_synch ), + .cluster_cg_en_o ( s_cluster_cg_en ), + .fetch_enable_reg_o ( fetch_enable_reg_int ), + .irq_id_o ( irq_id ), + .irq_ack_id_i ( irq_ack_id ), + .irq_req_o ( irq_req ), + .irq_ack_i ( irq_ack ), + .dbg_req_i ( s_dbg_irq ), + .dbg_req_o ( s_core_dbg_irq ), + .barrier_matched_o ( hmr_barrier_matched ), + + // HMR synch requests + .hmr_sw_resynch_req_i ( hmr_dmr_sw_resynch_req | hmr_tmr_sw_resynch_req ), + .hmr_sw_synch_req_i ( hmr_dmr_sw_synch_req | hmr_tmr_sw_synch_req ), + + .fregfile_disable_o ( s_fregfile_disable ), + + .TCDM_arb_policy_o ( s_TCDM_arb_policy ), + + .hwpe_cfg_master ( s_hwpe_cfg_bus ), + .hwpe_events_i ( s_hwpe_remap_evt ), + .hwpe_en_o ( s_hwpe_en ), + .hwpe_sel_o ( s_hwpe_sel ), + .hci_ctrl_o ( s_hci_ctrl ), + .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ), + .flush_valid_o ( s_icache_flush_valid ), + .flush_ready_i ( s_icache_flush_ready ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .l1_events_i ( s_icache_l1_events ) +); +//******************************************************** +//***************** CORE ISLANDS ************************* +//******************************************************** +//------------------------------------------------------// +// ██████╗ ██████╗ ██████╗ ███████╗ // +// ██╔════╝██╔═══██╗██╔══██╗██╔════╝ // +// ██║ ██║ ██║██████╔╝█████╗ // +// ██║ ██║ ██║██╔══██╗██╔══╝ // +// ╚██████╗╚██████╔╝██║ ██║███████╗ // +// ╚═════╝ ╚═════╝ ╚═╝ ╚═╝╚══════╝ // +//------------------------------------------------------// + +/* cluster cores + core-coupled accelerators / shared execution units */ +`REG_BUS_TYPEDEF_ALL(hmr_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) +hmr_reg_req_t hmr_reg_req; +hmr_reg_rsp_t hmr_reg_rsp; + +periph_to_reg #( + .AW ( AddrWidth ), + .DW ( DataWidth ), + .BW ( 8 ), + .IW ( Cfg.NumCores + 1 ), + .req_t ( hmr_reg_req_t ), + .rsp_t ( hmr_reg_rsp_t ) +) i_periph_to_hmr ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( s_periph_hmr_bus.req ), + .add_i ( s_periph_hmr_bus.add ), + .wen_i ( s_periph_hmr_bus.wen ), + .wdata_i ( s_periph_hmr_bus.wdata ), + .be_i ( s_periph_hmr_bus.be ), + .id_i ( s_periph_hmr_bus.id ), + .gnt_o ( s_periph_hmr_bus.gnt ), + .r_rdata_o ( s_periph_hmr_bus.r_rdata ), + .r_opc_o ( s_periph_hmr_bus.r_opc ), + .r_id_o ( s_periph_hmr_bus.r_id ), + .r_valid_o ( s_periph_hmr_bus.r_valid ), + .reg_req_o ( hmr_reg_req ), + .reg_rsp_i ( hmr_reg_rsp ) +); - //******************************************************** - //***************** CORE ISLANDS ************************* - //******************************************************** - //------------------------------------------------------// - // ██████╗ ██████╗ ██████╗ ███████╗ // - // ██╔════╝██╔═══██╗██╔══██╗██╔════╝ // - // ██║ ██║ ██║██████╔╝█████╗ // - // ██║ ██║ ██║██╔══██╗██╔══╝ // - // ╚██████╗╚██████╔╝██║ ██║███████╗ // - // ╚═════╝ ╚═════╝ ╚═╝ ╚═╝╚══════╝ // - //------------------------------------------------------// - - /* cluster cores + core-coupled accelerators / shared execution units */ - generate - for (genvar i=0; i */ +`include "hci_helpers.svh" + module tcdm_banks_wrap #( - parameter int unsigned BankSize = 256, //- -> OVERRIDE - parameter int unsigned NbBanks = 1, // --> OVERRIDE - parameter int unsigned DataWidth = 32, - parameter int unsigned AddrWidth = 32, - parameter int unsigned BeWidth = DataWidth/8, - parameter int unsigned IdWidth = 1 + parameter int unsigned BankSize = 256, //- -> OVERRIDE + parameter int unsigned NbBanks = 1, // --> OVERRIDE + parameter int unsigned DataWidth = 32, + parameter int unsigned AddrWidth = 32, + parameter int unsigned BeWidth = DataWidth/8, + parameter int unsigned IdWidth = 1, + parameter bit EnableEcc = 1, + parameter bit EccInterco = 0, + parameter int unsigned ProtectedWidth = DataWidth + 7, + parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_mode_i, - - hci_mem_intf.slave tcdm_slave[NbBanks-1:0] + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + // Scrubber + input logic [NbBanks-1:0] scrub_trigger_i, + output logic [NbBanks-1:0] scrub_fix_o, + output logic [NbBanks-1:0] scrub_uncorrectable_o, + // ECC + output logic [NbBanks-1:0] ecc_single_error_o, + output logic [NbBanks-1:0] ecc_multiple_error_o, + hci_core_intf.target tcdm_slave[0:NbBanks-1] ); - for(genvar i=0; i Don't know if this is needed, but OBI protocol requires it - logic [IdWidth-1:0] resp_id_d, resp_id_q; - assign resp_id_d = tcdm_slave[i].id; - assign tcdm_slave[i].r_id = resp_id_q; - - always_ff @(posedge clk_i or negedge rst_ni) begin : proc_resp_id - if(~rst_ni) begin - resp_id_q <= '0; - end else begin - resp_id_q <= resp_id_d; +for(genvar i=0; i= 4'h2 && addr[23:20] <= 4'h3) + && (addr >= cluster_peripherals_base + && addr <= cluster_peripherals_end) ) begin // decode peripheral to access pe_idx = addr[PE_ROUTING_MSB:PE_ROUTING_LSB]; - if (addr[23:20] == 4'h2 && addr[19:PE_ROUTING_MSB+1] == '0 && pe_idx < NB_SPERIPHS) begin + if (addr[31:20] == cluster_peripherals_base[31:20] && + addr[19:PE_ROUTING_MSB+1] == '0 && + pe_idx < NB_SPERIPHS) + begin if (pe_idx >= pulp_cluster_package::SPER_EVENT_U_ID && pe_idx < pulp_cluster_package::SPER_EVENT_U_ID + pulp_cluster_package::NB_SPERIPH_PLUGS_EU diff --git a/scripts/fault_injection_utils/pulp_extract_nets.tcl b/scripts/fault_injection_utils/pulp_extract_nets.tcl new file mode 100644 index 00000000..c566fbcc --- /dev/null +++ b/scripts/fault_injection_utils/pulp_extract_nets.tcl @@ -0,0 +1,310 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Michael Rogenmoser (michaero@iis.ee.ethz.ch) +# Riccardo Tedeschi (riccardo.tedeschi6@unibo.it) + +# Description: This file is used to extract specific groups of nets from the +# PULP Cluster, so they can be used in the fault injection script + +# Source generic netlist extraction procs +source [file join $script_base_path extract_nets.tcl] + +# == Base Path of a Cluster Core == +proc base_path {core} {return "pulp_cluster_tb/cluster_i/CORE\[$core\]/core_region_i"} + +# nets that would crash the simulation if flipped +lappend core_netlist_ignore *clk_i +lappend core_netlist_ignore *Clk_CI +lappend core_netlist_ignore *clk +lappend core_netlist_ignore *clk_ungated_i +lappend core_netlist_ignore *rst_ni +lappend core_netlist_ignore *rst_i +lappend core_netlist_ignore *rst_n +lappend core_netlist_ignore *rst +lappend core_netlist_ignore *Rst_RBI +lappend core_netlist_ignore *scan_cg_en_i +lappend core_netlist_ignore *testmode_i +lappend core_netlist_ignore *i_fpnew_bulk* + +# registers/memories: +# lappend core_netlist_ignore *_q +# lappend core_netlist_ignore *obi_pulp_adapter/ps TODOs + +# debug +lappend core_netlist_ignore *tracer_i* + +###################### +# Core Output Nets # +###################### + +proc get_core_output_nets {core} { + set core_output_netlist [get_output_netlist [base_path $core]] + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_we_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_be_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_addr_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_wdata_o + return [concat $core_output_netlist] +} + +#################### +# State Netlists # +#################### +proc get_core_state_nets {core} { + set state_list {\ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/write_pointer_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/wdata_b_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/wdata_a_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/waddr_onehot_b_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/valid_waiting \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/valid_inflight \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/utvec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/utvec_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/uepc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/ucause_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/trans_addr_q \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_wb_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_wb_delay_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_ex_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_ex_delay_is_null \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/gen_trigger_regs/tmatch_value_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/gen_trigger_regs/tmatch_control_exec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/status_cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/State_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_obi_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/state \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/ResReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/ResInv_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/RemSel_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/regfile_we_lsu \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/regfile_waddr_lsu \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_alu_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_alu_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/read_pointer_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/rdata_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/rdata_offset_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/r_instr_h \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/priv_lvl_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/prepost_useincr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/pc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/pc_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/pc_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/p_elw_busy_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_we_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_wdata_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_be_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_atop_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_addr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_signed_mode_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_sel_subword_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operator_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_is_clpx_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_imm_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_signed_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_clpx_shift_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_clpx_img_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/mult_i/mulh_CS \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/mult_i/mulh_carry_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mtvec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mtvec_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mstatus_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mscratch_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mie_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_store_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_pipe_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_minstret_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_load_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_ld_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_jump_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_jr_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_imiss_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_compressed_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_branch_taken_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_branch_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mhpmcounter_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mepc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/mem_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcountinhibit_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcounteren_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcause_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/jump_done_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/is_fetch_failed_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/is_compressed_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/int_controller_i/irq_sec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/int_controller_i/irq_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/instr_valid_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/instr_rdata_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/imm_vec_ext_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/illegal_insn_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/illegal_c_insn_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/id_valid_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/hwlp_update_pc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_start_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/hwlp_flush_cnt_delayed_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/hwlp_flush_after_resp \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_end_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/hwlp_end_4_id_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_counter_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/hwlp_addr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/frm_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/flush_cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/fflags_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/fetch_enable_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dscratch1_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dscratch0_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/depc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_req_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_req_entry_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_fsm_cs \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_force_wakeup_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dcsr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_we_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_type_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_type_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_sign_ext_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_sign_ext_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_req_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_reg_offset_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_misaligned_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_load_event_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_load_event_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/data_err_q \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/cycles \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/ctrl_fsm_cs \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/csr_op_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/csr_access_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/core_busy_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/CompInv_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/Cnt_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/BReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/branch_in_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/bmask_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/bmask_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/atop_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/AReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_operands_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_op_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_lat_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_lat \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/apu_lat \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_flags_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_vec_mode_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operator_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_is_subrot_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_is_clpx_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_clpx_shift_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/aligner_ready_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/addr_waiting \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/addr_inflight \ + } + + return [extract_netlists [subst $state_list] 1] +} + +############################## +# Get all nets from a core # +############################## + +proc get_all_core_nets {core} { + set core_path [base_path $core] + # set core_netlist_ignore_full [concat $::core_netlist_ignore [get_core_state_nets $core]] + set all_signals [extract_all_nets_recursive_filtered $core_path $::core_netlist_ignore] + # set state_signals [get_core_state_nets $core] + # set netlist_filtered {} + # foreach signal $all_signals { + # set sig_unpacked [lindex $signal 0] + # # echo $sig_unpacked + # foreach state_sig $state_signals { + # if {[string first $state_sig $sig_unpacked] == -1} { + # lappend netlist_filtered $sig_unpacked + # } + # } + # } + return $all_signals +} + +########################## +# Get all icache state # +########################## + +proc get_all_icache_state {} { + set icache_base /pulp_cluster_tb/cluster_i/icache_top_i/i_snitch_icache + + set l1_data_base $icache_base/gen_serial_lookup/i_lookup/i_data/i_tc_sram + set l1_tag_base $icache_base/gen_serial_lookup/i_lookup/gen_scm + + set l1_data [list] + for {set i 0} {$i < [examine -radix dec $l1_data_base/NumWords]} {incr i} { + lappend l1_data $l1_data_base/sram\[$i\] + } + set l1_tag [list] + for {set i 0} {$i < [examine -radix dec $icache_base/SET_COUNT]} {incr i} { + for {set j 0} {$j < [examine -radix dec $l1_tag_base/g_sets\[$i\]/i_tag/N_SCM_REGISTERS]} {incr j} { + lappend l1_tag $l1_tag_base/g_sets\[$i\]/i_tag/block_ram_gen/MemContent_int\[$j\] + } + } + + set l0_data [list] + set l0_tag [list] + for {set i 0} {$i < [examine -radix dec $icache_base/NR_FETCH_PORTS]} {incr i} { + for {set j 0} {$j < [examine -radix dec $icache_base/L0_LINE_COUNT]} {incr j} { + lappend l0_data $icache_base/gen_prefetcher\[$i\]/i_snitch_icache_l0/data\[$j\] + } + # Questa force does not work properly on arrays of structs, always forcing the first element instead of the one specified. + # Therefore, we limit our injections as well. + lappend l0_tag $icache_base/gen_prefetcher\[$i\]/i_snitch_icache_l0/tag\[0\].tag + lappend l0_tag $icache_base/gen_prefetcher\[$i\]/i_snitch_icache_l0/tag\[0\].vld + } + + return [concat $l1_data $l1_tag $l0_data $l0_tag] +} + +################## +# Memory signals # +################## + +# <------ banks ------> +# b1 b2 b3 b4 +# +----+----+----+----+ ^ +# | | | | | 3 | +# +----+----+----+----+ | +# | | | | | 2 | +# +----+----+----+----+ | words +# | | | | | 1 | +# +----+----+----+----+ | +# | | | | | 0 | +# +----+----+----+----+ v + +# == Path to a word in sram signal in tc_sram == +proc get_memory_word {bank word} {return "/pulp_cluster_tb/cluster_i/tcdm_banks_i/banks_gen\[$bank\]/gen_ecc_banks/gen_ecc_banks_and_connection/i_ecc_bank/i_bank/sram($word)"} + +proc get_memory_slice {bank_range word_range} { + set mem_slice [list] + for {set i [lindex $bank_range 0]} {$i < [lindex $bank_range end]} {incr i} { + for {set j [lindex $word_range 0]} {$j < [lindex $word_range end]} {incr j} { + lappend mem_slice [get_memory_word $i $j]} + } + return $mem_slice +} diff --git a/scripts/run_and_exit.tcl b/scripts/run_and_exit.tcl index 242b667c..5443a739 100644 --- a/scripts/run_and_exit.tcl +++ b/scripts/run_and_exit.tcl @@ -20,4 +20,11 @@ proc run_and_exit {} { quit -code [examine -radix decimal sim:/pulp_cluster_tb/ret_val(30:0)] } +if {[info exists ::env(FAULT_INJECTION)]} { + if {![info exists ::env(FAULT_INJECTION_SCRIPT)]} { + error "Error: Missing FAULT_INJECTION_SCRIPT to source!" + } + source $::env(FAULT_INJECTION_SCRIPT) +} + run_and_exit diff --git a/scripts/start.tcl b/scripts/start.tcl index 69413969..e1792a42 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -9,5 +9,12 @@ if {![info exists VSIM]} { $VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test +if {[info exists ::env(FAULT_INJECTION)]} { + if {![info exists ::env(FAULT_INJECTION_SCRIPT)]} { + error "Error: Missing FAULT_INJECTION_SCRIPT to source!" + } + source $::env(FAULT_INJECTION_SCRIPT) +} + add log -r /* run -all diff --git a/tb/dpi/elfloader.cpp b/tb/dpi/elfloader.cpp index 757c1258..4bb0fd62 100644 --- a/tb/dpi/elfloader.cpp +++ b/tb/dpi/elfloader.cpp @@ -350,4 +350,4 @@ extern "C" char read_elf(const char *filename) exit: return retval; -} \ No newline at end of file +} diff --git a/tb/mock_uart_axi.sv b/tb/mock_uart_axi.sv index dc730db3..80406a87 100644 --- a/tb/mock_uart_axi.sv +++ b/tb/mock_uart_axi.sv @@ -26,7 +26,7 @@ module mock_uart_axi #( logic uart_penable; logic uart_pwrite; - logic [31:0] uart_paddr; + logic [AxiAw-1:0] uart_paddr; logic uart_psel; logic [31:0] uart_pwdata; logic [31:0] uart_prdata; @@ -111,7 +111,7 @@ module mock_uart_axi #( .rst_ni ( rst_ni ), .penable_i ( uart_penable ), .pwrite_i ( uart_pwrite ), - .paddr_i ( uart_paddr ), + .paddr_i ( uart_paddr[31:0] ), .psel_i ( uart_psel ), .pwdata_i ( uart_pwdata ), .prdata_o ( uart_prdata ), diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 757d4aab..6187826e 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -25,14 +25,15 @@ import "DPI-C" function byte get_section(output longint address, output longint import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); module pulp_cluster_tb; - + + import pulp_cluster_package::*; import uvm_pkg::*; import axi_pkg::*; logic s_clk; logic s_rstn; logic s_rstn_cl; - + localparam time SYS_TCK = 8ns; localparam time SYS_TA = 2ns; localparam time SYS_TT = SYS_TCK - 2ns; @@ -44,8 +45,8 @@ module pulp_cluster_tb; .clk_o ( s_clk ), .rst_no ( s_rstn ) ); - - localparam AxiAw = 32; + + localparam AxiAw = 48; localparam AxiDw = 64; localparam AxiIw = 6; localparam NMst = 2; @@ -53,8 +54,18 @@ module pulp_cluster_tb; localparam AxiIwMst = AxiIw + $clog2(NMst); localparam AxiWideBeWidth = AxiDw/8; localparam AxiWideByteOffset = $clog2(AxiWideBeWidth); - localparam AxiUw = 1; - + localparam AxiUw = 10; + + localparam bit[AxiAw-1:0] ClustBase = 'h10000000; + localparam bit[AxiAw-1:0] ClustPeriphOffs = 'h00200000; + localparam bit[AxiAw-1:0] ClustExtOffs = 'h00400000; + localparam bit[ 5:0] ClustIdx = 'h0; + localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase; + localparam bit[AxiAw-1:0] L2BaseAddr = 'h1C000000; + localparam bit[AxiAw-1:0] L2Size = 'h00100000; + localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; + localparam bit[AxiAw-1:0] ClustReturnInt = 'h10200100; + typedef logic [AxiAw-1:0] axi_addr_t; typedef logic [AxiDw-1:0] axi_data_t; typedef logic [AxiDw/8-1:0] axi_strb_t; @@ -75,20 +86,20 @@ module pulp_cluster_tb; `AXI_TYPEDEF_AR_CHAN_T(ar_m_chan_t, axi_addr_t, axi_m_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(r_m_chan_t, axi_data_t, axi_m_id_t, axi_user_t) `AXI_TYPEDEF_REQ_T(axi_m_req_t, aw_m_chan_t, w_chan_t, ar_m_chan_t) - `AXI_TYPEDEF_RESP_T(axi_m_resp_t, b_m_chan_t, r_m_chan_t) + `AXI_TYPEDEF_RESP_T(axi_m_resp_t, b_m_chan_t, r_m_chan_t) typedef logic [AxiAw-1:0] addr_t; - typedef logic [AxiDw-1:0] data_t; + typedef logic [AxiDw-1:0] data_t; data_t memory [bit [31:0]]; int sections [bit [31:0]]; - + string binary ; - + logic s_cluster_en_sa_boot ; logic s_cluster_fetch_en ; logic s_cluster_eoc ; logic s_cluster_busy ; - + AXI_BUS #( .AXI_ADDR_WIDTH( AxiAw ), .AXI_DATA_WIDTH( AxiDw ), @@ -129,10 +140,10 @@ module pulp_cluster_tb; // Behavioural slaves axi_m_req_t axi_memreq; axi_m_resp_t axi_memrsp; - + `AXI_ASSIGN_TO_REQ(axi_memreq, axi_master[1]) `AXI_ASSIGN_FROM_RESP(axi_master[1], axi_memrsp) - + axi_sim_mem #( .AddrWidth ( AxiAw ), .DataWidth ( AxiDw ), @@ -140,8 +151,9 @@ module pulp_cluster_tb; .UserWidth ( AxiUw ), .axi_req_t ( axi_m_req_t ), .axi_rsp_t ( axi_m_resp_t ), + .UninitializedData ( "random" ), .ApplDelay ( SYS_TA ), - .AcqDelay ( SYS_TT ) + .AcqDelay ( SYS_TT ) ) sim_mem ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), @@ -174,31 +186,33 @@ module pulp_cluster_tb; .test_i ( '0 ), .uart ( axi_master[0] ) ); - + // XBAR - localparam int unsigned NumRules = NSlv+1; - typedef axi_pkg::xbar_rule_32_t rule_t; + localparam int unsigned NumRules = NSlv; + + typedef struct packed { + int unsigned idx; + logic [AxiAw-1:0] start_addr; + logic [AxiAw-1:0] end_addr; + } rule_t; + rule_t [NumRules-1:0] addr_map; assign addr_map[0] = '{ // UART idx: 0, - start_addr: 32'h4000_0000, - end_addr: 32'h4000_ffff + start_addr: 'h03002000, + end_addr: 'h03003000 }; assign addr_map[1] = '{ // 512KiB L2SPM idx: 1, - start_addr: 32'h1C00_0000, - end_addr: 32'h1C08_0000 + start_addr: L2BaseAddr, + end_addr: L2BaseAddr + L2Size }; assign addr_map[2] = '{ // Pulp Cluster idx: 2, - start_addr: 32'h1000_0000, - end_addr: 32'h1004_0000 - }; - assign addr_map[3] = '{ // Return address - idx: 1, // Just put it in axi_sim_mem - start_addr: 32'h1A10_4000, - end_addr: 32'h1A10_40F0 + start_addr: ClustBaseAddr, + end_addr: ClustBaseAddr + ClustExtOffs }; + // Crossbar Configuration and Instantiation localparam axi_pkg::xbar_cfg_t XbarCfg = '{ NoSlvPorts: NMst, @@ -243,7 +257,7 @@ module pulp_cluster_tb; .slv ( axi_master[2] ), .mst ( soc_to_cluster_axi_bus ) ); - + axi_cdc_src_intf #( .AXI_ADDR_WIDTH ( AxiAw ), .AXI_DATA_WIDTH ( AxiDw ), @@ -256,7 +270,7 @@ module pulp_cluster_tb; .src ( soc_to_cluster_axi_bus ), .dst ( async_soc_to_cluster_axi_bus ) ); - + axi_cdc_dst_intf #( .AXI_ADDR_WIDTH ( AxiAw ), .AXI_DATA_WIDTH ( AxiDw ), @@ -270,104 +284,136 @@ module pulp_cluster_tb; .dst ( axi_slave[1] ) ); - pulp_cluster #( - .NB_CORES ( `NB_CORES ), - .NB_HWPE_PORTS ( 4 ), - .NB_DMAS ( `NB_DMAS ), - .HWPE_PRESENT ( 0 ), - .TCDM_SIZE ( 128*1024 ), - .NB_TCDM_BANKS ( 16 ), - .SET_ASSOCIATIVE ( 4 ), - .CACHE_LINE ( 1 ), - .CACHE_SIZE ( 4096 ), - .ICACHE_DATA_WIDTH ( 128 ), - .L0_BUFFER_FEATURE ( "DISABLED" ), - .MULTICAST_FEATURE ( "DISABLED" ), - .SHARED_ICACHE ( "ENABLED" ), - .DIRECT_MAPPED_FEATURE ( "DISABLED" ), - .L2_SIZE ( 32'h10000 ), - .ROM_BOOT_ADDR ( 32'h1A000000 ), - .BOOT_ADDR ( 32'h1c008080 ), - .INSTR_RDATA_WIDTH ( 32 ), - .CLUST_FPU ( `CLUST_FPU ), - .CLUST_FP_DIVSQRT ( `CLUST_FP_DIVSQRT ), - .CLUST_SHARED_FP ( `CLUST_SHARED_FP ), - .CLUST_SHARED_FP_DIVSQRT ( `CLUST_SHARED_FP_DIVSQRT ), - .AXI_ADDR_WIDTH ( AxiAw ), - .AXI_DATA_S2C_WIDTH ( AxiDw ), - .AXI_DATA_C2S_WIDTH ( AxiDw ), - .AXI_USER_WIDTH ( AxiUw ), - .AXI_ID_IN_WIDTH ( AxiIw-2 ), - .AXI_ID_OUT_WIDTH ( AxiIw ), - .LOG_DEPTH ( 3 ), - .DATA_WIDTH ( 32 ), - .ADDR_WIDTH ( 32 ), - .LOG_CLUSTER ( 3 ), - .PE_ROUTING_LSB ( 10 ), - .EVNT_WIDTH ( 8 ) - ) cluster_i ( - .clk_i ( s_clk ), - .rst_ni ( s_rstn ), - .ref_clk_i ( s_clk ), - - .pmu_mem_pwdn_i ( 1'b0 ), - - .base_addr_i ( '0 ), - - .dma_pe_evt_ack_i ( '1 ), - .dma_pe_evt_valid_o ( ), - - .dma_pe_irq_ack_i ( 1'b1 ), - .dma_pe_irq_valid_o ( ), - - .dbg_irq_valid_i ( '0 ), - - .pf_evt_ack_i ( 1'b1 ), - .pf_evt_valid_o ( ), - - .async_cluster_events_wptr_i ( '0 ), - .async_cluster_events_rptr_o ( ), - .async_cluster_events_data_i ( '0 ), - - .en_sa_boot_i ( s_cluster_en_sa_boot ), - .test_mode_i ( 1'b0 ), - .fetch_en_i ( s_cluster_fetch_en ), - .eoc_o ( s_cluster_eoc ), - .busy_o ( s_cluster_busy ), - .cluster_id_i ( 6'b000000 ), - - .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), - .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), - .async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ), - .async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ), - .async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ), - .async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ), - .async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ), - .async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ), - .async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ), - .async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ), - .async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ), - .async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ), - .async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ), - .async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ), - .async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ), - - .async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ), - .async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ), - .async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ), - .async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ), - .async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ), - .async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ), - .async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ), - .async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ), - .async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ), - .async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ), - .async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ), - .async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ), - .async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ), - .async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ), - .async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data ) - ); + localparam pulp_cluster_cfg_t PulpClusterCfg = '{ + CoreType: pulp_cluster_package::RISCY, + NumCores: `NB_CORES, + DmaNumPlugs: `NB_DMAS, + DmaNumOutstandingBursts: 8, + DmaBurstLength: 256, + NumMstPeriphs: `NB_MPERIPHS, + NumSlvPeriphs: `NB_SPERIPHS, + ClusterAlias: 1, + ClusterAliasBase: 'h0, + NumSyncStages: 3, + UseHci: 1, + TcdmSize: 128*1024, + TcdmNumBank: 16, + HwpePresent: 1, + HwpeCfg: '{NumHwpes: 3, HwpeList: {SOFTEX, NEUREKA, REDMULE}}, + HwpeNumPorts: 9, + HMRPresent: 1, + HMRTmrEnabled: 1, + EnableECC: 1, + ECCInterco: 1, + iCacheNumBanks: 2, + iCacheNumLines: 1, + iCacheNumWays: 4, + iCacheSharedSize: 4*1024, + iCachePrivateSize: 512, + iCachePrivateDataWidth: 32, + EnableReducedTag: 1, + L2Size: 1000*1024, + DmBaseAddr: 'h60203000, + BootRomBaseAddr: BootAddr, + BootAddr: BootAddr, + EnablePrivateFpu: 1, + EnablePrivateFpDivSqrt: 0, + EnableSharedFpu: 0, + EnableSharedFpDivSqrt: 0, + NumSharedFpu: 0, + NumAxiIn: NumAxiSubordinatePorts, + NumAxiOut: NumAxiManagerPorts, + AxiIdInWidth: AxiIw-2, + AxiIdOutWidth:AxiIw, + AxiAddrWidth: AxiAw, + AxiDataInWidth: AxiDw, + AxiDataOutWidth: AxiDw, + AxiUserWidth: AxiUw, + AxiMaxInTrans: 64, + AxiMaxOutTrans: 64, + AxiCdcLogDepth: 3, + AxiCdcSyncStages: 3, + SyncStages: 3, + ClusterBaseAddr: ClustBaseAddr, + ClusterPeriphOffs: ClustPeriphOffs, + ClusterExternalOffs: ClustExtOffs, + EnableRemapAddress: 0, + default: '0 + }; + + pulp_cluster +`ifdef USE_PULP_PARAMETERS + #( + .Cfg ( PulpClusterCfg ) + ) +`endif + cluster_i ( + .clk_i ( s_clk ), + .rst_ni ( s_rstn ), + .pwr_on_rst_ni ( s_rstn ), + .ref_clk_i ( s_clk ), + .axi_isolate_i ( '0 ), + .axi_isolated_o ( ), + + .pmu_mem_pwdn_i ( 1'b0 ), + + .base_addr_i ( ClustBase[31:28] ), + + .dma_pe_evt_ack_i ( '1 ), + .dma_pe_evt_valid_o ( ), + + .dma_pe_irq_ack_i ( 1'b1 ), + .dma_pe_irq_valid_o ( ), + + .dbg_irq_valid_i ( '0 ), + .mbox_irq_i ( '0 ), + + .pf_evt_ack_i ( 1'b1 ), + .pf_evt_valid_o ( ), + + .async_cluster_events_wptr_i ( '0 ), + .async_cluster_events_rptr_o ( ), + .async_cluster_events_data_i ( '0 ), + + .en_sa_boot_i ( s_cluster_en_sa_boot ), + .test_mode_i ( 1'b0 ), + .fetch_en_i ( s_cluster_fetch_en ), + .eoc_o ( s_cluster_eoc ), + .busy_o ( s_cluster_busy ), + .cluster_id_i ( ClustIdx ), + + .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), + .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), + .async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ), + .async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ), + .async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ), + .async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ), + .async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ), + .async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ), + .async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ), + .async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ), + .async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ), + .async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ), + .async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ), + .async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ), + .async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ), + + .async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ), + .async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ), + .async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ), + .async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ), + .async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ), + .async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ), + .async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ), + .async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ), + .async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ), + .async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ), + .async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ), + .async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ), + .async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ), + .async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ), + .async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data ) + ); // Load ELF binary file task load_binary; @@ -422,10 +468,10 @@ module pulp_cluster_tb; initial begin assign s_cluster_en_sa_boot = 1'b0; - assign s_cluster_fetch_en = 1'b0; + assign s_cluster_fetch_en = 1'b0; axi_master_drv.reset_master(); axi_master_drv.reset_slave(); - + @(posedge s_rstn); @(posedge s_clk); @@ -433,79 +479,94 @@ module pulp_cluster_tb; $display("[TB] Testing %s", binary); load_binary(binary); - + foreach (sections[addr]) begin $display("[TB] Writing %h with %0d words", addr << 3, sections[addr]); // word = 8 bytes here for (int i = 0; i < sections[addr]; i++) begin - + aw_beat.ax_addr = ( addr << 3 ) + ( i * 8 ); aw_beat.ax_len = '0; aw_beat.ax_burst = axi_pkg::BURST_INCR; aw_beat.ax_size = 4'h3; - + w_beat.w_data = memory[addr + i][63:0]; w_beat.w_strb = '1; w_beat.w_last = '1; - + axi_master_drv.send_aw(aw_beat); axi_master_drv.send_w(w_beat); @(posedge s_clk); axi_master_drv.recv_b(b_beat); end // for (int i = 0; i < sections[addr]; i++) - $display("[TB] Completed\n"); - end + $display("[TB] Completed\n"); + end $display("[TB] Initialize ret_val\n"); - - aw_beat.ax_addr = 32'h1A10_40A0; + + aw_beat.ax_addr = ClustReturnInt; aw_beat.ax_len = '0; aw_beat.ax_burst = axi_pkg::BURST_INCR; aw_beat.ax_size = 4'h3; - - w_beat.w_data = '0; + + w_beat.w_data = '1; w_beat.w_strb = '1; w_beat.w_last = '1; - + axi_master_drv.send_aw(aw_beat); axi_master_drv.send_w(w_beat); @(posedge s_clk); axi_master_drv.recv_b(b_beat); $display("[TB] Launch cluster\n"); - + + for (int i = 0; i < `NB_CORES; i++) begin + aw_beat.ax_addr = ClustBase + ClustPeriphOffs + 'h40 + i*4; + aw_beat.ax_len = '0; + aw_beat.ax_burst = axi_pkg::BURST_INCR; + aw_beat.ax_size = 4'h3; + + w_beat.w_data = BootAddr; + w_beat.w_strb = 'h1; + w_beat.w_last = 'h1; + + axi_master_drv.send_aw(aw_beat); + axi_master_drv.send_w(w_beat); + @(posedge s_clk); + axi_master_drv.recv_b(b_beat); + end + @(negedge s_clk); - assign s_cluster_en_sa_boot = 1'b1; + assign s_cluster_en_sa_boot = 1'b1; @(negedge s_clk); - assign s_cluster_fetch_en = 1'b1; + assign s_cluster_fetch_en = 1'b1; ret_val = '0; - while(~ret_val[31]) begin - - ar_beat.ax_addr = 32'h1A10_40A0; - ar_beat.ax_len = '0; - ar_beat.ax_burst = axi_pkg::BURST_INCR; - ar_beat.ax_size = 4'h2; - - axi_master_drv.send_ar(ar_beat); - @(posedge s_clk); - axi_master_drv.recv_r(r_beat); - ret_val = r_beat.r_data; - repeat(1000) - @(posedge s_clk); - + while(~s_cluster_eoc) begin + repeat(1) + @(posedge s_clk); end - + + ar_beat.ax_addr = ClustReturnInt; + ar_beat.ax_len = '0; + ar_beat.ax_burst = axi_pkg::BURST_INCR; + ar_beat.ax_size = 4'h2; + + axi_master_drv.send_ar(ar_beat); + @(posedge s_clk); + axi_master_drv.recv_r(r_beat); + ret_val = r_beat.r_data; + $display("[TB] Received ret_val: %d\n", ret_val[30:0]); - + if(ret_val[30:0]==0) begin $display("[TB] Test passed\n"); $finish; end else begin $fatal(1,"[TB] Test not passed: ret_val!=0\n"); end - - end // initial begin - - -endmodule // pulp_cluster_tb + + end + + +endmodule : pulp_cluster_tb diff --git a/wave.do b/wave.do new file mode 100644 index 00000000..77679d61 --- /dev/null +++ b/wave.do @@ -0,0 +1,1966 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/rst_ni +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/ref_clk_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pwr_on_rst_ni +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pmu_mem_pwdn_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/base_addr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/test_mode_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/en_sa_boot_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/cluster_id_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/eoc_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/busy_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolate_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolated_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_evt_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_evt_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_irq_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_irq_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pf_evt_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pf_evt_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_irq_valid_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/mbox_irq_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_enable_reg_int +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_int +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/boot_addr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_halt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_resume +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_halted +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_havereset +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_running +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dbg_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/en_sa_boot_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolate_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/eoc_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_periphs_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_axi2mem_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_per2axi_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_axi2per_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dmac_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_cg_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_remap_evt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_evt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hci_ctrl +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_core_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_int_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_fregfile_disable +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_incoming_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_isolate_cluster +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_async +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_valid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_ready +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_data +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_addr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_gnt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_r_valid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_r_rdata +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_TCDM_arb_policy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/tcdm_sleep +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_id +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_ack_id +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_ack +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_core_dbg_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_rw_margin_L1 +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_cl_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_cl_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_fc_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_fc_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_gnt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_operands +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_op +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_type +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_flags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rready +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rvalid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rdata +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rflags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_special_core_icache_cfg +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_enable_l1_l15_prefetch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/mbox_irq_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr_reg_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr_reg_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_data_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/demux_data_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_data_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/demux_data_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/sys2hmr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr2core +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr2sys +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core2hmr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_core +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/setback +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/ext_perf +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__operands +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__op +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__type +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__flags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__rflags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/src_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_src_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/src_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_src_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_resp +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/clk_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/rst_ni +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/reg_request_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/reg_response_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_resynch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_sw_synch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_cores_synch_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_error_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_resynch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_sw_synch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_cores_synch_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_inputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_nominal_outputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_bus_outputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_fetch_en_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/enable_bus_vote_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_setback_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_inputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_nominal_outputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_bus_outputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_nominal_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_bus_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_nominal_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_bus_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_single_mismatch +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_en_as_master +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_dmr +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_tmr +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_core_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_core_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_setback_q +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_grp_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_setback_q +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_grp_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sp_store_is_zero +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sp_store_will_be_zero +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/top_register_reqs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/top_register_resps +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/hmr_hw2reg +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/hmr_reg2hw +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_register_reqs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_register_resps +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_reg2hw +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_hw2reg +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_incr_mismatches +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_incr_mismatches +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/clk_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/rst_ni +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/ref_clk_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/test_mode_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/en_sa_boot_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fetch_en_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/core_busy_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/core_clk_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fregfile_disable_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/boot_addr_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_cg_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/busy_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/mbox_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_cl_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_cl_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_fc_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_fc_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_ready_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_valid_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_data_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_halted_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_halt_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_resume_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eoc_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fetch_enable_reg_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_id_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_ack_id_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_req_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_ack_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_req_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_req_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/TCDM_arb_policy_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hwpe_events_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hwpe_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hci_ctrl_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/enable_l1_l15_prefetch_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_out_lo_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_out_hi_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_in_lo_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_in_hi_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_cluster_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_acc_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_dma_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_fetch_en_cc +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_req +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_add +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_wen +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_wdata +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_be +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_id +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_valid +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_ready +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_data +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/clk_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rst_ni +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/en_sa_boot_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/event_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/eoc_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/cluster_cg_en_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hwpe_en_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fregfile_disable_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halt_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_resume_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_enable_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_addr_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/TCDM_arb_policy_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rvalid_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rvalid_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/id_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/id_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rdata_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rdata_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/dbg_halt_mask_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/dbg_halt_mask_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_any_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_any_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/eoc_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/event_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hwpe_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fregfile_disable_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_addr_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_sync +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/start_fetch +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/start_boot +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/cluster_cg_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/TCDM_arb_policy_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halt_rising_edge +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_cs +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_ns +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/clk +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/rst_n +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/test_mode +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/evt_o +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/busy_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/clk_i +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/rst_ni +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/test_mode_i +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/evt_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/fsm_z_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/ctrl_z_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/enable +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/clear +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/soft_clear +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_buffer_depth_count +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_buffer_load +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_fill +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_store +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_shift +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_load +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/reg_enable +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/gate_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_cols_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_cols_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_rows_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_rows_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_streamer +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_streamer +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_scheduler +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_scheduler +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/reg_file +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_fifo_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_clock +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_d +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_bias_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/ctrl_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/accumulate +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/engine_flush +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/fma_is_boxed +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/noncomp_is_boxed +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/stage1_rnd +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/stage2_rnd +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op1 +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op2 +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op_mod +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_tag +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_aux +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_valid +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_ready +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flush +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/status +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/extension_bit +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/class_mask +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/is_class +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_tag +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_aux +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_valid +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_ready +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/setback_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clk_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/rst_ni} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/setback_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/hart_id} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_sleep} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/FILE} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/destination} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[1]} -group core_region -group core -radix unsigned {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/clk_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clk_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/rst_ni} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/setback_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/hart_id} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_sleep} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/FILE} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/destination} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/clk_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clk_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/rst_ni} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/setback_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/hart_id} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_sleep} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/FILE} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/destination} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/clk_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/clk_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/clk_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/rst_ni} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/setback_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/hart_id} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_sleep} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/boot_addr} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/FILE} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/destination} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[11]} -group core -radix unsigned {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {226440000000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 184 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {225717754960 ps} {227423563880 ps}