From 0181796a1062da7bfa280eea9bbaaf2192b41d56 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Fri, 29 Oct 2021 20:45:33 +0200 Subject: [PATCH] occamy: Expose `tc_sram` configuration inputs per memory type (pulp-platform/snitch#303) * tc_sram: Add implementation key and IO * vendor: Add `tech_cells_generic` patch * cluster: Add, propagate configurable memory cut configuration ports * doc: Regenerate schema-doc * occamy: Extend wth SRAM config ports at top * occamy: Connect CVA6 SRAM config * occamy: Reorder, count memory config structs * occamy+cluster: Further fixes * cva6: Add SRAM config ports * vendor: Add CVA6 patch * tc_sram: Add implementation stubs to fpga module * vendor: Add `tc_sram` FPGA patch --- ...occamy-properties-snitch-cluster-schema.md | 88 +++- ...itch_cluster-properties-sram_cfg_expose.md | 15 + ...es-sram_cfg_fields-additionalproperties.md | 19 + ...ster-properties-sram_cfg_fields-default.md | 15 + ...roperties-sram_cfg_fields-propertynames.md | 25 + ...itch_cluster-properties-sram_cfg_fields.md | 57 +++ docs/schema-doc/snitch_cluster.md | 88 +++- docs/schema-doc/snitch_cluster.schema.json | 2 +- hw/occamy/occamy_cva6.sv.tpl | 13 +- hw/occamy/occamy_pkg.sv.tpl | 26 + hw/occamy/occamy_quadrant_s1.sv.tpl | 13 +- hw/occamy/occamy_top.sv.tpl | 17 +- .../src/snitch_read_only_cache.sv | 20 +- hw/spm_interface/src/spm_1p_adv.sv | 13 +- hw/vendor/openhwgroup_cva6/src/ariane.sv | 27 +- .../src/cache_subsystem/cva6_icache.sv | 13 +- .../cva6_icache_axi_wrapper.sv | 12 +- .../cache_subsystem/std_cache_subsystem.sv | 20 +- .../src/cache_subsystem/std_nbdcache.sv | 16 +- .../src/cache_subsystem/wt_cache_subsystem.sv | 18 +- .../src/cache_subsystem/wt_dcache.sv | 13 +- .../src/cache_subsystem/wt_dcache_mem.sv | 13 +- .../0014-cva6-Add-SRAM-config-ports.patch | 461 ++++++++++++++++++ ...c_sram-Add-implementation-key-and-IO.patch | 74 +++ ...-implementation-stubs-to-fpga-module.patch | 51 ++ .../src/fpga/tc_sram_xilinx.sv | 14 + .../src/rtl/tc_sram.sv | 23 + target/sim/test/testharness.sv | 1 + target/sim/test/testharness.sv.tpl | 1 + util/solder/solder.py | 11 +- util/solder/solder.snitch_ro_cache.sv.tpl | 8 +- 31 files changed, 1112 insertions(+), 75 deletions(-) create mode 100644 docs/schema-doc/snitch_cluster-properties-sram_cfg_expose.md create mode 100644 docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-additionalproperties.md create mode 100644 docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-default.md create mode 100644 docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-propertynames.md create mode 100644 docs/schema-doc/snitch_cluster-properties-sram_cfg_fields.md create mode 100644 hw/vendor/patches/openhwgroup_cva6/0014-cva6-Add-SRAM-config-ports.patch create mode 100644 hw/vendor/patches/pulp_platform_tech_cells_generic/0004-tc_sram-Add-implementation-key-and-IO.patch create mode 100644 hw/vendor/patches/pulp_platform_tech_cells_generic/0005-tc_sram-Add-implementation-stubs-to-fpga-module.patch diff --git a/docs/schema-doc/occamy-properties-snitch-cluster-schema.md b/docs/schema-doc/occamy-properties-snitch-cluster-schema.md index 90da93bda..b0f45f9e0 100644 --- a/docs/schema-doc/occamy-properties-snitch-cluster-schema.md +++ b/docs/schema-doc/occamy-properties-snitch-cluster-schema.md @@ -16,24 +16,26 @@ Base description of a Snitch cluster and its internal structure and configuratio # Snitch Cluster Schema Properties -| Property | Type | Required | Nullable | Defined by | -| :------------------------------------------------ | :------- | :------- | :------------- | :--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -| [name](#name) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-name.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/name") | -| [boot_addr](#boot_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-boot_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/boot_addr") | -| [cluster_base_addr](#cluster_base_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-cluster_base_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/cluster_base_addr") | -| [tcdm](#tcdm) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-tcdm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/tcdm") | -| [addr_width](#addr_width) | `number` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-addr_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/addr_width") | -| [data_width](#data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/data_width") | -| [dma_data_width](#dma_data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_data_width") | -| [id_width_in](#id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/id_width_in") | -| [dma_id_width_in](#dma_id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_id_width_in") | -| [hart_base_id](#hart_base_id) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hart_base_id.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hart_base_id") | -| [mode](#mode) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-mode.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/mode") | -| [vm](#vm) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-vm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/vm") | -| [dma_axi_req_fifo_depth](#dma_axi_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_axi_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_axi_req_fifo_depth") | -| [dma_req_fifo_depth](#dma_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_req_fifo_depth") | -| [timing](#timing) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-timing-and-latency-tuning-parameter.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/timing") | -| [hives](#hives) | `array` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hives.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hives") | +| Property | Type | Required | Nullable | Defined by | +| :------------------------------------------------ | :-------- | :------- | :------------- | :--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| [name](#name) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-name.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/name") | +| [boot_addr](#boot_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-boot_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/boot_addr") | +| [cluster_base_addr](#cluster_base_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-cluster_base_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/cluster_base_addr") | +| [tcdm](#tcdm) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-tcdm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/tcdm") | +| [addr_width](#addr_width) | `number` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-addr_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/addr_width") | +| [data_width](#data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/data_width") | +| [dma_data_width](#dma_data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_data_width") | +| [id_width_in](#id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/id_width_in") | +| [dma_id_width_in](#dma_id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_id_width_in") | +| [hart_base_id](#hart_base_id) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hart_base_id.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hart_base_id") | +| [mode](#mode) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-mode.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/mode") | +| [vm](#vm) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-vm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/vm") | +| [dma_axi_req_fifo_depth](#dma_axi_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_axi_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_axi_req_fifo_depth") | +| [dma_req_fifo_depth](#dma_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_req_fifo_depth") | +| [sram_cfg_expose](#sram_cfg_expose) | `boolean` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_expose.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_expose") | +| [sram_cfg_fields](#sram_cfg_fields) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields") | +| [timing](#timing) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-timing-and-latency-tuning-parameter.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/timing") | +| [hives](#hives) | `array` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hives.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hives") | ## name @@ -391,6 +393,56 @@ The default value is: 3 ``` +## sram_cfg_expose + +Whether to expose memory cut configuration inputs for implementation + +`sram_cfg_expose` + +* is optional + +* Type: `boolean` + +* cannot be null + +* defined in: [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_expose.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_expose") + +### sram_cfg_expose Type + +`boolean` + +## sram_cfg_fields + +The names and widths of memory cut configuration inputs needed for implementation + +`sram_cfg_fields` + +* is optional + +* Type: `object` ([Details](snitch_cluster-properties-sram_cfg_fields.md)) + +* cannot be null + +* defined in: [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields") + +### sram_cfg_fields Type + +`object` ([Details](snitch_cluster-properties-sram_cfg_fields.md)) + +### sram_cfg_fields Constraints + +**minimum number of properties**: the minimum number of properties for this object is: `1` + +### sram_cfg_fields Default Value + +The default value is: + +```json +{ + "reserved": 1 +} +``` + ## timing diff --git a/docs/schema-doc/snitch_cluster-properties-sram_cfg_expose.md b/docs/schema-doc/snitch_cluster-properties-sram_cfg_expose.md new file mode 100644 index 000000000..623237975 --- /dev/null +++ b/docs/schema-doc/snitch_cluster-properties-sram_cfg_expose.md @@ -0,0 +1,15 @@ +# Untitled boolean in Snitch Cluster Schema Schema + +```txt +http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_expose +``` + +Whether to expose memory cut configuration inputs for implementation + +| Abstract | Extensible | Status | Identifiable | Custom Properties | Additional Properties | Access Restrictions | Defined In | +| :------------------ | :--------- | :------------- | :---------------------- | :---------------- | :-------------------- | :------------------ | :------------------------------------------------------------------------------- | +| Can be instantiated | No | Unknown status | Unknown identifiability | Forbidden | Allowed | none | [snitch_cluster.schema.json*](snitch_cluster.schema.json "open original schema") | + +## sram_cfg_expose Type + +`boolean` diff --git a/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-additionalproperties.md b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-additionalproperties.md new file mode 100644 index 000000000..d78bb0358 --- /dev/null +++ b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-additionalproperties.md @@ -0,0 +1,19 @@ +# Untitled number in Snitch Cluster Schema Schema + +```txt +http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields/additionalProperties +``` + + + +| Abstract | Extensible | Status | Identifiable | Custom Properties | Additional Properties | Access Restrictions | Defined In | +| :------------------ | :--------- | :------------- | :---------------------- | :---------------- | :-------------------- | :------------------ | :------------------------------------------------------------------------------- | +| Can be instantiated | No | Unknown status | Unknown identifiability | Forbidden | Allowed | none | [snitch_cluster.schema.json*](snitch_cluster.schema.json "open original schema") | + +## additionalProperties Type + +`number` + +## additionalProperties Constraints + +**minimum**: the value of this number must greater than or equal to: `1` diff --git a/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-default.md b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-default.md new file mode 100644 index 000000000..d4f8b3df7 --- /dev/null +++ b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-default.md @@ -0,0 +1,15 @@ +# Untitled undefined type in Snitch Cluster Schema Schema + +```txt +http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields/default +``` + + + +| Abstract | Extensible | Status | Identifiable | Custom Properties | Additional Properties | Access Restrictions | Defined In | +| :------------------ | :--------- | :------------- | :---------------------- | :---------------- | :-------------------- | :------------------ | :------------------------------------------------------------------------------- | +| Can be instantiated | No | Unknown status | Unknown identifiability | Forbidden | Allowed | none | [snitch_cluster.schema.json*](snitch_cluster.schema.json "open original schema") | + +## default Type + +unknown diff --git a/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-propertynames.md b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-propertynames.md new file mode 100644 index 000000000..2d1cd428b --- /dev/null +++ b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields-propertynames.md @@ -0,0 +1,25 @@ +# Untitled undefined type in Snitch Cluster Schema Schema + +```txt +http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields/propertyNames +``` + + + +| Abstract | Extensible | Status | Identifiable | Custom Properties | Additional Properties | Access Restrictions | Defined In | +| :------------------ | :--------- | :------------- | :---------------------- | :---------------- | :-------------------- | :------------------ | :------------------------------------------------------------------------------- | +| Can be instantiated | No | Unknown status | Unknown identifiability | Forbidden | Allowed | none | [snitch_cluster.schema.json*](snitch_cluster.schema.json "open original schema") | + +## propertyNames Type + +unknown + +## propertyNames Constraints + +**pattern**: the string must match the following regular expression: + +```regexp +^[A-Za-z_][A-Za-z0-9_]*$ +``` + +[try pattern](https://regexr.com/?expression=%5E%5BA-Za-z\_%5D%5BA-Za-z0-9\_%5D\*%24 "try regular expression with regexr.com") diff --git a/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields.md b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields.md new file mode 100644 index 000000000..b6b1a5379 --- /dev/null +++ b/docs/schema-doc/snitch_cluster-properties-sram_cfg_fields.md @@ -0,0 +1,57 @@ +# Untitled object in Snitch Cluster Schema Schema + +```txt +http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields +``` + +The names and widths of memory cut configuration inputs needed for implementation + +| Abstract | Extensible | Status | Identifiable | Custom Properties | Additional Properties | Access Restrictions | Defined In | +| :------------------ | :--------- | :------------- | :---------------------- | :---------------- | :-------------------- | :------------------ | :------------------------------------------------------------------------------- | +| Can be instantiated | No | Unknown status | Unknown identifiability | Forbidden | Allowed | none | [snitch_cluster.schema.json*](snitch_cluster.schema.json "open original schema") | + +## sram_cfg_fields Type + +`object` ([Details](snitch_cluster-properties-sram_cfg_fields.md)) + +## sram_cfg_fields Constraints + +**minimum number of properties**: the minimum number of properties for this object is: `1` + +## sram_cfg_fields Default Value + +The default value is: + +```json +{ + "reserved": 1 +} +``` + +# undefined Properties + +| Property | Type | Required | Nullable | Defined by | +| :-------------------- | :------- | :------- | :------------- | :------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| Additional Properties | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields-additionalproperties.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields/additionalProperties") | + +## Additional Properties + +Additional properties are allowed, as long as they follow this schema: + + + +* is optional + +* Type: `number` + +* cannot be null + +* defined in: [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields-additionalproperties.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields/additionalProperties") + +### additionalProperties Type + +`number` + +### additionalProperties Constraints + +**minimum**: the value of this number must greater than or equal to: `1` diff --git a/docs/schema-doc/snitch_cluster.md b/docs/schema-doc/snitch_cluster.md index 1c2dfe4cf..5e452bf87 100644 --- a/docs/schema-doc/snitch_cluster.md +++ b/docs/schema-doc/snitch_cluster.md @@ -16,24 +16,26 @@ Base description of a Snitch cluster and its internal structure and configuratio # Snitch Cluster Schema Properties -| Property | Type | Required | Nullable | Defined by | -| :------------------------------------------------ | :------- | :------- | :------------- | :--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -| [name](#name) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-name.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/name") | -| [boot_addr](#boot_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-boot_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/boot_addr") | -| [cluster_base_addr](#cluster_base_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-cluster_base_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/cluster_base_addr") | -| [tcdm](#tcdm) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-tcdm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/tcdm") | -| [addr_width](#addr_width) | `number` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-addr_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/addr_width") | -| [data_width](#data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/data_width") | -| [dma_data_width](#dma_data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_data_width") | -| [id_width_in](#id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/id_width_in") | -| [dma_id_width_in](#dma_id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_id_width_in") | -| [hart_base_id](#hart_base_id) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hart_base_id.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hart_base_id") | -| [mode](#mode) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-mode.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/mode") | -| [vm](#vm) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-vm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/vm") | -| [dma_axi_req_fifo_depth](#dma_axi_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_axi_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_axi_req_fifo_depth") | -| [dma_req_fifo_depth](#dma_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_req_fifo_depth") | -| [timing](#timing) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-timing-and-latency-tuning-parameter.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/timing") | -| [hives](#hives) | `array` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hives.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hives") | +| Property | Type | Required | Nullable | Defined by | +| :------------------------------------------------ | :-------- | :------- | :------------- | :--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| [name](#name) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-name.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/name") | +| [boot_addr](#boot_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-boot_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/boot_addr") | +| [cluster_base_addr](#cluster_base_addr) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-cluster_base_addr.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/cluster_base_addr") | +| [tcdm](#tcdm) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-tcdm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/tcdm") | +| [addr_width](#addr_width) | `number` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-addr_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/addr_width") | +| [data_width](#data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/data_width") | +| [dma_data_width](#dma_data_width) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_data_width.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_data_width") | +| [id_width_in](#id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/id_width_in") | +| [dma_id_width_in](#dma_id_width_in) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_id_width_in.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_id_width_in") | +| [hart_base_id](#hart_base_id) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hart_base_id.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hart_base_id") | +| [mode](#mode) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-mode.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/mode") | +| [vm](#vm) | `string` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-vm.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/vm") | +| [dma_axi_req_fifo_depth](#dma_axi_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_axi_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_axi_req_fifo_depth") | +| [dma_req_fifo_depth](#dma_req_fifo_depth) | `number` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-dma_req_fifo_depth.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/dma_req_fifo_depth") | +| [sram_cfg_expose](#sram_cfg_expose) | `boolean` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_expose.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_expose") | +| [sram_cfg_fields](#sram_cfg_fields) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields") | +| [timing](#timing) | `object` | Optional | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-timing-and-latency-tuning-parameter.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/timing") | +| [hives](#hives) | `array` | Required | cannot be null | [Snitch Cluster Schema](snitch_cluster-properties-hives.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/hives") | ## name @@ -391,6 +393,56 @@ The default value is: 3 ``` +## sram_cfg_expose + +Whether to expose memory cut configuration inputs for implementation + +`sram_cfg_expose` + +* is optional + +* Type: `boolean` + +* cannot be null + +* defined in: [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_expose.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_expose") + +### sram_cfg_expose Type + +`boolean` + +## sram_cfg_fields + +The names and widths of memory cut configuration inputs needed for implementation + +`sram_cfg_fields` + +* is optional + +* Type: `object` ([Details](snitch_cluster-properties-sram_cfg_fields.md)) + +* cannot be null + +* defined in: [Snitch Cluster Schema](snitch_cluster-properties-sram_cfg_fields.md "http://pulp-platform.org/snitch/snitch_cluster.schema.json#/properties/sram_cfg_fields") + +### sram_cfg_fields Type + +`object` ([Details](snitch_cluster-properties-sram_cfg_fields.md)) + +### sram_cfg_fields Constraints + +**minimum number of properties**: the minimum number of properties for this object is: `1` + +### sram_cfg_fields Default Value + +The default value is: + +```json +{ + "reserved": 1 +} +``` + ## timing diff --git a/docs/schema-doc/snitch_cluster.schema.json b/docs/schema-doc/snitch_cluster.schema.json index 064f95970..0dbd4aa8b 100644 --- a/docs/schema-doc/snitch_cluster.schema.json +++ b/docs/schema-doc/snitch_cluster.schema.json @@ -1 +1 @@ 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If not assigned, the next available index counting from 0 is chosen.","minimum":0,"maximum":31,"default":null},"indirection":{"type":"boolean","description":"Enable indirection extension.","default":false},"indir_out_spill":{"type":"boolean","description":"Whether to cut timing paths with a spill register at the address generator output; added only if indirection extension enabled.","default":true},"isect_slave_spill":{"type":"boolean","description":"Whether to cut timing paths with a spill register at the intersector index output; added only if this SSR is an intersection slave.","default":true},"isect_slave_credits":{"type":"number","description":"Number of elements by which intersected indices may outrun corresponding data; added only if this SSR is an intersection slave.","minimum":2,"default":8},"num_loops":{"type":"number","description":"Number of nested hardware loops in address generator.","minimum":1,"maximum":4,"default":4},"index_credits":{"type":"number","description":"Number of credits and buffer depth of the index word FIFO.","minimum":1,"default":3},"data_credits":{"type":"number","description":"Number of credits and buffer depth of the data word FIFO.","minimum":1,"default":4},"mux_resp_depth":{"type":"number","description":"Depth of response buffer in the TCDM multiplexer arbitrating between data and indices.","minimum":1,"default":3},"index_width":{"type":"number","description":"Internal bitwidth of indices in address generator.","minimum":1,"maximum":32,"default":16},"pointer_width":{"type":"number","description":"Internal bitwidth of pointers in address generator; must be larger than the TCDM word address mask.","maximum":32,"default":18},"shift_width":{"type":"number","description":"Internal bitwidth of additional left shift amount for indirect indices.","minimum":1,"maximum":32,"default":3},"rpt_width":{"type":"number","description":"Internal bitwidth of repetition counter for read streams.","minimum":1,"maximum":32,"default":4}}}}}}}}}}}} diff --git a/hw/occamy/occamy_cva6.sv.tpl b/hw/occamy/occamy_cva6.sv.tpl index 4cc95f458..00f772a5a 100644 --- a/hw/occamy/occamy_cva6.sv.tpl +++ b/hw/occamy/occamy_cva6.sv.tpl @@ -14,7 +14,8 @@ module occamy_cva6 import occamy_pkg::*; ( input logic time_irq_i, input logic debug_req_i, output ${soc_narrow_xbar.in_cva6.req_type()} axi_req_o, - input ${soc_narrow_xbar.in_cva6.rsp_type()} axi_resp_i + input ${soc_narrow_xbar.in_cva6.rsp_type()} axi_resp_i, + input sram_cfg_cva6_t sram_cfg_i ); <% cva6 = soc_narrow_xbar.in_cva6.copy(name="cva6_axi").declare(context).cut(context) %> @@ -76,7 +77,8 @@ module occamy_cva6 import occamy_pkg::*; ( .axi_aw_chan_t(${soc_narrow_xbar.in_cva6.aw_chan_type()}), .axi_w_chan_t(${soc_narrow_xbar.in_cva6.w_chan_type()}), .axi_req_t (${soc_narrow_xbar.in_cva6.req_type()}), - .axi_rsp_t (${soc_narrow_xbar.in_cva6.rsp_type()}) + .axi_rsp_t (${soc_narrow_xbar.in_cva6.rsp_type()}), + .sram_cfg_t (sram_cfg_t) ) i_cva6 ( .clk_i, .rst_ni, @@ -87,7 +89,12 @@ module occamy_cva6 import occamy_pkg::*; ( .time_irq_i (time_irq), .debug_req_i (debug_req), .axi_req_o (cva6_axi_req), - .axi_resp_i (cva6_axi_rsp) + .axi_resp_i (cva6_axi_rsp), + .sram_cfg_idata_i (sram_cfg_i.icache_data), + .sram_cfg_itag_i (sram_cfg_i.icache_tag), + .sram_cfg_ddata_i (sram_cfg_i.dcache_data), + .sram_cfg_dtag_i (sram_cfg_i.dcache_tag), + .sram_cfg_dvalid_dirty_i (sram_cfg_i.dcache_valid_dirty) ); endmodule diff --git a/hw/occamy/occamy_pkg.sv.tpl b/hw/occamy/occamy_pkg.sv.tpl index 4efeedb7d..8aeb588a8 100644 --- a/hw/occamy/occamy_pkg.sv.tpl +++ b/hw/occamy/occamy_pkg.sv.tpl @@ -23,6 +23,32 @@ package occamy_pkg; localparam int unsigned NrCoresCluster = occamy_cluster_pkg::NrCores; localparam int unsigned NrCoresS1Quadrant = NrClustersS1Quadrant * NrCoresCluster; + // Memory cut configurations: one per memory parameterization + typedef occamy_cluster_pkg::sram_cfg_t sram_cfg_t; + + typedef struct packed { + sram_cfg_t rocache_tag; + sram_cfg_t rocache_data; + occamy_cluster_pkg::sram_cfgs_t cluster; + } sram_cfg_quadrant_t; + + typedef struct packed { + sram_cfg_t dcache_valid_dirty; + sram_cfg_t dcache_tag; + sram_cfg_t dcache_data; + sram_cfg_t icache_tag; + sram_cfg_t icache_data; + } sram_cfg_cva6_t; + + typedef struct packed { + sram_cfg_t spm; + sram_cfg_cva6_t cva6; + sram_cfg_quadrant_t quadrant; + } sram_cfgs_t; + + localparam int unsigned SramCfgWidth = $bits(sram_cfg_t); + localparam int unsigned SramCfgCount = $bits(sram_cfgs_t)/SramCfgWidth; + typedef struct packed { logic [3:0] timer; logic [31:0] gpio; diff --git a/hw/occamy/occamy_quadrant_s1.sv.tpl b/hw/occamy/occamy_quadrant_s1.sv.tpl index 716993339..02cdee11c 100644 --- a/hw/occamy/occamy_quadrant_s1.sv.tpl +++ b/hw/occamy/occamy_quadrant_s1.sv.tpl @@ -43,7 +43,9 @@ module occamy_quadrant_s1 output ${soc_wide_xbar.in_s1_quadrant_0.req_type()} quadrant_wide_out_req_o, input ${soc_wide_xbar.in_s1_quadrant_0.rsp_type()} quadrant_wide_out_rsp_i, input ${soc_wide_xbar.out_s1_quadrant_0.req_type()} quadrant_wide_in_req_i, - output ${soc_wide_xbar.out_s1_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o + output ${soc_wide_xbar.out_s1_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o, + // SRAM configuration + input occamy_pkg::sram_cfg_quadrant_t sram_cfg_i ); // Calculate cluster base address based on `tile id`. @@ -93,7 +95,11 @@ module occamy_quadrant_s1 flush_valid="ro_flush_valid_i", \ flush_ready="ro_flush_ready_o", \ start_addr="ro_start_addr_i", \ - end_addr="ro_end_addr_i") + end_addr="ro_end_addr_i", \ + sram_cfg_data_t="sram_cfg_t", \ + sram_cfg_tag_t="sram_cfg_t", \ + sram_cfg_data_i="sram_cfg_i.rocache_data", \ + sram_cfg_tag_i="sram_cfg_i.rocache_tag") else: wide_cluster_out_ro_cache = wide_xbar_out_iwc @@ -162,7 +168,8 @@ module occamy_quadrant_s1 .wide_out_req_o (${wide_cluster_out.req_name()}), .wide_out_resp_i (${wide_cluster_out.rsp_name()}), .wide_in_req_i (${wide_cluster_in.req_name()}), - .wide_in_resp_o (${wide_cluster_in.rsp_name()}) + .wide_in_resp_o (${wide_cluster_in.rsp_name()}), + .sram_cfgs_i (sram_cfg_i.cluster) ); % endfor diff --git a/hw/occamy/occamy_top.sv.tpl b/hw/occamy/occamy_top.sv.tpl index d7f06bca6..72bb426e7 100644 --- a/hw/occamy/occamy_top.sv.tpl +++ b/hw/occamy/occamy_top.sv.tpl @@ -105,7 +105,10 @@ module occamy_top input ${soc_wide_xbar.out_pcie.rsp_type()} pcie_axi_rsp_i, input ${soc_wide_xbar.in_pcie.req_type()} pcie_axi_req_i, - output ${soc_wide_xbar.in_pcie.rsp_type()} pcie_axi_rsp_o + output ${soc_wide_xbar.in_pcie.rsp_type()} pcie_axi_rsp_o, + + /// SRAM configuration + input sram_cfgs_t sram_cfgs_i ); occamy_soc_reg_pkg::occamy_soc_reg2hw_t soc_ctrl_out; @@ -185,7 +188,8 @@ module occamy_top .time_irq_i (mtip[0]), .debug_req_i (debug_req[0]), .axi_req_o (${soc_narrow_xbar.in_cva6.req_name()}), - .axi_resp_i (${soc_narrow_xbar.in_cva6.rsp_name()}) + .axi_resp_i (${soc_narrow_xbar.in_cva6.rsp_name()}), + .sram_cfg_i (sram_cfgs_i.cva6) ); % for i in range(nr_s1_quadrants): @@ -245,7 +249,8 @@ module occamy_top .quadrant_wide_out_req_o (${wide_out.req_name()}), .quadrant_wide_out_rsp_i (${wide_out.rsp_name()}), .quadrant_wide_in_req_i (${wide_in.req_name()}), - .quadrant_wide_in_rsp_o (${wide_in.rsp_name()}) + .quadrant_wide_in_rsp_o (${wide_in.rsp_name()}), + .sram_cfg_i (sram_cfgs_i.quadrant) ); % endfor @@ -291,7 +296,8 @@ module occamy_top .DataWidth (${narrow_spm_cdc.dw}), .ByteWidth (8), .EnableInputPipeline (1'b1), - .EnableOutputPipeline (1'b1) + .EnableOutputPipeline (1'b1), + .sram_cfg_t (sram_cfg_t) ) i_spm_cut ( .clk_i (${narrow_spm_cdc.clk}), .rst_ni (${narrow_spm_cdc.rst}), @@ -303,7 +309,8 @@ module occamy_top .be_i (spm_strb), .rdata_o (spm_rdata), .rvalid_o (spm_rvalid), - .rerror_o (spm_rerror) + .rerror_o (spm_rerror), + .sram_cfg_i (sram_cfgs_i.spm) ); /// HBM2e Ports diff --git a/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv b/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv index 85133d974..83353022e 100644 --- a/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv +++ b/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv @@ -28,7 +28,10 @@ module snitch_read_only_cache #( parameter type slv_req_t = logic, parameter type slv_rsp_t = logic, parameter type mst_req_t = logic, - parameter type mst_rsp_t = logic + parameter type mst_rsp_t = logic, + /// Configuration input types for memory cuts used in implementation. + parameter type sram_cfg_data_t = logic, + parameter type sram_cfg_tag_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -40,7 +43,9 @@ module snitch_read_only_cache #( input slv_req_t axi_slv_req_i, output slv_rsp_t axi_slv_rsp_o, output mst_req_t axi_mst_req_o, - input mst_rsp_t axi_mst_rsp_i + input mst_rsp_t axi_mst_rsp_i, + input sram_cfg_data_t sram_cfg_data_i, + input sram_cfg_tag_t sram_cfg_tag_i ); `include "axi/typedef.svh" @@ -269,7 +274,11 @@ module snitch_read_only_cache #( ); // The lookup module contains the actual cache RAMs and performs lookups. - snitch_icache_lookup #(CFG) i_lookup ( + snitch_icache_lookup #( + .CFG ( CFG ), + .sram_cfg_tag_t ( sram_cfg_tag_t ), + .sram_cfg_data_t ( sram_cfg_data_t ) + ) i_lookup ( .clk_i, .rst_ni, @@ -296,7 +305,10 @@ module snitch_read_only_cache #( .write_tag_i ( write_tag ), .write_error_i ( write_error ), .write_valid_i ( write_valid ), - .write_ready_o ( write_ready ) + .write_ready_o ( write_ready ), + + .sram_cfg_tag_i, + .sram_cfg_data_i ); // The handler module deals with the result of the lookup. It also diff --git a/hw/spm_interface/src/spm_1p_adv.sv b/hw/spm_interface/src/spm_1p_adv.sv index 58c3dcf86..a80ab6084 100644 --- a/hw/spm_interface/src/spm_1p_adv.sv +++ b/hw/spm_interface/src/spm_1p_adv.sv @@ -30,7 +30,9 @@ module spm_1p_adv #( parameter type parity_t = logic [ecc_pkg::get_parity_width(DataWidth)-1:0], parameter type addr_t = logic [AddrWidth-1:0], parameter type data_t = logic [DataWidth-1:0], - parameter type be_t = logic [BeWidth-1:0] + parameter type be_t = logic [BeWidth-1:0], + /// Configuration input types for SRAMs used in implementation. + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -45,7 +47,9 @@ module spm_1p_adv #( output data_t rdata_o, // read data /// Read- or write transaction is valid. output logic rvalid_o, - output logic [1:0] rerror_o // Bit1: Uncorrectable, Bit0: Correctable + output logic [1:0] rerror_o, // Bit1: Uncorrectable, Bit0: Correctable + // SRAM configuration + input sram_cfg_t sram_cfg_i ); // Calculate the true SPM data width (i.e., DW with optional ECC). @@ -162,10 +166,13 @@ module spm_1p_adv #( .NumPorts (1), .SimInit (SimInit), .PrintSimCfg (PrintSimCfg), - .Latency (1) + .Latency (1), + .impl_in_t (sram_cfg_t) ) i_mem ( .clk_i(clk_i), .rst_ni(rst_ni), + .impl_i (sram_cfg_i), + .impl_o ( ), .req_i(req_q), .we_i(we_q), .addr_i(addr_q), diff --git a/hw/vendor/openhwgroup_cva6/src/ariane.sv b/hw/vendor/openhwgroup_cva6/src/ariane.sv index b4287664b..3dfa45313 100644 --- a/hw/vendor/openhwgroup_cva6/src/ariane.sv +++ b/hw/vendor/openhwgroup_cva6/src/ariane.sv @@ -33,14 +33,20 @@ module ariane import ariane_pkg::*; #( parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, parameter type axi_w_chan_t = ariane_axi::w_chan_t, parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_rsp_t = ariane_axi::resp_t, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, // Core ID, Cluster ID and boot address are considered more or less static input logic [63:0] boot_addr_i, // reset boot address input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) - + // SRAM config + input sram_cfg_t sram_cfg_idata_i, + input sram_cfg_t sram_cfg_itag_i, + input sram_cfg_t sram_cfg_ddata_i, + input sram_cfg_t sram_cfg_dtag_i, + input sram_cfg_t sram_cfg_dvalid_dirty_i, // Interrupt inputs input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async) input logic ipi_i, // inter-processor interrupts (async) @@ -656,7 +662,8 @@ module ariane import ariane_pkg::*; #( .AxiIdWidth ( AxiIdWidth ), .AxiUserWidth ( AxiUserWidth ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_rsp_t ( axi_rsp_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_cache_subsystem ( // to D$ .clk_i ( clk_i ), @@ -664,6 +671,11 @@ module ariane import ariane_pkg::*; #( .busy_o ( busy_cache_ctrl ), .stall_i ( stall_ctrl_cache ), .init_ni ( init_ctrl_cache_n ), + // SRAM config + .sram_cfg_idata_i ( sram_cfg_idata_i ), + .sram_cfg_itag_i ( sram_cfg_itag_i ), + .sram_cfg_ddata_i ( sram_cfg_ddata_i ), + .sram_cfg_dtag_i ( sram_cfg_dtag_i ), // I$ .icache_en_i ( icache_en_csr ), .icache_flush_i ( icache_flush_ctrl_cache ), @@ -710,7 +722,8 @@ module ariane import ariane_pkg::*; #( .axi_aw_chan_t ( axi_aw_chan_t ), .axi_w_chan_t ( axi_w_chan_t ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_rsp_t ( axi_rsp_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_cache_subsystem ( // to D$ .clk_i ( clk_i ), @@ -719,6 +732,12 @@ module ariane import ariane_pkg::*; #( .busy_o ( busy_cache_ctrl ), .stall_i ( stall_ctrl_cache ), .init_ni ( init_ctrl_cache_n ), + // SRAM config + .sram_cfg_idata_i ( sram_cfg_idata_i ), + .sram_cfg_itag_i ( sram_cfg_itag_i ), + .sram_cfg_ddata_i ( sram_cfg_ddata_i ), + .sram_cfg_dtag_i ( sram_cfg_dtag_i ), + .sram_cfg_dvalid_dirty_i ( sram_cfg_dvalid_dirty_i ), // I$ .icache_en_i ( icache_en_csr ), .icache_flush_i ( icache_flush_ctrl_cache ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache.sv index e2d703e7a..d4e956347 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache.sv @@ -27,11 +27,16 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #( parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions - parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions + parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, + // SRAM config + input sram_cfg_t sram_cfg_data_i, + input sram_cfg_t sram_cfg_tag_i, + input logic flush_i, // flush the icache, flush and kill have to be asserted together input logic en_i, // enable icache output logic miss_o, // to performance counter @@ -417,6 +422,7 @@ end else begin : gen_piton_offset for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin : gen_sram // Tag RAM tc_sram #( + .impl_in_t ( sram_cfg_t ), // tag + valid bit .DataWidth ( ICACHE_TAG_WIDTH+1 ), .NumWords ( ICACHE_NUM_WORDS ), @@ -424,6 +430,8 @@ end else begin : gen_piton_offset ) tag_sram ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_tag_i ), + .impl_o ( ), .req_i ( vld_req[i] ), .we_i ( vld_we ), .addr_i ( vld_addr ), @@ -439,12 +447,15 @@ end else begin : gen_piton_offset // Data RAM tc_sram #( + .impl_in_t ( sram_cfg_t ), .DataWidth ( ICACHE_LINE_WIDTH ), .NumWords ( ICACHE_NUM_WORDS ), .NumPorts ( 1 ) ) data_sram ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_data_i ), + .impl_o ( ), .req_i ( cl_req[i] ), .we_i ( cl_we ), .addr_i ( cl_index ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv index 114ec6e1c..f741d33e9 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -20,12 +20,17 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( parameter int unsigned AxiIdWidth = 0, parameter int unsigned AxiUserWidth = 0, parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_rsp_t = ariane_axi::resp_t, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, input riscv::priv_lvl_t priv_lvl_i, + // SRAM config + input sram_cfg_t sram_cfg_data_i, + input sram_cfg_t sram_cfg_tag_i, + input logic flush_i, // flush the icache, flush and kill have to be asserted together input logic en_i, // enable icache output logic miss_o, // to performance counter @@ -104,10 +109,13 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( cva6_icache #( // use ID 0 for icache reads .RdTxId ( 0 ), - .ArianeCfg ( ArianeCfg ) + .ArianeCfg ( ArianeCfg ), + .sram_cfg_t ( sram_cfg_t ) ) i_cva6_icache ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .sram_cfg_data_i ( sram_cfg_data_i ), + .sram_cfg_tag_i ( sram_cfg_tag_i ), .flush_i ( flush_i ), .en_i ( en_i ), .miss_o ( miss_o ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_cache_subsystem.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_cache_subsystem.sv index 30b5aabc3..3fe456683 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_cache_subsystem.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_cache_subsystem.sv @@ -25,7 +25,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, parameter type axi_w_chan_t = ariane_axi::w_chan_t, parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_rsp_t = ariane_axi::resp_t, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -33,6 +34,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( output logic busy_o, input logic stall_i, // stall new memory requests input logic init_ni, // do not init after reset + // SRAM config + input sram_cfg_t sram_cfg_idata_i, + input sram_cfg_t sram_cfg_itag_i, + input sram_cfg_t sram_cfg_ddata_i, + input sram_cfg_t sram_cfg_dtag_i, + input sram_cfg_t sram_cfg_dvalid_dirty_i, // I$ input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together @@ -82,11 +89,14 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( .AxiIdWidth ( AxiIdWidth ), .AxiUserWidth ( AxiUserWidth ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_rsp_t ( axi_rsp_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_cva6_icache_axi_wrapper ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .priv_lvl_i ( priv_lvl_i ), + .sram_cfg_data_i ( sram_cfg_idata_i ), + .sram_cfg_tag_i ( sram_cfg_itag_i ), .flush_i ( icache_flush_i ), .en_i ( icache_en_i ), .miss_o ( icache_miss_o ), @@ -110,10 +120,14 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( .AXI_DATA_WIDTH ( AxiDataWidth ), .AXI_ID_WIDTH ( AxiIdWidth ), .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ) + .axi_rsp_t ( axi_rsp_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_nbdcache ( .clk_i, .rst_ni, + .sram_cfg_data_i ( sram_cfg_ddata_i ), + .sram_cfg_tag_i ( sram_cfg_dtag_i ), + .sram_cfg_valid_dirty_i ( sram_cfg_dvalid_dirty_i ), .enable_i ( dcache_enable_i ), .flush_i ( dcache_flush_i ), .flush_ack_o ( dcache_flush_ack_o ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_nbdcache.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_nbdcache.sv index 3658597f4..5703bd129 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_nbdcache.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/std_nbdcache.sv @@ -19,10 +19,15 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( parameter int unsigned AXI_DATA_WIDTH = 0, parameter int unsigned AXI_ID_WIDTH = 0, parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_rsp_t = ariane_axi::resp_t, + parameter type sram_cfg_t = logic )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low + // SRAM config + input sram_cfg_t sram_cfg_data_i, + input sram_cfg_t sram_cfg_tag_i, + input sram_cfg_t sram_cfg_valid_dirty_i, // Cache management input logic enable_i, // from CSR input logic flush_i, // high until acknowledged @@ -184,12 +189,15 @@ import std_cache_pkg::*; // -------------- for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : sram_block tc_sram #( + .impl_in_t ( sram_cfg_t ), .DataWidth ( DCACHE_LINE_WIDTH ), .NumWords ( DCACHE_NUM_WORDS ), .NumPorts ( 1 ) ) data_sram ( .req_i ( req_ram [i] ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_data_i ), + .impl_o ( ), .we_i ( we_ram ), .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), .wdata_i ( wdata_ram.data ), @@ -199,12 +207,15 @@ import std_cache_pkg::*; ); tc_sram #( + .impl_in_t ( sram_cfg_t ), .DataWidth ( DCACHE_TAG_WIDTH ), .NumWords ( DCACHE_NUM_WORDS ), .NumPorts ( 1 ) ) tag_sram ( .req_i ( req_ram [i] ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_tag_i ), + .impl_o ( ), .we_i ( we_ram ), .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), .wdata_i ( wdata_ram.tag ), @@ -232,12 +243,15 @@ import std_cache_pkg::*; end tc_sram #( + .impl_in_t ( sram_cfg_t ), .DataWidth ( 4*DCACHE_DIRTY_WIDTH ), .NumWords ( DCACHE_NUM_WORDS ), .NumPorts ( 1 ) ) valid_dirty_sram ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_valid_dirty_i ), + .impl_o ( ), .req_i ( |req_ram ), .we_i ( we_ram ), .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_cache_subsystem.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_cache_subsystem.sv index c47088a16..b6b2a28d5 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_cache_subsystem.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_cache_subsystem.sv @@ -26,13 +26,19 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( parameter int unsigned AxiIdWidth = 0, parameter int unsigned AxiUserWidth = 0, parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter type axi_rsp_t = ariane_axi::resp_t, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, output logic busy_o, input logic stall_i, // stall new memory requests input logic init_ni, + // SRAM config + input sram_cfg_t sram_cfg_idata_i, + input sram_cfg_t sram_cfg_itag_i, + input sram_cfg_t sram_cfg_ddata_i, + input sram_cfg_t sram_cfg_dtag_i, // I$ input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together @@ -87,11 +93,14 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( cva6_icache #( // use ID 0 for icache reads .RdTxId ( 0 ), - .ArianeCfg ( ArianeCfg ) + .ArianeCfg ( ArianeCfg ), + .sram_cfg_t ( sram_cfg_t ) ) i_cva6_icache ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .flush_i ( icache_flush_i ), + .sram_cfg_data_i ( sram_cfg_idata_i ), + .sram_cfg_tag_i ( sram_cfg_itag_i ), .en_i ( icache_en_i ), .miss_o ( icache_miss_o ), .busy_o ( icache_busy ), @@ -116,10 +125,13 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( // use ID 1 for dcache reads and amos. note that the writebuffer // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. .RdAmoTxId ( 1 ), - .ArianeCfg ( ArianeCfg ) + .ArianeCfg ( ArianeCfg ), + .sram_cfg_t ( sram_cfg_t ) ) i_wt_dcache ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .sram_cfg_data_i ( sram_cfg_ddata_i ), + .sram_cfg_tag_i ( sram_cfg_dtag_i ), .enable_i ( dcache_enable_i ), .busy_o ( dcache_busy ), .stall_i ( stall_i ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache.sv index 7f4bc6ae3..fc347eaf4 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache.sv @@ -18,11 +18,16 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1, // contains cacheable regions - parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig + parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, + parameter type sram_cfg_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low + // SRAM config + input sram_cfg_t sram_cfg_data_i, + input sram_cfg_t sram_cfg_tag_i, + // Cache management input logic enable_i, // from CSR input logic flush_i, // high until acknowledged @@ -280,10 +285,14 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( wt_dcache_mem #( .Axi64BitCompliant ( ArianeCfg.Axi64BitCompliant ), - .NumPorts ( NumPorts ) + .NumPorts ( NumPorts ), + .sram_cfg_t ( sram_cfg_t ) ) i_wt_dcache_mem ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + // SRAM config + .sram_cfg_data_i ( sram_cfg_data_i ), + .sram_cfg_tag_i ( sram_cfg_tag_i ), // read ports .rd_prio_i ( rd_prio ), .rd_tag_i ( rd_tag ), diff --git a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache_mem.sv b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache_mem.sv index 979c8f3fc..2b1cef152 100644 --- a/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache_mem.sv +++ b/hw/vendor/openhwgroup_cva6/src/cache_subsystem/wt_dcache_mem.sv @@ -28,11 +28,16 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter - parameter int unsigned NumPorts = 3 + parameter int unsigned NumPorts = 3, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, + // SRAM config + input sram_cfg_t sram_cfg_data_i, + input sram_cfg_t sram_cfg_tag_i, + // ports input logic [NumPorts-1:0][DCACHE_TAG_WIDTH-1:0] rd_tag_i, // tag in - comes one cycle later input logic [NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx_i, @@ -253,12 +258,15 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : gen_data_banks // Data RAM tc_sram #( + .impl_in_t ( sram_cfg_t ), .DataWidth ( ariane_pkg::DCACHE_SET_ASSOC * 64 ), .NumWords ( wt_cache_pkg::DCACHE_NUM_WORDS ), .NumPorts ( 1 ) ) i_data_sram ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_data_i ), + .impl_o ( ), .req_i ( bank_req [k] ), .we_i ( bank_we [k] ), .addr_i ( bank_idx [k] ), @@ -275,6 +283,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( // Tag RAM tc_sram #( + .impl_in_t ( sram_cfg_t ), // tag + valid bit .DataWidth ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ), .NumWords ( wt_cache_pkg::DCACHE_NUM_WORDS ), @@ -282,6 +291,8 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( ) i_tag_sram ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .impl_i ( sram_cfg_tag_i ), + .impl_o ( ), .req_i ( vld_req[i] ), .we_i ( vld_we ), .addr_i ( vld_addr ), diff --git a/hw/vendor/patches/openhwgroup_cva6/0014-cva6-Add-SRAM-config-ports.patch b/hw/vendor/patches/openhwgroup_cva6/0014-cva6-Add-SRAM-config-ports.patch new file mode 100644 index 000000000..ce6f7bde2 --- /dev/null +++ b/hw/vendor/patches/openhwgroup_cva6/0014-cva6-Add-SRAM-config-ports.patch @@ -0,0 +1,461 @@ +From 66d6c3471e6d4fef28afeec4f779e5561ade1f3b Mon Sep 17 00:00:00 2001 +From: Paul Scheffler +Date: Thu, 21 Oct 2021 23:17:48 +0200 +Subject: [PATCH] cva6: Add SRAM config ports + +--- + src/ariane.sv | 27 ++++++++++++++++++++++---- + src/cache_subsystem/cva6_icache.sv | 13 ++++++++++++- + src/cache_subsystem/cva6_icache_axi_wrapper.sv | 12 ++++++++++-- + src/cache_subsystem/std_cache_subsystem.sv | 20 ++++++++++++++++--- + src/cache_subsystem/std_nbdcache.sv | 16 ++++++++++++++- + src/cache_subsystem/wt_cache_subsystem.sv | 18 ++++++++++++++--- + src/cache_subsystem/wt_dcache.sv | 13 +++++++++++-- + src/cache_subsystem/wt_dcache_mem.sv | 13 ++++++++++++- + 8 files changed, 115 insertions(+), 17 deletions(-) + +diff --git a/src/ariane.sv b/src/ariane.sv +index b428766..3dfa453 100644 +--- a/src/ariane.sv ++++ b/src/ariane.sv +@@ -33,14 +33,20 @@ module ariane import ariane_pkg::*; #( + parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, + parameter type axi_w_chan_t = ariane_axi::w_chan_t, + parameter type axi_req_t = ariane_axi::req_t, +- parameter type axi_rsp_t = ariane_axi::resp_t ++ parameter type axi_rsp_t = ariane_axi::resp_t, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + // Core ID, Cluster ID and boot address are considered more or less static + input logic [63:0] boot_addr_i, // reset boot address + input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) +- ++ // SRAM config ++ input sram_cfg_t sram_cfg_idata_i, ++ input sram_cfg_t sram_cfg_itag_i, ++ input sram_cfg_t sram_cfg_ddata_i, ++ input sram_cfg_t sram_cfg_dtag_i, ++ input sram_cfg_t sram_cfg_dvalid_dirty_i, + // Interrupt inputs + input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async) + input logic ipi_i, // inter-processor interrupts (async) +@@ -656,7 +662,8 @@ module ariane import ariane_pkg::*; #( + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .axi_req_t ( axi_req_t ), +- .axi_rsp_t ( axi_rsp_t ) ++ .axi_rsp_t ( axi_rsp_t ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_cache_subsystem ( + // to D$ + .clk_i ( clk_i ), +@@ -664,6 +671,11 @@ module ariane import ariane_pkg::*; #( + .busy_o ( busy_cache_ctrl ), + .stall_i ( stall_ctrl_cache ), + .init_ni ( init_ctrl_cache_n ), ++ // SRAM config ++ .sram_cfg_idata_i ( sram_cfg_idata_i ), ++ .sram_cfg_itag_i ( sram_cfg_itag_i ), ++ .sram_cfg_ddata_i ( sram_cfg_ddata_i ), ++ .sram_cfg_dtag_i ( sram_cfg_dtag_i ), + // I$ + .icache_en_i ( icache_en_csr ), + .icache_flush_i ( icache_flush_ctrl_cache ), +@@ -710,7 +722,8 @@ module ariane import ariane_pkg::*; #( + .axi_aw_chan_t ( axi_aw_chan_t ), + .axi_w_chan_t ( axi_w_chan_t ), + .axi_req_t ( axi_req_t ), +- .axi_rsp_t ( axi_rsp_t ) ++ .axi_rsp_t ( axi_rsp_t ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_cache_subsystem ( + // to D$ + .clk_i ( clk_i ), +@@ -719,6 +732,12 @@ module ariane import ariane_pkg::*; #( + .busy_o ( busy_cache_ctrl ), + .stall_i ( stall_ctrl_cache ), + .init_ni ( init_ctrl_cache_n ), ++ // SRAM config ++ .sram_cfg_idata_i ( sram_cfg_idata_i ), ++ .sram_cfg_itag_i ( sram_cfg_itag_i ), ++ .sram_cfg_ddata_i ( sram_cfg_ddata_i ), ++ .sram_cfg_dtag_i ( sram_cfg_dtag_i ), ++ .sram_cfg_dvalid_dirty_i ( sram_cfg_dvalid_dirty_i ), + // I$ + .icache_en_i ( icache_en_csr ), + .icache_flush_i ( icache_flush_ctrl_cache ), +diff --git a/src/cache_subsystem/cva6_icache.sv b/src/cache_subsystem/cva6_icache.sv +index e2d703e..d4e9563 100644 +--- a/src/cache_subsystem/cva6_icache.sv ++++ b/src/cache_subsystem/cva6_icache.sv +@@ -27,11 +27,16 @@ + + module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #( + parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions +- parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions ++ parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + ++ // SRAM config ++ input sram_cfg_t sram_cfg_data_i, ++ input sram_cfg_t sram_cfg_tag_i, ++ + input logic flush_i, // flush the icache, flush and kill have to be asserted together + input logic en_i, // enable icache + output logic miss_o, // to performance counter +@@ -417,6 +422,7 @@ end else begin : gen_piton_offset + for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin : gen_sram + // Tag RAM + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + // tag + valid bit + .DataWidth ( ICACHE_TAG_WIDTH+1 ), + .NumWords ( ICACHE_NUM_WORDS ), +@@ -424,6 +430,8 @@ end else begin : gen_piton_offset + ) tag_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_tag_i ), ++ .impl_o ( ), + .req_i ( vld_req[i] ), + .we_i ( vld_we ), + .addr_i ( vld_addr ), +@@ -439,12 +447,15 @@ end else begin : gen_piton_offset + + // Data RAM + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + .DataWidth ( ICACHE_LINE_WIDTH ), + .NumWords ( ICACHE_NUM_WORDS ), + .NumPorts ( 1 ) + ) data_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_data_i ), ++ .impl_o ( ), + .req_i ( cl_req[i] ), + .we_i ( cl_we ), + .addr_i ( cl_index ), +diff --git a/src/cache_subsystem/cva6_icache_axi_wrapper.sv b/src/cache_subsystem/cva6_icache_axi_wrapper.sv +index 114ec6e..f741d33 100644 +--- a/src/cache_subsystem/cva6_icache_axi_wrapper.sv ++++ b/src/cache_subsystem/cva6_icache_axi_wrapper.sv +@@ -20,12 +20,17 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( + parameter int unsigned AxiIdWidth = 0, + parameter int unsigned AxiUserWidth = 0, + parameter type axi_req_t = ariane_axi::req_t, +- parameter type axi_rsp_t = ariane_axi::resp_t ++ parameter type axi_rsp_t = ariane_axi::resp_t, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + input riscv::priv_lvl_t priv_lvl_i, + ++ // SRAM config ++ input sram_cfg_t sram_cfg_data_i, ++ input sram_cfg_t sram_cfg_tag_i, ++ + input logic flush_i, // flush the icache, flush and kill have to be asserted together + input logic en_i, // enable icache + output logic miss_o, // to performance counter +@@ -104,10 +109,13 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #( + cva6_icache #( + // use ID 0 for icache reads + .RdTxId ( 0 ), +- .ArianeCfg ( ArianeCfg ) ++ .ArianeCfg ( ArianeCfg ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_cva6_icache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .sram_cfg_data_i ( sram_cfg_data_i ), ++ .sram_cfg_tag_i ( sram_cfg_tag_i ), + .flush_i ( flush_i ), + .en_i ( en_i ), + .miss_o ( miss_o ), +diff --git a/src/cache_subsystem/std_cache_subsystem.sv b/src/cache_subsystem/std_cache_subsystem.sv +index 30b5aab..3fe4566 100644 +--- a/src/cache_subsystem/std_cache_subsystem.sv ++++ b/src/cache_subsystem/std_cache_subsystem.sv +@@ -25,7 +25,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( + parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, + parameter type axi_w_chan_t = ariane_axi::w_chan_t, + parameter type axi_req_t = ariane_axi::req_t, +- parameter type axi_rsp_t = ariane_axi::resp_t ++ parameter type axi_rsp_t = ariane_axi::resp_t, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, +@@ -33,6 +34,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( + output logic busy_o, + input logic stall_i, // stall new memory requests + input logic init_ni, // do not init after reset ++ // SRAM config ++ input sram_cfg_t sram_cfg_idata_i, ++ input sram_cfg_t sram_cfg_itag_i, ++ input sram_cfg_t sram_cfg_ddata_i, ++ input sram_cfg_t sram_cfg_dtag_i, ++ input sram_cfg_t sram_cfg_dvalid_dirty_i, + // I$ + input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) + input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together +@@ -82,11 +89,14 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .axi_req_t ( axi_req_t ), +- .axi_rsp_t ( axi_rsp_t ) ++ .axi_rsp_t ( axi_rsp_t ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_cva6_icache_axi_wrapper ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .priv_lvl_i ( priv_lvl_i ), ++ .sram_cfg_data_i ( sram_cfg_idata_i ), ++ .sram_cfg_tag_i ( sram_cfg_itag_i ), + .flush_i ( icache_flush_i ), + .en_i ( icache_en_i ), + .miss_o ( icache_miss_o ), +@@ -110,10 +120,14 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .axi_req_t ( axi_req_t ), +- .axi_rsp_t ( axi_rsp_t ) ++ .axi_rsp_t ( axi_rsp_t ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_nbdcache ( + .clk_i, + .rst_ni, ++ .sram_cfg_data_i ( sram_cfg_ddata_i ), ++ .sram_cfg_tag_i ( sram_cfg_dtag_i ), ++ .sram_cfg_valid_dirty_i ( sram_cfg_dvalid_dirty_i ), + .enable_i ( dcache_enable_i ), + .flush_i ( dcache_flush_i ), + .flush_ack_o ( dcache_flush_ack_o ), +diff --git a/src/cache_subsystem/std_nbdcache.sv b/src/cache_subsystem/std_nbdcache.sv +index 3658597..5703bd1 100644 +--- a/src/cache_subsystem/std_nbdcache.sv ++++ b/src/cache_subsystem/std_nbdcache.sv +@@ -19,10 +19,15 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter type axi_req_t = ariane_axi::req_t, +- parameter type axi_rsp_t = ariane_axi::resp_t ++ parameter type axi_rsp_t = ariane_axi::resp_t, ++ parameter type sram_cfg_t = logic + )( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low ++ // SRAM config ++ input sram_cfg_t sram_cfg_data_i, ++ input sram_cfg_t sram_cfg_tag_i, ++ input sram_cfg_t sram_cfg_valid_dirty_i, + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged +@@ -184,12 +189,15 @@ import std_cache_pkg::*; + // -------------- + for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : sram_block + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + .DataWidth ( DCACHE_LINE_WIDTH ), + .NumWords ( DCACHE_NUM_WORDS ), + .NumPorts ( 1 ) + ) data_sram ( + .req_i ( req_ram [i] ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_data_i ), ++ .impl_o ( ), + .we_i ( we_ram ), + .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), + .wdata_i ( wdata_ram.data ), +@@ -199,12 +207,15 @@ import std_cache_pkg::*; + ); + + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + .DataWidth ( DCACHE_TAG_WIDTH ), + .NumWords ( DCACHE_NUM_WORDS ), + .NumPorts ( 1 ) + ) tag_sram ( + .req_i ( req_ram [i] ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_tag_i ), ++ .impl_o ( ), + .we_i ( we_ram ), + .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), + .wdata_i ( wdata_ram.tag ), +@@ -232,12 +243,15 @@ import std_cache_pkg::*; + end + + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + .DataWidth ( 4*DCACHE_DIRTY_WIDTH ), + .NumWords ( DCACHE_NUM_WORDS ), + .NumPorts ( 1 ) + ) valid_dirty_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_valid_dirty_i ), ++ .impl_o ( ), + .req_i ( |req_ram ), + .we_i ( we_ram ), + .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), +diff --git a/src/cache_subsystem/wt_cache_subsystem.sv b/src/cache_subsystem/wt_cache_subsystem.sv +index c47088a..b6b2a28 100644 +--- a/src/cache_subsystem/wt_cache_subsystem.sv ++++ b/src/cache_subsystem/wt_cache_subsystem.sv +@@ -26,13 +26,19 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( + parameter int unsigned AxiIdWidth = 0, + parameter int unsigned AxiUserWidth = 0, + parameter type axi_req_t = ariane_axi::req_t, +- parameter type axi_rsp_t = ariane_axi::resp_t ++ parameter type axi_rsp_t = ariane_axi::resp_t, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + output logic busy_o, + input logic stall_i, // stall new memory requests + input logic init_ni, ++ // SRAM config ++ input sram_cfg_t sram_cfg_idata_i, ++ input sram_cfg_t sram_cfg_itag_i, ++ input sram_cfg_t sram_cfg_ddata_i, ++ input sram_cfg_t sram_cfg_dtag_i, + // I$ + input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) + input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together +@@ -87,11 +93,14 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( + cva6_icache #( + // use ID 0 for icache reads + .RdTxId ( 0 ), +- .ArianeCfg ( ArianeCfg ) ++ .ArianeCfg ( ArianeCfg ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_cva6_icache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( icache_flush_i ), ++ .sram_cfg_data_i ( sram_cfg_idata_i ), ++ .sram_cfg_tag_i ( sram_cfg_itag_i ), + .en_i ( icache_en_i ), + .miss_o ( icache_miss_o ), + .busy_o ( icache_busy ), +@@ -116,10 +125,13 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( + // use ID 1 for dcache reads and amos. note that the writebuffer + // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. + .RdAmoTxId ( 1 ), +- .ArianeCfg ( ArianeCfg ) ++ .ArianeCfg ( ArianeCfg ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_wt_dcache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .sram_cfg_data_i ( sram_cfg_ddata_i ), ++ .sram_cfg_tag_i ( sram_cfg_dtag_i ), + .enable_i ( dcache_enable_i ), + .busy_o ( dcache_busy ), + .stall_i ( stall_i ), +diff --git a/src/cache_subsystem/wt_dcache.sv b/src/cache_subsystem/wt_dcache.sv +index 7f4bc6a..fc347ea 100644 +--- a/src/cache_subsystem/wt_dcache.sv ++++ b/src/cache_subsystem/wt_dcache.sv +@@ -18,11 +18,16 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( + // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions + parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1, + // contains cacheable regions +- parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig ++ parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + ++ // SRAM config ++ input sram_cfg_t sram_cfg_data_i, ++ input sram_cfg_t sram_cfg_tag_i, ++ + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged +@@ -280,10 +285,14 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( + + wt_dcache_mem #( + .Axi64BitCompliant ( ArianeCfg.Axi64BitCompliant ), +- .NumPorts ( NumPorts ) ++ .NumPorts ( NumPorts ), ++ .sram_cfg_t ( sram_cfg_t ) + ) i_wt_dcache_mem ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ // SRAM config ++ .sram_cfg_data_i ( sram_cfg_data_i ), ++ .sram_cfg_tag_i ( sram_cfg_tag_i ), + // read ports + .rd_prio_i ( rd_prio ), + .rd_tag_i ( rd_tag ), +diff --git a/src/cache_subsystem/wt_dcache_mem.sv b/src/cache_subsystem/wt_dcache_mem.sv +index 979c8f3..2b1cef1 100644 +--- a/src/cache_subsystem/wt_dcache_mem.sv ++++ b/src/cache_subsystem/wt_dcache_mem.sv +@@ -28,11 +28,16 @@ + + module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( + parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter +- parameter int unsigned NumPorts = 3 ++ parameter int unsigned NumPorts = 3, ++ parameter type sram_cfg_t = logic + ) ( + input logic clk_i, + input logic rst_ni, + ++ // SRAM config ++ input sram_cfg_t sram_cfg_data_i, ++ input sram_cfg_t sram_cfg_tag_i, ++ + // ports + input logic [NumPorts-1:0][DCACHE_TAG_WIDTH-1:0] rd_tag_i, // tag in - comes one cycle later + input logic [NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx_i, +@@ -253,12 +258,15 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( + for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : gen_data_banks + // Data RAM + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + .DataWidth ( ariane_pkg::DCACHE_SET_ASSOC * 64 ), + .NumWords ( wt_cache_pkg::DCACHE_NUM_WORDS ), + .NumPorts ( 1 ) + ) i_data_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_data_i ), ++ .impl_o ( ), + .req_i ( bank_req [k] ), + .we_i ( bank_we [k] ), + .addr_i ( bank_idx [k] ), +@@ -275,6 +283,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( + + // Tag RAM + tc_sram #( ++ .impl_in_t ( sram_cfg_t ), + // tag + valid bit + .DataWidth ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ), + .NumWords ( wt_cache_pkg::DCACHE_NUM_WORDS ), +@@ -282,6 +291,8 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( + ) i_tag_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), ++ .impl_i ( sram_cfg_tag_i ), ++ .impl_o ( ), + .req_i ( vld_req[i] ), + .we_i ( vld_we ), + .addr_i ( vld_addr ), +-- +2.16.5 + diff --git a/hw/vendor/patches/pulp_platform_tech_cells_generic/0004-tc_sram-Add-implementation-key-and-IO.patch b/hw/vendor/patches/pulp_platform_tech_cells_generic/0004-tc_sram-Add-implementation-key-and-IO.patch new file mode 100644 index 000000000..bd36a4d27 --- /dev/null +++ b/hw/vendor/patches/pulp_platform_tech_cells_generic/0004-tc_sram-Add-implementation-key-and-IO.patch @@ -0,0 +1,74 @@ +From 6d432be0933aebab417e8c8a00863a4177c336a7 Mon Sep 17 00:00:00 2001 +From: Paul Scheffler +Date: Fri, 8 Oct 2021 18:04:37 +0200 +Subject: [PATCH] tc_sram: Add implementation key and IO + +--- + src/rtl/tc_sram.sv | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv +index 0e9ff59..5c063dc 100644 +--- a/src/rtl/tc_sram.sv ++++ b/src/rtl/tc_sram.sv +@@ -30,6 +30,13 @@ + // "none": Each bit gets initialized with 1'bx. (default) + // - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with + // the instantiated parameters and signal widths. ++// - ImplKey: Key by which an instance can refer to a specific implementation (e.g. macro). ++// May be used to look up additional parameters for implementation (e.g. generator, ++// line width, muxing) in an external reference, such as a configuration file. ++// - impl_in_t: Implementation-related inputs, such as pseudo-static macro configuration inputs. ++// - impl_out_t: Implementation-related outputs. To ensure the behavioral accuracy of this model, ++// these may *not* have any effects at the behavioral abstraction level. ++// - ImplOutSim: Static output assumed by `impl_out_t` in behavioral simulation. + // + // Ports: + // - `clk_i`: Clock +@@ -40,6 +47,8 @@ + // - `wdata_i`: Write data, has to be valid on request + // - `be_i`: Byte enable, active high + // - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low. ++// - `impl_i`: Implementation-related inputs ++// - `impl_o`: Implementation-related outputs + // + // Behaviour: + // - Address collision: When Ports are making a write access onto the same address, +@@ -58,6 +67,10 @@ module tc_sram #( + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter bit PrintSimCfg = 1'b0, // Print configuration ++ parameter ImplKey = "none", // Reference to specific implementation ++ parameter type impl_in_t = logic, // Type for implementation inputs ++ parameter type impl_out_t = logic, // Type for implementation outputs ++ parameter impl_out_t ImplOutSim = 'X, // Implementation output in simulation + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div +@@ -67,6 +80,11 @@ module tc_sram #( + ) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low ++`ifndef PULP_TC_SRAM_NOIMPL ++ // Implementation-related IO ++ input impl_in_t impl_i, ++ output impl_out_t impl_o, ++`endif + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable +@@ -77,6 +95,11 @@ module tc_sram #( + output data_t [NumPorts-1:0] rdata_o // read data + ); + ++`ifndef PULP_TC_SRAM_NOIMPL ++ // constant implementation output in behavioral simulation ++ assign impl_o = ImplOutSim; ++`endif ++ + // memory array + data_t sram [NumWords-1:0]; + // hold the read address when no read access is made +-- +2.16.5 + diff --git a/hw/vendor/patches/pulp_platform_tech_cells_generic/0005-tc_sram-Add-implementation-stubs-to-fpga-module.patch b/hw/vendor/patches/pulp_platform_tech_cells_generic/0005-tc_sram-Add-implementation-stubs-to-fpga-module.patch new file mode 100644 index 000000000..7bfd2d813 --- /dev/null +++ b/hw/vendor/patches/pulp_platform_tech_cells_generic/0005-tc_sram-Add-implementation-stubs-to-fpga-module.patch @@ -0,0 +1,51 @@ +From 44b4900b2dccbedccfd0db7d100b25963aec45fe Mon Sep 17 00:00:00 2001 +From: Paul Scheffler +Date: Mon, 25 Oct 2021 23:15:52 +0200 +Subject: [PATCH] tc_sram: Add implementation stubs to fpga module + +--- + src/fpga/tc_sram_xilinx.sv | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/src/fpga/tc_sram_xilinx.sv b/src/fpga/tc_sram_xilinx.sv +index c706802..48aa784 100644 +--- a/src/fpga/tc_sram_xilinx.sv ++++ b/src/fpga/tc_sram_xilinx.sv +@@ -24,6 +24,10 @@ module tc_sram #( + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "zeros", // Simulation initialization, fixed to zero here! + parameter bit PrintSimCfg = 1'b0, // Print configuration ++ parameter ImplKey = "none", // Reference to specific implementation ++ parameter type impl_in_t = logic, // Type for implementation inputs ++ parameter type impl_out_t = logic, // Type for implementation outputs ++ parameter impl_out_t ImplOutSim = 'X, // Implementation output in simulation + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div +@@ -33,6 +37,11 @@ module tc_sram #( + ) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low ++`ifndef PULP_TC_SRAM_NOIMPL ++ // Implementation-related IO ++ input impl_in_t impl_i, ++ output impl_out_t impl_o, ++`endif + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable +@@ -43,6 +52,11 @@ module tc_sram #( + output data_t [NumPorts-1:0] rdata_o // read data + ); + ++`ifndef PULP_TC_SRAM_NOIMPL ++ // constant implementation output in behavioral simulation ++ assign impl_o = ImplOutSim; ++`endif ++ + localparam int unsigned DataWidthAligned = ByteWidth * BeWidth; + localparam int unsigned Size = NumWords * DataWidthAligned; + +-- +2.16.5 + diff --git a/hw/vendor/pulp_platform_tech_cells_generic/src/fpga/tc_sram_xilinx.sv b/hw/vendor/pulp_platform_tech_cells_generic/src/fpga/tc_sram_xilinx.sv index c70680266..48aa78403 100644 --- a/hw/vendor/pulp_platform_tech_cells_generic/src/fpga/tc_sram_xilinx.sv +++ b/hw/vendor/pulp_platform_tech_cells_generic/src/fpga/tc_sram_xilinx.sv @@ -24,6 +24,10 @@ module tc_sram #( parameter int unsigned Latency = 32'd1, // Latency when the read data is available parameter SimInit = "zeros", // Simulation initialization, fixed to zero here! parameter bit PrintSimCfg = 1'b0, // Print configuration + parameter ImplKey = "none", // Reference to specific implementation + parameter type impl_in_t = logic, // Type for implementation inputs + parameter type impl_out_t = logic, // Type for implementation outputs + parameter impl_out_t ImplOutSim = 'X, // Implementation output in simulation // DEPENDENT PARAMETERS, DO NOT OVERWRITE! parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div @@ -33,6 +37,11 @@ module tc_sram #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low +`ifndef PULP_TC_SRAM_NOIMPL + // Implementation-related IO + input impl_in_t impl_i, + output impl_out_t impl_o, +`endif // input ports input logic [NumPorts-1:0] req_i, // request input logic [NumPorts-1:0] we_i, // write enable @@ -43,6 +52,11 @@ module tc_sram #( output data_t [NumPorts-1:0] rdata_o // read data ); +`ifndef PULP_TC_SRAM_NOIMPL + // constant implementation output in behavioral simulation + assign impl_o = ImplOutSim; +`endif + localparam int unsigned DataWidthAligned = ByteWidth * BeWidth; localparam int unsigned Size = NumWords * DataWidthAligned; diff --git a/hw/vendor/pulp_platform_tech_cells_generic/src/rtl/tc_sram.sv b/hw/vendor/pulp_platform_tech_cells_generic/src/rtl/tc_sram.sv index 0e9ff59d8..5c063dc70 100644 --- a/hw/vendor/pulp_platform_tech_cells_generic/src/rtl/tc_sram.sv +++ b/hw/vendor/pulp_platform_tech_cells_generic/src/rtl/tc_sram.sv @@ -30,6 +30,13 @@ // "none": Each bit gets initialized with 1'bx. (default) // - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with // the instantiated parameters and signal widths. +// - ImplKey: Key by which an instance can refer to a specific implementation (e.g. macro). +// May be used to look up additional parameters for implementation (e.g. generator, +// line width, muxing) in an external reference, such as a configuration file. +// - impl_in_t: Implementation-related inputs, such as pseudo-static macro configuration inputs. +// - impl_out_t: Implementation-related outputs. To ensure the behavioral accuracy of this model, +// these may *not* have any effects at the behavioral abstraction level. +// - ImplOutSim: Static output assumed by `impl_out_t` in behavioral simulation. // // Ports: // - `clk_i`: Clock @@ -40,6 +47,8 @@ // - `wdata_i`: Write data, has to be valid on request // - `be_i`: Byte enable, active high // - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low. +// - `impl_i`: Implementation-related inputs +// - `impl_o`: Implementation-related outputs // // Behaviour: // - Address collision: When Ports are making a write access onto the same address, @@ -58,6 +67,10 @@ module tc_sram #( parameter int unsigned Latency = 32'd1, // Latency when the read data is available parameter SimInit = "none", // Simulation initialization parameter bit PrintSimCfg = 1'b0, // Print configuration + parameter ImplKey = "none", // Reference to specific implementation + parameter type impl_in_t = logic, // Type for implementation inputs + parameter type impl_out_t = logic, // Type for implementation outputs + parameter impl_out_t ImplOutSim = 'X, // Implementation output in simulation // DEPENDENT PARAMETERS, DO NOT OVERWRITE! parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div @@ -67,6 +80,11 @@ module tc_sram #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low +`ifndef PULP_TC_SRAM_NOIMPL + // Implementation-related IO + input impl_in_t impl_i, + output impl_out_t impl_o, +`endif // input ports input logic [NumPorts-1:0] req_i, // request input logic [NumPorts-1:0] we_i, // write enable @@ -77,6 +95,11 @@ module tc_sram #( output data_t [NumPorts-1:0] rdata_o // read data ); +`ifndef PULP_TC_SRAM_NOIMPL + // constant implementation output in behavioral simulation + assign impl_o = ImplOutSim; +`endif + // memory array data_t sram [NumWords-1:0]; // hold the read address when no read access is made diff --git a/target/sim/test/testharness.sv b/target/sim/test/testharness.sv index be9966506..91454a89b 100644 --- a/target/sim/test/testharness.sv +++ b/target/sim/test/testharness.sv @@ -234,6 +234,7 @@ module testharness import occamy_pkg::*; ( occamy_top i_occamy ( .clk_i, .rst_ni, + .sram_cfgs_i ('0), .clk_periph_i (clk_i), .rst_periph_ni (rst_ni), .rtc_i, diff --git a/target/sim/test/testharness.sv.tpl b/target/sim/test/testharness.sv.tpl index ed79939e2..f824710d0 100644 --- a/target/sim/test/testharness.sv.tpl +++ b/target/sim/test/testharness.sv.tpl @@ -61,6 +61,7 @@ module testharness import occamy_pkg::*; ( occamy_top i_occamy ( .clk_i, .rst_ni, + .sram_cfgs_i ('0), .clk_periph_i (clk_i), .rst_periph_ni (rst_ni), .rtc_i, diff --git a/util/solder/solder.py b/util/solder/solder.py index 5b39262d6..196852429 100644 --- a/util/solder/solder.py +++ b/util/solder/solder.py @@ -776,7 +776,12 @@ def add_ro_cache(self, start_addr=None, end_addr=None, inst_name=None, - to=None): + to=None, + sram_cfg_data_t=None, + sram_cfg_tag_t=None, + sram_cfg_data_i=None, + sram_cfg_tag_i=None + ): # Generate the new bus. if to is None: bus = copy(self) @@ -810,6 +815,10 @@ def add_ro_cache(self, start_addr=start_addr or "'0", end_addr=end_addr or "'1", name=inst_name or "i_{}".format(name), + sram_cfg_data_t=sram_cfg_data_t or 'logic', + sram_cfg_tag_t=sram_cfg_tag_t or 'logic', + sram_cfg_data_i=sram_cfg_data_i or ' ', + sram_cfg_tag_i=sram_cfg_tag_i or ' ' ) + "\n") return bus diff --git a/util/solder/solder.snitch_ro_cache.sv.tpl b/util/solder/solder.snitch_ro_cache.sv.tpl index c0553ff56..7b7a7e45c 100644 --- a/util/solder/solder.snitch_ro_cache.sv.tpl +++ b/util/solder/solder.snitch_ro_cache.sv.tpl @@ -11,7 +11,9 @@ .slv_req_t (${axi_in.req_type()}), .slv_rsp_t (${axi_in.rsp_type()}), .mst_req_t (${axi_out.req_type()}), - .mst_rsp_t (${axi_out.rsp_type()}) + .mst_rsp_t (${axi_out.rsp_type()}), + .sram_cfg_data_t (${sram_cfg_data_t}), + .sram_cfg_tag_t (${sram_cfg_tag_t}) ) ${name} ( .clk_i (${axi_in.clk}), .rst_ni (${axi_in.rst}), @@ -23,5 +25,7 @@ .axi_slv_req_i (${axi_in.req_name()}), .axi_slv_rsp_o (${axi_in.rsp_name()}), .axi_mst_req_o (${axi_out.req_name()}), - .axi_mst_rsp_i (${axi_out.rsp_name()}) + .axi_mst_rsp_i (${axi_out.rsp_name()}), + .sram_cfg_data_i (${sram_cfg_data_i}), + .sram_cfg_tag_i (${sram_cfg_tag_i}) );