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base repository: pulp-platform/mempool
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base: v0.4.0
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head repository: pulp-platform/mempool
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compare: main
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7 contributors

Commits on Jul 4, 2021

  1. [software] Add Halide runtime and build scripts

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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  2. [software] Update gradient example for MemPool

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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  3. [software] Add Halide convolution example

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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  4. [software] Add CI script for Halide applications

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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  5. [software] Add halide matrix multiplication

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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  6. [CHANGELOG] Add Halide applications

    @SamuelRiedel
    SamuelRiedel committed Jul 4, 2021
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Commits on Jul 5, 2021

  1. [README] Explain Halide applications simulation flow

    @SamuelRiedel
    SamuelRiedel committed Jul 5, 2021
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  2. Merge pull request #1 from pulp-platform/halide 

    Halide applications
    @SamuelRiedel
    SamuelRiedel authored Jul 5, 2021
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Commits on Jul 6, 2021

  1. [hardware] 👾 Fix elaboration issue of the mempool_system

    @suehtamacv
    suehtamacv committed Jul 6, 2021
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Commits on Jul 9, 2021

  1. [hardware] 👾 Remove ROB assertions when elaborating the design

    @suehtamacv
    suehtamacv committed Jul 9, 2021
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  2. [CHANGELOG] Update Changelog

    @suehtamacv
    suehtamacv committed Jul 9, 2021
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  3. Merge pull request #2 from pulp-platform/synth-issues 

    Synthesis issues
    @suehtamacv
    suehtamacv authored Jul 9, 2021
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Commits on Jul 12, 2021

  1. [ci] Compile Verilator with Clang

    @suehtamacv
    suehtamacv committed Jul 12, 2021
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  2. [ci] Add CI flow for MemPool with 16 and 256 cores

    @suehtamacv
    suehtamacv committed Jul 12, 2021
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  3. [README] Update Verilator compile requirements

    @suehtamacv
    suehtamacv committed Jul 12, 2021
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Commits on Jul 13, 2021

  1. [CHANGELOG] Update Changelog

    @suehtamacv
    suehtamacv committed Jul 13, 2021
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  2. Merge pull request #5 from pulp-platform/verilator_clang 

    Verilation with LLVM
    @suehtamacv
    suehtamacv authored Jul 13, 2021
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Commits on Jul 15, 2021

  1. [hardware] Add initial version of axi interconnect module

    @SamuelRiedel @suehtamacv
    SamuelRiedel authored and suehtamacv committed Jul 15, 2021
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  2. [hardware] Integrate hierarchical axi interconnect into group

    @SamuelRiedel @suehtamacv
    SamuelRiedel authored and suehtamacv committed Jul 15, 2021
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  3. [hardware] Make hierarchical interconnect recursive and configurable

    @SamuelRiedel @suehtamacv
    SamuelRiedel authored and suehtamacv committed Jul 15, 2021
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  4. [hardware] Add testmode port to the group

    @suehtamacv
    suehtamacv committed Jul 15, 2021
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  5. [CHANGELOG] Update Changelog

    @suehtamacv
    suehtamacv committed Jul 15, 2021
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  6. Merge pull request #3 from pulp-platform/axi_interconnect 

    Hierarchical AXI Interconnect
    @suehtamacv
    suehtamacv authored Jul 15, 2021
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Commits on Jul 22, 2021

  1. [README] Update paper reference

    @suehtamacv
    suehtamacv committed Jul 22, 2021
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Commits on Aug 2, 2021

  1. Merge pull request #8 from pulp-platform/paper 

    Update BibTeX reference
    @suehtamacv
    suehtamacv authored Aug 2, 2021
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Commits on Aug 4, 2021

  1. [toolchain] Specify Halide's library install directory 

    Different Linux distributions use different default paths for the
installed libraries but we need a known path for the compile scripts.
    @SamuelRiedel @suehtamacv
    SamuelRiedel authored and suehtamacv committed Aug 4, 2021
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  2. [ci] Fix Halide's library install directory for GitLab

    @SamuelRiedel @suehtamacv
    SamuelRiedel authored and suehtamacv committed Aug 4, 2021
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  3. [ci] Link Verilator against libc++

    @suehtamacv
    suehtamacv committed Aug 4, 2021
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  4. [Makefile] 🎨 Change indentation of the Makefile defines

    @suehtamacv
    suehtamacv committed Aug 4, 2021
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  5. Merge pull request #6 from pulp-platform/gitlab/ci 

    Fix GitLab CI
    @suehtamacv
    suehtamacv authored Aug 4, 2021
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  6. [tb] Implement the traffic_generator with DPI calls

    @suehtamacv
    suehtamacv committed Aug 4, 2021
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  7. [Bender] Add the traffic generator to the testbench file list

    @suehtamacv
    suehtamacv committed Aug 4, 2021
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  8. [hardware] Instantiate the traffic_generator

    @suehtamacv
    suehtamacv committed Aug 4, 2021
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Commits on Aug 5, 2021

  1. [hardware] Add traffic generation parameters to the Makefile

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  2. [scripts] Add script to run the load-throughput analysis

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  3. [snitch] Augment reorder buffer size when using the traffic generator

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  4. [verilator] Remove compilation warnings from the memutil DPI functions

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  5. [tb] Account for free transaction IDs on the C++ traffic generator

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  6. [tb] Rename extension of Verilator's traffic_generator DPI file

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  7. [CHANGELOG] Update Changelog

    @suehtamacv
    suehtamacv committed Aug 5, 2021
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  8. Merge pull request #9 from pulp-platform/traffic 

    Load-throughput analysis
    @suehtamacv
    suehtamacv authored Aug 5, 2021
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Commits on Aug 9, 2021

  1. [hardware] Replace groups' butterflies with log. interconnects

    @suehtamacv
    suehtamacv committed Aug 9, 2021
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  2. [CHANGELOG] Update Changelog

    @suehtamacv
    suehtamacv committed Aug 9, 2021
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  3. Merge pull request #10 from pulp-platform/lic 

    Replace group's butterflies with logarithmic interconnects
    @suehtamacv
    suehtamacv authored Aug 9, 2021
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Commits on Aug 10, 2021

  1. [hardware] Fix the names in the wave scripts

    @SamuelRiedel
    SamuelRiedel committed Aug 10, 2021
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  2. Merge pull request #11 from pulp-platform/wave 

    [hardware] Fix the names in the wave scripts
    @SamuelRiedel
    SamuelRiedel authored Aug 10, 2021
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Commits on Aug 11, 2021

  1. [scripts] Add trace visualization script

    @huettern @SamuelRiedel
    huettern authored and SamuelRiedel committed Aug 11, 2021
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  2. [scripts] Make tracevis work for MemPool

    @SamuelRiedel
    SamuelRiedel committed Aug 11, 2021
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  3. [scripts] Avoid rounding errors in tracevis

    @SamuelRiedel
    SamuelRiedel committed Aug 11, 2021
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  4. [scripts] Format tracevis

    @SamuelRiedel
    SamuelRiedel committed Aug 11, 2021
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Showing 469 changed files with 55,724 additions and 17,962 deletions.
1 change: 1 addition & 0 deletions .clang-format-ignore
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# Exclude files from formatting requirement
# External dependencies
*/software/runtime/control_registers.h
*/software/runtime/encoding.h
*/software/riscv-tests
*/toolchain
2 changes: 1 addition & 1 deletion .github/CODEOWNERS
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# Global owners
* @SamuelRiedel @suehtamacv
* @SamuelRiedel @mbertuletti @sermazz @yichao-zh
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