From a3331d668c03b2ec8b3cf856733db7a51f596b15 Mon Sep 17 00:00:00 2001 From: mbertuletti Date: Mon, 11 Dec 2023 08:34:47 +0100 Subject: [PATCH] [tests] Add zvechalfinx hardware tests --- software/Makefile | 1 + software/riscv-tests/isa/Makefile | 2 + .../riscv-tests/isa/rv32uzvechalfinx/Makefrag | 16 +++++++ .../isa/rv32uzvechalfinx/vfadd_h.S | 38 +++++++++++++++++ .../isa/rv32uzvechalfinx/vfcpka_h.S | 42 +++++++++++++++++++ .../isa/rv32uzvechalfinx/vfmac_h.S | 40 ++++++++++++++++++ .../isa/rv32uzvechalfinx/vfmin_h.S | 37 ++++++++++++++++ .../isa/rv32uzvechalfinx/vfsgnj_h.S | 38 +++++++++++++++++ software/riscv-tests/isa/snitch_isa.mk | 10 +++++ 9 files changed, 224 insertions(+) create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/Makefrag create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfadd_h.S create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfmac_h.S create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfmin_h.S create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfsgnj_h.S diff --git a/software/Makefile b/software/Makefile index b58e81c4c..230298a7b 100644 --- a/software/Makefile +++ b/software/Makefile @@ -51,6 +51,7 @@ $(eval $(call rtl_mempool_tests_template,rv32ua)) $(eval $(call rtl_mempool_tests_template,rv32uzfinx)) $(eval $(call rtl_mempool_tests_template,rv32uzhinx)) $(eval $(call rtl_mempool_tests_template,rv32uzquarterinx)) +$(eval $(call rtl_mempool_tests_template,rv32uzvechalfinx)) else $(eval $(call rtl_mempool_tests_template,rv32ui)) $(eval $(call rtl_mempool_tests_template,rv32um)) diff --git a/software/riscv-tests/isa/Makefile b/software/riscv-tests/isa/Makefile index 08fceb1e5..cbb1c8c51 100644 --- a/software/riscv-tests/isa/Makefile +++ b/software/riscv-tests/isa/Makefile @@ -29,6 +29,7 @@ include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfinx/Makefrag include $(src_dir)/rv32uzhinx/Makefrag include $(src_dir)/rv32uzquarterinx/Makefrag +include $(src_dir)/rv32uzvechalfinx/Makefrag ifneq ($(COMPILER), llvm) include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -131,6 +132,7 @@ RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepa $(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uzquarterinx,-march=$(RISCV_ARCH) -mabi=ilp32)) +$(eval $(call compile_template,rv32uzvechalfinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32)) else $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32)) diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag b/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag new file mode 100644 index 000000000..f3f7351a4 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag @@ -0,0 +1,16 @@ +#======================================================================= +# Makefrag for rv32uzquarterinx tests +#----------------------------------------------------------------------- + +ifeq ($(COMPILER), llvm) +rv32uzvechalfinx_sc_tests = \ + vfadd_h \ + vfmac_h \ + vfmin_h \ + vfsgnj_h \ + vfcpka_h +endif + +rv32uzvechalfinx_p_tests = $(addprefix rv32uzvechalfinx-p-, $(rv32uzvechalfinx_sc_tests)) + +# Zvechalfinx extensions are not tested on Spike diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfadd_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfadd_h.S new file mode 100644 index 000000000..5977811bc --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfadd_h.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfadd_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, vfadd.h, 0xE4D24300, 0xE4D34100, 0x3C663C00 ); + TEST_RR_OP( 3, vfadd.h, 0x4248E4D2, 0x4248E4D3, 0x00003C66 ); + + TEST_RR_OP( 4, vfsub.h, 0xE4D23E00, 0xE4D34100, 0xBC663C00 ); + TEST_RR_OP( 5, vfsub.h, 0x4248E4D2, 0x4248E4D3, 0x0000BC66 ); + + TEST_RR_OP( 6, vfmul.h, 0x654E4100, 0xE4D34100, 0xBC663C00 ); + TEST_RR_OP( 7, vfmul.h, 0x0000654E, 0x4248E4D3, 0x0000BC66 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S new file mode 100644 index 000000000..60b340109 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfcpka_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 0x4048F5C3; // 3.14 + # 0xC048F5C3; // -3.14 + # 0x3FCF1AA0; // 1.618 + # 0xBFCF1AA0; // -1.618 + + # 0xFFFF4248; // 3.14 + # 0xFFFFC248; // -3.14 + # 0xFFFF3E79; // 1.618 + # 0xFFFFBE79; // -1.618 + + TEST_RR_OP( 2, vfcpka.h.s, 0x3E794248, 0x4048F5C3, 0x3FCF1AA0 ); + TEST_RR_OP( 3, vfcpka.h.s, 0xBE79C248, 0xC048F5C3, 0xBFCF1AA0 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfmac_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfmac_h.S new file mode 100644 index 000000000..365aa0d41 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfmac_h.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfmac_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 4100 2.5 + # E4D3 -1235 + # BC00 -1 + # 3C00 1 + # 64D4 1236 + # 4300 3.5 + + # CHECK RS1 RS2 RD + TEST_RRR_OP( 2, vfmac.h, 0x4100E4D3, 0x00000000, 0x3C003C00, 0x4100E4D3 ); + TEST_RRR_OP( 3, vfmac.h, 0xC60064D5, 0xC0003C00, 0x430064D4, 0x3C003C00 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfmin_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfmin_h.S new file mode 100644 index 000000000..04e4ad3e1 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfmin_h.S @@ -0,0 +1,37 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfmin_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, vfmin.h, 0x3C00E4D3, 0x4100E4D3, 0x3C003C66 ); + TEST_RR_OP( 3, vfmin.h, 0xE4D3E4D3, 0x3C667E00, 0xE4D3E4D3 ); + TEST_RR_OP( 4, vfmin.h, 0x0000C000, 0x4248BC00, 0x0000C000 ); + + TEST_RR_OP( 5, vfmax.h, 0x41003C66, 0x4100E4D3, 0x3C003C66 ); + TEST_RR_OP( 6, vfmax.h, 0x3C66E4D3, 0x3C667E00, 0xE4D3E4D3 ); + TEST_RR_OP( 7, vfmax.h, 0x4248BC00, 0x4248BC00, 0x0000C000 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfsgnj_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfsgnj_h.S new file mode 100644 index 000000000..9dc2461bd --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfsgnj_h.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfsgnj_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, vfsgnj.h, 0x410064D3, 0x4100E4D3, 0x3C003C66 ); + TEST_RR_OP( 3, vfsgnj.h, 0x64D3BC66, 0xE4D33C66, 0x3C66E4D3 ); + + TEST_RR_OP( 5, vfsgnjn.h, 0xC100E4D3, 0x4100E4D3, 0x3C003C66 ); + TEST_RR_OP( 6, vfsgnjn.h, 0xE4D33C66, 0xE4D33C66, 0x3C66E4D3 ); + + TEST_RR_OP( 8, vfsgnjx.h, 0x4100E4D3, 0x4100E4D3, 0x3C003C66 ); + TEST_RR_OP( 9, vfsgnjx.h, 0xE4D3BC66, 0xE4D33C66, 0x3C66E4D3 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/snitch_isa.mk b/software/riscv-tests/isa/snitch_isa.mk index 212114de2..146de1887 100644 --- a/software/riscv-tests/isa/snitch_isa.mk +++ b/software/riscv-tests/isa/snitch_isa.mk @@ -129,12 +129,22 @@ ifeq ($(zfinx_rv),1) fmadd_b \ fmin_b \ fsgnj_b + rv32uzvechalfinx_snitch_sc_tests = \ + vfadd_h \ + vfcpka_h \ + vfmac_h \ + vfmin_h \ + vfsgnj_h + rv32uzfinx_mempool_tests = $(addprefix rv32uzfinx-mempool-, $(rv32uzfinx_snitch_sc_tests)) rv32uzhinx_mempool_tests = $(addprefix rv32uzhinx-mempool-, $(rv32uzhinx_snitch_sc_tests)) rv32uzquarterinx_mempool_tests = $(addprefix rv32uzquarterinx-mempool-, $(rv32uzquarterinx_snitch_sc_tests)) + rv32uzvechalfinx_mempool_tests = $(addprefix rv32uzvechalfinx-mempool-, $(rv32uzvechalfinx_snitch_sc_tests)) + rtl_mempool_tests += $(rv32uzfinx_mempool_tests) rtl_mempool_tests += $(rv32uzhinx_mempool_tests) rtl_mempool_tests += $(rv32uzquarterinx_mempool_tests) + rtl_mempool_tests += $(rv32uzvechalfinx_mempool_tests) endif endif