From 727f154517e589ca7903d41f42c2f9283048862d Mon Sep 17 00:00:00 2001
From: Thomas Benz <tbenz@iis.ee.ethz.ch>
Date: Fri, 13 Jan 2023 15:58:08 +0100
Subject: [PATCH] Add more variants of the backend

---
 Bender.lock | 14 +++++++-------
 Makefile    | 28 +++++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/Bender.lock b/Bender.lock
index 2c684666..180ddb57 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -9,8 +9,8 @@ packages:
     - common_verification
     - tech_cells_generic
   common_cells:
-    revision: 9c1a1bdbd1a0928340863cad90c6fc0503da43a7
-    version: 1.27.1
+    revision: 4dc9413990622dcbf4b37a19f792834c800da5c7
+    version: 1.28.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -26,7 +26,7 @@ packages:
     revision: null
     version: null
     source:
-      Path: /home/bsc22h2/bachelor-thesis/mdma/src/backend
+      Path: /home/tbenz/git/bslk/idma/idma-pd/mDMA/src/backend
     dependencies:
     - axi
     - common_cells
@@ -36,7 +36,7 @@ packages:
     revision: null
     version: null
     source:
-      Path: /home/bsc22h2/bachelor-thesis/mdma/src/package
+      Path: /home/tbenz/git/bslk/idma/idma-pd/mDMA/src/package
     dependencies:
     - axi
   register_interface:
@@ -51,15 +51,15 @@ packages:
     revision: null
     version: null
     source:
-      Path: /home/bsc22h2/bachelor-thesis/mdma/src/backend/../../test
+      Path: /home/tbenz/git/bslk/idma/idma-pd/mDMA/src/backend/../../test
     dependencies:
     - axi
     - common_cells
     - idma_pkg
     - register_interface
   tech_cells_generic:
-    revision: aef525b2dc7670525fc293dfc55f167e371b8c35
-    version: 0.2.10
+    revision: a9cae21902e75b1434328ecf36f85327ba5717de
+    version: 0.2.11
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
diff --git a/Makefile b/Makefile
index c4c9d99a..a1e92393 100644
--- a/Makefile
+++ b/Makefile
@@ -9,11 +9,22 @@ BENDER ?= bender
 PYTHON ?= python3
 
 RTL_CFGS ?= \
+	gen_rtl_obi.obi.split \
 	gen_rtl_axi.obi.split \
 	gen_rtl_obi.axi.split \
 	gen_rtl_axi.axi.split \
 	gen_rtl_axi-obi.axi-obi.split \
-	gen_rtl_axi.axi.combined
+	gen_rtl_axi_lite.axi_lite.split \
+	gen_rtl_axi_stream-axi.axi_stream-axi.split \
+	gen_rtl_axi_stream.axi_stream.split \
+	gen_rtl_axi-init.axi.split \
+	gen_rtl_init.obi.split \
+	gen_rtl_tilelink.tilelink.split \
+	gen_rtl_tilelink-axi.tilelink-axi.split \
+	gen_rtl_tilelink-axi-obi-axi_lite-axi_stream-init.obi.split \
+	gen_rtl_obi.tilelink-axi-axi_lite-axi_stream-obi.split \
+	gen_rtl_tilelink-axi-axi_lite-axi_stream-init-obi.tilelink-axi-axi_lite-axi_stream-obi.split
+
 
 # Extracting word nr. $(1) from $(2)-separated list $(3)
 pw = $(word $(1), $(subst $(2), ,$(3)))
@@ -296,6 +307,14 @@ bender-rm:
 gen_rtl: $(RTL_CFGS)
 
 gen_rtl_%: util/idma_gen.py Makefile
+	$(PYTHON) util/idma_gen.py transportlayer \
+	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
+	--write-protocols $(subst -, ,$(call pw,2,.,$*)) \
+	--shifter $(call pw,3,.,$*)
+	$(PYTHON) util/idma_gen.py legalizer \
+	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
+	--write-protocols $(subst -, ,$(call pw,2,.,$*)) \
+	--shifter $(call pw,3,.,$*)
 	$(PYTHON) util/idma_gen.py backend \
 	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
 	--write-protocols $(subst -, ,$(call pw,2,.,$*)) \
@@ -306,6 +325,13 @@ gen_rtl_%: util/idma_gen.py Makefile
 	$(PYTHON) util/idma_gen.py testbench \
 	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
 	--write-protocols $(subst -, ,$(call pw,2,.,$*))
+	$(PYTHON) util/idma_gen.py wavefile \
+	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
+	--write-protocols $(subst -, ,$(call pw,2,.,$*)) \
+	--shifter $(call pw,3,.,$*)
+	$(PYTHON) util/idma_gen.py bender \
+	--read-protocols $(subst -, ,$(call pw,1,.,$*)) \
+	--write-protocols $(subst -, ,$(call pw,2,.,$*))
 
 rtl_clean:
 	rm  -f src/backend/Bender.yml