From ed868dc6a7ee8aa08110ff64cccd8d4176defe50 Mon Sep 17 00:00:00 2001 From: "Emanuele Parisi emanuele.parisi@unibo.it" Date: Mon, 15 Apr 2024 22:41:29 +0200 Subject: [PATCH] Add parameters to enable Zicfiss and Zicfilp --- core/cva6.sv | 2 ++ core/include/config_pkg.sv | 6 +++++- core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv | 4 ++++ 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/core/cva6.sv b/core/cva6.sv index a330870b1a..230632244a 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -203,6 +203,8 @@ module cva6 CVA6Cfg.XFVec, CVA6Cfg.CvxifEn, CVA6Cfg.ZiCondExtEn, + CVA6Cfg.ZiCfiSSEn, + CVA6Cfg.ZiCfiLPEn, CVA6Cfg.RVSCLIC, // Extended bit'(RVF), diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index fb458ecb23..a8526f4a7a 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -76,6 +76,10 @@ package config_pkg; bit CvxifEn; // Zicond RISC-V extension bit ZiCondExtEn; + // Control-Flow Integrity - Zicfiss extension + bit ZiCfiSSEn; + // Control-Flow Integrity - Zicfilp extension + bit ZiCfiLPEn; // CLIC extension bit RVSCLIC; // Single precision FP RISC-V extension @@ -108,7 +112,7 @@ package config_pkg; bit RVU; // Address to jump when halt request logic [63:0] HaltAddress; - // Address to jump when exception + // Address to jump when exception logic [63:0] ExceptionAddress; // Return address stack depth int unsigned RASDepth; diff --git a/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv b/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv index cb3d53cabd..0bff86365f 100644 --- a/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcsclic_sv39_config_pkg.sv @@ -27,6 +27,8 @@ package cva6_config_pkg; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigHExtEn = 1; localparam CVA6ConfigZiCondExtEn = 1; + localparam CVA6ConfigZiCfiSSEn = 1; + localparam CVA6ConfigZiCfiLPEn = 1; localparam CVA6ConfigSclicExtEn = 1; localparam CVA6ConfigAxiIdWidth = 4; @@ -98,6 +100,8 @@ package cva6_config_pkg; XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn), + ZiCfiSSEn: bit'(CVA6ConfigZiCfiSSEn), + ZiCfiLPEn: bit'(CVA6ConfigZiCfiLPEn), RVSCLIC: bit'(CVA6ConfigSclicExtEn), // Extended RVF: