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If we set parameter bit AxiVldRdy = 1'b0 with NumIn > 1
parameter bit AxiVldRdy = 1'b0
NumIn > 1
assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]) & ~sel; assign gnt_o[l*2+1] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2+1]) & sel;
above code shows that if gnt_o would not be asserted if req_i == 0.
gnt_o
req_i == 0
But if we set NumIn == 1, the following code shows that gnt_o is just the same value as gnt_i and don't depend on req_i
NumIn == 1
gnt_i
req_i
// just pass through in this corner case if (NumIn == unsigned'(1)) begin : gen_pass_through assign req_o = req_i[0]; assign gnt_o[0] = gnt_i; assign data_o = data_i[0]; assign idx_o = '0; // non-degenerate cases end
This causes inconsistent grant behavior between NumIn == 1 and NumIn > 1 and subtle bugs on my design which only occurs when NumIn == 1.
Making the following changes in NumIn == 1 maybe makes it better?
// just pass through in this corner case if (NumIn == unsigned'(1)) begin : gen_pass_through assign req_o = req_i[0]; assign gnt_o[0] = gnt_i & (AxiVldRdy | req_i[0]; assign data_o = data_i[0]; assign idx_o = '0; // non-degenerate cases end
The text was updated successfully, but these errors were encountered:
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If we set
parameter bit AxiVldRdy = 1'b0
withNumIn > 1
above code shows that if
gnt_o
would not be asserted ifreq_i == 0
.But if we set
NumIn == 1
, the following code shows thatgnt_o
is just the same value asgnt_i
and don't depend onreq_i
This causes inconsistent grant behavior between
NumIn == 1
andNumIn > 1
and subtle bugs on my design which only occurs whenNumIn == 1
.Making the following changes in
NumIn == 1
maybe makes it better?The text was updated successfully, but these errors were encountered: