From fd7e43414c621875750bdd7d1fead21200eecd79 Mon Sep 17 00:00:00 2001 From: bluew Date: Sun, 28 May 2023 22:44:06 +0200 Subject: [PATCH 1/3] src/gen: Fix whitespace problems --- src/gen/clicint.hjson | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gen/clicint.hjson b/src/gen/clicint.hjson index f2fa0de..3fbbbe9 100644 --- a/src/gen/clicint.hjson +++ b/src/gen/clicint.hjson @@ -21,10 +21,10 @@ regwidth: "32", registers: [ { name: "CLICINT", - desc: "CLIC interrupt pending, enable, attribute and control", - swaccess: "rw", - hwaccess: "hro", - fields: [ + desc: "CLIC interrupt pending, enable, attribute and control", + swaccess: "rw", + hwaccess: "hro", + fields: [ { bits: "31:24", name: "CTL", desc: "interrupt control for interrupt" }, { bits: "23:22", name: "ATTR_MODE", desc: "privilege mode of this interrupt", resval: 3}, //{ bits: "21:19", name: "reserved" }, @@ -34,7 +34,7 @@ { bits: "7", name: "IE", desc: "interrupt enable for interrupt" }, { bits: "0", name: "IP", desc: "interrupt pending for interrupt", hwaccess: "hrw" }, - ], + ], } ] } From 78380c4c211cfc4997fe2ce5e38b78ba6ea123a0 Mon Sep 17 00:00:00 2001 From: bluew Date: Sun, 28 May 2023 22:46:23 +0200 Subject: [PATCH 2/3] src: Fix interrupt enable bit offset --- src/clicint_reg_top.sv | 6 +++--- src/gen/clicint.hjson | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/clicint_reg_top.sv b/src/clicint_reg_top.sv index 0ec8ae1..6552ea0 100644 --- a/src/clicint_reg_top.sv +++ b/src/clicint_reg_top.sv @@ -116,7 +116,7 @@ module clicint_reg_top #( ); - // F[ie]: 7:7 + // F[ie]: 8:8 prim_subreg #( .DW (1), .SWACCESS("RW"), @@ -266,7 +266,7 @@ module clicint_reg_top #( assign clicint_ip_wd = reg_wdata[0]; assign clicint_ie_we = addr_hit[0] & reg_we & !reg_error; - assign clicint_ie_wd = reg_wdata[7]; + assign clicint_ie_wd = reg_wdata[8]; assign clicint_attr_shv_we = addr_hit[0] & reg_we & !reg_error; assign clicint_attr_shv_wd = reg_wdata[16]; @@ -286,7 +286,7 @@ module clicint_reg_top #( unique case (1'b1) addr_hit[0]: begin reg_rdata_next[0] = clicint_ip_qs; - reg_rdata_next[7] = clicint_ie_qs; + reg_rdata_next[8] = clicint_ie_qs; reg_rdata_next[16] = clicint_attr_shv_qs; reg_rdata_next[18:17] = clicint_attr_trig_qs; reg_rdata_next[23:22] = clicint_attr_mode_qs; diff --git a/src/gen/clicint.hjson b/src/gen/clicint.hjson index 3fbbbe9..b8f128c 100644 --- a/src/gen/clicint.hjson +++ b/src/gen/clicint.hjson @@ -31,7 +31,7 @@ { bits: "18:17", name: "ATTR_TRIG", desc: "specify trigger type for this interrupt" }, { bits: "16", name: "ATTR_SHV", desc: "enable hardware vectoring for this interrupt" }, - { bits: "7", name: "IE", desc: "interrupt enable for interrupt" }, + { bits: "8", name: "IE", desc: "interrupt enable for interrupt" }, { bits: "0", name: "IP", desc: "interrupt pending for interrupt", hwaccess: "hrw" }, ], From 02cfeebc00b110aa294351fa336fcbfc6e822ca6 Mon Sep 17 00:00:00 2001 From: bluew Date: Sun, 28 May 2023 22:48:58 +0200 Subject: [PATCH 3/3] src: Fix mnlbits saturation logic --- src/clic.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/clic.sv b/src/clic.sv index bbdd7ce..044da34 100644 --- a/src/clic.sv +++ b/src/clic.sv @@ -271,7 +271,7 @@ module clic import mclic_reg_pkg::*; import clicint_reg_pkg::*; #( always_comb begin // Saturate nlbits if nlbits > clicintctlbits (nlbits > 0 && nlbits <= 8) mnlbits = INTCTLBITS; - if (mnlbits <= INTCTLBITS) + if (mclic_reg2hw.mcliccfg.mnlbits.q <= INTCTLBITS) mnlbits = mclic_reg2hw.mcliccfg.mnlbits.q; end