From 77c2f87086d2120a5afbc25a2d56a9c1f3ea082f Mon Sep 17 00:00:00 2001 From: mojtaba Date: Thu, 3 Oct 2024 13:28:57 +0200 Subject: [PATCH 1/4] Add support for VCU118 --- sw/boot/cheshire.vcu118.dts | 20 ++ target/xilinx/constraints/vcu118.xdc | 199 ++++++++++++++++ target/xilinx/constraints/vcu128.xdc | 279 +++++++++++++++++++---- target/xilinx/scripts/common.tcl | 5 + target/xilinx/scripts/impl_ip.tcl | 75 ++++++ target/xilinx/src/cheshire_top_xilinx.sv | 5 + target/xilinx/src/dram_wrapper_xilinx.sv | 75 ++++++ target/xilinx/src/phy_definitions.svh | 30 +++ target/xilinx/xilinx.mk | 3 +- 9 files changed, 648 insertions(+), 43 deletions(-) create mode 100644 sw/boot/cheshire.vcu118.dts create mode 100644 target/xilinx/constraints/vcu118.xdc diff --git a/sw/boot/cheshire.vcu118.dts b/sw/boot/cheshire.vcu118.dts new file mode 100644 index 000000000..c9b0f1878 --- /dev/null +++ b/sw/boot/cheshire.vcu118.dts @@ -0,0 +1,20 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig +// Mojtaba Rostami + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; // CS + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + clock-frequency = <1000000>; + disable-wp; + }; +}; diff --git a/target/xilinx/constraints/vcu118.xdc b/target/xilinx/constraints/vcu118.xdc new file mode 100644 index 000000000..7c398c73f --- /dev/null +++ b/target/xilinx/constraints/vcu118.xdc @@ -0,0 +1,199 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler + +############# +# Sys Clock # +############# + +# 125 MHz input clock +set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p] +set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n] +create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p] + +# SoC clock is generated by clock wizard and its constraints +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50] + + +####### +# MIG # +####### + +# Dram axi clock : 333 MHz (defined by MIG constraints) + +# False-path incoming reset +set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn] + +# Constrain outgoing reset +set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000 + +# Limit delay across DRAM CDC (hold already false-pathed) +# tclint-disable line-length +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000 +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000 +# tclint-enable line-length + +############### +# Assign Pins # +############### + +# tclint-disable line-length, spacing + +set_property PACKAGE_PIN AW25 [get_ports uart_rx_i] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i] +set_property PACKAGE_PIN BB21 [get_ports uart_tx_o] +set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o] + + +# Active high reset (GPIO_SW_N) +set_property PACKAGE_PIN BB24 [get_ports sys_reset] +set_property IOSTANDARD LVCMOS18 [get_ports sys_reset] + +# tclint-enable line-length, spacing + +# SD Card +set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i] +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o] +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}] +set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}] +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}] +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}] +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o] + + +## DDR4 + +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n] +set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p] + +set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n] +set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}] +set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}] +set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}] +set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}] +set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}] +set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}] +set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}] +set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}] +set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}] +set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}] +set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}] +set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}] +set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}] +set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}] +set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}] +set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}] +set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}] +set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}] +set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}] +set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}] +set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}] +set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}] +set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}] +set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}] +set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}] +set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}] +set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}] +set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}] +set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}] +set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}] +set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}] +set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] + +set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}] +set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}] +set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}] +set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}] +set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}] +set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}] +set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}] +set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}] +set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}] +set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}] +set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}] +set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}] +set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}] +set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}] +set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}] +set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}] +set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}] +set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}] +set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}] +set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}] +set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}] +set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}] +set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}] +set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}] +set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}] +set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}] +set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}] +set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}] +set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}] +set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}] +set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}] +set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}] +set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}] +set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}] +set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}] +set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}] +set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}] +set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}] +set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}] +set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}] +set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}] +set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}] +set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}] +set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}] +set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}] +set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}] +set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}] +set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}] +set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}] +set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}] +set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}] +set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}] +set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}] +set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}] +set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}] +set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}] +set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}] +set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}] +set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}] +set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}] + +set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}] +set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}] +set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}] +set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}] + +set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}] +set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}] +set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}] +set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}] +set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}] +set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}] +set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}] +set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}] +set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}] +set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}] +set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}] +set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}] +set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}] +set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}] +set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}] +set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}] + +set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}] +set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n] + +########## + + diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc index c0857740e..f1d9d86b6 100644 --- a/target/xilinx/constraints/vcu128.xdc +++ b/target/xilinx/constraints/vcu128.xdc @@ -12,38 +12,28 @@ ############# # 100 MHz input clock -set SYS_TCK 10 -create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] +create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p] # SoC clock is generated by clock wizard and its constraints -set SOC_TCK 20.0 -set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50] ####### # MIG # ####### # Dram axi clock : 333 MHz (defined by MIG constraints) -set MIG_TCK 3 # False-path incoming reset -set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn] -set_false_path -hold -setup -through $MIG_RST_I +set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn] # Constrain outgoing reset -set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] -set_false_path -hold -through $MIG_RST_O -set_max_delay -through $MIG_RST_O $MIG_TCK +set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000 # Limit delay across DRAM CDC (hold already false-pathed) # tclint-disable line-length -set_max_delay -datapath_only \ - -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK -set_max_delay -datapath_only \ - -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000 +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000 # tclint-enable line-length ############### @@ -52,35 +42,240 @@ set_max_delay -datapath_only \ # tclint-disable line-length, spacing -set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 -set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 -set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 -set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property PACKAGE_PIN AW25 [get_ports uart_rx_i] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i] +set_property PACKAGE_PIN BB21 [get_ports uart_tx_o] +set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o] # Jtag GPIOs goes to the FMC XM105 where the debug cable is connected (example Digilent HS2) -set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND -set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; -set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD -set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; -set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] -set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; -set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; -set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] +# set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] +# set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] +# set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] +# set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] +# set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] +# set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] +# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] # Clock diff @ 100MHz -set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] -set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] -set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] -set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] -set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] -set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] +# set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +# set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +# set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] +# set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] +set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p] +set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n] +create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p] -# Active high reset -set_property PACKAGE_PIN BM29 [get_ports sys_reset] -set_property IOSTANDARD LVCMOS12 [get_ports sys_reset] +# Active high reset GPIO_SW_N +set_property PACKAGE_PIN BB24 [get_ports sys_reset] +set_property IOSTANDARD LVCMOS18 [get_ports sys_reset] # tclint-enable line-length, spacing + +# SD Card +set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i] +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o] +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}] +set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}] +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}] +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}] +set_property -dict { PACKAGE_PIN AV11 IOSTANDARD LVCMOS12 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o] + + +## DDR4 + +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n] +set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p] + +set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n] +set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}] +set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}] +set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}] +set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}] +set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}] +set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}] +set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}] +set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}] +set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}] +set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}] +set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}] +set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}] +set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}] +set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}] +set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}] +set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}] +set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}] +set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}] +set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}] +set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}] +set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}] +set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}] +set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}] +set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}] +set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}] +set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}] +set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}] +set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}] +set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}] +set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}] +set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}] +set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] + +set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}] +set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}] +set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}] +set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}] +set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}] +set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}] +set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}] +set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}] +set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}] +set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}] +set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}] +set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}] +set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}] +set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}] +set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}] +set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}] +set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}] +set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}] +set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}] +set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}] +set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}] +set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}] +set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}] +set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}] +set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}] +set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}] +set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}] +set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}] +set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}] +set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}] +set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}] +set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}] +set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}] +set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}] +set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}] +set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}] +set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}] +set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}] +set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}] +set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}] +set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}] +set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}] +set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}] +set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}] +set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}] +set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}] +set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}] +set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}] +set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}] +set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}] +set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}] +set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}] +set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}] +set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}] +set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}] +set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}] +set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}] +set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}] +set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}] +set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}] + +set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}] +set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}] +set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}] +set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}] + +set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}] +set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}] +set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}] +set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}] +set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}] +set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}] +set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}] +set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}] +set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}] +set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}] +set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}] +set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}] +set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}] +set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}] +set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}] +set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}] + +set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}] +set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n] + +########## + + +connect_debug_port i_ila/probe2 [get_nets [list vio_reset]] + + +connect_debug_port u_ila_1/clk [get_nets [list i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/addn_ui_clkout1]] +connect_debug_port u_ila_1/probe0 [get_nets [list i_dram_wrapper/c0_init_calib_complete]] +connect_debug_port dbg_hub/clk [get_nets clk] + + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 6 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list i_clkwiz/inst/clk_50]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 2 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {spi_cs_soc[0]} {spi_cs_soc[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 2 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {spi_cs_en[0]} {spi_cs_en[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 4 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {spi_sd_soc_out[0]} {spi_sd_soc_out[1]} {spi_sd_soc_out[2]} {spi_sd_soc_out[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 4 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {spi_sd_soc_in[0]} {spi_sd_soc_in[1]} {spi_sd_soc_in[2]} {spi_sd_soc_in[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {vio_boot_mode[0]} {vio_boot_mode[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 4 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {spi_sd_en[0]} {spi_sd_en[1]} {spi_sd_en[2]} {spi_sd_en[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list spi_sck_en]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list spi_sck_soc]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list vio_boot_mode_sel]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets soc_clk] + + diff --git a/target/xilinx/scripts/common.tcl b/target/xilinx/scripts/common.tcl index d49816b21..0cdf034b9 100644 --- a/target/xilinx/scripts/common.tcl +++ b/target/xilinx/scripts/common.tcl @@ -15,6 +15,11 @@ set fpart(vcu128) "xcvu37p-fsvh2892-2L-e" set hwdev(vcu128) "xcvu37p_0" set cfgmp(vcu128) "mt25qu02g-spi-x1_x2_x4" +# vcu118 board params +set bpart(vcu118) "xilinx.com:vcu118:part0:2.4" +set fpart(vcu118) "xcvu9p-flga2104-2L-e" +set hwdev(vcu118) "xcvu9p_0" + # Initialize an implementation project proc init_impl {xilinx_root argc argv} { diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl index be4aa9a41..ae009e915 100644 --- a/target/xilinx/scripts/impl_ip.tcl +++ b/target/xilinx/scripts/impl_ip.tcl @@ -87,6 +87,43 @@ switch $proj { CONFIG.CLKOUT4_PHASE_ERROR {89.971} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_RESET {true} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {125.000} \ + CONFIG.CLKOUT1_USED {true} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_50} \ + CONFIG.CLK_OUT2_PORT {clk_48} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {48.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {8.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {25} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {196.543} \ + CONFIG.CLKOUT1_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT2_JITTER {197.699} \ + CONFIG.CLKOUT2_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT3_JITTER {227.146} \ + CONFIG.CLKOUT3_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT4_JITTER {261.444} \ + CONFIG.CLKOUT4_PHASE_ERROR {222.305} \ + ] [get_ips $proj] + } default { nocfgexit $proj $board } } } @@ -116,6 +153,17 @@ switch $proj { CONFIG.C_NUM_PROBE_IN {0} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $proj] + } default { nocfgexit $proj $board } } } @@ -162,6 +210,33 @@ switch $proj { CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.C0.DDR4_Clamshell {false} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \ + CONFIG.System_Clock {Differential} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ + CONFIG.C0.DDR4_Ecc {false} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {31} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_CasWriteLatency {9} \ + CONFIG.C0.DDR4_TimePeriod {1250} \ + CONFIG.C0.DDR4_Specify_MandD {true} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {8} \ + CONFIG.C0.DDR4_DIVCLK_DIVIDE {2} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + ] [get_ips $proj] + } default { nocfgexit $proj $board } } } diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 563f2f5f7..50c7608d8 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -7,6 +7,7 @@ // Cyril Koenig // Yann Picod // Paul Scheffler +// Mojtaba Rostami `include "cheshire/typedef.svh" `include "phy_definitions.svh" @@ -52,7 +53,9 @@ module cheshire_top_xilinx import cheshire_pkg::*; ( input logic sd_cd_i, output logic sd_cmd_o, inout wire [3:0] sd_d_io, +`ifndef TARGET_VCU118 output logic sd_reset_o, +`endif output logic sd_sclk_o, `endif @@ -257,8 +260,10 @@ module cheshire_top_xilinx import cheshire_pkg::*; ( logic [3:0] spi_sd_en; `ifdef USE_SD +`ifndef TARGET_VCU118 // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; +`endif // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; // CS - SD DAT3 signal diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv index 2a4719a03..13e056321 100644 --- a/target/xilinx/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/src/dram_wrapper_xilinx.sv @@ -4,6 +4,7 @@ // // Cyril Koenig // Paul Scheffler +// Mojtaba Rostami // // Resize AXI AW, IW, and DW before connecting to a Xilinx DRAM controller. @@ -53,6 +54,19 @@ module dram_wrapper_xilinx #( integer MaxTxns; } dram_cfg_t; +`ifdef TARGET_VCU118 + localparam dram_cfg_t cfg = '{ + EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) + CdcLogDepth : 5, + IdWidth : 8, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64, + MaxUniqIds : 8, // TODO: suboptimal, but limited by CVA6/LLC + MaxTxns : 24 // TODO: suboptimal, but limited by CVA6/LLC + }; +`endif + `ifdef TARGET_VCU128 localparam dram_cfg_t cfg = '{ EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) @@ -223,6 +237,7 @@ module dram_wrapper_xilinx #( ///////////////////////// `ifdef USE_DDR4 +`ifdef TARGET_VCU128 ddr4 i_dram ( // Reset .sys_rst ( sys_rst_i ), // Active high @@ -296,6 +311,66 @@ module dram_wrapper_xilinx #( // PHY .* ); +`endif +`ifdef TARGET_VCU118 + ddr4 i_dram ( + // Reset + .sys_rst ( sys_rst_i ), // Active high + .c0_ddr4_aresetn ( soc_resetn_i ), + // Clock and reset out + .c0_sys_clk_p ( c0_sys_clk_p ), + .c0_sys_clk_n ( c0_sys_clk_n ), + + .c0_ddr4_ui_clk ( dram_axi_clk ), + .c0_ddr4_ui_clk_sync_rst ( dram_rst_o ), + // AXI + .c0_ddr4_s_axi_awid ( cdc_dram_req.aw.id ), + .c0_ddr4_s_axi_awaddr ( cdc_dram_req_aw_addr ), + .c0_ddr4_s_axi_awlen ( cdc_dram_req.aw.len ), + .c0_ddr4_s_axi_awsize ( cdc_dram_req.aw.size ), + .c0_ddr4_s_axi_awburst ( cdc_dram_req.aw.burst ), + .c0_ddr4_s_axi_awlock ( cdc_dram_req.aw.lock ), + .c0_ddr4_s_axi_awcache ( cdc_dram_req.aw.cache ), + .c0_ddr4_s_axi_awprot ( cdc_dram_req.aw.prot ), + .c0_ddr4_s_axi_awqos ( cdc_dram_req.aw.qos ), + .c0_ddr4_s_axi_awvalid ( cdc_dram_req.aw_valid ), + .c0_ddr4_s_axi_awready ( cdc_dram_rsp.aw_ready ), + .c0_ddr4_s_axi_wdata ( cdc_dram_req.w.data ), + .c0_ddr4_s_axi_wstrb ( cdc_dram_req.w.strb ), + .c0_ddr4_s_axi_wlast ( cdc_dram_req.w.last ), + .c0_ddr4_s_axi_wvalid ( cdc_dram_req.w_valid ), + .c0_ddr4_s_axi_wready ( cdc_dram_rsp.w_ready ), + .c0_ddr4_s_axi_bready ( cdc_dram_req.b_ready ), + .c0_ddr4_s_axi_bid ( cdc_dram_rsp.b.id ), + .c0_ddr4_s_axi_bresp ( cdc_dram_rsp.b.resp ), + .c0_ddr4_s_axi_bvalid ( cdc_dram_rsp.b_valid ), + .c0_ddr4_s_axi_arid ( cdc_dram_req.ar.id ), + .c0_ddr4_s_axi_araddr ( cdc_dram_req_ar_addr ), + .c0_ddr4_s_axi_arlen ( cdc_dram_req.ar.len ), + .c0_ddr4_s_axi_arsize ( cdc_dram_req.ar.size ), + .c0_ddr4_s_axi_arburst ( cdc_dram_req.ar.burst ), + .c0_ddr4_s_axi_arlock ( cdc_dram_req.ar.lock ), + .c0_ddr4_s_axi_arcache ( cdc_dram_req.ar.cache ), + .c0_ddr4_s_axi_arprot ( cdc_dram_req.ar.prot ), + .c0_ddr4_s_axi_arqos ( cdc_dram_req.ar.qos ), + .c0_ddr4_s_axi_arvalid ( cdc_dram_req.ar_valid ), + .c0_ddr4_s_axi_arready ( cdc_dram_rsp.ar_ready ), + .c0_ddr4_s_axi_rready ( cdc_dram_req.r_ready ), + .c0_ddr4_s_axi_rid ( cdc_dram_rsp.r.id ), + .c0_ddr4_s_axi_rdata ( cdc_dram_rsp.r.data ), + .c0_ddr4_s_axi_rresp ( cdc_dram_rsp.r.resp ), + .c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ), + .c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ), + // Others + .c0_init_calib_complete ( ), + .addn_ui_clkout1 ( dram_clk_o ), + .dbg_clk ( ), + .dbg_bus ( ), + // PHY + .* + ); + +`endif `endif ///////////////////////// diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index db651854b..58d0d6266 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -3,6 +3,14 @@ // SPDX-License-Identifier: SHL-0.51 // // Cyril Koenig +// Mojtaba Rostami + +`ifdef TARGET_VCU118 + `define USE_RESET + `define USE_SD + `define USE_DDR4 + `define USE_VIO +`endif `ifdef TARGET_VCU128 `define USE_RESET @@ -46,6 +54,27 @@ `define USE_DDR `endif +`ifdef TARGET_VCU118 +`define DDR4_INTF \ + input c0_sys_clk_p, \ + input c0_sys_clk_n, \ + output c0_ddr4_reset_n, \ + output [0:0] c0_ddr4_ck_t, \ + output [0:0] c0_ddr4_ck_c, \ + output c0_ddr4_act_n, \ + output [16:0] c0_ddr4_adr, \ + output [1:0] c0_ddr4_ba, \ + output [0:0] c0_ddr4_bg, \ + output [0:0] c0_ddr4_cke, \ + output [0:0] c0_ddr4_odt, \ + output [0:0] c0_ddr4_cs_n, \ + inout [7:0] c0_ddr4_dm_dbi_n, \ + inout [63:0] c0_ddr4_dq, \ + inout [7:0] c0_ddr4_dqs_c, \ + inout [7:0] c0_ddr4_dqs_t, +`endif + +`ifdef TARGET_VCU128 `define DDR4_INTF \ output c0_ddr4_reset_n, \ output [0:0] c0_ddr4_ck_t, \ @@ -61,6 +90,7 @@ inout [71:0] c0_ddr4_dq, \ inout [8:0] c0_ddr4_dqs_c, \ inout [8:0] c0_ddr4_dqs_t, +`endif `define DDR3_INTF \ output ddr3_ck_p, \ diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 5060f6c96..5e25b0cbd 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -35,10 +35,11 @@ $(CHS_XILINX_DIR)/build/%/out.xci: \ # Bitstreams # ############## -CHS_XILINX_BOARDS := genesys2 vcu128 +CHS_XILINX_BOARDS := genesys2 vcu128 vcu118 CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s CHS_XILINX_IPS_vcu128 := clkwiz vio ddr4 +CHS_XILINX_IPS_vcu118 := clkwiz vio ddr4 $(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@ From 44315f2b5aa16da5936d4813447ff432febf0941 Mon Sep 17 00:00:00 2001 From: mojtaba Date: Fri, 11 Oct 2024 13:38:29 +0200 Subject: [PATCH 2/4] Adjust vcu118.xdc and revert vcu128.xdc --- target/xilinx/constraints/vcu118.xdc | 34 +++- target/xilinx/constraints/vcu128.xdc | 279 ++++----------------------- 2 files changed, 66 insertions(+), 247 deletions(-) diff --git a/target/xilinx/constraints/vcu118.xdc b/target/xilinx/constraints/vcu118.xdc index 7c398c73f..16c4e1696 100644 --- a/target/xilinx/constraints/vcu118.xdc +++ b/target/xilinx/constraints/vcu118.xdc @@ -12,37 +12,51 @@ ############# # 125 MHz input clock -set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p] -set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n] -create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p] +set SYS_TCK 8 +create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] # SoC clock is generated by clock wizard and its constraints -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50] +set SOC_TCK 20.0 +set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk] ####### # MIG # ####### -# Dram axi clock : 333 MHz (defined by MIG constraints) +# Dram axi clock : 200 MHz (defined by MIG constraints) +set MIG_TCK 5 # False-path incoming reset -set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn] +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn] +set_false_path -hold -setup -through $MIG_RST_I # Constrain outgoing reset -set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] -set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000 +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK # Limit delay across DRAM CDC (hold already false-pathed) # tclint-disable line-length -set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000 -set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000 +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK # tclint-enable line-length ############### # Assign Pins # ############### +# Clock diff @ 125MHz +set_property IOSTANDARD LVDS [get_ports sys_clk_n] +set_property IOSTANDARD LVDS [get_ports sys_clk_p] +set_property PACKAGE_PIN AY24 [get_ports sys_clk_p] +set_property PACKAGE_PIN AY23 [get_ports sys_clk_n] + # tclint-disable line-length, spacing set_property PACKAGE_PIN AW25 [get_ports uart_rx_i] diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc index f1d9d86b6..c0857740e 100644 --- a/target/xilinx/constraints/vcu128.xdc +++ b/target/xilinx/constraints/vcu128.xdc @@ -12,28 +12,38 @@ ############# # 100 MHz input clock -create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p] +set SYS_TCK 10 +create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] # SoC clock is generated by clock wizard and its constraints -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50] +set SOC_TCK 20.0 +set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk] ####### # MIG # ####### # Dram axi clock : 333 MHz (defined by MIG constraints) +set MIG_TCK 3 # False-path incoming reset -set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn] +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn] +set_false_path -hold -setup -through $MIG_RST_I # Constrain outgoing reset -set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] -set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000 +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK # Limit delay across DRAM CDC (hold already false-pathed) # tclint-disable line-length -set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000 -set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000 +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK # tclint-enable line-length ############### @@ -42,240 +52,35 @@ set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mi # tclint-disable line-length, spacing -set_property PACKAGE_PIN AW25 [get_ports uart_rx_i] -set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i] -set_property PACKAGE_PIN BB21 [get_ports uart_tx_o] -set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o] +set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 # Jtag GPIOs goes to the FMC XM105 where the debug cable is connected (example Digilent HS2) -# set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] -# set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] -# set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] -# set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] -# set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] -# set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] -# set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] # Clock diff @ 100MHz -# set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] -# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] -# set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] -# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] -# set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] -# set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] -set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p] -set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n] -create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p] +set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] +set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] -# Active high reset GPIO_SW_N -set_property PACKAGE_PIN BB24 [get_ports sys_reset] -set_property IOSTANDARD LVCMOS18 [get_ports sys_reset] +# Active high reset +set_property PACKAGE_PIN BM29 [get_ports sys_reset] +set_property IOSTANDARD LVCMOS12 [get_ports sys_reset] # tclint-enable line-length, spacing - -# SD Card -set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i] -set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o] -set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}] -set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}] -set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}] -set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}] -set_property -dict { PACKAGE_PIN AV11 IOSTANDARD LVCMOS12 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset -set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o] - - -## DDR4 - -set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n] -set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p] -set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n] -set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p] - -set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n] -set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}] -set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}] -set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}] -set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}] -set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}] -set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}] -set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}] -set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}] -set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}] -set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}] -set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}] -set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}] -set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}] -set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}] -set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}] -set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}] -set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}] -set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}] -set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}] -set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}] -set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}] -set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}] -set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}] -set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}] -set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}] -set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}] -set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}] -set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}] -set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}] -set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}] -set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}] -set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] - -set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}] -set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}] -set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}] -set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}] -set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}] -set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}] -set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}] -set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}] -set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}] -set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}] -set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}] -set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}] -set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}] -set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}] -set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}] -set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}] -set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}] -set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}] -set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}] -set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}] -set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}] -set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}] -set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}] -set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}] -set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}] -set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}] -set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}] -set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}] -set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}] -set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}] -set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}] -set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}] -set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}] -set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}] -set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}] -set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}] -set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}] -set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}] -set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}] -set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}] -set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}] -set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}] -set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}] -set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}] -set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}] -set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}] -set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}] -set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}] -set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}] -set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}] -set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}] -set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}] -set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}] -set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}] -set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}] -set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}] -set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}] -set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}] -set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}] -set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}] - -set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}] -set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}] -set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}] -set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}] - -set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}] -set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}] -set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}] -set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}] -set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}] -set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}] -set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}] -set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}] -set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}] -set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}] -set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}] -set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}] -set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}] -set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}] -set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}] -set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}] - -set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}] -set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n] - -########## - - -connect_debug_port i_ila/probe2 [get_nets [list vio_reset]] - - -connect_debug_port u_ila_1/clk [get_nets [list i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/addn_ui_clkout1]] -connect_debug_port u_ila_1/probe0 [get_nets [list i_dram_wrapper/c0_init_calib_complete]] -connect_debug_port dbg_hub/clk [get_nets clk] - - -create_debug_core u_ila_0 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] -set_property C_INPUT_PIPE_STAGES 6 [get_debug_cores u_ila_0] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] -set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list i_clkwiz/inst/clk_50]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 2 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {spi_cs_soc[0]} {spi_cs_soc[1]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 2 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {spi_cs_en[0]} {spi_cs_en[1]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 4 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {spi_sd_soc_out[0]} {spi_sd_soc_out[1]} {spi_sd_soc_out[2]} {spi_sd_soc_out[3]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 4 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {spi_sd_soc_in[0]} {spi_sd_soc_in[1]} {spi_sd_soc_in[2]} {spi_sd_soc_in[3]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 2 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {vio_boot_mode[0]} {vio_boot_mode[1]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 4 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {spi_sd_en[0]} {spi_sd_en[1]} {spi_sd_en[2]} {spi_sd_en[3]}]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list spi_sck_en]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list spi_sck_soc]] -create_debug_port u_ila_0 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list vio_boot_mode_sel]] -set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] -set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets soc_clk] - - From 9acf49819c646708cb36e45d9730f8cabf1a4899 Mon Sep 17 00:00:00 2001 From: mojtaba Date: Fri, 11 Oct 2024 13:59:20 +0200 Subject: [PATCH 3/4] Fix AddrWidth for VCU118 target --- target/xilinx/src/dram_wrapper_xilinx.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv index 13e056321..76a30a438 100644 --- a/target/xilinx/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/src/dram_wrapper_xilinx.sv @@ -56,10 +56,10 @@ module dram_wrapper_xilinx #( `ifdef TARGET_VCU118 localparam dram_cfg_t cfg = '{ - EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) + EnCdc : 1, // 200 MHz AXI (cf. CdcLogDepth) CdcLogDepth : 5, IdWidth : 8, - AddrWidth : 32, + AddrWidth : 31, DataWidth : 512, StrobeWidth : 64, MaxUniqIds : 8, // TODO: suboptimal, but limited by CVA6/LLC From b3f156c62aa7cb64a33e430be31579b38942094f Mon Sep 17 00:00:00 2001 From: mojtaba Date: Fri, 11 Oct 2024 15:11:58 +0200 Subject: [PATCH 4/4] Mutualize DDR4 instantiation --- target/xilinx/src/dram_wrapper_xilinx.sv | 65 +++--------------------- 1 file changed, 6 insertions(+), 59 deletions(-) diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv index 76a30a438..116c3a44d 100644 --- a/target/xilinx/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/src/dram_wrapper_xilinx.sv @@ -237,11 +237,15 @@ module dram_wrapper_xilinx #( ///////////////////////// `ifdef USE_DDR4 -`ifdef TARGET_VCU128 ddr4 i_dram ( // Reset .sys_rst ( sys_rst_i ), // Active high +`ifdef TARGET_VCU128 .c0_sys_clk_i ( dram_clk_i ), +`elsif TARGET_VCU118 + .c0_sys_clk_p ( c0_sys_clk_p ), + .c0_sys_clk_n ( c0_sys_clk_n ), +`endif .c0_ddr4_aresetn ( soc_resetn_i ), // Clock and reset out .c0_ddr4_ui_clk ( dram_axi_clk ), @@ -285,6 +289,7 @@ module dram_wrapper_xilinx #( .c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ), .c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ), // TODO: Shouldn't we map this to an external reg port? +`ifdef TARGET_VCU128 // AXI control .c0_ddr4_s_axi_ctrl_awvalid ( '0 ), .c0_ddr4_s_axi_ctrl_awready ( ), @@ -303,64 +308,7 @@ module dram_wrapper_xilinx #( .c0_ddr4_s_axi_ctrl_rdata ( ), .c0_ddr4_s_axi_ctrl_rresp ( ), .c0_ddr4_interrupt ( ), - // Others - .c0_init_calib_complete ( ), - .addn_ui_clkout1 ( dram_clk_o ), - .dbg_clk ( ), - .dbg_bus ( ), - // PHY - .* - ); `endif -`ifdef TARGET_VCU118 - ddr4 i_dram ( - // Reset - .sys_rst ( sys_rst_i ), // Active high - .c0_ddr4_aresetn ( soc_resetn_i ), - // Clock and reset out - .c0_sys_clk_p ( c0_sys_clk_p ), - .c0_sys_clk_n ( c0_sys_clk_n ), - - .c0_ddr4_ui_clk ( dram_axi_clk ), - .c0_ddr4_ui_clk_sync_rst ( dram_rst_o ), - // AXI - .c0_ddr4_s_axi_awid ( cdc_dram_req.aw.id ), - .c0_ddr4_s_axi_awaddr ( cdc_dram_req_aw_addr ), - .c0_ddr4_s_axi_awlen ( cdc_dram_req.aw.len ), - .c0_ddr4_s_axi_awsize ( cdc_dram_req.aw.size ), - .c0_ddr4_s_axi_awburst ( cdc_dram_req.aw.burst ), - .c0_ddr4_s_axi_awlock ( cdc_dram_req.aw.lock ), - .c0_ddr4_s_axi_awcache ( cdc_dram_req.aw.cache ), - .c0_ddr4_s_axi_awprot ( cdc_dram_req.aw.prot ), - .c0_ddr4_s_axi_awqos ( cdc_dram_req.aw.qos ), - .c0_ddr4_s_axi_awvalid ( cdc_dram_req.aw_valid ), - .c0_ddr4_s_axi_awready ( cdc_dram_rsp.aw_ready ), - .c0_ddr4_s_axi_wdata ( cdc_dram_req.w.data ), - .c0_ddr4_s_axi_wstrb ( cdc_dram_req.w.strb ), - .c0_ddr4_s_axi_wlast ( cdc_dram_req.w.last ), - .c0_ddr4_s_axi_wvalid ( cdc_dram_req.w_valid ), - .c0_ddr4_s_axi_wready ( cdc_dram_rsp.w_ready ), - .c0_ddr4_s_axi_bready ( cdc_dram_req.b_ready ), - .c0_ddr4_s_axi_bid ( cdc_dram_rsp.b.id ), - .c0_ddr4_s_axi_bresp ( cdc_dram_rsp.b.resp ), - .c0_ddr4_s_axi_bvalid ( cdc_dram_rsp.b_valid ), - .c0_ddr4_s_axi_arid ( cdc_dram_req.ar.id ), - .c0_ddr4_s_axi_araddr ( cdc_dram_req_ar_addr ), - .c0_ddr4_s_axi_arlen ( cdc_dram_req.ar.len ), - .c0_ddr4_s_axi_arsize ( cdc_dram_req.ar.size ), - .c0_ddr4_s_axi_arburst ( cdc_dram_req.ar.burst ), - .c0_ddr4_s_axi_arlock ( cdc_dram_req.ar.lock ), - .c0_ddr4_s_axi_arcache ( cdc_dram_req.ar.cache ), - .c0_ddr4_s_axi_arprot ( cdc_dram_req.ar.prot ), - .c0_ddr4_s_axi_arqos ( cdc_dram_req.ar.qos ), - .c0_ddr4_s_axi_arvalid ( cdc_dram_req.ar_valid ), - .c0_ddr4_s_axi_arready ( cdc_dram_rsp.ar_ready ), - .c0_ddr4_s_axi_rready ( cdc_dram_req.r_ready ), - .c0_ddr4_s_axi_rid ( cdc_dram_rsp.r.id ), - .c0_ddr4_s_axi_rdata ( cdc_dram_rsp.r.data ), - .c0_ddr4_s_axi_rresp ( cdc_dram_rsp.r.resp ), - .c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ), - .c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ), // Others .c0_init_calib_complete ( ), .addn_ui_clkout1 ( dram_clk_o ), @@ -370,7 +318,6 @@ module dram_wrapper_xilinx #( .* ); -`endif `endif /////////////////////////