From bd518095c3af2c85b71205d7f7c0563cd0e800c3 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Mon, 6 Jan 2025 21:29:26 +0100 Subject: [PATCH] target/xilinx: Fix Tcl lint on genesys2 constraints --- target/xilinx/constraints/genesys2.xdc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 9feb8fe2..2326a7e7 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -77,11 +77,15 @@ set_output_delay -max -clock $soc_clk [expr { $SOC_TCK * 0.35 }] [get_ports vga* # SPIM # ######## -set_input_delay -min -clock $soc_clk [expr { 0.10 * $SOC_TCK }] [get_ports {sd_d_* sd_cd_i spih_sd_*}] -set_input_delay -max -clock $soc_clk [expr { 0.35 * $SOC_TCK }] [get_ports {sd_d_* sd_cd_i spih_sd_*}] +set_input_delay -min -clock $soc_clk [expr { 0.10 * $SOC_TCK }] [ \ + get_ports {sd_d_* sd_cd_i spih_sd_*}] +set_input_delay -max -clock $soc_clk [expr { 0.35 * $SOC_TCK }] [ \ + get_ports {sd_d_* sd_cd_i spih_sd_*}] # TODO: fix this by raising it back up... -set_output_delay -min -clock $soc_clk [expr { 0.020 * $SOC_TCK }] [get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}] -set_output_delay -max -clock $soc_clk [expr { 0.063 * $SOC_TCK }] [get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}] +set_output_delay -min -clock $soc_clk [expr { 0.020 * $SOC_TCK }] [ \ + get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}] +set_output_delay -max -clock $soc_clk [expr { 0.063 * $SOC_TCK }] [ \ + get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}] ####### # I2C #