diff --git a/Bender.lock b/Bender.lock
index 68ba293e..041038db 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -162,7 +162,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp-ethernet:
-    revision: a8e69091528d5e8d2a7091082643e5a7c81d2ffd
+    revision: 85739c2d1ccd6c1c2ea1c5b95effcace234baa81
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git
diff --git a/Bender.yml b/Bender.yml
index fb465c6a..24c6b5f5 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "a8e6909"  } # branch: chs-hs
+  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "85739c2"  } # branch: chs-hs
 
 export_include_dirs:
   - hw/include
diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c
index c52bfe91..9e25f4c8 100644
--- a/sw/tests/ethernet.c
+++ b/sw/tests/ethernet.c
@@ -66,9 +66,9 @@ int main(void) {
         *tx_addr = data_to_write[i];
   }
 
-  *reg32(ETH_BASE, MACLO_OFFSET)          = 0x00890702;
+  *reg32(ETH_BASE, MACLO_OFFSET)          = 0x89000123;
   // High 16 bit Mac Address
-  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00802301;
+  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00800207;
   // DMA Source Address
   *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)  = TX_BASE;
   // DMA Destination Address
@@ -83,23 +83,16 @@ int main(void) {
   // Validate Request to DMA
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
 
-  uint32_t *mdio;
-  // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET);  
-  mdio = 0x0300c008;
-  printf("MDIO value: 0x%08X\n", *mdio);
-  
   // configure ethernet
-  *reg32(ETH_BASE, MACLO_OFFSET)          = 0x00890702;  
-  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00802301; 
+  *reg32(ETH_BASE, MACLO_OFFSET)          = 0x89000123;
+  *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00800207; 
   // rx irq
   while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) );
-   
   // dma length ready, dma can be configured now
   while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET)));
 
   *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)  = 0x0; 
   *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET)  = RX_BASE;
-  // *reg32(ETH_BASE, IDMA_LENGTH_OFFSET)    = DATA_CHUNK*BYTE_SIZE;
   *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5;
   *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0;
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
index 0f91bc54..57828058 100644
--- a/target/sim/src/vip_cheshire_soc.sv
+++ b/target/sim/src/vip_cheshire_soc.sv
@@ -724,37 +724,37 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
 
   initial begin
     
+    wait_for_reset();
+
+    @(posedge clk)
+
+    reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);
-     $display("0");
-    reg_drv_rx.send_write( 'h0300c000, 32'h00222222, 'hf, reg_error); //lower 32bits of MAC address
-    @(posedge clk);
-     $display("1");
-    reg_drv_rx.send_write( 'h0300c004, 'h801111, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
-    @(posedge clk);
-     $display("2");
-    
+
+    reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
     
-    // while(1) begin
-    //   reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error);   // req ready 
-    //   if( dma_en )
-    //     break;
-    //   @(posedge clk);
-    // end
+    @(posedge eth_rx_irq);
+
+    while(1) begin
+      reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error);   // req ready with packet length
+      if( dma_en )
+        break;
+      @(posedge clk);
+    end
     
     reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR  
     @(posedge clk);
     
-    $display("3");
     reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR
     @(posedge clk);
-    $display("4");
+
     reg_drv_rx.send_write( 'h0300c028, 32'h5,'hf , reg_error); // src protocol
     @(posedge clk);
-    $display("5");
+
     reg_drv_rx.send_write( 'h0300c02c, 32'h0,'hf , reg_error); // dst protocol
     @(posedge clk);
-    $display("6");
+
     reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error);   // req valid
     @(posedge clk);
     
@@ -766,15 +766,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
       end
       @(posedge clk);
     end
-    
-    @(posedge eth_rx_irq);
-     
 
     // Tx test starts here: external back to core
-    reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address
+    reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);
   
-    reg_drv_rx.send_write( 'h0300c004, 32'h00802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
+    reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
 
     reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR