diff --git a/Bender.lock b/Bender.lock
index f609b398..ed3b2f45 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -69,8 +69,8 @@ packages:
     - common_cells
     - register_interface
   clic:
-    revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf
-    version: 2.0.0
+    revision: f15060eda9d2c0a9597a80365d0344d87a92749a
+    version: null
     source:
       Git: https://github.com/pulp-platform/clic.git
     dependencies:
@@ -99,7 +99,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 38af8d4962b2bfa77dfd7aac9d949c0be263d656
+    revision: 5f1bcd1ba7f2a60122a942ab6a025a60a5ab3ca0
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
diff --git a/Bender.yml b/Bender.yml
index 7ee80283..314fd7d7 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -18,11 +18,11 @@ dependencies:
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.2  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.9 }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.3  }
-  clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
+  clic:                     { git: "https://github.com/pulp-platform/clic.git",                   rev: virt       }
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: nw/v2r-chs }
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: ez/v2r2 }
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.3  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index 4c0589d4..cd49a73b 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -196,6 +196,11 @@ package cheshire_pkg;
     aw_bt   AxiRtNumAddrRegions;
     bit     AxiRtCutPaths;
     bit     AxiRtEnableChecks;
+    // Parameters for CLIC
+    bit     ClicVsclic;
+    bit     ClicVsprio;
+    byte_bt ClicNumVsctxts;
+    aw_bt   ClicPrioWidth;
   } cheshire_cfg_t;
 
   //////////////////
@@ -508,6 +513,7 @@ package cheshire_pkg;
     ret.CachedRegionLength    = {SizeSpm, SizeLlcOut,             cfg.Cva6ExtCieLength};
     ret.DebugEn               = 1;
     ret.RVSCLIC               = cfg.Clic;
+    ret.RVVCLIC               = cfg.ClicVsclic;
     ret.CLICNumInterruptSrc   = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
     // TODO: Should some things be removed from the main config?
     // TODO: Should other things be added to the main config?
@@ -579,7 +585,7 @@ package cheshire_pkg;
     Vga               : 1,
     Usb               : 1,
     AxiRt             : 0,
-    Clic              : 0,
+    Clic              : 1,
     IrqRouter         : 0,
     BusErr            : 1,
     // Debug
@@ -639,6 +645,11 @@ package cheshire_pkg;
     AxiRtWBufferDepth   : 16,
     AxiRtNumAddrRegions : 2,
     AxiRtCutPaths       : 1,
+    // CLIC
+    ClicVsclic        : 1,
+    ClicVsprio        : 1,
+    ClicNumVsctxts    : 64,
+    ClicPrioWidth     : 1,
     // All non-set values should be zero
     default: '0
   };
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index c1a45e50..a5c2d072 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -598,6 +598,8 @@ module cheshire_soc import cheshire_pkg::*; #(
     logic [$clog2(NumClicIntrs)-1:0] clic_irq_id;
     logic [7:0]        clic_irq_level;
     riscv::priv_lvl_t  clic_irq_priv;
+    logic              clic_irq_v;
+    logic [5:0]        clic_irq_vsid;
 
     cva6 #(
       .CVA6Cfg        ( build_config_pkg::build_config(Cva6Cfg) ),
@@ -621,6 +623,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       .clic_irq_id_i    ( clic_irq_id    ),
       .clic_irq_level_i ( clic_irq_level ),
       .clic_irq_priv_i  ( clic_irq_priv  ),
+      .clic_irq_v_i     ( clic_irq_v     ),
+      .clic_irq_vsid_i  ( clic_irq_vsid  ),
       .clic_irq_shv_i   ( clic_irq_shv   ),
       .clic_irq_ready_o ( clic_irq_ready ),
       .clic_kill_req_i  ( clic_irq_kill_req ),
@@ -675,12 +679,16 @@ module cheshire_soc import cheshire_pkg::*; #(
       };
 
       clic #(
-        .N_SOURCE   ( NumClicIntrs ),
-        .INTCTLBITS ( Cfg.ClicIntCtlBits ),
-        .reg_req_t  ( reg_req_t ),
-        .reg_rsp_t  ( reg_rsp_t ),
-        .SSCLIC     ( 1 ),
-        .USCLIC     ( 0 )
+        .N_SOURCE    ( NumClicIntrs ),
+        .INTCTLBITS  ( Cfg.ClicIntCtlBits ),
+        .reg_req_t   ( reg_req_t ),
+        .reg_rsp_t   ( reg_rsp_t ),
+        .SSCLIC      ( 1 ),
+        .USCLIC      ( 0 ),
+        .VSCLIC      ( Cfg.ClicVsclic ),
+        .N_VSCTXTS   ( Cfg.ClicNumVsctxts ),
+        .VSPRIO      ( Cfg.ClicVsprio ),
+        .VsprioWidth ( Cfg.ClicPrioWidth )
       ) i_clic (
         .clk_i,
         .rst_ni,
@@ -693,6 +701,8 @@ module cheshire_soc import cheshire_pkg::*; #(
         .irq_level_o    ( clic_irq_level ),
         .irq_shv_o      ( clic_irq_shv   ),
         .irq_priv_o     ( clic_irq_priv  ),
+        .irq_v_o        ( clic_irq_v     ),
+        .irq_vsid_o     ( clic_irq_vsid  ),
         .irq_kill_req_o ( clic_irq_kill_req ),
         .irq_kill_ack_i ( clic_irq_kill_ack )
       );
@@ -704,6 +714,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       assign clic_irq_level    = '0;
       assign clic_irq_shv      = '0;
       assign clic_irq_priv     = riscv::priv_lvl_t'(0);
+      assign clic_irq_v        = '0;
+      assign clic_irq_vsid     = '0;
       assign clic_irq_kill_req = '0;
 
     end