Add support for VCU118 block design #287
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CyrilKoe
changed the title
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Ready for review. Both FPGA boot in CI |
| @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk | |||
| ###################### | |||
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| CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git | |||
| CAR_NONFREE_COMMIT ?= 59e53134 | |||
| CAR_NONFREE_COMMIT ?= e39aebd1 | |||
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make sure to open a PR on the nonfree repo
| @@ -24,7 +27,17 @@ design flow to link Carfield with external IPs. This flow is less human readable | |||
| integrating more complex IPs as Xilinx Ethernet. *Note that this may require you to own the | |||
| respective licenses.* | |||
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| ## Building the vanilla bistream | |||
| ## For impatient readers | |||
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For impatient readers -> Quick Start
| > #### External JTAG chain | ||
| > | ||
| > Similarly to the VCU128 we use GPIOs to connect an external JTAG-USB dongle (Digilent HS2). Unlike the VCU128, the availability of GPIOs directly on the board allow us to connect the HS2 without an FMC debug board (see constraints for related pins). | ||
| >**WARNING: this setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as |
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we can use a warning block:
> :warning: [text]
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| // Copyright 2022 ETH Zurich and University of Bologna. | |||
| @@ -0,0 +1,538 @@ | |||
| # Copyright 2020 ETH Zurich and University of Bologna. | |||
| # | ||
| # This file was generated for vivado 2020.2 | ||
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| ################################################################ |
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iirc, these block design scripts are generated with Vivado; during our flow, is this taken as an input, or generated as output during he flow and then used? if the latter, maybe we could not check it in and generate it during the flow in a dedicated generated folder, so that it can be used.
I did not have a look at the full flow: which one is the case o the current flow?
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| # Copyright 2020 ETH Zurich and University of Bologna. | |||
| @@ -46,6 +46,7 @@ $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml | |||
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| # Compile bitstream | |||
| $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl | |||
| @if [ "$(GEN_NO_HYPERBUS)" != "1" ] && [ "$(XILINX_ELABORATION_ONLY)" != "1" ]; then echo "Hyperbus not supported yet in this branch"; fi; | |||
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what does "[...] not supported yet in this branch" mean? Since this would land in main, I guess this is a leftover of your dev branch? I think the echo message could be improved for better clarity
Tests: