From 363cf596157169ae631498a96f9149f509630f11 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Tue, 9 Jul 2024 18:37:07 +0200 Subject: [PATCH] vcu118: Ethernet debug --- carfield.mk | 2 +- sw/boot/carfield_bd.dts | 6 +++++- .../flavor_bd/scripts/carfield_bd_vcu118.tcl | 9 +++++---- .../carfield_ip/src/carfield_xilinx_ip.v | 20 +++++++++---------- 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/carfield.mk b/carfield.mk index d4cdbf2d..a0dd2780 100644 --- a/carfield.mk +++ b/carfield.mk @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= d24785a0 +CAR_NONFREE_COMMIT ?= 5a024891 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC diff --git a/sw/boot/carfield_bd.dts b/sw/boot/carfield_bd.dts index 090ee6a4..4fc775e6 100644 --- a/sw/boot/carfield_bd.dts +++ b/sw/boot/carfield_bd.dts @@ -75,8 +75,12 @@ reg = <3>; #phy-cells = <1>; device_type = "ethernet-phy"; - ti,sgmii-ref-clock-output-enable; + //ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; + //ti,6-wire-mode; + //ti,rx-internal-delay = <0x8>; + //ti,tx-internal-delay = <0xa>; + //ti,fifo-depth = <0x1>; }; }; }; diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl index b25e42f0..5aa32acf 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl @@ -237,8 +237,6 @@ proc create_root_design { parentCell } { set_property -dict [ list \ CONFIG.POLARITY {ACTIVE_LOW} \ ] $pcie_perstn - set phy_reset_out [ create_bd_port -dir O -from 0 -to 0 -type rst phy_reset_out ] - set uart_rx_i [ create_bd_port -dir I uart_rx_i ] set uart_tx_o [ create_bd_port -dir O uart_tx_o ] @@ -258,11 +256,15 @@ proc create_root_design { parentCell } { CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk} \ CONFIG.ENABLE_LVDS {true} \ CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds} \ + CONFIG.InstantiateBitslice0 {false} \ CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ - CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out} \ + CONFIG.PHYADDR {0} \ + CONFIG.PHYRST_BOARD_INTERFACE {Custom} \ CONFIG.PHY_TYPE {SGMII} \ CONFIG.gtlocation {X0Y4} \ CONFIG.lvdsclkrate {625} \ + CONFIG.rxlane0_placement {DIFF_PAIR_0} \ + CONFIG.rxnibblebitslice0used {false} \ CONFIG.tx_in_upper_nibble {false} \ CONFIG.txlane0_placement {DIFF_PAIR_2} \ ] $axi_ethernet_0 @@ -476,7 +478,6 @@ proc create_root_design { parentCell } { connect_bd_net -net axi_dma_0_s2mm_sts_reset_out_n [get_bd_pins axi_dma_0/s2mm_sts_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxs_arstn] connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins concat_irq/In0] connect_bd_net -net axi_ethernet_0_mac_irq [get_bd_pins axi_ethernet_0/mac_irq] [get_bd_pins concat_irq/In5] - connect_bd_net -net axi_ethernet_0_phy_rst_n [get_bd_ports phy_reset_out] [get_bd_pins axi_ethernet_0/phy_rst_n] connect_bd_net -net carfield_xilinx_ip_0_dram_axi_m_aclk [get_bd_pins carfield_xilinx_ip_0/dram_axi_m_aclk] [get_bd_pins xbar_dram/aclk] connect_bd_net -net carfield_xilinx_ip_0_periph_axi_m_aclk [get_bd_pins carfield_xilinx_ip_0/periph_axi_m_aclk] [get_bd_pins xbar_periph_out/aclk] connect_bd_net -net carfield_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins carfield_xilinx_ip_0/uart_tx_o] diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v index 3f87e6b7..1551260b 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v @@ -12,13 +12,13 @@ module carfield_xilinx_ip ( (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH" *) input wire cpu_reset , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_10" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 10000000" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 CLK.CLK_10 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_10, FREQ_HZ 10000000" *) input wire clk_10 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_20" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 20000000" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 CLK.CLK_20 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_20, FREQ_HZ 20000000" *) input wire clk_20 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_50" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000, ASSOCIATED_BUSIF periph_axi_s" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 CLK.CLK_50 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_50, FREQ_HZ 50000000, ASSOCIATED_BUSIF periph_axi_s" *) input wire clk_50 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_100" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 CLK.CLK_100 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_100, FREQ_HZ 100000000" *) input wire clk_100 , input wire testmode_i , @@ -49,7 +49,7 @@ module carfield_xilinx_ip // MASTER AXI DRAM -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARADDR" *) output wire [47:0] dram_axi_m_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARBURST" *) output wire [1:0] dram_axi_m_axi_arburst, @@ -125,12 +125,12 @@ module carfield_xilinx_ip output wire dram_axi_m_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 dram_axi CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dram_axi, ASSOCIATED_BUSIF dram_axi, FREQ_HZ 50000000" *) output wire dram_axi_m_aclk, -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 dram_axi RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dram_axi, ASSOCIATED_BUSIF dram_axi, POLARITY ACTIVE_LOW" *) output wire dram_axi_m_aresetn, // MASTER AXI PERIPHERAL -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARADDR" *) output wire [47:0] periph_axi_m_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARBURST" *) output wire [1:0] periph_axi_m_axi_arburst, @@ -204,14 +204,14 @@ module carfield_xilinx_ip output wire [7:0] periph_axi_m_axi_wstrb, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WVALID" *) output wire periph_axi_m_axi_wvalid, -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 periph_axi_m CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, ASSOCIATED_BUSIF periph_axi_m, FREQ_HZ 500000000" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 periph_axi_m CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, ASSOCIATED_BUSIF periph_axi_m, FREQ_HZ 50000000" *) output wire periph_axi_m_aclk, -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 periph_axi_m RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 periph_axi_m RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, ASSOCIATED_BUSIF periph_axi_m, POLARITY ACTIVE_LOW" *) output wire periph_axi_m_aresetn, // SLAVE AXI PERIPHERAL -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARADDR" *) input wire [47:0] periph_axi_s_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARBURST" *) input wire [1:0] periph_axi_s_axi_arburst,