From 3627e4f737db7a1c836aa91d0ade68830cdd7120 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Tue, 9 Jul 2024 10:14:07 +0200 Subject: [PATCH] fpga: Cleaning PR --- target/xilinx/flavor_bd/constraints/vcu118.xdc | 2 +- ...tag.tcl => carfield_bd_ext_jtag_vcu118.tcl} | 3 +-- .../scripts/carfield_bd_ext_jtag_vcu128.tcl | 18 ++++++++++++++++++ target/xilinx/flavor_bd/scripts/run.tcl | 2 +- target/xilinx/scripts/flash_spi.tcl | 15 ++++----------- 5 files changed, 25 insertions(+), 15 deletions(-) rename target/xilinx/flavor_bd/scripts/{carfield_bd_ext_jtag.tcl => carfield_bd_ext_jtag_vcu118.tcl} (93%) create mode 100644 target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu128.tcl diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc index 9f17d43c..3c70a4ff 100644 --- a/target/xilinx/flavor_bd/constraints/vcu118.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu118.xdc @@ -37,4 +37,4 @@ set_property BOARD_PART_PIN default_250mhz_clk1_p [get_ports default_250mhz_clk1 set_property PACKAGE_PIN D12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 set_property PACKAGE_PIN E12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 -set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 \ No newline at end of file +set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu118.tcl similarity index 93% rename from target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl rename to target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu118.tcl index 6ea36dbc..d594ef35 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu118.tcl @@ -1,4 +1,4 @@ -# Copyright 2020 ETH Zurich and University of Bologna. +# Copyright 2024 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 # @@ -8,7 +8,6 @@ set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] - connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i] connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i] diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu128.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu128.tcl new file mode 100644 index 00000000..f64f2480 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag_vcu128.tcl @@ -0,0 +1,18 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ] +set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] +set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] +set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] +set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] +set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ] +connect_bd_net -net carfield_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_gnd_o] +connect_bd_net -net carfield_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_vdd_o] +connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o] +connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i] +connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i] +connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i] diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl index 3700bfb0..dfba2c5f 100644 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -28,7 +28,7 @@ source scripts/carfield_bd_$::env(XILINX_BOARD).tcl # Add the ext_jtag pins to block design if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { - source scripts/carfield_bd_ext_jtag.tcl + source scripts/carfield_bd_ext_jtag_$::env(XILINX_BOARD).tcl import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc } diff --git a/target/xilinx/scripts/flash_spi.tcl b/target/xilinx/scripts/flash_spi.tcl index 1a98000a..c5e7f470 100644 --- a/target/xilinx/scripts/flash_spi.tcl +++ b/target/xilinx/scripts/flash_spi.tcl @@ -24,17 +24,10 @@ if {$::env(XILINX_BOARD) eq "vcu128"} { set hw_mem_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] } -if {$::env(XILINX_BOARD) eq "vcu118"} { - write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ - -loaddata "up $offset $file" \ - -checksum \ - -file $mcs_file -} else { - write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ - -loaddata "up $offset $file" \ - -checksum \ - -file $mcs_file -} +write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ +-loaddata "up $offset $file" \ +-checksum \ +-file $mcs_file set_property PARAM.FREQUENCY 15000000 [get_hw_targets *]