diff --git a/hw/BUILD b/hw/BUILD
index c6b06081767c7..cd4f65e441b31 100644
--- a/hw/BUILD
+++ b/hw/BUILD
@@ -42,10 +42,24 @@ fusesoc_build(
     ],
     data = ["//hw/ip/otbn:all_files"],
     make_options = ":make_options",
-    output_groups = {
-        "binary": ["sim-verilator/Vchip_sim_tb"],
-    },
-    systems = ["lowrisc:dv:chip_verilator_sim"],
+    output_groups = select({
+        "//sw/device:is_english_breakfast": {
+            "binary": ["sim-verilator/Vchip_englishbreakfast_verilator"],
+        },
+        "//conditions:default": {
+            "binary": ["sim-verilator/Vchip_sim_tb"],
+        },
+    }),
+    systems = select({
+        "//sw/device:is_english_breakfast": ["lowrisc:systems:chip_englishbreakfast_verilator"],
+        "//conditions:default": ["lowrisc:dv:chip_verilator_sim"],
+    }),
+    # Note: the `fileset_top(gen)` flags used below are specific to the OpenTitan
+    # project to select the correct RTL fileset.
+    use_flags = select({
+        "//sw/device:is_english_breakfast": ["fileset_topgen"],
+        "//conditions:default": ["fileset_top"],
+    }),
     tags = [
         "manual",
         "verilator",
@@ -114,9 +128,11 @@ filegroup(
         "//:tool_requirements.py",
         "//hw/ip:all_files",
         "//hw/ip_templates:all_files",
-        "//hw/top_earlgrey:all_files",
         "//util:check_tool_requirements.py",
-    ],
+    ] + select({
+        "//sw/device:is_english_breakfast": ["//hw/top_englishbreakfast:all_files"],
+        "//conditions:default": ["//hw/top_earlgrey:all_files"],
+    }),
     visibility = ["//visibility:public"],
 )
 
diff --git a/rules/fusesoc.bzl b/rules/fusesoc.bzl
index 2d40d7c439699..f6b9eea7bac24 100644
--- a/rules/fusesoc.bzl
+++ b/rules/fusesoc.bzl
@@ -66,10 +66,8 @@ def _fusesoc_build_impl(ctx):
         format_each = "--cores-root=%s",
     )
 
-    args.add_all([
-        "run",
-        "--flag=fileset_top",
-    ])
+    args.add("run")
+    args.add_all(["--flag={}".format(f) for f in ctx.attr.use_flags])
     args.add(ctx.attr.target, format = "--target=%s")
     args.add_all([
         "--setup",
@@ -80,8 +78,6 @@ def _fusesoc_build_impl(ctx):
     args.add_all(ctx.attr.systems)
     args.add_all(flags)
 
-    # Note: the `fileset_top` flag used above is specific to the OpenTitan
-    # project to select the correct RTL fileset.
     ctx.actions.run(
         mnemonic = "FuseSoC",
         outputs = outputs,
@@ -109,6 +105,7 @@ fusesoc_build = rule(
         "data": attr.label_list(allow_files = True, doc = "Files needed at runtime"),
         "target": attr.string(mandatory = True, doc = "Target name (e.g. 'sim')"),
         "systems": attr.string_list(mandatory = True, doc = "Systems to build"),
+        "use_flags": attr.string_list(doc = "Custom fusesoc use flags"),
         "flags": attr.string_list(doc = "Flags controlling the FuseSOC system build"),
         "output_groups": attr.string_list_dict(
             allow_empty = True,
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
index cef063ead25ba..f025bffc7f9d1 100755
--- a/util/topgen-fusesoc.py
+++ b/util/topgen-fusesoc.py
@@ -10,7 +10,6 @@
 import argparse
 import sys
 import yaml
-import shutil
 import subprocess
 import os