diff --git a/sw/device/lib/dif/dif_pwrmgr.c b/sw/device/lib/dif/dif_pwrmgr.c index e316a22e80d7e..9f36b93e554f9 100644 --- a/sw/device/lib/dif/dif_pwrmgr.c +++ b/sw/device/lib/dif/dif_pwrmgr.c @@ -69,6 +69,7 @@ static const bitfield_field32_t kDomainConfigBitfield = { static_assert(kDifPwrmgrWakeupRequestSourceOne == (1u << PWRMGR_WAKEUP_EN_EN_0_BIT), "Layout of WAKEUP_EN register changed."); +#if !OT_IS_ENGLISH_BREAKFAST static_assert(kDifPwrmgrWakeupRequestSourceOne == (1u << PWRMGR_PARAM_SYSRST_CTRL_AON_WKUP_REQ_IDX), "Layout of WAKE_INFO register changed."); @@ -87,6 +88,9 @@ static_assert(kDifPwrmgrWakeupRequestSourceFive == static_assert(kDifPwrmgrWakeupRequestSourceSix == (1u << PWRMGR_PARAM_SENSOR_CTRL_AON_WKUP_REQ_IDX), "Layout of WAKE_INFO register changed."); +#else +#warning dif_pwrmgr is incorrect for English Breakfast +#endif /** * Relevant bits of the RESET_EN register must start at `0` and be in the same @@ -95,9 +99,11 @@ static_assert(kDifPwrmgrWakeupRequestSourceSix == static_assert(kDifPwrmgrResetRequestSourceOne == (1u << PWRMGR_RESET_EN_EN_0_BIT), "Layout of RESET_EN register changed."); +#if !OT_IS_ENGLISH_BREAKFAST static_assert(kDifPwrmgrResetRequestSourceTwo == (1u << PWRMGR_RESET_EN_EN_1_BIT), "Layout of RESET_EN register changed."); +#endif /** * `dif_pwrmgr_irq_t` constants must match the corresponding generated values. diff --git a/sw/device/lib/dif/dif_pwrmgr.h b/sw/device/lib/dif/dif_pwrmgr.h index a028f5998be17..c025f11cee79e 100644 --- a/sw/device/lib/dif/dif_pwrmgr.h +++ b/sw/device/lib/dif/dif_pwrmgr.h @@ -87,6 +87,8 @@ typedef uint8_t dif_pwrmgr_domain_config_t; * See also: `dif_pwrmgr_request_sources_t`. * * Note: This needs to be updated once the HW is finalized. + * + * FIXME: this needs to be renamed to include names and handle multiple tops */ typedef enum dif_pwrmgr_wakeup_request_source { kDifPwrmgrWakeupRequestSourceOne = (1u << 0), diff --git a/sw/device/lib/testing/rand_testutils.c b/sw/device/lib/testing/rand_testutils.c index 27befae2b2ab1..d30ef6fd299e2 100644 --- a/sw/device/lib/testing/rand_testutils.c +++ b/sw/device/lib/testing/rand_testutils.c @@ -14,8 +14,6 @@ #include "sw/device/lib/testing/rv_core_ibex_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - /** * The polynomial co-efficients used in the 32-bit LFSR implementation. * diff --git a/sw/device/lib/testing/test_framework/BUILD b/sw/device/lib/testing/test_framework/BUILD index 48c0ffd6cf2a4..7dc0536f62609 100644 --- a/sw/device/lib/testing/test_framework/BUILD +++ b/sw/device/lib/testing/test_framework/BUILD @@ -183,7 +183,7 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":check", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", "//sw/device/lib/dif:rv_plic", @@ -258,6 +258,7 @@ cc_library( ":ottf_start", ":ottf_test_config", ":status", + "//hw/top:devicetables", "//sw/device/lib/arch:device", "//sw/device/lib/base:macros", "//sw/device/lib/base:mmio", @@ -320,7 +321,7 @@ dual_cc_library( "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:irq", "//sw/device/lib/testing:spi_device_testutils", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", ], shared = [ "//sw/device/lib/base:status", @@ -399,7 +400,7 @@ cc_library( ":check", ":freertos_config", ":ottf_start", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", "//sw/device/lib/dif:rv_timer", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:hart", diff --git a/sw/device/lib/testing/test_framework/freertos_port.c b/sw/device/lib/testing/test_framework/freertos_port.c index a69dfbc596444..1fb73611bed86 100644 --- a/sw/device/lib/testing/test_framework/freertos_port.c +++ b/sw/device/lib/testing/test_framework/freertos_port.c @@ -14,7 +14,7 @@ #include "external/freertos/include/task.h" #include "external/freertos/portable/GCC/RISC-V/portmacro.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. +#include "devicetables.h" // Generated. // NOTE: some of the function names below do NOT, and cannot, conform to the // style guide, since they are specific implementations of FreeRTOS defined diff --git a/sw/device/lib/testing/test_framework/ottf_console.c b/sw/device/lib/testing/test_framework/ottf_console.c index 748be8ea16c58..fd2bafc11b1b8 100644 --- a/sw/device/lib/testing/test_framework/ottf_console.c +++ b/sw/device/lib/testing/test_framework/ottf_console.c @@ -20,10 +20,12 @@ #include "sw/device/lib/testing/test_framework/ottf_isrs.h" #include "sw/device/lib/testing/test_framework/ottf_test_config.h" -// TODO: make this toplevel agnostic. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" #include "spi_device_regs.h" // Generated. +static const dt_rv_plic_t *kRvPlicDt = &kDtRvPlic[0]; +static const dt_uart_t *kUart0Dt = &kDtUart[0]; + #define MODULE_ID MAKE_MODULE_ID('o', 't', 'c') /** @@ -43,7 +45,7 @@ enum { /** * HART PLIC Target. */ - kPlicTarget = kTopEarlgreyPlicTargetIbex0, + kPlicTarget = 0, }; // Potential DIF handles for OTTF console communication. @@ -129,7 +131,7 @@ void ottf_console_init(void) { // configured. The default is to use UART0. if (base_addr == 0) { CHECK(kOttfTestConfig.console.type == kOttfConsoleUart); - base_addr = TOP_EARLGREY_UART0_BASE_ADDR; + base_addr = dt_uart_reg_block(kUart0Dt, kDtUartRegBlockCore); } ottf_console_configure_uart(base_addr); @@ -256,24 +258,16 @@ void ottf_console_configure_spi_device(uintptr_t base_addr) { } static uint32_t get_flow_control_watermark_plic_id(void) { - switch (kOttfTestConfig.console.base_addr) { -#if !OT_IS_ENGLISH_BREAKFAST - case TOP_EARLGREY_UART2_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart2RxWatermark; - case TOP_EARLGREY_UART3_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart3RxWatermark; -#endif - case TOP_EARLGREY_UART1_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart1RxWatermark; - case TOP_EARLGREY_UART0_BASE_ADDR: - default: - return kTopEarlgreyPlicIrqIdUart0RxWatermark; + for (size_t i = 0; i < kDtUartCount; i++) { + if (kOttfTestConfig.console.base_addr == dt_uart_reg_block(&kDtUart[i], kDtUartRegBlockCore)) { + return dt_uart_irq_to_plic_id(&kDtUart[i], kDtUartIrqRxWatermark); + } } + return dt_uart_irq_to_plic_id(kUart0Dt, kDtUartIrqRxWatermark); } void ottf_console_flow_control_enable(void) { - CHECK_DIF_OK(dif_rv_plic_init( - mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR), &ottf_plic)); + CHECK_DIF_OK(dif_rv_plic_init_from_dt(kRvPlicDt, &ottf_plic)); dif_uart_t *uart = (dif_uart_t *)ottf_console_get(); CHECK_DIF_OK(dif_uart_watermark_rx_set(uart, kFlowControlRxWatermark)); diff --git a/sw/device/lib/testing/test_framework/ottf_isrs.c b/sw/device/lib/testing/test_framework/ottf_isrs.c index 2629cea926879..0801505d316f9 100644 --- a/sw/device/lib/testing/test_framework/ottf_isrs.c +++ b/sw/device/lib/testing/test_framework/ottf_isrs.c @@ -13,9 +13,11 @@ #include "sw/device/lib/runtime/print.h" #include "sw/device/lib/testing/test_framework/check.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" dif_rv_plic_t ottf_plic; +static const dt_uart_t *kUart0Dt = &kDtUart[0]; +static const dt_sram_ctrl_t *kSramCtrlDt = &kDtSramCtrl[1]; // Fault reasons from // https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf @@ -79,10 +81,11 @@ void ottf_generic_fault_print(uint32_t *exc_info, const char *reason, } uint32_t *sp = exc_info + kExcWords; base_printf("\n"); - uint32_t *ram_start = (uint32_t *)TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR; + uint32_t *ram_start = (uint32_t *)dt_sram_ctrl_reg_block(kSramCtrlDt, kDtSramCtrlRegBlockRam); + // FIXME figure out how to handle memory sizes without a bunch of ifdefs: maybe add a DT field? uint32_t *ram_end = - (uint32_t *)(TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + - TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES); + (uint32_t *)(dt_sram_ctrl_reg_block(kSramCtrlDt, kDtSramCtrlRegBlockRam) + + 0x20000); extern const char _text_start[], _text_end[]; const uint32_t text_start = (uint32_t)_text_start; @@ -194,14 +197,13 @@ bool ottf_console_flow_control_isr(uint32_t *exc_info) { return false; } OT_WEAK void ottf_external_isr(uint32_t *exc_info) { - const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0; + const uint32_t kPlicTarget = 0; dif_rv_plic_irq_id_t plic_irq_id; CHECK_DIF_OK(dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id)); - top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t) - top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id]; + dt_device_id_t peripheral = dt_plic_id_to_device_id(plic_irq_id); - if (peripheral == kTopEarlgreyPlicPeripheralUart0 && + if (peripheral == dt_uart_device_id(kUart0Dt) && ottf_console_flow_control_isr(exc_info)) { // Complete the IRQ at PLIC. CHECK_DIF_OK( diff --git a/sw/device/lib/testing/test_framework/ottf_main.c b/sw/device/lib/testing/test_framework/ottf_main.c index a18878fb8cfcd..f98aa23d94d57 100644 --- a/sw/device/lib/testing/test_framework/ottf_main.c +++ b/sw/device/lib/testing/test_framework/ottf_main.c @@ -28,8 +28,10 @@ #include "sw/device/lib/testing/test_framework/status.h" #include "sw/device/silicon_creator/lib/manifest_def.h" -// TODO: make this toplevel agnostic. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" + +static const dt_rv_core_ibex_t *kRvCoreIbexDt = &kDtRvCoreIbex[0]; +static const dt_rstmgr_t *kRstmgrDt = &kDtRstmgr[0]; #define MODULE_ID MAKE_MODULE_ID('o', 't', 'm') @@ -153,8 +155,7 @@ void _ottf_main(void) { // Clear reset reason register. dif_rstmgr_t rstmgr; - CHECK_DIF_OK(dif_rstmgr_init( - mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr)); + CHECK_DIF_OK(dif_rstmgr_init_from_dt(kRstmgrDt, &rstmgr)); if (kOttfTestConfig.clear_reset_reason) { CHECK_DIF_OK(dif_rstmgr_reset_info_clear(&rstmgr)); } @@ -170,8 +171,8 @@ void _ottf_main(void) { // Initialize a global random number generator testutil context to provide // tests with a source of entropy for randomizing test behaviors. dif_rv_core_ibex_t rv_core_ibex; - CHECK_DIF_OK(dif_rv_core_ibex_init( - mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), + CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt( + kRvCoreIbexDt, &rv_core_ibex)); rand_testutils_rng_ctx = rand_testutils_init(&rv_core_ibex); diff --git a/sw/device/lib/testing/test_framework/ottf_test_config.h b/sw/device/lib/testing/test_framework/ottf_test_config.h index b00d0a40865da..6bc08aaaccff7 100644 --- a/sw/device/lib/testing/test_framework/ottf_test_config.h +++ b/sw/device/lib/testing/test_framework/ottf_test_config.h @@ -21,6 +21,8 @@ typedef struct ottf_console { ottf_console_type_t type; /** * Base address of the communication IP interface to use for the OTTF console. + * + * FIXME We need to change that to use values in an enumeration. */ uintptr_t base_addr; /**