From 2fa6c6318560bd14c12206de3332c23426a8175e Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Wed, 27 Nov 2024 23:45:35 +0100 Subject: [PATCH] WIP Signed-off-by: Amaury Pouly --- hw/BUILD | 16 +++++ hw/top/BUILD | 20 +++++- hw/top_darjeeling/data/autogen/defs.bzl | 1 + .../sw/autogen/top_darjeeling_memory.ld | 4 +- hw/top_earlgrey/data/autogen/defs.bzl | 1 + rules/host.bzl | 4 ++ rules/linker.bzl | 31 ++++++++- rules/opentitan/defs.bzl | 4 +- rules/opentitan/hw.bzl | 16 ++++- .../examples/sram_program/sram_program.ld | 2 +- sw/device/lib/arch/BUILD | 2 +- sw/device/lib/arch/device_sim_dv.c | 15 ++++- sw/device/lib/dif/dif_pinmux.c | 44 +++++++++++++ sw/device/lib/dif/dif_pinmux.h | 27 ++++++++ sw/device/lib/dif/dif_rstmgr.c | 4 +- sw/device/lib/testing/BUILD | 4 +- sw/device/lib/testing/rand_testutils.c | 2 - sw/device/lib/testing/spi_device_testutils.c | 20 ++++-- sw/device/lib/testing/spi_device_testutils.h | 13 ---- sw/device/lib/testing/test_framework/BUILD | 62 +++++++++++++++--- .../testing/test_framework/freertos_port.c | 7 +- .../lib/testing/test_framework/ottf_common.ld | 6 +- .../lib/testing/test_framework/ottf_console.c | 28 ++++---- .../lib/testing/test_framework/ottf_isrs.c | 25 +++++--- .../lib/testing/test_framework/ottf_main.c | 10 +-- .../test_framework/ottf_region_alias.ld | 7 ++ .../test_framework/ottf_silicon_creator_a.ld | 9 ++- .../test_framework/ottf_silicon_creator_b.ld | 9 ++- .../ottf_silicon_creator_virtual.ld | 2 +- .../test_framework/ottf_silicon_owner_a.ld | 9 ++- .../test_framework/ottf_silicon_owner_b.ld | 9 ++- .../ottf_silicon_owner_virtual.ld | 9 +-- sw/device/lib/testing/test_rom/BUILD | 30 ++++++--- sw/device/lib/testing/test_rom/test_rom.ld | 2 +- .../lib/testing/test_rom/test_rom_start.S | 52 +++++++++++---- sw/device/silicon_creator/lib/BUILD | 15 +++-- sw/device/silicon_creator/lib/boot_svc/BUILD | 4 +- sw/device/silicon_creator/lib/drivers/BUILD | 6 +- sw/device/silicon_creator/lib/drivers/hmac.c | 64 ++++++++++--------- .../silicon_creator/lib/drivers/lifecycle.c | 16 ++--- sw/device/silicon_creator/lib/manifest.c | 9 ++- .../silicon_creator/manuf/lib/sram_program.ld | 2 +- sw/device/silicon_creator/rom/rom.ld | 2 +- .../rom_ext/e2e/handoff/fault_slot_a.ld | 2 +- .../silicon_creator/rom_ext/rom_ext_slot_a.ld | 2 +- .../silicon_creator/rom_ext/rom_ext_slot_b.ld | 2 +- .../rom_ext/rom_ext_slot_virtual.ld | 2 +- .../bare_metal/bare_metal_slot_a.ld | 2 +- .../bare_metal/bare_metal_slot_b.ld | 2 +- .../bare_metal/bare_metal_slot_virtual.ld | 2 +- sw/device/tests/BUILD | 5 +- sw/device/tests/uart_smoketest.c | 5 +- util/make_new_dif/templates/dif_autogen.c.tpl | 2 + util/make_new_dif/templates/dif_autogen.h.tpl | 4 ++ util/py/packages/impl/object_size/memory.py | 2 +- util/topgen/templates/data_defs.tpl | 1 + util/topgen/templates/toplevel_memory.ld.tpl | 8 +++ 57 files changed, 467 insertions(+), 198 deletions(-) create mode 100644 sw/device/lib/testing/test_framework/ottf_region_alias.ld diff --git a/hw/BUILD b/hw/BUILD index c6b06081767c7f..09a8062f560249 100644 --- a/hw/BUILD +++ b/hw/BUILD @@ -5,12 +5,15 @@ load("@rules_pkg//pkg:mappings.bzl", "pkg_files") load("//rules:fusesoc.bzl", "fusesoc_build") +package(default_visibility = ["//visibility:public"]) + # This configuration exposes fusesoc's "verilator_options" option to the # command line. This is intended to allow CI to specifically build a single # -threaded Verilated model to suit it's resource constraints. # By default, the Verilated model should be built to # run with 4 threads. load("@bazel_skylib//rules:common_settings.bzl", "string_list_flag") +load("//hw/top:defs.bzl", "opentitan_select_top") string_list_flag( name = "verilator_options", @@ -20,6 +23,19 @@ string_list_flag( ], ) +# HACK +# This alias points to the correct sim_dv execution environment based on the top. +[ + alias( + name = env, + actual = opentitan_select_top({ + "earlgrey": "//hw/top_earlgrey:{}".format(env), + "darjeeling": "//hw/top_darjeeling:{}".format(env), + }, "//invalid/top"), + ) + for env in ["sim_dv_base", "sim_dv"] +] + # This configuration exposes fusesoc's "make_options" to enable parallel # compilation of the verilated model. Compilation takes about 30m of cpu time # and 5m of time that isn't parallelized by this option, so this should reduce diff --git a/hw/top/BUILD b/hw/top/BUILD index 9c27947d0b1137..54cbc73a08095f 100644 --- a/hw/top/BUILD +++ b/hw/top/BUILD @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 load("@bazel_skylib//rules:common_settings.bzl", "string_flag") -load("//rules/opentitan:hw.bzl", "select_top", "select_top_lib") +load("//rules/opentitan:hw.bzl", "select_top", "select_top_lib", "select_top_ld") load("//rules/opentitan:util.bzl", "flatten") load( "//rules:autogen.bzl", @@ -71,6 +71,24 @@ alias( }), ) +[ + select_top_ld( + name = "top_{}_ld".format(top), + all_tops = ALL_TOPS, + top = top, + ) + for top in ALL_TOP_NAMES +] + +# Point to the right top library. +alias( + name = "top_ld", + actual = select({ + "is_{}".format(top): ":top_{}_ld".format(top) + for top in ALL_TOP_NAMES + }), +) + [ opentitan_ip_c_header( name = "{}_c_regs".format(ip), diff --git a/hw/top_darjeeling/data/autogen/defs.bzl b/hw/top_darjeeling/data/autogen/defs.bzl index 8c6c19f1739f3f..aa021702b4c619 100644 --- a/hw/top_darjeeling/data/autogen/defs.bzl +++ b/hw/top_darjeeling/data/autogen/defs.bzl @@ -44,6 +44,7 @@ DARJEELING = opentitan_top( name = "darjeeling", hjson = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson", top_lib = "//hw/top_darjeeling/sw/autogen:top_darjeeling", + top_ld = "//hw/top_darjeeling/sw/autogen:top_darjeeling_memory", ips = [ AES, ALERT_HANDLER, diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld index 731c6ad3ab18cc..e12774d3cf42ab 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld @@ -14,8 +14,8 @@ MEMORY { ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000 rom0(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000 rom1(rx) : ORIGIN = 0x00020000, LENGTH = 0x10000 - rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = None - owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = None + rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000 + owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000 } /** diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index ee70e9a4003d9f..4ffb0e9367e9ae 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -48,6 +48,7 @@ EARLGREY = opentitan_top( name = "earlgrey", hjson = "//hw/top_earlgrey/data/autogen:top_earlgrey.gen.hjson", top_lib = "//hw/top_earlgrey/sw/autogen:top_earlgrey", + top_ld = "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", ips = [ ADC_CTRL, AES, diff --git a/rules/host.bzl b/rules/host.bzl index 434713d9bcd7e6..fb940edf176d48 100644 --- a/rules/host.bzl +++ b/rules/host.bzl @@ -23,6 +23,9 @@ def _host_tools_transition_impl(settings, attr): "//hw/bitstream/universal:rom": "//hw/bitstream/universal:none", "//hw/bitstream/universal:otp": "//hw/bitstream/universal:none", "//hw/bitstream/universal:env": "//hw/bitstream/universal:none", + # WARNING This is a horrible hack: when we transition to host, we pretend + # that this is earlgrey so opentitantool can compile... + "//hw/top": "earlgrey", } return ret @@ -39,5 +42,6 @@ host_tools_transition = transition( "//hw/bitstream/universal:rom", "//hw/bitstream/universal:otp", "//hw/bitstream/universal:env", + "//hw/top", ], ) diff --git a/rules/linker.bzl b/rules/linker.bzl index 04242e59cbd0fb..28e74a815e6de2 100644 --- a/rules/linker.bzl +++ b/rules/linker.bzl @@ -5,7 +5,23 @@ """Rules for declaring linker scripts and linker script fragments.""" def _ld_library_impl(ctx): - files = [] + ctx.files.includes + substitutions = { + key: ctx.expand_location(subst) + for (key, subst) in ctx.attr.substitutions.items() + } + + def get_file(f): + if ctx.attr.substitutions == {}: + return f + fout = ctx.actions.declare_file(ctx.label.name + "_" + f.basename) + ctx.actions.expand_template( + template = f, + output = fout, + substitutions = substitutions, + ) + return fout + + files = [get_file(f) for f in ctx.files.includes] user_link_flags = [] # Disable non-volatile scratch region and counters if building for english @@ -21,12 +37,15 @@ def _ld_library_impl(ctx): ] if ctx.file.script: - files += ctx.files.script + files.append(get_file(ctx.file.script)) user_link_flags += [ - "-Wl,-T,{}".format(ctx.file.script.path), + "-Wl,-T,{}".format(files[-1].path), ] return [ + DefaultInfo( + files = depset(files), + ), cc_common.merge_cc_infos( direct_cc_infos = [CcInfo( linking_context = cc_common.create_linking_context( @@ -57,6 +76,10 @@ ld_library = rule( alignment for segments and not to include the headers in the first segment (this is the -nmagic option of GNU ld). See https://reviews.llvm.org/D61201 for more details. + + If the substitution dictionary is not empty, the content of the file will + be expanded using bazel's `actions.expand_template`. If some substitutions + refer to label not present in `deps`, they need to be added to `subst_deps`. """, attrs = { "script": attr.label(allow_single_file = True), @@ -71,5 +94,7 @@ ld_library = rule( "non_page_aligned_segments": attr.bool( default = False, ), + "substitutions": attr.string_dict(), + "subst_deps": attr.label_list() }, ) diff --git a/rules/opentitan/defs.bzl b/rules/opentitan/defs.bzl index d96a346a28c352..590135829ef190 100644 --- a/rules/opentitan/defs.bzl +++ b/rules/opentitan/defs.bzl @@ -99,7 +99,9 @@ opentitan_manual_test = _opentitan_manual_test EARLGREY_TEST_ENVS = { "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": None, "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None, - "//hw/top_earlgrey:sim_dv": None, + # "//hw/top_earlgrey:sim_dv": None, + # HACK + "//hw:sim_dv": None, "//hw/top_earlgrey:sim_verilator": None, } diff --git a/rules/opentitan/hw.bzl b/rules/opentitan/hw.bzl index 76ed2afa9aae20..07f3b56cab04c2 100644 --- a/rules/opentitan/hw.bzl +++ b/rules/opentitan/hw.bzl @@ -17,7 +17,7 @@ def opentitan_ip(name, hjson): hjson = hjson, ) -def opentitan_top(name, hjson, top_lib, ips): +def opentitan_top(name, hjson, top_lib, top_ld, ips): """ Return a structure describing a top. @@ -32,6 +32,7 @@ def opentitan_top(name, hjson, top_lib, ips): name = name, hjson = hjson, top_lib = top_lib, + top_ld = top_ld, ips = ips, ) @@ -124,3 +125,16 @@ def select_top_lib(name, all_tops, top): name = name, actual = libs[0], ) + +def select_top_ld(name, all_tops, top): + """ + Create an alias to the top library. + """ + libs = [_top.top_ld for _top in all_tops if _top.name == top] + if len(libs) == 0: + fail("not top found with name {}".format(top)) + + native.alias( + name = name, + actual = libs[0], + ) diff --git a/sw/device/examples/sram_program/sram_program.ld b/sw/device/examples/sram_program/sram_program.ld index cad27f7955d3c8..05b5f08f28e82e 100644 --- a/sw/device/examples/sram_program/sram_program.ld +++ b/sw/device/examples/sram_program/sram_program.ld @@ -15,7 +15,7 @@ OUTPUT_ARCH(riscv); */ __DYNAMIC = 0; -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld _stack_end = ORIGIN(ram_main) + LENGTH(ram_main); diff --git a/sw/device/lib/arch/BUILD b/sw/device/lib/arch/BUILD index 5d41cd20882523..0782a714feacde 100644 --- a/sw/device/lib/arch/BUILD +++ b/sw/device/lib/arch/BUILD @@ -89,7 +89,7 @@ cc_library( ":device", "//hw/top:rv_core_ibex_c_regs", "//hw/top:uart_c_regs", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", ], ) diff --git a/sw/device/lib/arch/device_sim_dv.c b/sw/device/lib/arch/device_sim_dv.c index 036ac9f10ca2bb..1635fc14aec1ae 100644 --- a/sw/device/lib/arch/device_sim_dv.c +++ b/sw/device/lib/arch/device_sim_dv.c @@ -6,10 +6,19 @@ #include "sw/device/lib/arch/device.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #include "rv_core_ibex_regs.h" #include "uart_regs.h" +#if defined(OPENTITAN_IS_EARLGREY) +#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#define RV_CORE_IBEX_CFG_BASE_ADDR TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR +#elif defined(OPENTITAN_IS_DARJEELING) +#include "hw/top_darjeeling/sw/autogen/top_darjeeling.h" +#define RV_CORE_IBEX_CFG_BASE_ADDR TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR +#else +#error unsupported top +#endif + /** * Device-specific symbol definitions for the DV simulation device. */ @@ -58,11 +67,11 @@ const uint32_t kAstCheckPollCpuCycles = CALCULATE_AST_CHECK_POLL_CPU_CYCLES(kClockFreqCpuHz); const uintptr_t kDeviceTestStatusAddress = - TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + + RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET; const uintptr_t kDeviceLogBypassUartAddress = - TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + + RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET + 0x04; void device_fpga_version_print(void) {} diff --git a/sw/device/lib/dif/dif_pinmux.c b/sw/device/lib/dif/dif_pinmux.c index 1fe833da324e9f..0f05787cf5bb65 100644 --- a/sw/device/lib/dif/dif_pinmux.c +++ b/sw/device/lib/dif/dif_pinmux.c @@ -48,11 +48,21 @@ static bool dif_pinmux_get_sleep_status_bit(dif_pinmux_pad_kind_t kind, switch (kind) { case kDifPinmuxPadKindMio: num_pads = PINMUX_PARAM_N_MIO_PADS; + // Only platforms with few MIOs, there is a single register with no index. +#ifdef PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET reg_base = PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET; +#else + reg_base = PINMUX_MIO_PAD_SLEEP_STATUS_REG_OFFSET; +#endif break; case kDifPinmuxPadKindDio: num_pads = PINMUX_PARAM_N_DIO_PADS; + // Only platforms with few DIOs, there is a single register with no index. +#ifdef PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_OFFSET + reg_base = PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_OFFSET; +#else reg_base = PINMUX_DIO_PAD_SLEEP_STATUS_REG_OFFSET; +#endif break; default: return false; @@ -334,6 +344,40 @@ dif_result_t dif_pinmux_pad_write_attrs(const dif_pinmux_t *pinmux, return kDifOk; } +dif_result_t dif_pinmux_pad_from_dt_pad(dt_pad_t pad, + dif_pinmux_index_t *index_out, + dif_pinmux_pad_kind_t *type_out) { + if (index_out == NULL || type_out == NULL) { + return kDifBadArg; + } + switch (dt_pad_type(pad)) { + case kDtPadTypeMio: + *type_out = kDifPinmuxPadKindMio; + *index_out = dt_pad_mio_pad(pad); + return kDifOk; + case kDtPadTypeDio: + *type_out = kDifPinmuxPadKindDio; + *index_out = dt_pad_dio_pad(pad); + return kDifOk; + default: + return kDifBadArg; + } +} + + +dif_result_t dif_pinmux_pad_write_attrs_dt(const dif_pinmux_t *pinmux, + dt_pad_t pad, + dif_pinmux_pad_attr_t attrs_in, + dif_pinmux_pad_attr_t *attrs_out) { + dif_pinmux_index_t index; + dif_pinmux_pad_kind_t type; + dif_result_t res = dif_pinmux_pad_from_dt_pad(pad, &index, &type); + if (res == kDifOk) { + res = dif_pinmux_pad_write_attrs(pinmux, index, type, attrs_in, attrs_out); + } + return res; +} + dif_result_t dif_pinmux_pad_get_attrs(const dif_pinmux_t *pinmux, dif_pinmux_index_t pad, dif_pinmux_pad_kind_t type, diff --git a/sw/device/lib/dif/dif_pinmux.h b/sw/device/lib/dif/dif_pinmux.h index b06f22b754da85..3d8fb3b00325a7 100644 --- a/sw/device/lib/dif/dif_pinmux.h +++ b/sw/device/lib/dif/dif_pinmux.h @@ -364,6 +364,21 @@ OT_WARN_UNUSED_RESULT dif_result_t dif_pinmux_mio_select_output(const dif_pinmux_t *pinmux, dt_pad_t pad, dt_pin_t pin); +/** Convert a `dt_pad_t` into a pair (`dif_pinmux_index_t`, `dif_pinmux_pad_kind_t`) + * that can be used for pad control functions (`dif_pinmux_pad_*` functions). + * + * This function is there to handle legacy calls to various pad functions. + * + * @param pad A pad. + * @param index_out[out] The index of this pad. + * @param type_out[out] The type of pad. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_pinmux_pad_from_dt_pad(dt_pad_t pad, + dif_pinmux_index_t *index_out, + dif_pinmux_pad_kind_t *type_out); + /** * Writes attributes for a pad. * @@ -400,6 +415,18 @@ dif_result_t dif_pinmux_pad_write_attrs(const dif_pinmux_t *pinmux, dif_pinmux_pad_attr_t attrs_in, dif_pinmux_pad_attr_t *attrs_out); +/** + * Write attributes for a pad. + * + * See `dif_pinmux_pad_write_attrs` except that the pad is represented by + * a `dt_pad_t` instead of a pair (index,type). + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_pinmux_pad_write_attrs_dt(const dif_pinmux_t *pinmux, + dt_pad_t pad, + dif_pinmux_pad_attr_t attrs_in, + dif_pinmux_pad_attr_t *attrs_out); + /** * Get attributes for a pad. * diff --git a/sw/device/lib/dif/dif_rstmgr.c b/sw/device/lib/dif/dif_rstmgr.c index 0417f55938da42..544c3f517bd8fb 100644 --- a/sw/device/lib/dif/dif_rstmgr.c +++ b/sw/device/lib/dif/dif_rstmgr.c @@ -16,7 +16,7 @@ #include "rstmgr_regs.h" // Generated. // These assertions are only defined for the Earl Grey chip. -#if !OT_IS_ENGLISH_BREAKFAST +#ifdef OPENTITAN_IS_EARLGREY // This macro simplifies the `static_assert` check to make sure that the // public reset info register bitfield matches register bits. #define RSTMGR_RESET_INFO_CHECK(pub_name, priv_name) \ @@ -53,7 +53,7 @@ static_assert( static_assert( DIF_RSTMGR_ALERT_INFO_MAX_SIZE == RSTMGR_ALERT_INFO_CTRL_INDEX_MASK, "Alert info dump max size has grown, please update the public define!"); -#endif // !OT_IS_ENGLISH_BREAKFAST +#endif // OPENTITAN_IS_EARLGREY /** * Checks whether alert_info capture is disabled. diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 40a90279783b9c..02442f82fad3da 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD @@ -337,7 +337,7 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":rv_core_ibex_testutils", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", "//sw/device/lib/arch:device", "//sw/device/lib/base:memory", "//sw/device/lib/dif:rv_core_ibex", @@ -439,7 +439,7 @@ cc_library( hdrs = ["spi_device_testutils.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", "//sw/device/lib/base:status", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:spi_device", diff --git a/sw/device/lib/testing/rand_testutils.c b/sw/device/lib/testing/rand_testutils.c index 27befae2b2ab12..d30ef6fd299e29 100644 --- a/sw/device/lib/testing/rand_testutils.c +++ b/sw/device/lib/testing/rand_testutils.c @@ -14,8 +14,6 @@ #include "sw/device/lib/testing/rv_core_ibex_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - /** * The polynomial co-efficients used in the 32-bit LFSR implementation. * diff --git a/sw/device/lib/testing/spi_device_testutils.c b/sw/device/lib/testing/spi_device_testutils.c index b081542c4d6822..fe63a53ba676ca 100644 --- a/sw/device/lib/testing/spi_device_testutils.c +++ b/sw/device/lib/testing/spi_device_testutils.c @@ -7,8 +7,21 @@ #include "sw/device/lib/dif/dif_spi_device.h" #include "sw/device/lib/testing/test_framework/check.h" +#include "devicetables.h" + #define MODULE_ID MAKE_MODULE_ID('s', 'd', 't') +/* + * The SPI device pins for which `spi_device_testutils_configure_pad_attrs()` + * configures the pad attributes. + */ +static const dt_pad_index_t spi_device_direct_pads[4] = { + kDtPadSpiDeviceSd3, // sio[3] + kDtPadSpiDeviceSd2, // sio[2] + kDtPadSpiDeviceSd1, // sio[1] + kDtPadSpiDeviceSd0 // sio[0] +}; + status_t spi_device_testutils_configure_passthrough( dif_spi_device_handle_t *spi_device, uint32_t filters, bool upload_write_commands) { @@ -331,8 +344,8 @@ status_t spi_device_testutils_configure_pad_attrs(dif_pinmux_t *pinmux) { dif_pinmux_pad_attr_t in_attr = {.slew_rate = 1, .drive_strength = 3}; dif_result_t res; for (uint32_t i = 0; i <= ARRAYSIZE(spi_device_direct_pads); ++i) { - res = dif_pinmux_pad_write_attrs(pinmux, spi_device_direct_pads[i], - kDifPinmuxPadKindDio, in_attr, &out_attr); + dt_pad_t pad = kDtPad[spi_device_direct_pads[i]]; + res = dif_pinmux_pad_write_attrs_dt(pinmux, pad, in_attr, &out_attr); if (res == kDifError) { // Some target platforms may not support the specified value for slew rate // and drive strength. If that's the case, use the values actually @@ -348,8 +361,7 @@ status_t spi_device_testutils_configure_pad_attrs(dif_pinmux_t *pinmux) { "strength"); in_attr.drive_strength = out_attr.drive_strength; } - TRY(dif_pinmux_pad_write_attrs(pinmux, spi_device_direct_pads[i], - kDifPinmuxPadKindDio, in_attr, &out_attr)); + TRY(dif_pinmux_pad_write_attrs_dt(pinmux, pad, in_attr, &out_attr)); // Note: fallthrough with the modified `in_attr` so that the same // attributes are used for all pads. } diff --git a/sw/device/lib/testing/spi_device_testutils.h b/sw/device/lib/testing/spi_device_testutils.h index 2abd812ddae038..c3333ea0299d9b 100644 --- a/sw/device/lib/testing/spi_device_testutils.h +++ b/sw/device/lib/testing/spi_device_testutils.h @@ -13,8 +13,6 @@ #include "sw/device/lib/dif/dif_spi_device.h" #include "sw/device/lib/testing/json/spi_passthru.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - /** * A set of typical opcodes for named flash commands. */ @@ -58,17 +56,6 @@ enum spi_device_command_slot { kSpiDeviceWriteCommandSlotBase = 11, }; -/* - * The SPI device pads for which `spi_device_testutils_configure_pad_attrs()` - * configures the pad attributes. - */ -static const top_earlgrey_direct_pads_t spi_device_direct_pads[4] = { - kTopEarlgreyDirectPadsSpiDeviceSd3, // sio[3] - kTopEarlgreyDirectPadsSpiDeviceSd2, // sio[2] - kTopEarlgreyDirectPadsSpiDeviceSd1, // sio[1] - kTopEarlgreyDirectPadsSpiDeviceSd0 // sio[0] -}; - /** * Configure the SPI device in passthrough mode, allowing the following * commands to pass through: diff --git a/sw/device/lib/testing/test_framework/BUILD b/sw/device/lib/testing/test_framework/BUILD index df480c15396648..da0fd69d714857 100644 --- a/sw/device/lib/testing/test_framework/BUILD +++ b/sw/device/lib/testing/test_framework/BUILD @@ -13,6 +13,7 @@ load( "verilator_params", ) load("//rules:linker.bzl", "ld_library") +load("//hw/top:defs.bzl", "opentitan_select_top") load("@bazel_skylib//lib:dicts.bzl", "dicts") package(default_visibility = ["//visibility:public"]) @@ -90,13 +91,44 @@ ld_library( ], ) +ld_library( + name = "ottf_ld_elfash", + includes = ["ottf_region_alias.ld"], + substitutions = { + "@@OTTF_REGION_ALIAS@@": "eflash", + }, +) + +ld_library( + name = "ottf_ld_ram", + includes = ["ottf_region_alias.ld"], + substitutions = { + "@@OTTF_REGION_ALIAS@@": "ctn", + }, +) + + +alias( + name = "ottf_ld_region_alias", + actual = opentitan_select_top({ + "darjeeling": ":ottf_ld_ram", + }, ":ottf_ld_elfash") +) + +COMMON_LINKER_SUBST = { + "@@TOP_MEMORY_LD@@": "$(location //hw/top:top_ld)", + "@@OTTF_LD_ALIAS@@": "$(location :ottf_ld_region_alias)", +} + ld_library( name = "ottf_ld_silicon_creator_slot_a", script = "ottf_silicon_creator_a.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) ld_library( @@ -104,8 +136,10 @@ ld_library( script = "ottf_silicon_creator_b.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) ld_library( @@ -113,8 +147,10 @@ ld_library( script = "ottf_silicon_creator_virtual.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) ld_library( @@ -122,8 +158,10 @@ ld_library( script = "ottf_silicon_owner_a.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) ld_library( @@ -131,8 +169,10 @@ ld_library( script = "ottf_silicon_owner_b.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) ld_library( @@ -140,8 +180,10 @@ ld_library( script = "ottf_silicon_owner_virtual.ld", deps = [ ":ottf_ld_common", - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + ":ottf_ld_region_alias", + "//hw/top:top_ld", ], + substitutions = COMMON_LINKER_SUBST, ) # TODO(#12905): Use a slightly hollowed out version of the silicon_creator @@ -183,7 +225,7 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":check", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", "//sw/device/lib/dif:rv_plic", @@ -213,7 +255,7 @@ cc_library( ":check", ":ottf_isrs", ":test_framework_manifest_def", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", "//sw/device/lib/crt", @@ -320,7 +362,7 @@ dual_cc_library( "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:irq", "//sw/device/lib/testing:spi_device_testutils", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", ], shared = [ "//sw/device/lib/base:status", @@ -399,7 +441,7 @@ cc_library( ":check", ":freertos_config", ":ottf_start", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", "//sw/device/lib/dif:rv_timer", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:hart", diff --git a/sw/device/lib/testing/test_framework/freertos_port.c b/sw/device/lib/testing/test_framework/freertos_port.c index a69dfbc5964448..40dba26dc3b519 100644 --- a/sw/device/lib/testing/test_framework/freertos_port.c +++ b/sw/device/lib/testing/test_framework/freertos_port.c @@ -14,7 +14,7 @@ #include "external/freertos/include/task.h" #include "external/freertos/portable/GCC/RISC-V/portmacro.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. +#include "devicetables.h" // NOTE: some of the function names below do NOT, and cannot, conform to the // style guide, since they are specific implementations of FreeRTOS defined @@ -35,7 +35,7 @@ OT_SET_BSS_SECTION(".freertos.heap", uint8_t ucHeap[configTOTAL_HEAP_SIZE];) #if configUSE_PREEMPTION static dif_rv_timer_t timer; -static const uint32_t kTimerHartId = (uint32_t)kTopEarlgreyPlicTargetIbex0; +static const uint32_t kTimerHartId = (uint32_t)0; static const uint32_t kTimerComparatorId = 0; static const uint64_t kTimerDeadline = 100; // Counter must reach 100 for an IRQ to be triggered. @@ -59,8 +59,7 @@ void vPortSetupTimerInterrupt(void) { LOG_INFO("Configuring timer interrupt ..."); // Initialize and reset the timer. - CHECK_DIF_OK(dif_rv_timer_init( - mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR), &timer)); + CHECK_DIF_OK(dif_rv_timer_init_from_dt(&kDtRvTimer[0], &timer)); CHECK_DIF_OK(dif_rv_timer_reset(&timer)); // Compute and set tick parameters (i.e., step, prescale, etc.). diff --git a/sw/device/lib/testing/test_framework/ottf_common.ld b/sw/device/lib/testing/test_framework/ottf_common.ld index 86a433fd751ab1..86eaecc0c235f2 100644 --- a/sw/device/lib/testing/test_framework/ottf_common.ld +++ b/sw/device/lib/testing/test_framework/ottf_common.ld @@ -53,9 +53,9 @@ _manifest_entry_point = _ottf_start - _ottf_start_address; * the flash region. Otherwise, the value kHardenedBoolTrue (0x739) is * selected. */ -_manifest_address_translation = (_text_start >= ORIGIN(eflash) && - _text_start < (ORIGIN(eflash) - + LENGTH(eflash))) ? 0x1d4 : 0x739; +_manifest_address_translation = (_text_start >= ORIGIN(ottf_flash) && + _text_start < (ORIGIN(ottf_flash) + + LENGTH(ottf_flash))) ? 0x1d4 : 0x739; /** * NOTE: We have to align each section to word boundaries as our current diff --git a/sw/device/lib/testing/test_framework/ottf_console.c b/sw/device/lib/testing/test_framework/ottf_console.c index 748be8ea16c58c..2332d523d35101 100644 --- a/sw/device/lib/testing/test_framework/ottf_console.c +++ b/sw/device/lib/testing/test_framework/ottf_console.c @@ -21,7 +21,7 @@ #include "sw/device/lib/testing/test_framework/ottf_test_config.h" // TODO: make this toplevel agnostic. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" #include "spi_device_regs.h" // Generated. #define MODULE_ID MAKE_MODULE_ID('o', 't', 'c') @@ -43,7 +43,7 @@ enum { /** * HART PLIC Target. */ - kPlicTarget = kTopEarlgreyPlicTargetIbex0, + kPlicTarget = 0, }; // Potential DIF handles for OTTF console communication. @@ -129,7 +129,7 @@ void ottf_console_init(void) { // configured. The default is to use UART0. if (base_addr == 0) { CHECK(kOttfTestConfig.console.type == kOttfConsoleUart); - base_addr = TOP_EARLGREY_UART0_BASE_ADDR; + base_addr = dt_uart_reg_block(&kDtUart[0], kDtUartRegBlockCore); } ottf_console_configure_uart(base_addr); @@ -256,24 +256,18 @@ void ottf_console_configure_spi_device(uintptr_t base_addr) { } static uint32_t get_flow_control_watermark_plic_id(void) { - switch (kOttfTestConfig.console.base_addr) { -#if !OT_IS_ENGLISH_BREAKFAST - case TOP_EARLGREY_UART2_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart2RxWatermark; - case TOP_EARLGREY_UART3_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart3RxWatermark; -#endif - case TOP_EARLGREY_UART1_BASE_ADDR: - return kTopEarlgreyPlicIrqIdUart1RxWatermark; - case TOP_EARLGREY_UART0_BASE_ADDR: - default: - return kTopEarlgreyPlicIrqIdUart0RxWatermark; + for (size_t i = 0; i < kDtUartCount; i++) { + const dt_uart_t *uart = &kDtUart[i]; + if (kOttfTestConfig.console.base_addr == dt_uart_reg_block(uart, kDtUartRegBlockCore)) { + return dt_uart_irq_to_plic_id(uart, kDtUartIrqRxWatermark); + } } + // This should not be reachable. + abort (); } void ottf_console_flow_control_enable(void) { - CHECK_DIF_OK(dif_rv_plic_init( - mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR), &ottf_plic)); + CHECK_DIF_OK(dif_rv_plic_init_from_dt(&kDtRvPlic[0], &ottf_plic)); dif_uart_t *uart = (dif_uart_t *)ottf_console_get(); CHECK_DIF_OK(dif_uart_watermark_rx_set(uart, kFlowControlRxWatermark)); diff --git a/sw/device/lib/testing/test_framework/ottf_isrs.c b/sw/device/lib/testing/test_framework/ottf_isrs.c index 2629cea9268794..551e839e8e9dd0 100644 --- a/sw/device/lib/testing/test_framework/ottf_isrs.c +++ b/sw/device/lib/testing/test_framework/ottf_isrs.c @@ -13,7 +13,7 @@ #include "sw/device/lib/runtime/print.h" #include "sw/device/lib/testing/test_framework/check.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" dif_rv_plic_t ottf_plic; @@ -79,10 +79,17 @@ void ottf_generic_fault_print(uint32_t *exc_info, const char *reason, } uint32_t *sp = exc_info + kExcWords; base_printf("\n"); - uint32_t *ram_start = (uint32_t *)TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR; - uint32_t *ram_end = - (uint32_t *)(TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + - TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES); + uint32_t ram_base_addr = dt_sram_ctrl_reg_block(&kDtSramCtrl[kDtIndexSramCtrlMain], kDtSramCtrlRegBlockRam); + uint32_t *ram_start = (uint32_t *)ram_base_addr; + // FIXME replace this with DT when possible. +#if defined(OPENTITAN_IS_EARLGREY) + uint32_t ram_size = TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES; +#elif defined(OPENTITAN_IS_DARJEELING) + uint32_t ram_size = TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES; +#else +#error unsupported top +#endif + uint32_t *ram_end = (uint32_t *)(ram_base_addr + ram_size); extern const char _text_start[], _text_end[]; const uint32_t text_start = (uint32_t)_text_start; @@ -194,14 +201,12 @@ bool ottf_console_flow_control_isr(uint32_t *exc_info) { return false; } OT_WEAK void ottf_external_isr(uint32_t *exc_info) { - const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0; + const uint32_t kPlicTarget = 0; dif_rv_plic_irq_id_t plic_irq_id; CHECK_DIF_OK(dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id)); - top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t) - top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id]; - - if (peripheral == kTopEarlgreyPlicPeripheralUart0 && + dt_device_id_t devid = dt_plic_id_to_device_id(plic_irq_id); + if (devid == dt_uart_device_id(&kDtUart[0]) && ottf_console_flow_control_isr(exc_info)) { // Complete the IRQ at PLIC. CHECK_DIF_OK( diff --git a/sw/device/lib/testing/test_framework/ottf_main.c b/sw/device/lib/testing/test_framework/ottf_main.c index a18878fb8cfcd9..ce05d96f0d1740 100644 --- a/sw/device/lib/testing/test_framework/ottf_main.c +++ b/sw/device/lib/testing/test_framework/ottf_main.c @@ -28,8 +28,7 @@ #include "sw/device/lib/testing/test_framework/status.h" #include "sw/device/silicon_creator/lib/manifest_def.h" -// TODO: make this toplevel agnostic. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" #define MODULE_ID MAKE_MODULE_ID('o', 't', 'm') @@ -153,8 +152,7 @@ void _ottf_main(void) { // Clear reset reason register. dif_rstmgr_t rstmgr; - CHECK_DIF_OK(dif_rstmgr_init( - mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr)); + CHECK_DIF_OK(dif_rstmgr_init_from_dt(&kDtRstmgr[0], &rstmgr)); if (kOttfTestConfig.clear_reset_reason) { CHECK_DIF_OK(dif_rstmgr_reset_info_clear(&rstmgr)); } @@ -170,9 +168,7 @@ void _ottf_main(void) { // Initialize a global random number generator testutil context to provide // tests with a source of entropy for randomizing test behaviors. dif_rv_core_ibex_t rv_core_ibex; - CHECK_DIF_OK(dif_rv_core_ibex_init( - mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), - &rv_core_ibex)); + CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(&kDtRvCoreIbex[0], &rv_core_ibex)); rand_testutils_rng_ctx = rand_testutils_init(&rv_core_ibex); // Run the test. diff --git a/sw/device/lib/testing/test_framework/ottf_region_alias.ld b/sw/device/lib/testing/test_framework/ottf_region_alias.ld new file mode 100644 index 00000000000000..f95719643f48a2 --- /dev/null +++ b/sw/device/lib/testing/test_framework/ottf_region_alias.ld @@ -0,0 +1,7 @@ +/* Copyright lowRISC contributors (OpenTitan project). */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +REGION_ALIAS("ottf_flash", @@OTTF_REGION_ALIAS@@) + +_rom_ext_region_size = 0x1000; \ No newline at end of file diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld index 20319078379d86..99b4549752d73e 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_a.ld @@ -10,15 +10,14 @@ * This linker script generates a binary to run rom. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ +INCLUDE @@OTTF_LD_ALIAS@@ /** * Symbols to be used in the setup of the address translation for the OTTF run * at the Silicon Creator boot stage in slot A. */ -_ottf_size = LENGTH(eflash) / 2; -_ottf_start_address = ORIGIN(eflash); - -REGION_ALIAS("ottf_flash", eflash); +_ottf_size = LENGTH(ottf_flash) / 2; +_ottf_start_address = ORIGIN(ottf_flash); INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld index 7687ee5b68635e..d8629246799275 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_b.ld @@ -10,15 +10,14 @@ * This linker script generates a binary to run rom. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ +INCLUDE @@OTTF_LD_ALIAS@@ /** * Symbols to be used in the setup of the address translation for the OTTF run * at the Silicon Creator boot stage in slot B. */ -_ottf_size = LENGTH(eflash) / 2; -_ottf_start_address = ORIGIN(eflash) + _ottf_size; - -REGION_ALIAS("ottf_flash", eflash); +_ottf_size = LENGTH(ottf_flash) / 2; +_ottf_start_address = ORIGIN(ottf_flash) + _ottf_size; INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld b/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld index 8345c31a8aee0b..6296cbeddc7006 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_creator_virtual.ld @@ -10,7 +10,7 @@ * This linker script generates a binary to run rom. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /** * Symbols to be used in the setup of the address translation for the OTTF run diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld index f3a0d12855223c..00a3d525ddd1f8 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_a.ld @@ -10,16 +10,15 @@ * This linker script generates a binary to run BL0 tests. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ +INCLUDE @@OTTF_LD_ALIAS@@ /** * Symbols to be used in the setup of the address translation for the OTTF run * at the BL0 boot stage in slot A. */ /* TODO(#9045): Move ROM_EXT size to a common location. */ -_ottf_size = (LENGTH(eflash) / 2) - 0x10000; -_ottf_start_address = ORIGIN(eflash) + 0x10000; - -REGION_ALIAS("ottf_flash", eflash); +_ottf_size = (LENGTH(ottf_flash) / 2) - _rom_ext_region_size; +_ottf_start_address = ORIGIN(ottf_flash) + _rom_ext_region_size; INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld index 2664ae9ea3f89d..edffead5e13e0d 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_b.ld @@ -10,16 +10,15 @@ * This linker script generates a binary to run BL0 tests. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ +INCLUDE @@OTTF_LD_ALIAS@@ /** * Symbols to be used in the setup of the address translation for the OTTF run * at the BL0 boot stage in slot B. */ /* TODO(#9045): Move ROM_EXT size to a common location. */ -_ottf_size = (LENGTH(eflash) / 2) - 0x10000; -_ottf_start_address = ORIGIN(eflash) + (LENGTH(eflash) / 2) + 0x10000; - -REGION_ALIAS("ottf_flash", eflash); +_ottf_size = (LENGTH(ottf_flash) / 2) - _rom_ext_region_size; +_ottf_start_address = ORIGIN(ottf_flash) + (LENGTH(ottf_flash) / 2) + _rom_ext_region_size; INCLUDE sw/device/lib/testing/test_framework/ottf_common.ld diff --git a/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld b/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld index a85ecaa4c63fc4..a9bb7622ed5bf3 100644 --- a/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld +++ b/sw/device/lib/testing/test_framework/ottf_silicon_owner_virtual.ld @@ -10,15 +10,16 @@ * This linker script generates a binary to run BL0 tests. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ +INCLUDE @@OTTF_LD_ALIAS@@ /** * Symbols to be used in the setup of the address translation for ROM_EXT. */ /* TODO(#9045): Move BL0 size to a common location. */ -_ottf_size = LENGTH(owner_virtual) - 64K; -_ottf_start_address = ORIGIN(owner_virtual) + 64K; -ASSERT((_ottf_size <= (LENGTH(eflash) / 2)), +_ottf_size = LENGTH(owner_virtual) - _rom_ext_region_size; +_ottf_start_address = ORIGIN(owner_virtual) + _rom_ext_region_size; +ASSERT((_ottf_size <= (LENGTH(ottf_flash) / 2)), "Error: BL0 flash is bigger than slot."); REGION_ALIAS("ottf_flash", owner_virtual); diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD index a78bd77e8fd2ce..dec719fb0eda95 100644 --- a/sw/device/lib/testing/test_rom/BUILD +++ b/sw/device/lib/testing/test_rom/BUILD @@ -2,6 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +load("//hw/top:defs.bzl", "opentitan_select_top", "opentitan_if_ip") load( "//rules/opentitan:defs.bzl", "OPENTITAN_CPU", @@ -19,10 +20,13 @@ ld_library( name = "linker_script", script = "test_rom.ld", deps = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory", + "//hw/top:top_ld", "//sw/device:info_sections", "//sw/device/silicon_creator/lib/base:static_critical_sections", ], + substitutions = { + "@@TOP_MEMORY_LD@@": "$(location //hw/top:top_ld)", + }, ) opentitan_binary( @@ -31,7 +35,7 @@ opentitan_binary( "//hw/top_earlgrey:fpga_cw310", "//hw/top_earlgrey:fpga_cw305", "//hw/top_earlgrey:fpga_cw340", - "//hw/top_earlgrey:sim_dv_base", + "//hw:sim_dv_base", "//hw/top_earlgrey:sim_verilator_base", ], kind = "rom", @@ -101,12 +105,23 @@ cc_library( ], ) +cc_library( + name = "darjeeling_test_rom_lib", + srcs = [ + "darjeeling_fake_driver_funcs.c", + ], + deps = [ + "//sw/device/lib/dif:rstmgr", + "//sw/device/silicon_creator/lib/drivers:retention_sram", + ], +) + alias( name = "target_test_rom_lib", - actual = select({ - "//sw/device:is_english_breakfast": ":english_breakfast_test_rom_lib", - "//conditions:default": ":earl_grey_test_rom_lib", - }), + actual = opentitan_select_top({ + "darjeeling": ":darjeeling_test_rom_lib", + # "english_breakfast": ":english_breakfast_test_rom_lib", + }, ":earl_grey_test_rom_lib"), visibility = ["//visibility:private"], ) @@ -161,7 +176,6 @@ cc_library( "//hw/top:clkmgr_c_regs", "//hw/top:csrng_c_regs", "//hw/top:edn_c_regs", - "//hw/top:entropy_src_c_regs", "//hw/top:flash_ctrl_c_regs", "//hw/top:otp_ctrl_c_regs", "//hw/top:sensor_ctrl_c_regs", @@ -190,7 +204,7 @@ cc_library( "//sw/device/silicon_creator/lib:chip_info", "//sw/device/silicon_creator/lib/base:sec_mmio", "//sw/device/silicon_creator/lib/base:static_critical", - ], + ] + opentitan_if_ip("entropy_src", ["//hw/top:entropy_src_c_regs"], []), ) opentitan_test( diff --git a/sw/device/lib/testing/test_rom/test_rom.ld b/sw/device/lib/testing/test_rom/test_rom.ld index fe768a8fbd0a06..f4ecac77e2e7db 100644 --- a/sw/device/lib/testing/test_rom/test_rom.ld +++ b/sw/device/lib/testing/test_rom/test_rom.ld @@ -15,7 +15,7 @@ OUTPUT_ARCH(riscv) */ __DYNAMIC = 0; -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE @@TOP_MEMORY_LD@@ /** * The boot address, which indicates the location of the initial interrupt diff --git a/sw/device/lib/testing/test_rom/test_rom_start.S b/sw/device/lib/testing/test_rom/test_rom_start.S index c8941e94a6ea63..8bc09e14084eb2 100644 --- a/sw/device/lib/testing/test_rom/test_rom_start.S +++ b/sw/device/lib/testing/test_rom/test_rom_start.S @@ -8,23 +8,45 @@ #include "clkmgr_regs.h" #include "csrng_regs.h" #include "edn_regs.h" -#include "entropy_src_regs.h" #include "otp_ctrl_regs.h" #include "sensor_ctrl_regs.h" #include "sram_ctrl_regs.h" -#ifndef OT_IS_ENGLISH_BREAKFAST +#if defined(OT_IS_ENGLISH_BREAKFAST) +#include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h" +#define OTP_CTRL_CORE_BASE_ADDR TOP_ENGLISHBREAKFAST_OTP_CTRL_CORE_BASE_ADDR +#define AST_BASE_ADDR TOP_ENGLISHBREAKFAST_AST_BASE_ADDR +#define CLKMGR_AON_BASE_ADDR TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR +#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR +#define ENTROPY_SRC_BASE_ADDR TOP_ENGLISHBREAKFAST_ENTROPY_SRC_BASE_ADDR +#define CSRNG_BASE_ADDR TOP_ENGLISHBREAKFAST_CSRNG_BASE_ADDR +#define EDN0_BASE_ADDR TOP_ENGLISHBREAKFAST_EDN0_BASE_ADDR + +#elif defined(OPENTITAN_IS_EARLGREY) #include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h" -#define OTP_CTRL_CORE_BASE_ADDR TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR -#define AST_BASE_ADDR TOP_EARLGREY_AST_BASE_ADDR -#define CLKMGR_AON_BASE_ADDR TOP_EARLGREY_CLKMGR_AON_BASE_ADDR -#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR +#define OTP_CTRL_CORE_BASE_ADDR TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR +#define AST_BASE_ADDR TOP_EARLGREY_AST_BASE_ADDR +#define CLKMGR_AON_BASE_ADDR TOP_EARLGREY_CLKMGR_AON_BASE_ADDR +#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR +#define ENTROPY_SRC_BASE_ADDR TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR +#define CSRNG_BASE_ADDR TOP_EARLGREY_CSRNG_BASE_ADDR +#define EDN0_BASE_ADDR TOP_EARLGREY_EDN0_BASE_ADDR +#elif defined(OPENTITAN_IS_DARJEELING) +#include "hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h" +#define OTP_CTRL_CORE_BASE_ADDR TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR +#define AST_BASE_ADDR TOP_DARJEELING_AST_BASE_ADDR +#define CLKMGR_AON_BASE_ADDR TOP_DARJEELING_CLKMGR_AON_BASE_ADDR +#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR +#define CSRNG_BASE_ADDR TOP_DARJEELING_CSRNG_BASE_ADDR +#define EDN0_BASE_ADDR TOP_DARJEELING_EDN0_BASE_ADDR +/* No entropy source */ +#undef ENTROPY_SRC_BASE_ADDR #else -#include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h" -#define OTP_CTRL_CORE_BASE_ADDR TOP_ENGLISHBREAKFAST_OTP_CTRL_CORE_BASE_ADDR -#define AST_BASE_ADDR TOP_ENGLISHBREAKFAST_AST_BASE_ADDR -#define CLKMGR_AON_BASE_ADDR TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR -#define SRAM_CTRL_MAIN_REGS_BASE_ADDR TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR +#error unsupported top +#endif + +#ifdef ENTROPY_SRC_BASE_ADDR +#include "entropy_src_regs.h" #endif /** @@ -191,9 +213,10 @@ _start: sw t0, CLKMGR_JITTER_ENABLE_REG_OFFSET(a0) .L_ast_init_skip: +#ifdef ENTROPY_SRC_BASE_ADDR // The following sequence enables the minimum level of entropy required to // initialize memory scrambling, as well as the entropy distribution network. - li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + li a0, ENTROPY_SRC_BASE_ADDR // Note for BOOT_ROM initialization the FIPS_ENABLE bit is set to kMultiBitBool4False // to prevent the release of FIPS entropy until all the thresholds are set li t0, (MULTIBIT_ASM_BOOL4_FALSE << ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET) | \ @@ -206,15 +229,16 @@ _start: li t0, (MULTIBIT_ASM_BOOL4_TRUE << ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET) sw t0, ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET(a0) +#endif - li a0, TOP_EARLGREY_CSRNG_BASE_ADDR + li a0, CSRNG_BASE_ADDR li t0, (MULTIBIT_ASM_BOOL4_TRUE << CSRNG_CTRL_ENABLE_OFFSET) | \ (MULTIBIT_ASM_BOOL4_TRUE << CSRNG_CTRL_SW_APP_ENABLE_OFFSET) | \ (MULTIBIT_ASM_BOOL4_TRUE << CSRNG_CTRL_READ_INT_STATE_OFFSET) | \ (MULTIBIT_ASM_BOOL4_FALSE << CSRNG_CTRL_FIPS_FORCE_ENABLE_OFFSET) sw t0, CSRNG_CTRL_REG_OFFSET(a0) - li a0, TOP_EARLGREY_EDN0_BASE_ADDR + li a0, EDN0_BASE_ADDR li t0, (MULTIBIT_ASM_BOOL4_TRUE << EDN_CTRL_EDN_ENABLE_OFFSET) | \ (MULTIBIT_ASM_BOOL4_TRUE << EDN_CTRL_BOOT_REQ_MODE_OFFSET) | \ (MULTIBIT_ASM_BOOL4_FALSE << EDN_CTRL_AUTO_REQ_MODE_OFFSET) | \ diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index 7876ba8a45678e..77130844bc5492 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -94,7 +94,7 @@ cc_library( srcs = ["boot_log.c"], hdrs = ["boot_log.h"], deps = [ - ":nonce", + ":nonce_header", "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:chip_info", "//sw/device/silicon_creator/lib:error", @@ -275,7 +275,7 @@ dual_cc_library( ), deps = dual_inputs( device = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", ], host = [ "//sw/device/lib/base:global_mock", @@ -457,11 +457,18 @@ cc_library( hdrs = ["attestation.h"], ) +cc_library( + name = "nonce_header", + hdrs = ["nonce.h"], +) + cc_library( name = "nonce", srcs = ["nonce.c"], - hdrs = ["nonce.h"], - deps = ["//sw/device/silicon_creator/lib/drivers:rnd"], + deps = [ + ":nonce_header", + "//sw/device/silicon_creator/lib/drivers:rnd" + ], ) cc_library( diff --git a/sw/device/silicon_creator/lib/boot_svc/BUILD b/sw/device/silicon_creator/lib/boot_svc/BUILD index ea72dabaf6859a..6c11f2560c8c2b 100644 --- a/sw/device/silicon_creator/lib/boot_svc/BUILD +++ b/sw/device/silicon_creator/lib/boot_svc/BUILD @@ -129,7 +129,7 @@ cc_library( "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", "//sw/device/silicon_creator/lib:error", - "//sw/device/silicon_creator/lib:nonce", + "//sw/device/silicon_creator/lib:nonce_header", "//sw/device/silicon_creator/lib/base:chip", "//sw/device/silicon_creator/lib/ownership:datatypes", ], @@ -154,7 +154,7 @@ cc_library( "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", "//sw/device/silicon_creator/lib:error", - "//sw/device/silicon_creator/lib:nonce", + "//sw/device/silicon_creator/lib:nonce_header", "//sw/device/silicon_creator/lib/base:chip", "//sw/device/silicon_creator/lib/ownership:datatypes", ], diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD index 5613eb25fb3b63..b34f0073911002 100644 --- a/sw/device/silicon_creator/lib/drivers/BUILD +++ b/sw/device/silicon_creator/lib/drivers/BUILD @@ -200,7 +200,7 @@ dual_cc_library( deps = dual_inputs( device = [ "//hw/top:hmac_c_regs", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", ], host = [ "//sw/device/lib/base:global_mock", @@ -400,7 +400,7 @@ dual_cc_library( deps = dual_inputs( device = [ "//hw/top:lc_ctrl_c_regs", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:devicetables", ], host = [ "//sw/device/lib/base:global_mock", @@ -422,7 +422,7 @@ cc_test( deps = [ dual_cc_device_library_of(":lifecycle"), "//hw/top:lc_ctrl_c_regs", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", "//sw/device/silicon_creator/testing:rom_test", "@googletest//:gtest_main", ], diff --git a/sw/device/silicon_creator/lib/drivers/hmac.c b/sw/device/silicon_creator/lib/drivers/hmac.c index bd63109d1b901f..e5e0d3ffbb0d49 100644 --- a/sw/device/silicon_creator/lib/drivers/hmac.c +++ b/sw/device/silicon_creator/lib/drivers/hmac.c @@ -11,16 +11,22 @@ #include "sw/device/silicon_creator/lib/error.h" #include "hmac_regs.h" // Generated. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" + +static const dt_hmac_t *kHmacDt = &kDtHmac[0]; + +static inline uint32_t hmac_base(void) { + return dt_hmac_reg_block(kHmacDt, kDtHmacRegBlockCore); +} void hmac_sha256_configure(bool big_endian_digest) { // Clear the config, stopping the SHA engine. - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, 0u); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, 0u); // Disable and clear interrupts. INTR_STATE register is rw1c. - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_ENABLE_REG_OFFSET, + abs_mmio_write32(hmac_base() + HMAC_INTR_ENABLE_REG_OFFSET, 0u); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET, + abs_mmio_write32(hmac_base() + HMAC_INTR_STATE_REG_OFFSET, UINT32_MAX); uint32_t reg = 0; @@ -33,12 +39,12 @@ void hmac_sha256_configure(bool big_endian_digest) { HMAC_CFG_DIGEST_SIZE_VALUE_SHA2_256); reg = bitfield_field32_write(reg, HMAC_CFG_KEY_LENGTH_FIELD, HMAC_CFG_KEY_LENGTH_VALUE_KEY_256); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, reg); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, reg); } inline void hmac_sha256_start(void) { uint32_t cmd = bitfield_bit32_write(0, HMAC_CMD_HASH_START_BIT, true); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, cmd); + abs_mmio_write32(hmac_base() + HMAC_CMD_REG_OFFSET, cmd); } void hmac_sha256_update(const void *data, size_t len) { @@ -46,34 +52,34 @@ void hmac_sha256_update(const void *data, size_t len) { // Individual byte writes are needed if the buffer isn't word aligned. for (; len != 0 && (uintptr_t)data_sent & 3; --len) { - abs_mmio_write8(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET, + abs_mmio_write8(hmac_base() + HMAC_MSG_FIFO_REG_OFFSET, *data_sent++); } for (; len >= sizeof(uint32_t); len -= sizeof(uint32_t)) { uint32_t data_aligned = read_32(data_sent); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET, + abs_mmio_write32(hmac_base() + HMAC_MSG_FIFO_REG_OFFSET, data_aligned); data_sent += sizeof(uint32_t); } // Handle non-32bit aligned bytes at the end of the buffer. for (; len != 0; --len) { - abs_mmio_write8(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET, + abs_mmio_write8(hmac_base() + HMAC_MSG_FIFO_REG_OFFSET, *data_sent++); } } void hmac_sha256_update_words(const uint32_t *data, size_t len) { for (size_t i = 0; i < len; i++) { - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET, + abs_mmio_write32(hmac_base() + HMAC_MSG_FIFO_REG_OFFSET, data[i]); } } inline void hmac_sha256_process(void) { uint32_t cmd = bitfield_bit32_write(0, HMAC_CMD_HASH_PROCESS_BIT, true); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, cmd); + abs_mmio_write32(hmac_base() + HMAC_CMD_REG_OFFSET, cmd); } /** @@ -84,10 +90,10 @@ inline void hmac_sha256_process(void) { static void wait_for_done(void) { uint32_t reg = 0; do { - reg = abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + + reg = abs_mmio_read32(hmac_base() + HMAC_INTR_STATE_REG_OFFSET); } while (!bitfield_bit32_read(reg, HMAC_INTR_STATE_HMAC_DONE_BIT)); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET, + abs_mmio_write32(hmac_base() + HMAC_INTR_STATE_REG_OFFSET, reg); } @@ -96,7 +102,7 @@ void hmac_sha256_final_truncated(uint32_t *digest, size_t len) { uint32_t result, incr; uint32_t reg = - abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET); + abs_mmio_read32(hmac_base() + HMAC_CFG_REG_OFFSET); if (bitfield_bit32_read(reg, HMAC_CFG_DIGEST_SWAP_BIT)) { // Big-endian output. result = HMAC_DIGEST_0_REG_OFFSET; @@ -114,7 +120,7 @@ void hmac_sha256_final_truncated(uint32_t *digest, size_t len) { // just in case. len = len <= kHmacDigestNumWords ? len : kHmacDigestNumWords; for (uint32_t i = 0; i < len; ++i, result += incr) { - digest[i] = abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + result); + digest[i] = abs_mmio_read32(hmac_base() + result); } } @@ -129,7 +135,7 @@ void hmac_sha256_save(hmac_context_t *ctx) { // Issue the STOP command to halt the operation and compute the intermediate // digest. uint32_t cmd = bitfield_bit32_write(0, HMAC_CMD_HASH_STOP_BIT, true); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, cmd); + abs_mmio_write32(hmac_base() + HMAC_CMD_REG_OFFSET, cmd); wait_for_done(); // Read the digest registers. Note that endianness does not matter here, @@ -137,58 +143,58 @@ void hmac_sha256_save(hmac_context_t *ctx) { // them. for (uint32_t i = 0; i < kHmacDigestNumWords; i++) { ctx->digest[i] = - abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_DIGEST_0_REG_OFFSET + + abs_mmio_read32(hmac_base() + HMAC_DIGEST_0_REG_OFFSET + i * sizeof(uint32_t)); } // Read the message length registers. - ctx->msg_len_lower = abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + + ctx->msg_len_lower = abs_mmio_read32(hmac_base() + HMAC_MSG_LENGTH_LOWER_REG_OFFSET); - ctx->msg_len_upper = abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + + ctx->msg_len_upper = abs_mmio_read32(hmac_base() + HMAC_MSG_LENGTH_UPPER_REG_OFFSET); // Momentarily clear the `sha_en` bit, which clears the digest. uint32_t cfg = - abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, + abs_mmio_read32(hmac_base() + HMAC_CFG_REG_OFFSET); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, bitfield_bit32_write(cfg, HMAC_CFG_SHA_EN_BIT, false)); // Restore the full original configuration. - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, cfg); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, cfg); } void hmac_sha256_restore(const hmac_context_t *ctx) { // Clear the `sha_en` bit to ensure the message length registers are // writeable. Leave the rest of the configuration unchanged. uint32_t cfg = - abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET); + abs_mmio_read32(hmac_base() + HMAC_CFG_REG_OFFSET); cfg = bitfield_bit32_write(cfg, HMAC_CFG_SHA_EN_BIT, false); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, cfg); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, cfg); // Write the digest registers. Note that endianness does not matter here, // because we will simply restore the registers in the same order as we saved // them. for (uint32_t i = 0; i < kHmacDigestNumWords; i++) { - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_DIGEST_0_REG_OFFSET + + abs_mmio_write32(hmac_base() + HMAC_DIGEST_0_REG_OFFSET + i * sizeof(uint32_t), ctx->digest[i]); } // Write the message length registers. abs_mmio_write32( - TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_LENGTH_LOWER_REG_OFFSET, + hmac_base() + HMAC_MSG_LENGTH_LOWER_REG_OFFSET, ctx->msg_len_lower); abs_mmio_write32( - TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_LENGTH_UPPER_REG_OFFSET, + hmac_base() + HMAC_MSG_LENGTH_UPPER_REG_OFFSET, ctx->msg_len_upper); // Re-enable the SHA engine. cfg = bitfield_bit32_write(cfg, HMAC_CFG_SHA_EN_BIT, true); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, cfg); + abs_mmio_write32(hmac_base() + HMAC_CFG_REG_OFFSET, cfg); // Issue the CONTINUE command to restart the operation. uint32_t cmd = bitfield_bit32_write(0, HMAC_CMD_HASH_CONTINUE_BIT, true); - abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, cmd); + abs_mmio_write32(hmac_base() + HMAC_CMD_REG_OFFSET, cmd); } extern void hmac_sha256_init(void); diff --git a/sw/device/silicon_creator/lib/drivers/lifecycle.c b/sw/device/silicon_creator/lib/drivers/lifecycle.c index d047695286171b..8eb5d242ed2956 100644 --- a/sw/device/silicon_creator/lib/drivers/lifecycle.c +++ b/sw/device/silicon_creator/lib/drivers/lifecycle.c @@ -12,12 +12,12 @@ #include "sw/device/lib/base/macros.h" #include "sw/device/silicon_creator/lib/base/sec_mmio.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #include "lc_ctrl_regs.h" +#include "devicetables.h" -enum { - kBase = TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR, -}; +static inline uint32_t lc_ctrl_base(void) { + return dt_lc_ctrl_reg_block(&kDtLcCtrl[0], kDtLcCtrlRegBlockRegs); +} lifecycle_state_t lifecycle_state_get(void) { uint32_t raw_state = lifecycle_raw_state_get(); @@ -67,7 +67,7 @@ lifecycle_state_t lifecycle_state_get(void) { uint32_t lifecycle_raw_state_get(void) { uint32_t value = bitfield_field32_read( - sec_mmio_read32(kBase + LC_CTRL_LC_STATE_REG_OFFSET), + sec_mmio_read32(lc_ctrl_base() + LC_CTRL_LC_STATE_REG_OFFSET), LC_CTRL_LC_STATE_STATE_FIELD); return value; } @@ -82,15 +82,15 @@ void lifecycle_device_id_get(lifecycle_device_id_t *device_id) { launder32(r) < kLifecycleDeviceIdNumWords; ++i, --r) { device_id->device_id[i] = sec_mmio_read32( - kBase + LC_CTRL_DEVICE_ID_0_REG_OFFSET + i * sizeof(uint32_t)); + lc_ctrl_base() + LC_CTRL_DEVICE_ID_0_REG_OFFSET + i * sizeof(uint32_t)); } HARDENED_CHECK_EQ(i, kLifecycleDeviceIdNumWords); HARDENED_CHECK_EQ(r, SIZE_MAX); } void lifecycle_hw_rev_get(lifecycle_hw_rev_t *hw_rev) { - uint32_t reg0 = sec_mmio_read32(kBase + LC_CTRL_HW_REVISION0_REG_OFFSET); - uint32_t reg1 = sec_mmio_read32(kBase + LC_CTRL_HW_REVISION1_REG_OFFSET); + uint32_t reg0 = sec_mmio_read32(lc_ctrl_base() + LC_CTRL_HW_REVISION0_REG_OFFSET); + uint32_t reg1 = sec_mmio_read32(lc_ctrl_base() + LC_CTRL_HW_REVISION1_REG_OFFSET); *hw_rev = (lifecycle_hw_rev_t){ .silicon_creator_id = (uint16_t)bitfield_field32_read( reg0, LC_CTRL_HW_REVISION0_SILICON_CREATOR_ID_FIELD), diff --git a/sw/device/silicon_creator/lib/manifest.c b/sw/device/silicon_creator/lib/manifest.c index 4e3e6b7fc8ebfd..dfa4a923617e28 100644 --- a/sw/device/silicon_creator/lib/manifest.c +++ b/sw/device/silicon_creator/lib/manifest.c @@ -6,12 +6,17 @@ #include "sw/device/silicon_creator/lib/base/chip.h" -#ifdef OT_IS_ENGLISH_BREAKFAST +#if defined(OT_IS_ENGLISH_BREAKFAST) #include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h" #define EFLASH_SIZE_BYES TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES -#else +#elif defined(OPENTITAN_IS_EARLGREY) #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #define EFLASH_SIZE_BYES TOP_EARLGREY_EFLASH_SIZE_BYTES +#elif defined(OPENTITAN_IS_DARJEELING) +#include "hw/top_darjeeling/sw/autogen/top_darjeeling.h" +#define EFLASH_SIZE_BYES TOP_DARJEELING_RAM_MAIN_SIZE_BYTES +#else +#error unsupported top #endif static_assert(CHIP_ROM_EXT_SIZE_MIN >= CHIP_MANIFEST_SIZE, diff --git a/sw/device/silicon_creator/manuf/lib/sram_program.ld b/sw/device/silicon_creator/manuf/lib/sram_program.ld index 250938cd16ce46..7ccafcbe3218f5 100644 --- a/sw/device/silicon_creator/manuf/lib/sram_program.ld +++ b/sw/device/silicon_creator/manuf/lib/sram_program.ld @@ -15,7 +15,7 @@ OUTPUT_ARCH(riscv); */ __DYNAMIC = 0; -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld _stack_end = ORIGIN(ram_main) + LENGTH(ram_main); diff --git a/sw/device/silicon_creator/rom/rom.ld b/sw/device/silicon_creator/rom/rom.ld index b4fc44ac6414e7..bc1a8c03382eee 100644 --- a/sw/device/silicon_creator/rom/rom.ld +++ b/sw/device/silicon_creator/rom/rom.ld @@ -15,7 +15,7 @@ OUTPUT_ARCH(riscv) */ __DYNAMIC = 0; -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /** * The boot address, which indicates the location of the initial interrupt diff --git a/sw/device/silicon_creator/rom_ext/e2e/handoff/fault_slot_a.ld b/sw/device/silicon_creator/rom_ext/e2e/handoff/fault_slot_a.ld index 626d1c6c013d9e..2349a26a799af0 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/handoff/fault_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/e2e/handoff/fault_slot_a.ld @@ -12,7 +12,7 @@ * linker script only targets Slot A. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /* Slot A starts at the start of the eFlash plus the fixed size of the first * Silicon Owner stage */ diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld index 61fa142539e3e8..9de88ca514f5f5 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld @@ -12,7 +12,7 @@ * the upper half of flash), this linker script only targets Slot A. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /* Slot A starts at begining of the eFlash. */ _rom_ext_size = LENGTH(eflash) / 2; diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld index 0c4c2e4382290d..4b47c8ec834136 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld @@ -12,7 +12,7 @@ * the upper half of flash), this linker script only targets Slot B. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /* Slot B starts at the half-size mark of the eFlash. */ _rom_ext_size = LENGTH(eflash) / 2; diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld index e7bcc43fe83a42..32da8db842239f 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld @@ -14,7 +14,7 @@ * to the virtual address. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /** * Symbols to be used in the setup of the address translation for ROM_EXT. diff --git a/sw/device/silicon_owner/bare_metal/bare_metal_slot_a.ld b/sw/device/silicon_owner/bare_metal/bare_metal_slot_a.ld index bf31d1c91b381b..4a496036074985 100644 --- a/sw/device/silicon_owner/bare_metal/bare_metal_slot_a.ld +++ b/sw/device/silicon_owner/bare_metal/bare_metal_slot_a.ld @@ -12,7 +12,7 @@ * linker script only targets Slot A. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /* Slot A starts at the start of the eFlash plus the fixed size of the first * Silicon Owner stage */ diff --git a/sw/device/silicon_owner/bare_metal/bare_metal_slot_b.ld b/sw/device/silicon_owner/bare_metal/bare_metal_slot_b.ld index a11a809dff9eee..21bc55cbb69a8f 100644 --- a/sw/device/silicon_owner/bare_metal/bare_metal_slot_b.ld +++ b/sw/device/silicon_owner/bare_metal/bare_metal_slot_b.ld @@ -12,7 +12,7 @@ * linker script only targets Slot B. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /* Slot B starts at the half-size mark of the eFlash plus the fixed size of the * ROM_EXT. diff --git a/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual.ld b/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual.ld index 69bd18c9a3770b..317d5fcf97a17b 100644 --- a/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual.ld +++ b/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual.ld @@ -12,7 +12,7 @@ * both slots. */ -INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +INCLUDE top_memory.ld /** * Symbols to be used in the setup of the address translation for ROM_EXT. diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 4bc5ac1c072b87..797bfa92dc3c8c 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -96,6 +96,7 @@ opentitan_test( { "//hw/top_earlgrey:fpga_cw310_sival": None, "//hw/top_earlgrey:silicon_creator": None, + "//hw/top_darjeeling:sim_dv_dj": None, }, ), deps = [ @@ -2954,7 +2955,6 @@ opentitan_test( EARLGREY_TEST_ENVS, { "//hw/top_earlgrey:silicon_creator": None, - "//hw/top_earlgrey:sim_dv": None, }, ), fpga = fpga_params( @@ -4106,7 +4106,8 @@ opentitan_test( }, ), deps = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//hw/top:top_lib", + "//hw/top:devicetables", "//sw/device/lib/arch:device", "//sw/device/lib/base:mmio", "//sw/device/lib/dif:uart", diff --git a/sw/device/tests/uart_smoketest.c b/sw/device/tests/uart_smoketest.c index 26002eaaaf06a8..3429af1b9495e5 100644 --- a/sw/device/tests/uart_smoketest.c +++ b/sw/device/tests/uart_smoketest.c @@ -9,7 +9,7 @@ #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "devicetables.h" static const uint8_t kSendData[] = "Smoke test!"; @@ -18,8 +18,7 @@ OTTF_DEFINE_TEST_CONFIG(.enable_concurrency = false, bool test_main(void) { dif_uart_t uart; - CHECK_DIF_OK(dif_uart_init( - mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR), &uart)); + CHECK_DIF_OK(dif_uart_init_from_dt(&kDtUart[0], &uart)); CHECK(kUartBaudrate <= UINT32_MAX, "kUartBaudrate must fit in uint32_t"); CHECK(kClockFreqPeripheralHz <= UINT32_MAX, "kClockFreqPeripheralHz must fit in uint32_t"); diff --git a/util/make_new_dif/templates/dif_autogen.c.tpl b/util/make_new_dif/templates/dif_autogen.c.tpl index 9fe848de4ba10a..789e8df5ffba6c 100644 --- a/util/make_new_dif/templates/dif_autogen.c.tpl +++ b/util/make_new_dif/templates/dif_autogen.c.tpl @@ -64,6 +64,7 @@ dif_result_t dif_${ip.name_snake}_init( } ${ip.name_snake}->base_addr = base_addr; + ${ip.name_snake}->dt = NULL; return kDifOk; } @@ -77,6 +78,7 @@ dif_result_t dif_${ip.name_snake}_init_from_dt( } ${ip.name_snake}->base_addr = mmio_region_from_addr(dt_${ip.name_snake}_reg_block(dt, kDt${ip.name_camel}RegBlockDefault)); + ${ip.name_snake}->dt = dt; return kDifOk; } diff --git a/util/make_new_dif/templates/dif_autogen.h.tpl b/util/make_new_dif/templates/dif_autogen.h.tpl index b9f49b8f626dd3..04803b760c6822 100644 --- a/util/make_new_dif/templates/dif_autogen.h.tpl +++ b/util/make_new_dif/templates/dif_autogen.h.tpl @@ -49,6 +49,10 @@ typedef struct dif_${ip.name_snake} { * The base address for the ${ip.name_snake} hardware registers. */ mmio_region_t base_addr; + /** + * Pointer to the corresponding device table. Can be NULL. + */ + const dt_${ip.name_snake}_t *dt; } dif_${ip.name_snake}_t; /** diff --git a/util/py/packages/impl/object_size/memory.py b/util/py/packages/impl/object_size/memory.py index 20d7e61917dd19..284faff95e575a 100644 --- a/util/py/packages/impl/object_size/memory.py +++ b/util/py/packages/impl/object_size/memory.py @@ -8,7 +8,7 @@ @cache def parse_memory_file() -> dict[str, Memory]: - # FIXME: Actually parse hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld + # FIXME: Actually parse top_memory.ld memories = ( ("rom", range(0x00008000, 0x00008000 + 0x8000)), ("ram_main", range(0x10000000, 0x10000000 + 0x20000)), diff --git a/util/topgen/templates/data_defs.tpl b/util/topgen/templates/data_defs.tpl index 8a9d6b5be5ae9a..40c4dc7d44ae95 100644 --- a/util/topgen/templates/data_defs.tpl +++ b/util/topgen/templates/data_defs.tpl @@ -26,6 +26,7 @@ ${top_name.upper()} = opentitan_top( name = "${top_name}", hjson = "//hw/top_${top_name}/data/autogen:top_${top_name}.gen.hjson", top_lib = "//hw/top_${top_name}/sw/autogen:top_${top_name}", + top_ld = "//hw/top_${top_name}/sw/autogen:top_${top_name}_memory", ips = [ % for ip in all_ips.keys(): ${ip.upper()}, diff --git a/util/topgen/templates/toplevel_memory.ld.tpl b/util/topgen/templates/toplevel_memory.ld.tpl index b5e5d6d8adff50..cb2eca7407f3f7 100644 --- a/util/topgen/templates/toplevel_memory.ld.tpl +++ b/util/topgen/templates/toplevel_memory.ld.tpl @@ -40,6 +40,14 @@ def get_virtual_memory_size(top): for _, mem in mod["memory"].items(): if mem["label"] == "eflash": return hex(int(mem["size"], 0) // 2) + # if no flash_ctrl is present, but a ctn memory region is, + # use that size instead + for mod in top["module"]: + if "memory" in mod: + for _, mem in mod["memory"].items(): + if mem["label"] == "ctn": + return hex(0x00100000 // 2) + return None %>\