From 4947fcf6d44c930170b14706b7a8044bd74021ad Mon Sep 17 00:00:00 2001
From: maksyuki <maksyuki@126.com>
Date: Sat, 24 Feb 2024 13:57:49 +0800
Subject: [PATCH] chore: modify readme badge and def config file

---
 README.md           |  2 +-
 src/def_config.toml | 27 ++++++++++++++++++---------
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/README.md b/README.md
index 6fbff89..4f0f068 100644
--- a/README.md
+++ b/README.md
@@ -12,7 +12,7 @@
       <img alt="stars" src="https://img.shields.io/github/stars/oscc-soc/ci?color=blue&style=flat-square" />
     </a>
     <a href="https://github.com/oscc-soc/ci">
-      <img src="https://img.shields.io/tokei/lines/github/oscc-soc/ci?color=red&style=flat-square">
+      <img src="https://tokei.rs/b1/github/oscc-soc/ci?color=rosybrown&style=flat-square">
     </a>
     <a href="https://github.com/oscc-soc/ci">
       <img src="https://img.shields.io/badge/toolchain-python-red?style=flat-square">
diff --git a/src/def_config.toml b/src/def_config.toml
index 7c6a980..fbcd9f7 100644
--- a/src/def_config.toml
+++ b/src/def_config.toml
@@ -1,27 +1,36 @@
 # This is the default submit config
+# NOTE: below config if have bracket in line comment, that mean 
+# this config only supports string in bracket, other words dont support!
+
 [meta]
 project = "demo"
 author  = "Ben"
 version = "1.0"
 
-[core]
-name     = "ysyx_xxxxxxxx.v" # core name
-top      = "ysyx_xxxxxxxx"   # top name
-clk_name = "clk"             # top clock signal name
+[dut]
+file        = "ysyx_xxxxxxxx.v" # dut file name TODO: support filelist
+top         = "ysyx_xxxxxxxx"   # top module name
+clk         = "clk"             # top clock signal name
+commit      = ""                # support ["", "vcs", "dc"] leave a blank mean
+                                # test vcs+dc, otherwise ci only run specific test 
+                                # which commit equal below testsuit's commit_flag.
+                                # Now iverilog and verilator test are not supported.
+                                # example: commit == "dc" mean only run dc test
 
 [iverilog]
-commit_info = "iv"
+commit_flag = "iv"
 
 [verilator]
-commit_info = "ver"
+commit_flag = "ver"
 
 [vcs]
-commit_info = "vcs"
+commit_flag = "vcs"
+freq        = 25
 prog        = 'all'  # format: [prog]-[type] prog: [hello, memtest, rtthread] type: [flash, mem, sdram]
 debug       = {wave = "off", prog = "hello-flash"}
 
 [dc]
-commit_info = "dc"
+commit_flag = "dc"
 freq        = 100   # [100, 800, step: 50]
 corner      = "TYP" # [WCZ MAX WCL TYP MIN ML MZ]
-retiming    = "off" # [off on]
\ No newline at end of file
+retime      = "off" # [off on]
\ No newline at end of file