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    • Benchmarking framework for ISPD'23 contest and TCHES'25 paper.
      Shell
      1000Updated Nov 30, 2024Nov 30, 2024
    • Tcl
      0000Updated Sep 23, 2024Sep 23, 2024
    • REPQC

      Public
      Reverse engineering post-quantum cryptography in order to insert hardware trojans
      Verilog
      0100Updated Jul 29, 2024Jul 29, 2024
    • reference block design for the ASAP7nm library in Cadence Innovus
      Verilog
      113311Updated Jun 25, 2024Jun 25, 2024
    • SALSy

      Public
      This repository contains several scripts for enhancing the security of the digital designs in the physical (back-end) level.
      Tcl
      Other
      0000Updated May 22, 2024May 22, 2024
    • KRATT

      Public
      A Removal and Structural Analysis Attack
      1000Updated Nov 17, 2023Nov 17, 2023
    • vlcm

      Public
      Multiplerless Design of Very Large Constant Multiplications
      1000Updated Nov 16, 2023Nov 16, 2023
    • HIID

      Public
      A Logic Locking Tool
      1000Updated Nov 3, 2023Nov 3, 2023
    • The measurement of the SRAM PUF on 65nm commercial technology.
      0200Updated Oct 13, 2023Oct 13, 2023
    • Scripts and other material related to the resynthesis-based attack strategy against logic locking
      Perl
      2100Updated May 25, 2023May 25, 2023
    • v2bench

      Public
      a very simple tool to convert verilog to bench files
      C++
      MIT License
      0000Updated May 4, 2023May 4, 2023
    • eASIC

      Public
      This repository consists of RTL, constraints and reports for the paper accepted in Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Shanghai, P.R. China, December 16-18, 2021.
      Tcl
      1501Updated Mar 18, 2023Mar 18, 2023
    • 0200Updated Jan 18, 2023Jan 18, 2023
    • qatt

      Public
      Query Attack
      0000Updated Jan 13, 2023Jan 13, 2023
    • TTech-LIB

      Public
      Verilog
      1500Updated Nov 1, 2021Nov 1, 2021
    • Source files of a SABER cryptocore that was taped out in September 2021. This is a collaborative work between TalTech and TU Graz.
      Verilog
      0300Updated Sep 17, 2021Sep 17, 2021