diff --git a/sim/wally.do b/sim/wally.do
index 928710400..cbdddca02 100644
--- a/sim/wally.do
+++ b/sim/wally.do
@@ -79,15 +79,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 } else {
     if {$1 eq "soc"} {
         set bsg_dir ../soc/src/basejump_stl
-        vlog -lint -work wkdir/work_${1}_${2} +define+den2048Mb+sg5+x32+FULL_MEM +incdir+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_noc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
-        vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1+../config/deriv/$1+../config/shared+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
-    }
-    else {
-        vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
+        vlog -lint +define+den2048Mb+sg5+x32+FULL_MEM +incdir+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_noc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
+        vlog -lint +incdir+../config/$1+../config/deriv/$1+../config/shared+$bsg_dir/bsg_clk_gen+$bsg_dir/bsg_dmc+$bsg_dir/bsg_misc+$bsg_dir/bsg_tag+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
+    } else {
+        vlog +incdir+../config/$1+../config/deriv/$1+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,7063,13286
     }
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
-    vsim workopt +nowarn3829  -fatal 7
+    vsim workopt +nowarn3829 -fatal 7 -suppress 3009,3999,8885
 
     view wave
     #-- display input and output signals as hexidecimal values