The lookup aggregation, i.e. phi
The fixed tables. The parameter is considered to the indexed table.
self and other values to be equal, and is used
by ==.!=. The default implementation is almost always
diff --git a/rustdoc/kimchi_msm/witness/struct.Witness.html b/rustdoc/kimchi_msm/witness/struct.Witness.html
index bca4c1075f..d6a8787cfd 100644
--- a/rustdoc/kimchi_msm/witness/struct.Witness.html
+++ b/rustdoc/kimchi_msm/witness/struct.Witness.html
@@ -10,7 +10,7 @@
cols: Box<[T; N_WIT]>A witness row is represented by an array of N witness columns When T is a vector, then the witness describes the rows of the circuit.
-par_iter. Read moreIterate over the columns in the circuit.
@@ -20,7 +20,7 @@ Vec<G>: IntoParallelIterator,Iterate over the columns in the circuit, in parallel.
&'data mut T reference.self. Read moreself. Read moreThis method takes a witness and a vector of evaluations to the zero +) -> RelaxedWitness<G, W>
This method takes a witness and a vector of evaluations to the zero polynomial, returning a relaxed witness which is composed by the extended witness and the error vector that is set to the zero polynomial.
diff --git a/rustdoc/o1vm/interpreters/riscv32im/interpreter/fn.interpret_mtype.html b/rustdoc/o1vm/interpreters/riscv32im/interpreter/fn.interpret_mtype.html index 5818cc50d6..9bedf79d6a 100644 --- a/rustdoc/o1vm/interpreters/riscv32im/interpreter/fn.interpret_mtype.html +++ b/rustdoc/o1vm/interpreters/riscv32im/interpreter/fn.interpret_mtype.html @@ -1,4 +1,4 @@ -pub fn interpret_mtype<Env: InterpreterEnv>(env: &mut Env, instr: MInstruction)Interpret an M-type instruction. +
pub fn interpret_mtype<Env: InterpreterEnv>(env: &mut Env, instr: MInstruction)Interpret an M-type instruction. The encoding of an M-type instruction is as follows:
| 31 27 | 26 25 | 24 20 | 19 15 | 14 12 | 11 7 | 6 0 |
| 00000 | 01 | rs2 | rs1 | funct3 | rd | opcode |
diff --git a/rustdoc/o1vm/interpreters/riscv32im/interpreter/index.html b/rustdoc/o1vm/interpreters/riscv32im/interpreter/index.html
index 7a78e9c5ee..669c3416ba 100644
--- a/rustdoc/o1vm/interpreters/riscv32im/interpreter/index.html
+++ b/rustdoc/o1vm/interpreters/riscv32im/interpreter/index.html
@@ -1,4 +1,4 @@
-o1vm::interpreters::riscv32im::interpreter - Rust Module o1vm::interpreters::riscv32im::interpreter
source · Expand description
This module implement an interpreter for the RISCV32 IM instruction set
+
o1vm::interpreters::riscv32im::interpreter - Rust Module o1vm::interpreters::riscv32im::interpreter
source · Expand description
This module implement an interpreter for the RISCV32 IM instruction set
architecture.
The implementation mostly follows (and copy) code from the MIPS interpreter
available here.
diff --git a/rustdoc/src/o1vm/interpreters/riscv32im/interpreter.rs.html b/rustdoc/src/o1vm/interpreters/riscv32im/interpreter.rs.html
index d01a644e44..984c25c175 100644
--- a/rustdoc/src/o1vm/interpreters/riscv32im/interpreter.rs.html
+++ b/rustdoc/src/o1vm/interpreters/riscv32im/interpreter.rs.html
@@ -2263,6 +2263,16 @@
2263
2264
2265
+2266
+2267
+2268
+2269
+2270
+2271
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//! This module implement an interpreter for the RISCV32 IM instruction set
//! architecture.
//!
@@ -4515,7 +4525,17 @@
env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
}
MInstruction::Div => {
- unimplemented!("Div")
+ let rs1 = env.read_register(&rs1);
+ let rs2 = env.read_register(&rs2);
+ // FIXME: constrain
+ let res = {
+ let pos = env.alloc_scratch();
+ unsafe { env.div_signed(&rs1, &rs2, pos) }
+ };
+ env.write_register(&rd, res);
+
+ env.set_instruction_pointer(next_instruction_pointer.clone());
+ env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
}
MInstruction::Divu => {
unimplemented!("Divu")