[Core]: Add lh, ld, lw, lbu, lhu, lwu implementations and test them

RISCV.NET.Core.Test/GenerateTestBinary.fs

@@ -1,9 +1,13 @@
 module RISCV.NET.Core.Tests.GenerateTestBinary
 
 open System
+open System.Runtime.CompilerServices
 open RISCV.NET.Core.Tests.FsExecute
 
-type Gen (name : string, source : string[]) =
+type Gen (source : string[], [<CallerMemberName>] ?name : string) =
+  let name =
+    name |> Option.map (fun name -> name.Trim [| '(' ; ')' |]) |> Option.get
+
   let compile =
     $"clang -Wl,-Ttext=0x0 -nostdlib --target=riscv64 -march=rv64g -mno-relax -o {name} {name}.s"
 

RISCV.NET.Core.Test/Instructions.fs

@@ -8,8 +8,8 @@ open RISCV.NET.Core.StartUp
 
 [<Test>]
 let Addi () =
-  use gen = new Gen ("addi", [| "addi x29, x0, 5" ; "addi x30, x0, 37" |])
-  let cpu = CPU (gen.Code)
+  use gen = new Gen [| "addi x29, x0, 5" ; "addi x30, x0, 37" |]
+  let cpu = CPU gen.Code
   cpu.StartUp ()
 
   Assert.That (cpu.Registers[29], Is.EqualTo 5)
@@ -18,44 +18,98 @@ let Addi () =
 [<Test>]
 let Add () =
   use gen =
-    new Gen (
-      "add",
-      [| "addi x29, x0, 5"
-         "addi x30, x0, 37"
-         "add x31, x30, x29" |]
-    )
-
-  let cpu = CPU (gen.Code)
+    new Gen [| "addi x29, x0, 5"
+               "addi x30, x0, 37"
+               "add x31, x30, x29" |]
+
+  let cpu = CPU gen.Code
   cpu.StartUp ()
 
   Assert.That (cpu.Registers[31], Is.EqualTo 42)
 
 [<Test>]
 let Sb () =
-  use gen = new Gen ("sb", [| "addi x30, x0, 0x99" ; "sb x30, 0x500(x0)" |])
-  let cpu = CPU (gen.Code)
+  use gen = new Gen [| "addi x30, x0, 0x99" ; "sb x30, 0x500(x0)" |]
+  let cpu = CPU gen.Code
   cpu.StartUp ()
 
   Assert.That (cpu.Bus.Dram.Value[0x500], Is.EqualTo 0x99)
 
 [<Test>]
 let Lb () =
   use gen =
-    new Gen (
-      "lb",
-      [| "addi x30, x0, 0x99"
-         "sb x30, 0x500(x0)"
-         "lb x29, 0x500(x0)" |]
-    )
-
-  let cpu = CPU (gen.Code)
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lb x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
+  cpu.StartUp ()
+
+  Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
+
+[<Test>]
+let Lh () =
+  use gen =
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lh x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
+  cpu.StartUp ()
+
+  Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
+
+[<Test>]
+let Lw () =
+  use gen =
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lw x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
+  cpu.StartUp ()
+
+  Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
+
+[<Test>]
+let Lbu () =
+  use gen =
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lbu x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
+  cpu.StartUp ()
+
+  Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
+
+[<Test>]
+let Lwu () =
+  use gen =
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lwu x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
+  cpu.StartUp ()
+
+  Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
+
+[<Test>]
+let Lhu () =
+  use gen =
+    new Gen [| "addi x30, x0, 0x99"
+               "sb x30, 0x500(x0)"
+               "lhu x29, 0x500(x0)" |]
+
+  let cpu = CPU gen.Code
   cpu.StartUp ()
 
   Assert.That (cpu.Registers[29], Is.EqualTo 0x99)
 
 [<Test>]
 let Ld () =
-  use gen = new Gen ("ld", [| "ld x28, 0x500(x0)" |])
+  use gen = new Gen [| "ld x28, 0x500(x0)" |]
 
   let cpu = CPU gen.Code
 

RISCV.NET.Core/Instructions.fs

@@ -71,8 +71,13 @@ type CPU with
 
         match instruction.funct3 with
         | 0x0u -> instruction |> this.Lb
+        | 0x1u -> instruction |> this.Lh
+        | 0x2u -> instruction |> this.Lw
         | 0x3u -> instruction |> this.Ld
-        | func3 -> failwith $"Invalid func3 0x%04X{func3}"
+        | 0x4u -> instruction |> this.Lbu
+        | 0x5u -> instruction |> this.Lhu
+        | 0x6u -> instruction |> this.Lwu
+        | _ -> failwith "unreachable"
 
       | 0x13u -> InstructionType.I.Decode instruction |> this.Addi
       | 0x33u -> r_instruction |> this.Add
@@ -108,13 +113,49 @@ type CPU with
       (this.Load (this.Registers[instruction.rs1] + instruction.imm) 8UL)
       |> uint64
 
+  member private this.Lbu (instruction : InstructionType.I) =
+    Log.Info
+      $"lbu x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
+
+    this.Registers[instruction.rd] <-
+      (this.Load (this.Registers[instruction.rs1] + instruction.imm) 8UL)
+
+  member private this.Lh (instruction : InstructionType.I) =
+    Log.Info
+      $"lh x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
+
+    this.Registers[instruction.rd] <-
+      (this.Load (this.Registers[instruction.rs1] + instruction.imm) 16UL)
+      |> uint64
+
+  member private this.Lhu (instruction : InstructionType.I) =
+    Log.Info
+      $"lhu x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
+
+    this.Registers[instruction.rd] <-
+      (this.Load (this.Registers[instruction.rs1] + instruction.imm) 16UL)
+
+  member private this.Lw (instruction : InstructionType.I) =
+    Log.Info
+      $"lw x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
+
+    this.Registers[instruction.rd] <-
+      (this.Load (this.Registers[instruction.rs1] + instruction.imm) 32UL)
+      |> uint64
+
+  member private this.Lwu (instruction : InstructionType.I) =
+    Log.Info
+      $"lwu x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
+
+    this.Registers[instruction.rd] <-
+      (this.Load (this.Registers[instruction.rs1] + instruction.imm) 32UL)
+
   member private this.Ld (instruction : InstructionType.I) =
     Log.Info
       $"ld x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})"
 
     this.Registers[instruction.rd] <-
       this.Load (this.Registers[instruction.rs1] + instruction.imm) 64UL
-      |> uint64
 
   member private this.Sb (instruction : InstructionType.S) =
     Log.Info