diff --git a/.github/Screenshot_20241110_170923.png b/.github/Screenshot_20241110_170923.png deleted file mode 100644 index a7b0a1e..0000000 Binary files a/.github/Screenshot_20241110_170923.png and /dev/null differ diff --git a/README.md b/README.md index cddcb4f..6435d58 100644 --- a/README.md +++ b/README.md @@ -31,19 +31,29 @@ This project aims to run RISC-V Emulator > [!WARNING] > As you can see, this is not a mature solution, and it is almost impossible to become a mature solution. The performance of the simulator built through the above solution will inevitably have serious problems. The value of this project lies in my personal research and study, or to bring inspiration to others `:)` - -## Structure ``` -. -├── RiscV.NET.Core -├── RiscV.NET.Core.Native.Test -├── RiscV.NET.Native +| 11/11/2024 10:15:17 PM [Info] LOADING MEMORY +| 11/11/2024 10:15:17 PM [Info] A 12-byte EXECUTABLE FILE HAS BEEN LOADED +| 11/11/2024 10:15:17 PM [Info] BUS SUCCESSFULLY INSTALLED +| 11/11/2024 10:15:17 PM [Info] ---------- BEGIN ---------- +| 11/11/2024 10:15:17 PM [Info] addi x29, x0, 0x0005 +| 11/11/2024 10:15:17 PM [Info] addi x30, x0, 0x0025 +| 11/11/2024 10:15:17 PM [Info] add x31, x30, x29 +| 11/11/2024 10:15:17 PM [Info] ----------- END ----------- ++------+-----------+-----+-----------+-----+-----------+-----+-----------+ +| REG | VAL | REG | VAL | REG | VAL | REG | VAL | ++------+-----------+-----+-----------+-----+-----------+-----+-----------+ +| zero | 0x0000000 | ra | 0x0000000 | sp | 0x7FFFFFF | gp | 0x0000000 | +| tp | 0x0000000 | t0 | 0x0000000 | t1 | 0x0000000 | t2 | 0x0000000 | +| s0 | 0x0000000 | s1 | 0x0000000 | a0 | 0x0000000 | a1 | 0x0000000 | +| a2 | 0x0000000 | a3 | 0x0000000 | a4 | 0x0000000 | a5 | 0x0000000 | +| a6 | 0x0000000 | a7 | 0x0000000 | s2 | 0x0000000 | s3 | 0x0000000 | +| s4 | 0x0000000 | s5 | 0x0000000 | s6 | 0x0000000 | s7 | 0x0000000 | +| s8 | 0x0000000 | s9 | 0x0000000 | s10 | 0x0000000 | s11 | 0x0000000 | +| t3 | 0x0000000 | t4 | 0x0000005 | t5 | 0x0000025 | t6 | 0x000002A | ++------+-----------+-----+-----------+-----+-----------+-----+-----------+ ``` -- __RiscV.NET.Core__: The core of RiscV.NET, using .NET Core standard class library and Fable compatible class library to ensure platform independence. -- __RiscV.NET.Core.Native.Test__: Native RiscV.NET.Core tests, not related to RiscV.NET.Native. -- __RiscV.NET.Native__: The native RiscV.NET.Core interface can be compiled into a local executable file through .NET Native AOT to run, or simply run on .NET CLR. - ## Reference - [RISC-V Assembler Reference](https://mark.theis.site/riscv/asm) - [RISC-V ISA: A rapid way to learn the RISC-V ISA](https://risc-v.guru/instructions/) diff --git a/RISCV.NET.Core/Instructions.fs b/RISCV.NET.Core/Instructions.fs index 2415f49..0b8f71a 100644 --- a/RISCV.NET.Core/Instructions.fs +++ b/RISCV.NET.Core/Instructions.fs @@ -75,27 +75,27 @@ type CPU with match s_instruction.funct3 with | 0x0u -> s_instruction |> this.Sb | _ -> failwith "unreachable" - | invalid_opcode -> failwith $"Invalid opcode 0x%07X{invalid_opcode}" + | invalid_opcode -> failwith $"Invalid opcode 0x%04X{invalid_opcode}" end this.UpdatePC () member private this.Addi (instruction : InstructionType.I) = Log.Info - $"addi x{instruction.rd}, x{instruction.rs1}, 0x%07X{instruction.imm}" + $"addi x{instruction.rd}, x{instruction.rs1}, 0x%04X{instruction.imm}" this.Registers[instruction.rd] <- this.Registers[instruction.rs1] + instruction.imm member private this.Add (instruction : InstructionType.R) = - Log.Info $"addi x{instruction.rd}, x{instruction.rs1}, x{instruction.rs2}" + Log.Info $"add x{instruction.rd}, x{instruction.rs1}, x{instruction.rs2}" this.Registers[instruction.rd] <- this.Registers[instruction.rs1] + this.Registers[instruction.rs2] member private this.Lb (instruction : InstructionType.I) = Log.Info - $"lb x{instruction.rd}, 0x%07X{instruction.imm}(x{instruction.rs1})" + $"lb x{instruction.rd}, 0x%04X{instruction.imm}(x{instruction.rs1})" this.Registers[instruction.rd] <- (this.Load (this.Registers[instruction.rs1] + instruction.imm) 8UL) @@ -103,7 +103,7 @@ type CPU with member private this.Sb (instruction : InstructionType.S) = Log.Info - $"sb x{instruction.rs2}, 0x%07X{instruction.imm}(x{instruction.rs1})" + $"sb x{instruction.rs2}, 0x%04X{instruction.imm}(x{instruction.rs1})" this.Store (this.Registers[instruction.rs1] + instruction.imm) diff --git a/RISCV.NET.Core/Main.fs b/RISCV.NET.Core/Main.fs deleted file mode 100644 index 63f840b..0000000 --- a/RISCV.NET.Core/Main.fs +++ /dev/null @@ -1,10 +0,0 @@ -module RISCV.NET.Core.Main - -open RISCV.NET.Core.CPU - -[] -let main argv = - let cpu = CPU ([||]) - cpu.DumpRegisters () - - 0 diff --git a/RISCV.NET.Core/RISCV.NET.Core.fsproj b/RISCV.NET.Core/RISCV.NET.Core.fsproj index fa37004..c0854fe 100644 --- a/RISCV.NET.Core/RISCV.NET.Core.fsproj +++ b/RISCV.NET.Core/RISCV.NET.Core.fsproj @@ -1,19 +1,18 @@ - - Exe - net9.0 - - - - - - - - - - - - - - + + Exe + net9.0 + + + + + + + + + + + + + \ No newline at end of file diff --git a/RISCV.NET.Native/Program.fs b/RISCV.NET.Native/Program.fs new file mode 100644 index 0000000..4c2c356 --- /dev/null +++ b/RISCV.NET.Native/Program.fs @@ -0,0 +1,13 @@ +module RISCV.NET.Native.Program + +open System +open RISCV.NET.Core.CPU +open RISCV.NET.Core.StartUp + +[] +let main args = + + let cpu = CPU (IO.File.ReadAllBytes args[0]) + cpu.StartUp () + + 0 \ No newline at end of file diff --git a/RISCV.NET.Native/RISCV.NET.Native.fsproj b/RISCV.NET.Native/RISCV.NET.Native.fsproj new file mode 100644 index 0000000..4b5c1cb --- /dev/null +++ b/RISCV.NET.Native/RISCV.NET.Native.fsproj @@ -0,0 +1,16 @@ + + + + Exe + net9.0 + + + + + + + + + + + diff --git a/riscv.net.sln b/riscv.net.sln index a3e7058..4d9ecf4 100644 --- a/riscv.net.sln +++ b/riscv.net.sln @@ -7,6 +7,8 @@ Project("{F2A71F9B-5D33-465A-A702-920D77279786}") = "RISCV.NET.Core", "RISCV.NET EndProject Project("{F2A71F9B-5D33-465A-A702-920D77279786}") = "RISCV.NET.Core.Test", "RISCV.NET.Core.Test\RISCV.NET.Core.Test.fsproj", "{1CB3715D-92DE-4D74-BD8D-DFDC1AFA4151}" EndProject +Project("{F2A71F9B-5D33-465A-A702-920D77279786}") = "RISCV.NET.Native", "RISCV.NET.Native\RISCV.NET.Native.fsproj", "{F0770CA6-36B7-4A7A-971A-B1DC2E3A8C19}" +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Any CPU = Debug|Any CPU @@ -24,5 +26,9 @@ Global {1CB3715D-92DE-4D74-BD8D-DFDC1AFA4151}.Debug|Any CPU.Build.0 = Debug|Any CPU {1CB3715D-92DE-4D74-BD8D-DFDC1AFA4151}.Release|Any CPU.ActiveCfg = Release|Any CPU {1CB3715D-92DE-4D74-BD8D-DFDC1AFA4151}.Release|Any CPU.Build.0 = Release|Any CPU + {F0770CA6-36B7-4A7A-971A-B1DC2E3A8C19}.Debug|Any CPU.ActiveCfg = Debug|Any CPU + {F0770CA6-36B7-4A7A-971A-B1DC2E3A8C19}.Debug|Any CPU.Build.0 = Debug|Any CPU + {F0770CA6-36B7-4A7A-971A-B1DC2E3A8C19}.Release|Any CPU.ActiveCfg = Release|Any CPU + {F0770CA6-36B7-4A7A-971A-B1DC2E3A8C19}.Release|Any CPU.Build.0 = Release|Any CPU EndGlobalSection EndGlobal