-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathtdp_ram.v
198 lines (181 loc) · 4.37 KB
/
tdp_ram.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
/**
* Copyright (C) 2018, Miklos Maroti
* This is free software released under the 3-clause BSD licence.
*/
`default_nettype none
/**
* This ram will be inferred as a DP8KC with read before write and
* non-registered output (odata appears one clock cycle after enable).
*/
module true_dual_port_ram_readfirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
end
endmodule
/**
* This ram will be inferred as a DP8KC with read before write and
* registered output (odata appears two clock cycles after enable).
*/
module true_dual_port_ram_readfirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0] memory [(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
memory[addr1] <= idata1;
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
memory[addr2] <= idata2;
end
odata2 <= odata2_reg;
end
endmodule
/**
* This ram will be inferred as a DP8KC with write before read and
* non-registered output (odata appears one clock cycles after enable).
*/
module true_dual_port_ram_writefirst_reg1 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
always @(posedge clock1)
begin
if (enable1)
begin
odata1 <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1 <= idata1;
end
end
end
always @(posedge clock2)
begin
if (enable2)
begin
odata2 <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2 <= idata2;
end
end
end
endmodule
/**
* This ram will be inferred as a DP8KC with write before read and
* registered output (odata appears two clock cycles after enable).
*/
module true_dual_port_ram_writefirst_reg2 #(parameter integer DATA_WIDTH = 8, ADDR_WIDTH = 10) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0] memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1)
begin
if (enable1)
begin
odata1_reg <= memory[addr1];
if (write1)
begin
memory[addr1] <= idata1;
odata1_reg <= idata1;
end
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2)
begin
if (enable2)
begin
odata2_reg <= memory[addr2];
if (write2)
begin
memory[addr2] <= idata2;
odata2_reg <= idata2;
end
end
odata2 <= odata2_reg;
end
endmodule