Diverging from the Tydi specification - unofficial solutions

[matthijsr]

At time of writing, there are a few issues and inconsistencies with the Tydi spec, tracked here:
abs-tudelft/tydi#221
abs-tudelft/tydi#222
abs-tudelft/tydi#223
abs-tudelft/tydi#224
abs-tudelft/tydi#225
abs-tudelft/tydi#226

This issue will track the intermediate representation's unofficial solutions, until the issues themselves have been resolved.

[matthijsr]

Flattening when both streams have user and/or keep properties

abs-tudelft/tydi#221

The Split function will fail when it encounters a situation where two physical Streams have identical names.

[matthijsr]

Requirements for "last" signalling conflict for Streams with lower complexities and multiple element lanes

abs-tudelft/tydi#222

Instead of

C < 4 It is illegal to assert the last bit for dimension 0 when the respective data lane is inactive, except for empty sequences.

The intermediate representation adheres to

C < 4 It is illegal to assert any last bit when the transfer data is inactive, except for empty sequences.

[matthijsr]

It is not clear whether "stai" and "endi" signals are significant when "strb" is low.

abs-tudelft/tydi#223

The intermediate representation assumes that

stai and endi are only significant when all strb bits are driven high

[matthijsr]

Transferring empty outer lists at lower complexities

abs-tudelft/tydi#224

The intermediate representation amends

[C<4] It is illegal to assert a last bit for dimension j without also asserting the last bits for dimensions j′<j in the same lane.

to say

[C<4] It is illegal to assert a last bit for dimension j without also asserting the last bits for dimensions j′<j in the same lane, except for empty sequences.

[matthijsr]

Inconsistency: Strobe only encodes individual lane validity at C≥8

abs-tudelft/tydi#225

The intermediate representation assumes that Strobe encodes individual lane validity at C≥7.

[matthijsr]

Requirements when C<5, Dimensionality = 0 and Throughput > 1

abs-tudelft/tydi#226

Right now, the IR adheres to the requirements. But should this cause further issues, the following is an option:

Instead of

endi is contingent on (C≥5∨D≥1)∧N>1

the intermediate representation can assume that

endi is contingent on N>1