12V voltage Regulator-cache.lib

EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_R_POT
#
DEF Device_R_POT RV 0 40 Y N 1 F N
F0 "RV" -175 0 50 V V C CNN
F1 "Device_R_POT" -100 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Potentiometer*
$ENDFPLIST
DRAW
S 40 100 -40 -100 0 1 10 N
P 2 0 1 0 100 0 60 0 N
P 4 0 1 0 45 0 90 20 90 -20 45 0 F
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
X 3 3 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Transistor_FET_IRLIZ44N
#
DEF Transistor_FET_IRLIZ44N Q 0 20 Y N 1 F N
F0 "Q" 250 75 50 H V L CNN
F1 "Transistor_FET_IRLIZ44N" 250 0 50 H V L CNN
F2 "Package_TO_SOT_THT:TO-220F-3_Vertical" 250 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
$FPLIST
 TO?220F*
$ENDFPLIST
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
P 4 0 1 0 110 20 115 15 145 15 150 10 N
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
X G 1 -200 0 100 R 50 50 1 1 I
X D 2 100 200 100 D 50 50 1 1 P
X S 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-12V
#
DEF power_-12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-12V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -12V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
#End Library