From 907c78225576a869b5875491b70b560139313a34 Mon Sep 17 00:00:00 2001 From: Kinza Qamar Date: Tue, 21 Jan 2025 17:58:06 +0000 Subject: [PATCH] [rom_ctrl, dv] Exclusion of a case where sramreqfifo_wready is false Signed-off-by: Kinza Qamar --- hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el b/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el index cd6ce460eb99b..0759f0753202a 100644 --- a/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el +++ b/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el @@ -137,6 +137,12 @@ Condition 37 "2164803938" "(tl_i_int.a_valid & reqfifo_wready & ((~error_interna // u_sram_byte. But this makes req_o false and hence sram_ack false. Condition 43 "2041272341" "(sram_ack & ((~we_o))) 1 -1" (2 "10") +// It is impossible to get !sramreqfifo_wready. The depth of sramreqfifo is 2. sramreqfifo_wready +// can be false if the fifo is full. But this can't happen as we don't fill the fifo without +// removing the last item that was pushed in the fifo. +Condition 34 "1999653721" "((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready) + 1 -1" (3 "110") + // The case !empty when under_rst=1 is impossible as fifo clears on reset. INSTANCE: tb.dut.u_tl_adapter_rom.u_rspfifo Condition 7 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1"