diff --git a/hw/ip/prim/prim.core b/hw/ip/prim/prim.core index 5aa7a57ca52247..8801e4b1ab7df7 100644 --- a/hw/ip/prim/prim.core +++ b/hw/ip/prim/prim.core @@ -13,7 +13,6 @@ filesets: - lowrisc:prim:util - lowrisc:prim:diff_decode # for prim_alert_sender/receiver - lowrisc:prim:pad_wrapper - - lowrisc:prim:prim_pkg - lowrisc:prim:clock_mux2 - lowrisc:prim:clock_inv - lowrisc:prim:buf diff --git a/hw/ip/prim/prim_and2.core b/hw/ip/prim/prim_and2.core deleted file mode 100644 index 10cfee5c45a08e..00000000000000 --- a/hw/ip/prim/prim_and2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:and2" -description: "Generic 2-input and" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_and2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: and2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_buf.core b/hw/ip/prim/prim_buf.core deleted file mode 100644 index 9f10e8d67082c8..00000000000000 --- a/hw/ip/prim/prim_buf.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:buf" -description: "Generic buffer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_buf.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: buf - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_buf.core b/hw/ip/prim/prim_clock_buf.core deleted file mode 100644 index 54b95ae1bf6d8a..00000000000000 --- a/hw/ip/prim/prim_clock_buf.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_buf" -description: "Generic clock buffer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_buf.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_buf - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_div.core b/hw/ip/prim/prim_clock_div.core deleted file mode 100644 index 954f08d185062b..00000000000000 --- a/hw/ip/prim/prim_clock_div.core +++ /dev/null @@ -1,46 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_div" -description: "Generic clock divide" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_div.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_div - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_gating.core b/hw/ip/prim/prim_clock_gating.core deleted file mode 100644 index 04cf68bd1ece77..00000000000000 --- a/hw/ip/prim/prim_clock_gating.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_gating" -description: "Clock gating primitives" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_gating.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_gating - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_gp_mux2.core b/hw/ip/prim/prim_clock_gp_mux2.core index 2c9894d4651d1c..249d0ea8fa6298 100644 --- a/hw/ip/prim/prim_clock_gp_mux2.core +++ b/hw/ip/prim/prim_clock_gp_mux2.core @@ -8,7 +8,7 @@ description: "2-input glitch free clock multiplexer" filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg + - lowrisc:prim:clock_gating files: - rtl/prim_clock_gp_mux2.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/prim_clock_inv.core b/hw/ip/prim/prim_clock_inv.core deleted file mode 100644 index a6dcab935a14cf..00000000000000 --- a/hw/ip/prim/prim_clock_inv.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_inv" -description: "Clock inverter with scanmode bypass mux" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_inv.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_inv - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_clock_mux2.core b/hw/ip/prim/prim_clock_mux2.core deleted file mode 100644 index 5f703aded3eed6..00000000000000 --- a/hw/ip/prim/prim_clock_mux2.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_mux2" -description: "2-input clock multiplexer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_clock_mux2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: clock_mux2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flash.core b/hw/ip/prim/prim_flash.core deleted file mode 100644 index 7e293a1dde4aa5..00000000000000 --- a/hw/ip/prim/prim_flash.core +++ /dev/null @@ -1,52 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flash" -description: "Flash memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - # TODO olofk/fusesoc#404: The below dependency is already added to prim_generic_flash.core. - # However, the generator for the prim:ram1p does not kick in, causing compile errors. - - lowrisc:prim:ram_1p - - lowrisc:prim:clock_inv - - lowrisc:prim:clock_gating - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flash.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flash - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop.core b/hw/ip/prim/prim_flop.core deleted file mode 100644 index b707f1c473ecea..00000000000000 --- a/hw/ip/prim/prim_flop.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop" -description: "Generic flop" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop_2sync.core b/hw/ip/prim/prim_flop_2sync.core deleted file mode 100644 index 698580be257df1..00000000000000 --- a/hw/ip/prim/prim_flop_2sync.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop_2sync" -description: "Flop-based synchronizer" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop_2sync.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop_2sync - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_flop_en.core b/hw/ip/prim/prim_flop_en.core deleted file mode 100644 index 608384d18be818..00000000000000 --- a/hw/ip/prim/prim_flop_en.core +++ /dev/null @@ -1,47 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:flop_en" -description: "Generic enable flop" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_flop_en.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: flop_en - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_onehot_check.core b/hw/ip/prim/prim_onehot_check.core index ed8a7aaf17e6aa..35643db4e49576 100644 --- a/hw/ip/prim/prim_onehot_check.core +++ b/hw/ip/prim/prim_onehot_check.core @@ -10,8 +10,6 @@ filesets: depend: - lowrisc:prim:util - lowrisc:prim:assert - # TODO: remove then #13337 is resolved. - - lowrisc:prim:prim_pkg files: - rtl/prim_onehot_check.sv file_type: systemVerilogSource diff --git a/hw/ip/prim/prim_otp.core b/hw/ip/prim/prim_otp.core deleted file mode 100644 index 90d0eca4681711..00000000000000 --- a/hw/ip/prim/prim_otp.core +++ /dev/null @@ -1,50 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:otp" -description: "One-Time Programmable (OTP) memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - # TODO(#6604): these two dependencies are needed to - # make sure the corresponding prims are generated by primgen. - - lowrisc:prim:clock_gating - - lowrisc:prim:clock_inv - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_otp.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: otp - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pad_attr.core b/hw/ip/prim/prim_pad_attr.core deleted file mode 100644 index 10219fbfcb9fcf..00000000000000 --- a/hw/ip/prim/prim_pad_attr.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:pad_attr" -description: "PAD wrapper attributes" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:pad_wrapper_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_pad_attr.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: pad_attr - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pad_wrapper.core b/hw/ip/prim/prim_pad_wrapper.core deleted file mode 100644 index e700faf1ce6050..00000000000000 --- a/hw/ip/prim/prim_pad_wrapper.core +++ /dev/null @@ -1,49 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:pad_wrapper" -description: "PAD wrapper" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:pad_wrapper_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_pad_wrapper.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: pad_wrapper - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_pkg.core b/hw/ip/prim/prim_pkg.core deleted file mode 100644 index eea8326962f1ec..00000000000000 --- a/hw/ip/prim/prim_pkg.core +++ /dev/null @@ -1,23 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim:prim_pkg:0.1" -description: "Constants used by the primitives" -filesets: - primgen_dep: - depend: - - lowrisc:prim:primgen - -generate: - impl: - generator: primgen - parameters: - action: generate_prim_pkg - -targets: - default: - filesets: - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/util/primgen/prim_pkg.core.tpl b/hw/ip/prim/prim_pkg_legacy.core similarity index 65% rename from hw/ip/prim/util/primgen/prim_pkg.core.tpl rename to hw/ip/prim/prim_pkg_legacy.core index b51a34c5e00fc7..1e7bdc9770e668 100644 --- a/hw/ip/prim/util/primgen/prim_pkg.core.tpl +++ b/hw/ip/prim/prim_pkg_legacy.core @@ -2,13 +2,16 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim_abstract:prim_pkg:0.1" -description: "Constants used by the primitives" + +name: "lowrisc:prim:prim_pkg_legacy" +description: "Legacy prim_pkg core for old enums" +virtual: + - lowrisc:prim:prim_pkg filesets: files_rtl: files: - - prim_pkg.sv + - rtl/prim_pkg_legacy.sv file_type: systemVerilogSource targets: diff --git a/hw/ip/prim/prim_ram_1p.core b/hw/ip/prim/prim_ram_1p.core deleted file mode 100644 index b12882c61c3a37..00000000000000 --- a/hw/ip/prim/prim_ram_1p.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_1p" -description: "1 port random-access memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_1p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_1p.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_1p - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_ram_1r1w.core b/hw/ip/prim/prim_ram_1r1w.core deleted file mode 100644 index 18acb862097306..00000000000000 --- a/hw/ip/prim/prim_ram_1r1w.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_1r1w" -description: "Random-access memory with 1 read-only port and 1 write-only port" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_2p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_1r1w.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_1r1w - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_ram_2p.core b/hw/ip/prim/prim_ram_2p.core deleted file mode 100644 index 696c2248d689bb..00000000000000 --- a/hw/ip/prim/prim_ram_2p.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:ram_2p" -description: "2 port random-access memory" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:ram_2p_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_ram_2p.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: ram_2p - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_rom.core b/hw/ip/prim/prim_rom.core deleted file mode 100644 index 0aa76a4e310e06..00000000000000 --- a/hw/ip/prim/prim_rom.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:rom" -description: "Read-only memory (ROM)" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:rom_pkg - - lowrisc:prim:primgen - - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_rom.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: rom - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_rst_sync.core b/hw/ip/prim/prim_rst_sync.core index 9657f877164e0e..4821bddc958ee0 100644 --- a/hw/ip/prim/prim_rst_sync.core +++ b/hw/ip/prim/prim_rst_sync.core @@ -8,9 +8,7 @@ description: "Primitive Reset synchronizer" filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg - # Needed because the generic prim_flop_2sync has a - # dependency on prim:flop. + - lowrisc:prim:clock_mux2 - lowrisc:prim:flop_2sync - lowrisc:prim:mubi - lowrisc:prim:cdc_rand_delay diff --git a/hw/ip/prim/prim_usb_diff_rx.core b/hw/ip/prim/prim_usb_diff_rx.core deleted file mode 100644 index c323df0a2acab0..00000000000000 --- a/hw/ip/prim/prim_usb_diff_rx.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:usb_diff_rx" -description: "Differential receiver for USB." -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_usb_diff_rx.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: usb_diff_rx - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_xnor2.core b/hw/ip/prim/prim_xnor2.core deleted file mode 100644 index becb3067a26f2b..00000000000000 --- a/hw/ip/prim/prim_xnor2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:xnor2" -description: "Generic 2-input xnor" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xnor2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: xnor2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/prim_xor2.core b/hw/ip/prim/prim_xor2.core deleted file mode 100644 index 7bf51d9f4c16eb..00000000000000 --- a/hw/ip/prim/prim_xor2.core +++ /dev/null @@ -1,48 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:xor2" -description: "Generic 2-input xor" -filesets: - primgen_dep: - depend: - - lowrisc:prim:prim_pkg - - lowrisc:prim:primgen - - lowrisc:prim:assert - - files_verilator_waiver: - depend: - # common waivers - - lowrisc:lint:common - file_type: vlt - - files_ascentlint_waiver: - depend: - # common waivers - - lowrisc:lint:common - files: - - lint/prim_xor2.waiver - file_type: waiver - - files_veriblelint_waiver: - depend: - # common waivers - - lowrisc:lint:common - -generate: - impl: - generator: primgen - parameters: - prim_name: xor2 - -targets: - default: - filesets: - - tool_verilator ? (files_verilator_waiver) - - tool_ascentlint ? (files_ascentlint_waiver) - - tool_veriblelint ? (files_veriblelint_waiver) - - primgen_dep - generate: - - impl diff --git a/hw/ip/prim/primgen.core b/hw/ip/prim/primgen.core deleted file mode 100644 index 167f7965937d02..00000000000000 --- a/hw/ip/prim/primgen.core +++ /dev/null @@ -1,10 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim:primgen:0.1" - -generators: - primgen: - interpreter: python3 - command: util/primgen.py diff --git a/hw/ip/prim/util/primgen/prim_pkg.sv.tpl b/hw/ip/prim/rtl/prim_pkg_legacy.sv similarity index 63% rename from hw/ip/prim/util/primgen/prim_pkg.sv.tpl rename to hw/ip/prim/rtl/prim_pkg_legacy.sv index def5d496250c06..31aee24c474ce5 100644 --- a/hw/ip/prim/util/primgen/prim_pkg.sv.tpl +++ b/hw/ip/prim/rtl/prim_pkg_legacy.sv @@ -2,14 +2,16 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Constants for use in primitives - -// This file is auto-generated. +// Legacy constants that were used in some IPs +// These are deprecated and should be removed. package prim_pkg; // Implementation target specialization typedef enum integer { - ${',\n '.join(techlib_enums)} + ImplGeneric, + ImplXilinx, + ImplBadbit, + ImplXilinx_ultrascale } impl_e; endpackage : prim_pkg diff --git a/hw/ip/prim/util/primgen.py b/hw/ip/prim/util/primgen.py deleted file mode 100755 index 3e3ba4123d4df1..00000000000000 --- a/hw/ip/prim/util/primgen.py +++ /dev/null @@ -1,497 +0,0 @@ -#!/usr/bin/env python3 -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -import os -import re -import shutil -import sys - -import yaml -from mako.template import Template - -# Make vendored packages available in the search path. -sys.path.append(os.path.join(os.path.dirname(__file__), 'vendor')) - -try: - from yaml import CSafeDumper as YamlDumper - from yaml import CSafeLoader as YamlLoader -except ImportError: - from yaml import SafeDumper as YamlDumper - from yaml import SafeLoader as YamlLoader - - -def _split_vlnv(core_vlnv): - (vendor, library, name, version) = core_vlnv.split(':', 4) - return { - 'vendor': vendor, - 'library': library, - 'name': name, - 'version': version - } - - -def _prim_cores(cores, prim_name=None): - """ Get all cores of primitives found by fusesoc - - If prim_name is given, only primitives with the given name are returned. - Otherwise, all primitives are returned, independent of their name. - """ - - def _filter_primitives(core): - """ Filter a list of cores to find the primitives we're interested in - - Matching cores follow the pattern - "lowrisc:prim_:", where "" and - "" are placeholders. - """ - - vlnv = _split_vlnv(core[0]) - if (vlnv['vendor'] == 'lowrisc' and - vlnv['library'].startswith('prim_') and - (prim_name is None or vlnv['name'] == prim_name)): - - return core - return None - - return dict(filter(_filter_primitives, cores.items())) - - -def _techlibs(prim_cores): - techlibs = set() - for name, info in prim_cores.items(): - vlnv = _split_vlnv(name) - techlibs.add(_library_to_techlib_name(vlnv['library'])) - return techlibs - - -def _library_to_techlib_name(library): - return library[len("prim_"):] - - -def _core_info_for_techlib(prim_cores, techlib): - for name, info in prim_cores.items(): - vlnv = _split_vlnv(name) - if _library_to_techlib_name(vlnv['library']) == techlib: - return (name, info) - - -def _enum_name_for_techlib(techlib_name, qualified=True): - name = "Impl" + techlib_name.capitalize() - if qualified: - name = "prim_pkg::" + name - return name - - -def _top_module_file(core_files, module_name): - module_filename = module_name + '.sv' - for file in core_files: - if os.path.basename(file) == module_filename: - return file - - -def _parse_module_header_verible(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header using Verible - - Implementation of _parse_module_header() which uses verible-verilog-syntax - to do the parsing. This is the primary implementation and is used when - supported Verible version is available. - - See _parse_module_header() for API details. - """ - - from google_verible_verilog_syntax_py.verible_verilog_syntax import ( - PreOrderTreeIterator, VeribleVerilogSyntax) - - parser = VeribleVerilogSyntax() - - data = parser.parse_file(generic_impl_filepath, - options={"skip_null": True}) - if data.errors: - for err in data.errors: - print( - f'Verible: {err.phase} error in line {err.line} column {err.column}' + - (': {err.message}' if err.message else '.')) - # Intentionally not raising an exception here. - # There are chances that Verible recovered from errors. - if not data.tree: - raise ValueError(f"Unable to parse {generic_impl_filepath!r}.") - - module = data.tree.find({"tag": "kModuleDeclaration"}) - header = module.find({"tag": "kModuleHeader"}) - if not header: - raise ValueError("Unable to extract module header from %s." % - (generic_impl_filepath, )) - - name = header.find({"tag": ["SymbolIdentifier", "EscapedIdentifier"]}, - iter_=PreOrderTreeIterator) - if not name: - raise ValueError("Unable to extract module name from %s." % - (generic_impl_filepath, )) - - imports = header.find_all({"tag": "kPackageImportDeclaration"}) - - parameters_list = header.find({"tag": "kFormalParameterList"}) - parameters = set() - if parameters_list: - for parameter in sorted( - parameters_list.iter_find_all({"tag": "kParamDeclaration"})): - if parameter.find({"tag": "parameter"}): - parameter_id = parameter.find( - {"tag": ["SymbolIdentifier", "EscapedIdentifier"]}) - parameters.add(parameter_id.text) - - ports = header.find({"tag": "kPortDeclarationList"}) - - return { - 'module_header': header.text, - 'package_import_declaration': '\n'.join([i.text for i in imports]), - 'parameter_port_list': parameters_list.text if parameters_list else '', - 'ports': ports.text if ports else '', - 'parameters': parameters, - 'parser': 'Verible' - } - - -def _parse_module_header_fallback(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header using RegExp - - Legacy implementation of _parse_module_header() using regular expressions. - It is not as robust as Verible-backed implementation, but doesn't need - Verible to work. - - See _parse_module_header() for API details. - """ - - # Grammar fragments from the SV2017 spec: - # - # module_nonansi_header ::= - # { attribute_instance } module_keyword [ lifetime ] module_identifier - # { package_import_declaration } [ parameter_port_list ] list_of_ports ; - # module_ansi_header ::= - # { attribute_instance } module_keyword [ lifetime ] module_identifier - # { package_import_declaration }1 [ parameter_port_list ] [ list_of_port_declarations ] - # package_import_declaration ::= - # import package_import_item { , package_import_item } ; - # package_import_item ::= - # package_identifier :: identifier - # | package_identifier :: * - - RE_MODULE_HEADER = ( - r'(?:\s|^)' - r'(?P' # start: capture the whole module header - r'module\s+' # module_keyword - r'(?:(?:static|automatic)\s+)?' + # lifetime (optional) - module_name + # module_identifier - # package_import_declaration (optional, skipped) - r'\s*(?P(?:import\s+[^;]+;)+)?' - r'\s*(?:#\s*\((?P[^;]+)\))?' # parameter_port_list (optional) - r'\s*\(\s*(?P[^;]+)\s*\)' # list_of_port_declarations or list_of_ports - r'\s*;' # trailing semicolon - r')' # end: capture the whole module header - ) - - data = "" - with open(generic_impl_filepath, encoding="utf-8") as file: - data = file.read() - re_module_header = re.compile(RE_MODULE_HEADER, re.DOTALL) - matches = re_module_header.search(data) - if not matches: - raise ValueError("Unable to extract module header from %s." % - (generic_impl_filepath, )) - - parameter_port_list = matches.group('parameter_port_list') or '' - return { - 'module_header': - matches.group('module_header').strip(), - 'package_import_declaration': - matches.group('package_import_declaration') or '', - 'parameter_port_list': - parameter_port_list, - 'ports': - matches.group('ports').strip() or '', - 'parameters': - _parse_parameter_port_list(parameter_port_list), - 'parser': - 'Fallback (regex)' - } - - -def test_parse_parameter_port_list(): - assert _parse_parameter_port_list("parameter enum_t P") == {'P'} - assert _parse_parameter_port_list("parameter integer P") == {'P'} - assert _parse_parameter_port_list("parameter logic [W-1:0] P") == {'P'} - assert _parse_parameter_port_list("parameter logic [W-1:0] P = '0") == { - 'P' - } - assert _parse_parameter_port_list("parameter logic [W-1:0] P = 'b0") == { - 'P' - } - assert _parse_parameter_port_list("parameter logic [W-1:0] P = 2'd0") == { - 'P' - } - - -def _parse_parameter_port_list(parameter_port_list): - """ Parse a list of ports in a module header into individual parameters """ - - # Grammar (SV2017): - # - # parameter_port_list ::= - # # ( list_of_param_assignments { , parameter_port_declaration } ) - # | # ( parameter_port_declaration { , parameter_port_declaration } ) - # | #( ) - # parameter_port_declaration ::= - # parameter_declaration - # | local_parameter_declaration - # | data_type list_of_param_assignments - # | type list_of_type_assignments - - # XXX: Not covering the complete grammar, e.g. `parameter x, y` - RE_PARAMS = ( - r'parameter\s+' - r'(?:[a-zA-Z0-9_\]\[:\s\$-]+\s+)?' # type - r'(?P\w+)' # name - r'(?:\s*=\s*[^,;]+)?' # initial value - ) - re_params = re.compile(RE_PARAMS) - parameters = set() - for m in re_params.finditer(parameter_port_list): - parameters.add(m.group('name')) - return list(sorted(parameters)) - - -def _parse_module_header(generic_impl_filepath, module_name): - """ Parse a SystemVerilog file to extract the 'module' header - - Return a dict with the following entries: - - module_header: the whole module header (including the 'module' keyword) - - package_import_declaration: import declarations - - parameter_port_list: parameter/localparam declarations in the header - - ports: the list of ports. The portlist can be ANSI or non-ANSI style (with - or without signal declarations; see the SV spec for details). - - parser: parser used to extract the data. - """ - - try: - return _parse_module_header_verible(generic_impl_filepath, module_name) - except Exception as e: - print(e) - print("Verible parser failed, using regex fallback instead.") - return _parse_module_header_fallback(generic_impl_filepath, - module_name) - - -def _check_gapi(gapi): - if 'cores' not in gapi: - print("Key 'cores' not found in GAPI structure. " - "Install a compatible version with " - "'pip3 install --user -r python-requirements.txt'.") - return False - return True - - -def _generate_prim_pkg(gapi): - all_prim_cores = _prim_cores(gapi['cores']) - techlibs = _techlibs(all_prim_cores) - - techlib_enums = [] - - # Insert the required generic library first to ensure it gets enum value 0 - techlib_enums.append(_enum_name_for_techlib('generic', qualified=False)) - - for techlib in techlibs: - if techlib == 'generic': - # The generic implementation is required and handled separately. - continue - techlib_enums.append(_enum_name_for_techlib(techlib, qualified=False)) - - # Render prim_pkg.sv file - print("Creating prim_pkg.sv") - prim_pkg_sv_tpl_filepath = os.path.join(os.path.dirname(__file__), - 'primgen', 'prim_pkg.sv.tpl') - prim_pkg_sv_tpl = Template(filename=prim_pkg_sv_tpl_filepath) - - prim_pkg_sv = prim_pkg_sv_tpl.render(encoding="utf-8", - techlib_enums=techlib_enums) - with open('prim_pkg.sv', 'w') as f: - f.write(prim_pkg_sv) - - # Copy prim_pkg.core (no changes needed) - prim_pkg_core_src = os.path.join(os.path.dirname(__file__), 'primgen', - 'prim_pkg.core.tpl') - prim_pkg_core_dest = 'prim_pkg.core' - shutil.copyfile(prim_pkg_core_src, prim_pkg_core_dest) - print("Core file written to %s." % (prim_pkg_core_dest, )) - - -def _instance_sv(prim_name, techlib, parameters): - if not parameters: - s = " prim_{techlib}_{prim_name} u_impl_{techlib} (\n" - else: - s = " prim_{techlib}_{prim_name} #(\n" - s += ",\n".join(" .{p}({p})".format(p=p) for p in parameters) - s += "\n ) u_impl_{techlib} (\n" - s += " .*\n" \ - " );\n" - return s.format(prim_name=prim_name, techlib=techlib) - - -def _create_instances(prim_name, techlibs, parameters): - """ Build SystemVerilog code instantiating primitives from the techlib """ - - # Sort list of technology libraries to produce a stable ordering in the - # generated wrapper. - techlibs_wo_generic = sorted( - [techlib for techlib in techlibs if techlib != 'generic']) - techlibs_generic_last = techlibs_wo_generic + ['generic'] - - if not techlibs_wo_generic: - # Don't output the if/else blocks if there no alternatives exist. - # We still want the generate block to keep hierarchical path names - # stable, even if more than one techlib is found. - s = " if (1) begin : gen_generic\n" - s += _instance_sv(prim_name, "generic", parameters) + "\n" - s += " end" - return s - - nr_techlibs = len(techlibs_generic_last) - out = "" - for pos, techlib in enumerate(techlibs_generic_last): - is_first = pos == 0 - is_last = pos == nr_techlibs - 1 - - s = "" - if not is_first: - s += "else " - if not is_last: - s += "if (Impl == {techlib_enum}) " - - # TODO: wildcard port lists are against our style guide, but it's safer - # to let the synthesis tool figure out the connectivity than us trying - # to parse the port list into individual signals. - s += "begin : gen_{techlib}\n" + _instance_sv(prim_name, techlib, - parameters) + "end" - - if not is_last: - s += " " - - out += s.format(prim_name=prim_name, - techlib=techlib, - techlib_enum=_enum_name_for_techlib(techlib)) - return out - - -def _generate_abstract_impl(gapi): - prim_name = gapi['parameters']['prim_name'] - prim_cores = _prim_cores(gapi['cores'], prim_name) - - techlibs = _techlibs(prim_cores) - - if 'generic' not in techlibs: - raise ValueError("Techlib generic is required, but not found for " - "primitive %s." % prim_name) - print("Implementations for primitive %s: %s" % - (prim_name, ', '.join(techlibs))) - - # Extract port list out of generic implementation - generic_core = _core_info_for_techlib(prim_cores, 'generic')[1] - generic_module_name = 'prim_generic_' + prim_name - top_module_filename = _top_module_file(generic_core['files'], - generic_module_name) - top_module_file = os.path.join(generic_core['core_root'], - top_module_filename) - - print("Inspecting generic module %s" % (top_module_file, )) - generic_hdr = _parse_module_header(top_module_file, generic_module_name) - - # Render abstract primitive HDL from template - print("Creating SystemVerilog module for abstract primitive") - abstract_prim_sv_tpl_filepath = os.path.join(os.path.dirname(__file__), - 'primgen', - 'abstract_prim.sv.tpl') - abstract_prim_sv_tpl = Template(filename=abstract_prim_sv_tpl_filepath) - - abstract_prim_sv = abstract_prim_sv_tpl.render( - encoding="utf-8", - prim_name=prim_name, - module_header_imports=generic_hdr['package_import_declaration'], - module_header_params=generic_hdr['parameter_port_list'], - module_header_ports=generic_hdr['ports'], - num_techlibs=len(techlibs), - # Creating the code to instantiate the primitives in the Mako templating - # language is tricky to do; do it in Python instead. - instances=_create_instances(prim_name, techlibs, - generic_hdr['parameters']), - parser_info=generic_hdr['parser']) - abstract_prim_sv_filepath = 'prim_%s.sv' % (prim_name) - with open(abstract_prim_sv_filepath, 'w') as f: - f.write(abstract_prim_sv) - print("Abstract primitive written to %s" % - (os.path.abspath(abstract_prim_sv_filepath), )) - - # Create core file depending on all primitive implementations we have in the - # techlibs. - print("Creating core file for primitive %s." % (prim_name, )) - abstract_prim_core_filepath = os.path.abspath('prim_%s.core' % (prim_name)) - dependencies = [] - dependencies.append('lowrisc:prim:prim_pkg') - dependencies += [ - _core_info_for_techlib(prim_cores, t)[0] for t in techlibs - ] - abstract_prim_core = { - 'name': "lowrisc:prim_abstract:%s" % (prim_name, ), - 'filesets': { - 'files_rtl': { - 'depend': dependencies, - 'files': [ - abstract_prim_sv_filepath, - ], - 'file_type': 'systemVerilogSource' - }, - }, - 'targets': { - 'default': { - 'filesets': [ - 'files_rtl', - ], - }, - }, - } - with open(abstract_prim_core_filepath, 'w') as f: - # FuseSoC requires this line to appear first in the YAML file. - # Inserting this line through the YAML serializer requires ordered dicts - # to be used everywhere, which is annoying syntax-wise on Python <3.7, - # where native dicts are not sorted. - f.write('CAPI=2:\n') - yaml.dump(abstract_prim_core, f, encoding="utf-8", Dumper=YamlDumper) - print("Core file written to %s" % (abstract_prim_core_filepath, )) - - -def _get_action_from_gapi(gapi, default_action): - if 'parameters' in gapi and 'action' in gapi['parameters']: - return gapi['parameters']['action'] - return default_action - - -def main(): - gapi_filepath = sys.argv[1] - with open(gapi_filepath) as f: - gapi = yaml.load(f, Loader=YamlLoader) - - if not _check_gapi(gapi): - sys.exit(1) - - action = _get_action_from_gapi(gapi, 'generate_abstract_impl') - - if action == 'generate_abstract_impl': - return _generate_abstract_impl(gapi) - elif action == 'generate_prim_pkg': - return _generate_prim_pkg(gapi) - else: - raise ValueError("Invalid action: %s" % (action, )) - - -if __name__ == '__main__': - main() diff --git a/hw/ip/prim/util/primgen/abstract_prim.sv.tpl b/hw/ip/prim/util/primgen/abstract_prim.sv.tpl deleted file mode 100644 index 9b3432a3fecea9..00000000000000 --- a/hw/ip/prim/util/primgen/abstract_prim.sv.tpl +++ /dev/null @@ -1,33 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// This file is auto-generated. -// Used parser: ${parser_info} - -% if num_techlibs > 1: -`ifndef PRIM_DEFAULT_IMPL - `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric -`endif -% endif - -// This is to prevent AscentLint warnings in the generated -// abstract prim wrapper. These warnings occur due to the .* -// use. TODO: we may want to move these inline waivers -// into a separate, generated waiver file for consistency. -//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ -module prim_${prim_name} -${module_header_imports} -#( -${module_header_params} -) ( - ${module_header_ports} -); -% if num_techlibs > 1: - localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; -% endif - -${instances} - -endmodule -//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ diff --git a/hw/ip/prim_generic/prim_generic.core b/hw/ip/prim_generic/prim_generic.core new file mode 100644 index 00000000000000..ca5abc125e81bc --- /dev/null +++ b/hw/ip/prim_generic/prim_generic.core @@ -0,0 +1,37 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_generic:all:0.1" +description: "Technology-independent prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_generic:and2 + - lowrisc:prim_generic:buf + - lowrisc:prim_generic:clock_buf + - lowrisc:prim_generic:clock_div + - lowrisc:prim_generic:clock_gating + - lowrisc:prim_generic:clock_inv + - lowrisc:prim_generic:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_generic:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_generic:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_generic:pad_attr + - lowrisc:prim_generic:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:usb_diff_rx + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_generic:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core index 35bf0a05b8ba68..84ff84b786cb51 100644 --- a/hw/ip/prim_generic/prim_generic_and2.core +++ b/hw/ip/prim_generic/prim_generic_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:and2" description: "Generic 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core index 1e9380006dee3b..42342e7cfe583c 100644 --- a/hw/ip/prim_generic/prim_generic_buf.core +++ b/hw/ip/prim_generic/prim_generic_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core index a0527957ea17d8..d9cb24827fbce5 100644 --- a/hw/ip/prim_generic/prim_generic_clock_buf.core +++ b/hw/ip/prim_generic/prim_generic_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core index 806654072b0d88..6bd3aee3f02910 100644 --- a/hw/ip/prim_generic/prim_generic_clock_div.core +++ b/hw/ip/prim_generic/prim_generic_clock_div.core @@ -5,10 +5,13 @@ CAPI=2: name: "lowrisc:prim_generic:clock_div" description: "Generic clock divide" +virtual: + - lowrisc:prim:clock_div + filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg + - lowrisc:prim:assert - lowrisc:prim:flop - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core index c1e878180b117b..ce65b1b9e3c879 100644 --- a/hw/ip/prim_generic/prim_generic_clock_gating.core +++ b/hw/ip/prim_generic/prim_generic_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core index 4f48b07a98d943..e9982ef38a07c1 100644 --- a/hw/ip/prim_generic/prim_generic_clock_inv.core +++ b/hw/ip/prim_generic/prim_generic_clock_inv.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_inv" description: "Clock inverter with scanmode bypass mux" +virtual: + - lowrisc:prim:clock_inv + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core index f4f343d498a7d4..7cfca422af0656 100644 --- a/hw/ip/prim_generic/prim_generic_clock_mux2.core +++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 736caad5944fd1..08a6f9b74b09ab 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flash" description: "prim" +virtual: + - lowrisc:prim:flash + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core index c66701bc1adb48..162735a9bbc027 100644 --- a/hw/ip/prim_generic/prim_generic_flop.core +++ b/hw/ip/prim_generic/prim_generic_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop" description: "generic flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core index 19ee312bd4cd71..eb2b6677001965 100644 --- a/hw/ip/prim_generic/prim_generic_flop_2sync.core +++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop_2sync" description: "Generic implementation of a flop-based synchronizer" +virtual: + - lowrisc:prim:flop_2sync + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core index 8e39916ee58801..556ee9abec0e88 100644 --- a/hw/ip/prim_generic/prim_generic_flop_en.core +++ b/hw/ip/prim_generic/prim_generic_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:flop_en" description: "generic enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core index db270f07437e35..054d97a55b251a 100644 --- a/hw/ip/prim_generic/prim_generic_otp.core +++ b/hw/ip/prim_generic/prim_generic_otp.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:otp" description: "Technology-independent One-Time Programmable (OTP) memory emulation" +virtual: + - lowrisc:prim:otp + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core index 0629996c26265f..451ae4c8d63eb1 100644 --- a/hw/ip/prim_generic/prim_generic_pad_attr.core +++ b/hw/ip/prim_generic/prim_generic_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:pad_attr" description: "Technology-independent pad attribute WARL module (for sim only!)" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core index ab7f0a1c737ba6..9e7ffc6ba1d4dd 100644 --- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core +++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:pad_wrapper" description: "Technology-independent pad wrapper implementation (for sim only!)" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core index ea3848b121dac4..52b98b589910dd 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1p.core +++ b/hw/ip/prim_generic/prim_generic_ram_1p.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_1p" description: "Single port RAM" +virtual: + - lowrisc:prim:ram_1p + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core index 2cc6529619fb96..302a516a2d5666 100644 --- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core +++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_1r1w" description: "prim" +virtual: + - lowrisc:prim:ram_1r1w + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core index 13c411459d11e3..7da402948ca41a 100644 --- a/hw/ip/prim_generic/prim_generic_ram_2p.core +++ b/hw/ip/prim_generic/prim_generic_ram_2p.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:ram_2p" description: "prim" +virtual: + - lowrisc:prim:ram_2p + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core index 5bf3b6ce38ea2c..32d3cb04e240f2 100644 --- a/hw/ip/prim_generic/prim_generic_rom.core +++ b/hw/ip/prim_generic/prim_generic_rom.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:rom" description: "Technology-independent Read-Only Memory (ROM) implementation" +virtual: + - lowrisc:prim:rom + filesets: files_rtl: depend: diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core index d1c34a6a04a168..59d18043ab0f88 100644 --- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core +++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:usb_diff_rx" description: "Generic differential USB receiver for emulation purposes" +virtual: + - lowrisc:prim:usb_diff_rx + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core index 24e3a125e32674..c8e86b40174012 100644 --- a/hw/ip/prim_generic/prim_generic_xnor2.core +++ b/hw/ip/prim_generic/prim_generic_xnor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:xnor2" description: "Generic 2-input xnor" +virtual: + - lowrisc:prim:xnor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core index e3cf88c20c4300..6d945cef6be270 100644 --- a/hw/ip/prim_generic/prim_generic_xor2.core +++ b/hw/ip/prim_generic/prim_generic_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_generic:xor2" description: "Generic 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_generic/rtl/prim_generic_and2.sv b/hw/ip/prim_generic/rtl/prim_generic_and2.sv index df1b65fa3b7ca7..6a9cca480bfd90 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_and2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_and2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_buf.sv b/hw/ip/prim_generic/rtl/prim_generic_buf.sv index ede99f1d640623..82517a7cf5b5ad 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_buf.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_buf.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv index d660aab686bfd3..36a596cca15653 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_buf #( +module prim_clock_buf #( // Turning off these verilator lints because keeping these parameters makes it consistent with // the IP in hw/ip/prim_xilinx/rtl/ . /* verilator lint_off UNUSED */ diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv index 798aa35ec0e12a..ae9fd2c78f3c7f 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_div #( +module prim_clock_div #( parameter int unsigned Divisor = 2, parameter logic ResetValue = 0 ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv index 6f80f6e89baa70..dc092ea56f881d 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv @@ -7,7 +7,7 @@ // The logic assumes that en_i is synchronized (so the instantiation site might need to put a // synchronizer before en_i). -module prim_generic_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, // this parameter has no function in generic parameter bit FpgaBufGlobal = 1'b1 // this parameter has no function in generic ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv index 2f56d3287fa8ad..3a05ea5ca9fcd8 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv @@ -5,7 +5,7 @@ // Clock inverter // Varies on the process -module prim_generic_clock_inv #( +module prim_clock_inv #( parameter bit HasScanMode = 1'b1, parameter bit NoFpgaBufG = 1'b0 // only used in FPGA case ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv b/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv index 85418e0da2d49d..69b571c16f4f8b 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 // this parameter serves no function in the generic model ) ( input clk0_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv index 2349dd8f2e231b..e2f0bd4fbb62aa 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv @@ -5,7 +5,7 @@ // Overall flash wrapper // -module prim_generic_flash #( +module prim_flash #( parameter int NumBanks = 2, // number of banks parameter int InfosPerBank = 1, // info pages per bank parameter int InfoTypes = 1, // different info types diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv index 566a2e8fa2084e..b094c18e6d0231 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv @@ -5,7 +5,7 @@ // Emulate a single generic flash bank // -module prim_generic_flash_bank #( +module prim_flash_bank #( parameter int InfosPerBank = 1, // info pages per bank parameter int InfoTypes = 1, // different info types parameter int InfoTypesWidth = 1, // different info types diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop.sv b/hw/ip/prim_generic/rtl/prim_generic_flop.sv index 426b44e042eaf0..d2357d2725dc94 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flop.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flop.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv b/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv index 94ca795fca2a1e..aaea0ea7a14981 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_flop_en #( +module prim_flop_en #( parameter int Width = 1, parameter bit EnSecBuf = 0, parameter logic [Width-1:0] ResetValue = 0 diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_generic_otp.sv index 5fe826d6602bda..6336f969be23a8 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_otp.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_otp.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_generic_otp +module prim_otp import prim_otp_pkg::*; #( // Native OTP word size. This determines the size_i granule. diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv index 80e93f82bcb8f6..75afdedcb37658 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_generic_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( parameter pad_type_e PadType = BidirStd // currently ignored in the generic model diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv index 7ff382c302a331..fe987354bf3dfb 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_generic_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this model. diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv index d2e835ac339156..ab4b5ca282ad6e 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv @@ -6,7 +6,7 @@ `include "prim_assert.sv" -module prim_generic_ram_1p import prim_ram_1p_pkg::*; #( +module prim_ram_1p import prim_ram_1p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv index aafecf8adba8f9..292f4df3fe608f 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv @@ -6,7 +6,7 @@ // This module is for simulation and small size SRAM. // Implementing ECC should be done inside wrapper not this model. `include "prim_assert.sv" -module prim_generic_ram_1r1w import prim_ram_2p_pkg::*; #( +module prim_ram_1r1w import prim_ram_2p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv index f44e828bfbf44d..2160ba88e607cd 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv @@ -6,7 +6,7 @@ // This module is for simulation and small size SRAM. // Implementing ECC should be done inside wrapper not this model. `include "prim_assert.sv" -module prim_generic_ram_2p import prim_ram_2p_pkg::*; #( +module prim_ram_2p import prim_ram_2p_pkg::*; #( parameter int Width = 32, // bit parameter int Depth = 128, parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask diff --git a/hw/ip/prim_generic/rtl/prim_generic_rom.sv b/hw/ip/prim_generic/rtl/prim_generic_rom.sv index acf5f379ca4540..00f531ca1f0f80 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_rom.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_rom.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_rom import prim_rom_pkg::*; #( +module prim_rom import prim_rom_pkg::*; #( parameter int Width = 32, parameter int Depth = 2048, // 8kB default parameter MemInitFile = "", // VMEM file to initialize the memory with diff --git a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv b/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv index a0b8e19c87cb62..71c88e33a61fe6 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_generic_usb_diff_rx #( +module prim_usb_diff_rx #( parameter int CalibW = 32 ) ( inout input_pi, // differential input diff --git a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv b/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv index 90eb684d2f1c02..0306df176d21eb 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_xnor2 #( +module prim_xnor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv b/hw/ip/prim_generic/rtl/prim_generic_xor2.sv index 4f303c7730a8ba..059dd60b2ecc96 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_xor2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_generic_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx/prim_xilinx.core b/hw/ip/prim_xilinx/prim_xilinx.core new file mode 100644 index 00000000000000..bb4891f74eddf8 --- /dev/null +++ b/hw/ip/prim_xilinx/prim_xilinx.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_xilinx:all:0.1" +description: "Xilinx 7-series prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_xilinx:and2 + - lowrisc:prim_xilinx:buf + - lowrisc:prim_xilinx:clock_buf + - lowrisc:prim_generic:clock_div + - lowrisc:prim_xilinx:clock_gating + - lowrisc:prim_generic:clock_inv + - lowrisc:prim_xilinx:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_xilinx:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_xilinx:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_xilinx:pad_attr + - lowrisc:prim_xilinx:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_xilinx:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_xilinx/prim_xilinx_and2.core b/hw/ip/prim_xilinx/prim_xilinx_and2.core index 9c86c83f4eafa4..5db713bd5b3ddb 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_and2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:and2" description: "Xilinx 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_buf.core b/hw/ip/prim_xilinx/prim_xilinx_buf.core index bc4e7a2e262bd9..d5cd793214d946 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core index f1bfbe8f126b72..b458d4db454f3a 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core index 587c7e5a3589ee..e80bd4a44114a4 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core index 5d94cd0c71a141..e08e8301d829e3 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop.core b/hw/ip/prim_xilinx/prim_xilinx_flop.core index b94d12c75e912d..427449775d7e25 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:flop" description: "Xilinx flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core index e40394b832c6a2..0edee3a33f08ab 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core +++ b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:flop_en" description: "Xilinx enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core index 6c1031337b9187..866ef847ac2c8a 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:pad_attr" description: "Pad attribute WARL module for Xilinx pads" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core index 765845a0bc83f1..cba9144762ec88 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core +++ b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:pad_wrapper" description: "prim" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx/prim_xilinx_xor2.core b/hw/ip/prim_xilinx/prim_xilinx_xor2.core index e7f699cf84ba09..e46943e84115ad 100644 --- a/hw/ip/prim_xilinx/prim_xilinx_xor2.core +++ b/hw/ip/prim_xilinx/prim_xilinx_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx:xor2" description: "Xilinx 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv index 69d8683612d7f0..76a0699a018ec1 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv index 7bdeea9cb79769..dd772bbd12ac55 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv @@ -4,7 +4,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv index 51945f44020971..0169f74048d620 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_clock_buf #( +module prim_clock_buf #( // The following options allow a user to choose the type of buffer // associated with this cell. // NoFpgaBuf -> No fpga clock buffer is selected, this will be constructed diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv index 7eaac02a07440c..99bc6850a2d2f5 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, parameter bit FpgaBufGlobal = 1'b1 ) ( diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv index ee7390d9c27657..81066ad40bb149 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 ) ( input clk0_i, @@ -33,4 +33,4 @@ module prim_xilinx_clock_mux2 #( `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) -endmodule : prim_xilinx_clock_mux2 +endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv index 45deeadeec8d1c..04c8962e5c17f4 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv index c4de058a91bd26..bc95d39e5c758c 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_flop_en #( +module prim_flop_en #( parameter int Width = 1, // This parmaeter does nothing for prim_xilinx parameter bit EnSecBuf = 0, diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv index 7267465e8c15fe..5955d72b183157 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_xilinx_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( // This parameter is ignored in this Xilinx variant. @@ -56,4 +56,4 @@ module prim_xilinx_pad_attr end -endmodule : prim_xilinx_pad_attr +endmodule : prim_pad_attr diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv index afb9c1794e2166..4c2a539de9ae11 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_xilinx_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this Xilinx variant. @@ -123,4 +123,4 @@ module prim_xilinx_pad_wrapper assert_static_in_generate_config_not_available(); end -endmodule : prim_xilinx_pad_wrapper +endmodule : prim_pad_wrapper diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv index 0eb9c14235d9ef..d00a027eec7273 100644 --- a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv +++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core new file mode 100644 index 00000000000000..471e14f974c065 --- /dev/null +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:prim_xilinx_ultrascale:all:0.1" +description: "Xilinx Ultrascale prim library" + +filesets: + files_rtl: + depend: + - lowrisc:prim_xilinx_ultrascale:and2 + - lowrisc:prim_xilinx_ultrascale:buf + - lowrisc:prim_xilinx_ultrascale:clock_buf + - lowrisc:prim_xilinx_ultrascale:clock_div + - lowrisc:prim_xilinx_ultrascale:clock_gating + - lowrisc:prim_xilinx_ultrascale:clock_inv + - lowrisc:prim_xilinx_ultrascale:clock_mux2 + - lowrisc:prim_generic:flash + - lowrisc:prim_xilinx_ultrascale:flop + - lowrisc:prim_generic:flop_2sync + - lowrisc:prim_xilinx_ultrascale:flop_en + - lowrisc:prim_generic:otp + - lowrisc:prim_xilinx_ultrascale:pad_attr + - lowrisc:prim_xilinx_ultrascale:pad_wrapper + - lowrisc:prim_generic:ram_1p + - lowrisc:prim_generic:ram_1r1w + - lowrisc:prim_generic:ram_2p + - lowrisc:prim_generic:rom + - lowrisc:prim_generic:xnor2 + - lowrisc:prim_xilinx_ultrascale:xor2 + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core index 61d31548bff88c..ee2214956f8f7a 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:and2" description: "Xilinx 2-input and" +virtual: + - lowrisc:prim:and2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core index 11ca450bed1273..616e78504f6f89 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:buf" description: "buffer" +virtual: + - lowrisc:prim:buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core index 086ff20487efd1..f182ea3d71a180 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_buf" description: "clock buffer" +virtual: + - lowrisc:prim:clock_buf + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core index 1a24d8c4ef3e44..af7ee41bb1deec 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core @@ -5,10 +5,13 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_div" description: "Xilinx ultrascale clock divide" +virtual: + - lowrisc:prim:clock_div + filesets: files_rtl: depend: - - lowrisc:prim:prim_pkg + - lowrisc:prim:assert - lowrisc:prim:flop - lowrisc:prim:clock_inv - lowrisc:prim:clock_buf diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core index 8440287fe548fc..26df5f421777c0 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_gating" description: "prim" +virtual: + - lowrisc:prim:clock_gating + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core index da24344f1ebe5d..af0561157981f6 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_inv" description: "clock buffer" +virtual: + - lowrisc:prim:clock_inv + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core index 8159e4c616eed3..642464ca36a618 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:clock_mux2" description: "two-input clock multiplexer primitive" +virtual: + - lowrisc:prim:clock_mux2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core index a85e3be191a8ff..2406237e2e7a30 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:flop" description: "Xilinx flop" +virtual: + - lowrisc:prim:flop + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core index 8b79324323b005..9b0f752c6c0302 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:flop_en" description: "Xilinx enable flop" +virtual: + - lowrisc:prim:flop_en + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core index 4a205e5eb037fd..6c99f0177a674d 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:pad_attr" description: "Pad attribute WARL module for Xilinx pads" +virtual: + - lowrisc:prim:pad_attr + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core index 4356a9f661db7c..623620aeb1a776 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:pad_wrapper" description: "prim" +virtual: + - lowrisc:prim:pad_wrapper + filesets: files_rtl: depend: diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core index 3b14815dcdfd02..6318ace2a58676 100644 --- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core +++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core @@ -5,6 +5,9 @@ CAPI=2: name: "lowrisc:prim_xilinx_ultrascale:xor2" description: "Xilinx 2-input xor" +virtual: + - lowrisc:prim:xor2 + filesets: files_rtl: files: diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv index a2d3b5fd2769c4..76a0699a018ec1 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_and2 #( +module prim_and2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv index 2a4a7436c32cf8..dd772bbd12ac55 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv @@ -4,7 +4,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_buf #( +module prim_buf #( parameter int Width = 1 ) ( input [Width-1:0] in_i, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv index 773505b626317e..055cf23d4626c3 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_buf #( +module prim_clock_buf #( parameter bit NoFpgaBuf = 1'b0, parameter bit RegionSel = 1'b0 // serves no function in Ultrascale ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv index 1787584fe2142c..fa264d51a43105 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_clock_div #( +module prim_clock_div #( parameter int unsigned Divisor = 2, parameter logic ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv index c554e71eee5f50..ff01102bc9215f 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_gating #( +module prim_clock_gating #( parameter bit NoFpgaGate = 1'b0, parameter bit FpgaBufGlobal = 1'b1 // No function in Ultrascale ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv index 581dbc3c35210d..1bddcee17acb37 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module prim_xilinx_ultrascale_clock_inv #( +module prim_clock_inv #( parameter bit HasScanMode = 1'b1, parameter bit NoFpgaBufG = 1'b0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv index b6341d6edc6966..81066ad40bb149 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv @@ -4,7 +4,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_clock_mux2 #( +module prim_clock_mux2 #( parameter bit NoFpgaBufG = 1'b0 ) ( input clk0_i, @@ -33,4 +33,4 @@ module prim_xilinx_ultrascale_clock_mux2 #( `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0) `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0) -endmodule : prim_xilinx_ultrascale_clock_mux2 +endmodule : prim_clock_mux2 diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv index 1cc12692c84055..04c8962e5c17f4 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_flop #( +module prim_flop #( parameter int Width = 1, parameter logic [Width-1:0] ResetValue = 0 ) ( diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv index f1acacda6f54e4..bc95d39e5c758c 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_flop_en #( +module prim_flop_en #( parameter int Width = 1, // This parmaeter does nothing for prim_xilinx parameter bit EnSecBuf = 0, diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv index e28b665b2a2981..5955d72b183157 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_pad_attr +module prim_pad_attr import prim_pad_wrapper_pkg::*; #( // This parameter is ignored in this Xilinx variant. @@ -56,4 +56,4 @@ module prim_xilinx_ultrascale_pad_attr end -endmodule : prim_xilinx_ultrascale_pad_attr +endmodule : prim_pad_attr diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv index a3d05a39ae8bfc..e43770c28837a8 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv @@ -7,7 +7,7 @@ `include "prim_assert.sv" -module prim_xilinx_ultrascale_pad_wrapper +module prim_pad_wrapper import prim_pad_wrapper_pkg::*; #( // These parameters are ignored in this Xilinx variant. @@ -120,4 +120,4 @@ module prim_xilinx_ultrascale_pad_wrapper assert_static_in_generate_config_not_available(); end -endmodule : prim_xilinx_ultrascale_pad_wrapper +endmodule : prim_pad_wrapper diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv index 373ba583088da0..d00a027eec7273 100644 --- a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv +++ b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv @@ -6,7 +6,7 @@ // Prevent Vivado from performing optimizations on/across this module. (* DONT_TOUCH = "yes" *) -module prim_xilinx_ultrascale_xor2 #( +module prim_xor2 #( parameter int Width = 1 ) ( input [Width-1:0] in0_i, diff --git a/hw/top_earlgrey/chip_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core index ff10ddbc9768db..64ca129a650fb4 100644 --- a/hw/top_earlgrey/chip_earlgrey_asic.core +++ b/hw/top_earlgrey/chip_earlgrey_asic.core @@ -14,6 +14,8 @@ filesets: - "fileset_partner ? (partner:systems:scan_role_pkg)" - "!fileset_partner ? (lowrisc:systems:ast)" - "!fileset_partner ? (lowrisc:systems:scan_role_pkg)" + - "!fileset_partner ? (lowrisc:prim:prim_pkg_legacy)" + - "!fileset_partner ? (lowrisc:prim_generic:all)" files: - rtl/autogen/chip_earlgrey_asic.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core index 22f1bb09eb0c55..529bc36986dd79 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310.core @@ -11,6 +11,8 @@ filesets: - lowrisc:systems:top_earlgrey_pkg - lowrisc:systems:ast - lowrisc:systems:padring + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_xilinx:all files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core index 1741cc236caa44..6ba614a3d4ae26 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core @@ -11,6 +11,8 @@ filesets: - lowrisc:systems:top_earlgrey_pkg - lowrisc:systems:ast - lowrisc:systems:padring + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_xilinx:all files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core index 5af4f5775edc0d..19a7bf70c6c9e5 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw340.core +++ b/hw/top_earlgrey/chip_earlgrey_cw340.core @@ -11,6 +11,8 @@ filesets: - lowrisc:systems:top_earlgrey_pkg - lowrisc:systems:ast - lowrisc:systems:padring + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_xilinx_ultrascale:all files: - rtl/clkgen_xil_ultrascale.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core index 6c6b694f7021a5..da5af2d66dc429 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.core +++ b/hw/top_earlgrey/chip_earlgrey_verilator.core @@ -13,6 +13,8 @@ filesets: - lowrisc:prim:clock_div - lowrisc:systems:ast - lowrisc:systems:scan_role_pkg + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_generic:all files: - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core index c37f2a7854cc99..9ccf8aafbbb709 100644 --- a/hw/top_earlgrey/ip/ast/ast.core +++ b/hw/top_earlgrey/ip/ast/ast.core @@ -18,9 +18,11 @@ filesets: - lowrisc:ip:pinmux_reg - lowrisc:ip:pinmux_component - lowrisc:prim:assert - - lowrisc:prim:prim_pkg - lowrisc:prim:mubi - lowrisc:prim:multibit_sync + # TODO: prim_pkg is deprecated. + - lowrisc:prim:prim_pkg + - lowrisc:prim:multibit_sync - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:edn_pkg - lowrisc:ip_interfaces:alert_handler_reg diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core index edacf154d38571..1c81a7548c7b73 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core @@ -12,6 +12,8 @@ filesets: - lowrisc:systems:ast - lowrisc:systems:topgen - lowrisc:systems:padring + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_xilinx:all file_type: systemVerilogSource files_constraints: diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core index a3002ac3a9e037..b4ab4b155350f8 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core @@ -28,6 +28,8 @@ filesets: - lowrisc:dv:sw_test_status - lowrisc:dv:dv_test_status - lowrisc:prim:clock_div + - lowrisc:prim:prim_pkg_legacy + - lowrisc:prim_generic:all files: - rtl/chip_englishbreakfast_verilator.sv: { file_type: systemVerilogSource }