From 53440164a5c927fa66e9b5d43a7fd5b274e912e2 Mon Sep 17 00:00:00 2001
From: Alexander Williams <awill@opentitan.org>
Date: Fri, 14 Jun 2024 21:34:12 -0700
Subject: [PATCH] [prim] Rename all files to match virtual cores

We expect file names to match module names. Now that the IPs are virtual
cores, rename the files to match the module names that are the new "ABI"
(so to speak).

Adjust prim_generic, prim_xilinx, and prim_xilinx_ultrascale libraries.

Signed-off-by: Alexander Williams <awill@opentitan.org>
---
 .../lint/prim_generic_clock_buf.vlt           |  2 +-
 .../lint/prim_generic_clock_buf.waiver        |  4 ++--
 .../lint/prim_generic_clock_div.waiver        | 12 +++++------
 .../lint/prim_generic_clock_gating.vlt        |  4 ++--
 .../lint/prim_generic_clock_gating.waiver     |  8 ++++----
 .../lint/prim_generic_clock_mux2.vlt          |  2 +-
 .../lint/prim_generic_clock_mux2.waiver       |  2 +-
 .../lint/prim_generic_flash.waiver            |  4 ++--
 hw/ip/prim_generic/lint/prim_generic_otp.vlt  |  4 ++--
 .../prim_generic/lint/prim_generic_otp.waiver |  8 ++++----
 .../lint/prim_generic_pad_wrapper.waiver      | 20 +++++++++----------
 .../lint/prim_generic_ram_1p.waiver           |  8 ++++----
 .../lint/prim_generic_ram_1r1w.waiver         |  8 ++++----
 .../prim_generic/lint/prim_generic_ram_2p.vlt |  2 +-
 .../lint/prim_generic_ram_2p.waiver           | 10 +++++-----
 .../prim_generic/lint/prim_generic_rom.waiver |  4 ++--
 .../lint/prim_generic_usb_diff_rx.waiver      |  8 ++++----
 hw/ip/prim_generic/prim_generic_and2.core     |  2 +-
 hw/ip/prim_generic/prim_generic_buf.core      |  2 +-
 .../prim_generic/prim_generic_clock_buf.core  |  2 +-
 .../prim_generic/prim_generic_clock_div.core  |  2 +-
 .../prim_generic_clock_gating.core            |  2 +-
 .../prim_generic/prim_generic_clock_inv.core  |  2 +-
 .../prim_generic/prim_generic_clock_mux2.core |  2 +-
 hw/ip/prim_generic/prim_generic_flash.core    |  2 +-
 hw/ip/prim_generic/prim_generic_flop.core     |  2 +-
 .../prim_generic/prim_generic_flop_2sync.core |  2 +-
 hw/ip/prim_generic/prim_generic_flop_en.core  |  2 +-
 hw/ip/prim_generic/prim_generic_otp.core      |  2 +-
 hw/ip/prim_generic/prim_generic_pad_attr.core |  2 +-
 .../prim_generic_pad_wrapper.core             |  2 +-
 hw/ip/prim_generic/prim_generic_ram_1p.core   |  2 +-
 hw/ip/prim_generic/prim_generic_ram_1r1w.core |  2 +-
 hw/ip/prim_generic/prim_generic_ram_2p.core   |  2 +-
 hw/ip/prim_generic/prim_generic_rom.core      |  2 +-
 .../prim_generic_usb_diff_rx.core             |  2 +-
 hw/ip/prim_generic/prim_generic_xnor2.core    |  2 +-
 hw/ip/prim_generic/prim_generic_xor2.core     |  2 +-
 .../{prim_generic_and2.sv => prim_and2.sv}    |  0
 .../rtl/{prim_generic_buf.sv => prim_buf.sv}  |  0
 ...generic_clock_buf.sv => prim_clock_buf.sv} |  0
 ...generic_clock_div.sv => prim_clock_div.sv} |  0
 ...c_clock_gating.sv => prim_clock_gating.sv} |  0
 ...generic_clock_inv.sv => prim_clock_inv.sv} |  0
 ...neric_clock_mux2.sv => prim_clock_mux2.sv} |  0
 .../{prim_generic_flash.sv => prim_flash.sv}  |  0
 .../{prim_generic_flop.sv => prim_flop.sv}    |  0
 ...neric_flop_2sync.sv => prim_flop_2sync.sv} |  0
 ...rim_generic_flop_en.sv => prim_flop_en.sv} |  0
 .../rtl/{prim_generic_otp.sv => prim_otp.sv}  |  0
 ...m_generic_pad_attr.sv => prim_pad_attr.sv} |  0
 ...ric_pad_wrapper.sv => prim_pad_wrapper.sv} |  0
 ...{prim_generic_ram_1p.sv => prim_ram_1p.sv} |  0
 ...m_generic_ram_1r1w.sv => prim_ram_1r1w.sv} |  0
 ...{prim_generic_ram_2p.sv => prim_ram_2p.sv} |  0
 .../rtl/{prim_generic_rom.sv => prim_rom.sv}  |  0
 ...ric_usb_diff_rx.sv => prim_usb_diff_rx.sv} |  0
 .../{prim_generic_xnor2.sv => prim_xnor2.sv}  |  0
 .../{prim_generic_xor2.sv => prim_xor2.sv}    |  0
 .../lint/prim_xilinx_pad_wrapper.waiver       |  4 ++--
 hw/ip/prim_xilinx/prim_xilinx_and2.core       |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_buf.core        |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_clock_buf.core  |  2 +-
 .../prim_xilinx/prim_xilinx_clock_gating.core |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_flop.core       |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_flop_en.core    |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_pad_attr.core   |  2 +-
 .../prim_xilinx/prim_xilinx_pad_wrapper.core  |  2 +-
 hw/ip/prim_xilinx/prim_xilinx_xor2.core       |  2 +-
 .../rtl/{prim_xilinx_and2.sv => prim_and2.sv} |  0
 .../rtl/{prim_xilinx_buf.sv => prim_buf.sv}   |  0
 ..._xilinx_clock_buf.sv => prim_clock_buf.sv} |  0
 ...x_clock_gating.sv => prim_clock_gating.sv} |  0
 ...ilinx_clock_mux2.sv => prim_clock_mux2.sv} |  0
 .../rtl/{prim_xilinx_flop.sv => prim_flop.sv} |  0
 ...prim_xilinx_flop_en.sv => prim_flop_en.sv} |  0
 ...im_xilinx_pad_attr.sv => prim_pad_attr.sv} |  0
 ...inx_pad_wrapper.sv => prim_pad_wrapper.sv} |  0
 .../rtl/{prim_xilinx_xor2.sv => prim_xor2.sv} |  0
 .../prim_xilinx_ultrascale_pad_wrapper.waiver |  4 ++--
 .../prim_xilinx_ultrascale_and2.core          |  2 +-
 .../prim_xilinx_ultrascale_buf.core           |  2 +-
 .../prim_xilinx_ultrascale_clock_buf.core     |  2 +-
 .../prim_xilinx_ultrascale_clock_div.core     |  2 +-
 .../prim_xilinx_ultrascale_clock_gating.core  |  2 +-
 .../prim_xilinx_ultrascale_clock_inv.core     |  2 +-
 .../prim_xilinx_ultrascale_clock_mux2.core    |  2 +-
 .../prim_xilinx_ultrascale_flop.core          |  2 +-
 .../prim_xilinx_ultrascale_flop_en.core       |  2 +-
 .../prim_xilinx_ultrascale_pad_attr.core      |  2 +-
 .../prim_xilinx_ultrascale_pad_wrapper.core   |  2 +-
 .../prim_xilinx_ultrascale_xor2.core          |  2 +-
 ...xilinx_ultrascale_and2.sv => prim_and2.sv} |  0
 ...m_xilinx_ultrascale_buf.sv => prim_buf.sv} |  0
 ...rascale_clock_buf.sv => prim_clock_buf.sv} |  0
 ...rascale_clock_div.sv => prim_clock_div.sv} |  0
 ...e_clock_gating.sv => prim_clock_gating.sv} |  0
 ...rascale_clock_inv.sv => prim_clock_inv.sv} |  0
 ...scale_clock_mux2.sv => prim_clock_mux2.sv} |  0
 ...xilinx_ultrascale_flop.sv => prim_flop.sv} |  0
 ..._ultrascale_flop_en.sv => prim_flop_en.sv} |  0
 ...ltrascale_pad_attr.sv => prim_pad_attr.sv} |  0
 ...ale_pad_wrapper.sv => prim_pad_wrapper.sv} |  0
 ...xilinx_ultrascale_xor2.sv => prim_xor2.sv} |  0
 105 files changed, 102 insertions(+), 102 deletions(-)
 rename hw/ip/prim_generic/rtl/{prim_generic_and2.sv => prim_and2.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_buf.sv => prim_buf.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_clock_buf.sv => prim_clock_buf.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_clock_div.sv => prim_clock_div.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_clock_gating.sv => prim_clock_gating.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_clock_inv.sv => prim_clock_inv.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_clock_mux2.sv => prim_clock_mux2.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_flash.sv => prim_flash.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_flop.sv => prim_flop.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_flop_2sync.sv => prim_flop_2sync.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_flop_en.sv => prim_flop_en.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_otp.sv => prim_otp.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_pad_attr.sv => prim_pad_attr.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_pad_wrapper.sv => prim_pad_wrapper.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_ram_1p.sv => prim_ram_1p.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_ram_1r1w.sv => prim_ram_1r1w.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_ram_2p.sv => prim_ram_2p.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_rom.sv => prim_rom.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_usb_diff_rx.sv => prim_usb_diff_rx.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_xnor2.sv => prim_xnor2.sv} (100%)
 rename hw/ip/prim_generic/rtl/{prim_generic_xor2.sv => prim_xor2.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_and2.sv => prim_and2.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_buf.sv => prim_buf.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_buf.sv => prim_clock_buf.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_gating.sv => prim_clock_gating.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_clock_mux2.sv => prim_clock_mux2.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_flop.sv => prim_flop.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_flop_en.sv => prim_flop_en.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_pad_attr.sv => prim_pad_attr.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_pad_wrapper.sv => prim_pad_wrapper.sv} (100%)
 rename hw/ip/prim_xilinx/rtl/{prim_xilinx_xor2.sv => prim_xor2.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_and2.sv => prim_and2.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_buf.sv => prim_buf.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_buf.sv => prim_clock_buf.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_div.sv => prim_clock_div.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_gating.sv => prim_clock_gating.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_inv.sv => prim_clock_inv.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_clock_mux2.sv => prim_clock_mux2.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_flop.sv => prim_flop.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_flop_en.sv => prim_flop_en.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_pad_attr.sv => prim_pad_attr.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_pad_wrapper.sv => prim_pad_wrapper.sv} (100%)
 rename hw/ip/prim_xilinx_ultrascale/rtl/{prim_xilinx_ultrascale_xor2.sv => prim_xor2.sv} (100%)

diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt
index c61d4c6ea4579b..3952982334e691 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_buf.vlt
@@ -5,4 +5,4 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_buf.sv" -match "Parameter is not used: 'NoFpgaBuf'"
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver
index 89ab9b8ffb29df..4fedf9534568f6 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_buf.waiver
@@ -2,6 +2,6 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# primitives: prim_generic_clock_buf
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \
+# primitives: prim_clock_buf
+waive -rules PARAM_NOT_USED -location {prim_clock_buf.sv} -regexp {Parameter '(NoFpgaBuf|RegionSel)' not used} \
       -comment "parameter unused but required to maintain uniform interface"
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver
index d748ccb33db5db..a0cf1d02788580 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_div.waiver
@@ -2,19 +2,19 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_clock_div
+# waiver file for prim_clock_div
 
-waive -rules CLOCK_EDGE -location {prim_generic_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \
+waive -rules CLOCK_EDGE -location {prim_clock_div.sv} -msg {Falling edge of clock 'clk_i' used here, should use rising edge} \
       -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
 
-waive -rules DUAL_EDGE_CLOCK -location {prim_generic_clock_div.sv} -regexp {.*} \
+waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \
       -comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
 
-waive -rules CLOCK_MUX -location {prim_generic_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
+waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
       -comment "A mux is used during scan bypass, and for switching between div by 2 and div by 1 clocks"
 
-waive -rules CLOCK_USE -location {prim_generic_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \
+waive -rules CLOCK_USE -location {prim_clock_div.sv} -regexp {'clk_i' is connected to 'prim_clock_mux2' port 'clk1_i', and used as a clock} \
       -comment "This clock mux usage is OK."
 
-waive -rules SAME_NAME_TYPE -location {prim_generic_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \
+waive -rules SAME_NAME_TYPE -location {prim_clock_div.sv} -regexp {'ResetValue' is used as a parameter here, and as an enumeration value at} \
       -comment "Reused parameter name."
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt
index 2c6c5af87cebb1..8663692959ad77 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_gating.vlt
@@ -5,5 +5,5 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'"
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'NoFpgaGate'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_gating.sv" -match "Parameter is not used: 'FpgaBufGlobal'"
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver
index 1eb8561142030f..e68c145996c5ca 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_gating.waiver
@@ -3,11 +3,11 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # primitives: prim_clock_gating
-waive -rules LATCH                -location {prim_generic_clock_gating.sv} -regexp {'en_latch' is a latch} \
+waive -rules LATCH                -location {prim_clock_gating.sv} -regexp {'en_latch' is a latch} \
       -comment "clock gating cell creates a latch"
-waive -rules COMBO_NBA            -location {prim_generic_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \
+waive -rules COMBO_NBA            -location {prim_clock_gating.sv} -regexp {Non-blocking assignment to 'en_latch'} \
       -comment "clock gating cell creates a latch"
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \
+waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'NoFpgaGate' not used} \
       -comment "parameter unused but required to maintain uniform interface"
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \
+waive -rules PARAM_NOT_USED -location {prim_clock_gating.sv} -regexp {Parameter 'FpgaBufGlobal' not used} \
       -comment "parameter unused but required to maintain uniform interface"
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
index d62099a9af5385..23cd4fa4ab687b 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
@@ -5,4 +5,4 @@
 
 `verilator_config
 
-lint_off -rule UNUSED -file "*/rtl/prim_generic_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'"
+lint_off -rule UNUSED -file "*/rtl/prim_clock_mux2.sv" -match "Parameter is not used: 'NoFpgaBufG'"
diff --git a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
index 42d76a8dfa003d..62d6c52363ed04 100644
--- a/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
@@ -4,5 +4,5 @@
 #
 # waiver file for prim_clock_mux2
 
-waive -rules PARAM_NOT_USED -location {prim_generic_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \
+waive -rules PARAM_NOT_USED -location {prim_clock_mux2.sv} -regexp {.*Parameter 'NoFpgaBufG' not used in.*} \
       -comment "This parameter serves no function in the generic model"
diff --git a/hw/ip/prim_generic/lint/prim_generic_flash.waiver b/hw/ip/prim_generic/lint/prim_generic_flash.waiver
index d733a25619b09c..eb693f1f819592 100644
--- a/hw/ip/prim_generic/lint/prim_generic_flash.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_flash.waiver
@@ -2,8 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_flash
+# waiver file for prim_flash
 
 # The prim generic module does not make use of the IO ports
-waive -rules INOUT_AS_IN -location {prim_generic_flash.sv} \
+waive -rules INOUT_AS_IN -location {prim_flash.sv} \
       -regexp {Inout port 'flash_.*_io' has no driver}
diff --git a/hw/ip/prim_generic/lint/prim_generic_otp.vlt b/hw/ip/prim_generic/lint/prim_generic_otp.vlt
index 3aa735e9887e3b..2cb488200856b2 100644
--- a/hw/ip/prim_generic/lint/prim_generic_otp.vlt
+++ b/hw/ip/prim_generic/lint/prim_generic_otp.vlt
@@ -6,5 +6,5 @@
 `verilator_config
 
 // The generic OTP module doesn't use vendor-specific parameters
-lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestOffset*"
-lint_off -rule UNUSED -file "*/rtl/prim_generic_otp.sv" -match "*VendorTestSize*"
+lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestOffset*"
+lint_off -rule UNUSED -file "*/rtl/prim_otp.sv" -match "*VendorTestSize*"
diff --git a/hw/ip/prim_generic/lint/prim_generic_otp.waiver b/hw/ip/prim_generic/lint/prim_generic_otp.waiver
index c2313ab038aeda..fa309feacba2fc 100644
--- a/hw/ip/prim_generic/lint/prim_generic_otp.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_otp.waiver
@@ -7,10 +7,10 @@ waive -rules {CONST_FF} -location {prim_ram_1p_adv.sv} \
       -msg {Flip-flop 'rerror_q' is driven by constant zeros in module 'prim_ram_1p_adv' (Depth=1024,Width=22,EnableInputPipeline=1,EnableOutputPipeline=1)} \
       -comment "The read error bits are unused and hence set to zero."
 
-waive -rules {INOUT_AS_IN} -location {prim_generic_otp.sv} \
-      -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_generic_otp'} \
+waive -rules {INOUT_AS_IN} -location {prim_otp.sv} \
+      -msg {Inout port 'ext_voltage_io' has no driver in module 'prim_otp'} \
       -comment "This signal is not driven in the generic model."
 
-waive -rules {PARAM_NOT_USED} -location {prim_generic_otp.sv} \
-      -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_generic_otp'} \
+waive -rules {PARAM_NOT_USED} -location {prim_otp.sv} \
+      -regexp {Parameter '(VendorTestOffset|VendorTestSize)' not used in module 'prim_otp'} \
       -comment "These two parameters are not used in the generic model."
diff --git a/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver b/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
index e9e9acd1ab272e..5908b606afea50 100644
--- a/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
@@ -2,26 +2,26 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_pad_wrapper
+# waiver file for prim_pad_wrapper
 # note that this code is NOT synthesizable and meant for sim only
 
-waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_generic_pad_wrapper.sv} \
+waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} -location {prim_pad_wrapper.sv} \
       -comment "This is a bidirectional pad inout."
 waive -rules TRI_DRIVER -regexp {'in_raw_o' is driven by a tristate driver} \
       -comment "This is a bidirectional pad inout."
-waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_generic_pad_wrapper.sv} \
+waive -rules MULTI_DRIVEN -regexp {.* drivers on 'inout_io' here} -location {prim_pad_wrapper.sv} \
       -comment "The pad simulation model has multiple drivers to emulate different IO terminations."
-waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_generic_pad_wrapper.sv} \
+waive -rules SELF_ASSIGN -regexp {LHS signal 'inout_io' encountered on the RHS of a continuous assignment statement} -location {prim_pad_wrapper.sv} \
       -comment "This implements a keeper termination (it's basically an explicit TRIREG)"
-waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules DRIVE_STRENGTH -regexp {Drive strength .* encountered on assignment to 'inout_io'} -location {prim_pad_wrapper.sv} \
       -comment "The pad simulation model uses driving strength attributes to emulate different IO terminations."
-waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_generic_pad_wrapper.sv} \
+waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i*' is not read from} -location {prim_pad_wrapper.sv} \
       -comment "Some IO attributes may not be implemented."
-waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_generic_pad_wrapper.sv} \
+waive -rules Z_USE -regexp {Constant with 'Z literal value '1'bz' encountered} -location {prim_pad_wrapper.sv} \
       -comment "This z assignment is correct."
-waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules PARAM_NOT_USED -regexp {Parameter 'Variant' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \
       -comment "This parameter has been provisioned for later and is currently unused."
-waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_generic_pad_wrapper'} -location {prim_generic_pad_wrapper.sv} \
+waive -rules PARAM_NOT_USED -regexp {Parameter 'ScanRole' not used in module 'prim_pad_wrapper'} -location {prim_pad_wrapper.sv} \
       -comment "This parameter has been provisioned for later and is currently unused."
-waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_generic_pad_wrapper'} \
+waive -rules INPUT_NOT_READ -msg {Input port 'clk_scan_i' is not read from in module 'prim_pad_wrapper'} \
       -comment "This clock is not read in RTL since it will be connected after synthesis during DFT insertion"
diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver
index 997c72c77cccc9..0c4983f3f11f1d 100644
--- a/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_ram_1p.waiver
@@ -2,11 +2,11 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_1p
+# waiver file for prim_ram_1p
 
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1p.sv.* is not read from in module 'prim_generic_ram_1p'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1p.sv.* is not read from in module 'prim_ram_1p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_1p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"
diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
index 0a717f45d065a4..c57a0decaa36af 100644
--- a/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
@@ -2,11 +2,11 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_1r1w
+# waiver file for prim_ram_1r1w
 
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1r1w.sv.* is not read from in module 'prim_generic_ram_1r1w'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_1r1w.sv.* is not read from in module 'prim_ram_1r1w'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"
diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt b/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt
index c2c00c8c1b7a8d..5baf84e9a3c9c2 100644
--- a/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt
+++ b/hw/ip/prim_generic/lint/prim_generic_ram_2p.vlt
@@ -6,4 +6,4 @@
 `verilator_config
 
 // That is the nature of a dual-port memory: both write ports can access the same storage simultaneously.
-lint_off -rule MULTIDRIVEN -file "*/rtl/prim_generic_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*"
+lint_off -rule MULTIDRIVEN -file "*/rtl/prim_ram_2p.sv" -match "Signal has multiple driving blocks with different clocking: '*.mem'*"
diff --git a/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver b/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver
index 69590e898d3a6a..d3f9dcbedf48c2 100644
--- a/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_ram_2p.waiver
@@ -2,13 +2,13 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_2p
+# waiver file for prim_ram_2p
 
-waive -rules MULTI_PROC_ASSIGN -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \
+waive -rules MULTI_PROC_ASSIGN -location {prim_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \
       -comment "That is the nature of a dual-port memory: both write ports can access the same storage simultaneously"
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_2p.sv.* is not read from in module 'prim_generic_ram_2p'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_ram_2p.sv.* is not read from in module 'prim_ram_2p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
-waive -rules IFDEF_CODE -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+waive -rules IFDEF_CODE -location {prim_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"
diff --git a/hw/ip/prim_generic/lint/prim_generic_rom.waiver b/hw/ip/prim_generic/lint/prim_generic_rom.waiver
index 351694ba18c7b4..c6a44351c61612 100644
--- a/hw/ip/prim_generic/lint/prim_generic_rom.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_rom.waiver
@@ -2,7 +2,7 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_rom
+# waiver file for prim_rom
 
-waive -rules NOT_DRIVEN  -location {prim_generic_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_generic_rom'} \
+waive -rules NOT_DRIVEN  -location {prim_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_rom'} \
       -comment "since this is a ROM, the signal mem has no driver, but it is populated using an initialization file"
diff --git a/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver b/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
index 3ae5442bbe3417..af8022ee4edc19 100644
--- a/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
+++ b/hw/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
@@ -2,12 +2,12 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_usb_diff_rx
+# waiver file for prim_usb_diff_rx
 # note that this code is NOT synthesizable and meant for sim only
 
-waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules TRI_DRIVER -regexp {'(input_pi|input_ni)' is driven by a tristate driver} -location {prim_usb_diff_rx.sv} \
       -comment "This models the pullup behavior, hence the TRI driver."
-waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules MULTI_DRIVEN -regexp {'(input_pi|input_ni)' has 2 drivers, also driven at} -location {prim_usb_diff_rx.sv} \
       -comment "The simulation model has multiple drivers to emulate different IO terminations."
-waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_generic_usb_diff_rx.sv} \
+waive -rules DRIVE_STRENGTH -regexp {Drive strength '\(weak0,pull1\)' encountered on assignment to '(input_pi|input_ni)'} -location {prim_usb_diff_rx.sv} \
       -comment "The simulation model uses driving strength attributes to emulate different IO terminations."
diff --git a/hw/ip/prim_generic/prim_generic_and2.core b/hw/ip/prim_generic/prim_generic_and2.core
index 84ff84b786cb51..e18e8b48a2d650 100644
--- a/hw/ip/prim_generic/prim_generic_and2.core
+++ b/hw/ip/prim_generic/prim_generic_and2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_and2.sv
+      - rtl/prim_and2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_buf.core b/hw/ip/prim_generic/prim_generic_buf.core
index 42342e7cfe583c..9db9568d253ebf 100644
--- a/hw/ip/prim_generic/prim_generic_buf.core
+++ b/hw/ip/prim_generic/prim_generic_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_buf.sv
+      - rtl/prim_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_clock_buf.core b/hw/ip/prim_generic/prim_generic_clock_buf.core
index d9cb24827fbce5..d11883d9ea4f7f 100644
--- a/hw/ip/prim_generic/prim_generic_clock_buf.core
+++ b/hw/ip/prim_generic/prim_generic_clock_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_clock_buf.sv
+      - rtl/prim_clock_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_clock_div.core b/hw/ip/prim_generic/prim_generic_clock_div.core
index 6bd3aee3f02910..0c33b7398f10d2 100644
--- a/hw/ip/prim_generic/prim_generic_clock_div.core
+++ b/hw/ip/prim_generic/prim_generic_clock_div.core
@@ -16,7 +16,7 @@ filesets:
       - lowrisc:prim:clock_inv
       - lowrisc:prim:clock_buf
     files:
-      - rtl/prim_generic_clock_div.sv
+      - rtl/prim_clock_div.sv
     file_type: systemVerilogSource
 
   files_ascentlint_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_clock_gating.core b/hw/ip/prim_generic/prim_generic_clock_gating.core
index ce65b1b9e3c879..9d79c9d5403030 100644
--- a/hw/ip/prim_generic/prim_generic_clock_gating.core
+++ b/hw/ip/prim_generic/prim_generic_clock_gating.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_clock_gating.sv
+      - rtl/prim_clock_gating.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_clock_inv.core b/hw/ip/prim_generic/prim_generic_clock_inv.core
index e9982ef38a07c1..399b220bb6f447 100644
--- a/hw/ip/prim_generic/prim_generic_clock_inv.core
+++ b/hw/ip/prim_generic/prim_generic_clock_inv.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:clock_mux2
     files:
-      - rtl/prim_generic_clock_inv.sv
+      - rtl/prim_clock_inv.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core
index 7cfca422af0656..de600aea58b3de 100644
--- a/hw/ip/prim_generic/prim_generic_clock_mux2.core
+++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core
@@ -13,7 +13,7 @@ filesets:
     depend:
       - lowrisc:prim:assert
     files:
-      - rtl/prim_generic_clock_mux2.sv
+      - rtl/prim_clock_mux2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core
index 08a6f9b74b09ab..13035b8278b461 100644
--- a/hw/ip/prim_generic/prim_generic_flash.core
+++ b/hw/ip/prim_generic/prim_generic_flash.core
@@ -19,7 +19,7 @@ filesets:
       - lowrisc:ip:flash_ctrl_prim_reg_top
     files:
       - rtl/prim_generic_flash_bank.sv
-      - rtl/prim_generic_flash.sv
+      - rtl/prim_flash.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_flop.core b/hw/ip/prim_generic/prim_generic_flop.core
index 162735a9bbc027..e899f79042ee05 100644
--- a/hw/ip/prim_generic/prim_generic_flop.core
+++ b/hw/ip/prim_generic/prim_generic_flop.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_flop.sv
+      - rtl/prim_flop.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_flop_2sync.core b/hw/ip/prim_generic/prim_generic_flop_2sync.core
index 82f2b6e98718de..a67519a8696f91 100644
--- a/hw/ip/prim_generic/prim_generic_flop_2sync.core
+++ b/hw/ip/prim_generic/prim_generic_flop_2sync.core
@@ -16,7 +16,7 @@ filesets:
       # Needed for DV.
       - lowrisc:prim:cdc_rand_delay
     files:
-      - rtl/prim_generic_flop_2sync.sv
+      - rtl/prim_flop_2sync.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_flop_en.core b/hw/ip/prim_generic/prim_generic_flop_en.core
index 556ee9abec0e88..e1c70ecfc605a0 100644
--- a/hw/ip/prim_generic/prim_generic_flop_en.core
+++ b/hw/ip/prim_generic/prim_generic_flop_en.core
@@ -13,7 +13,7 @@ filesets:
     depend:
       - lowrisc:prim:sec_anchor
     files:
-      - rtl/prim_generic_flop_en.sv
+      - rtl/prim_flop_en.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_otp.core b/hw/ip/prim_generic/prim_generic_otp.core
index 054d97a55b251a..70e12ce53bdbc7 100644
--- a/hw/ip/prim_generic/prim_generic_otp.core
+++ b/hw/ip/prim_generic/prim_generic_otp.core
@@ -19,7 +19,7 @@ filesets:
       - lowrisc:prim:otp_pkg
       - lowrisc:ip:otp_ctrl_prim_reg_top
     files:
-      - rtl/prim_generic_otp.sv
+      - rtl/prim_otp.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core
index 451ae4c8d63eb1..c80c59e00dbf39 100644
--- a/hw/ip/prim_generic/prim_generic_pad_attr.core
+++ b/hw/ip/prim_generic/prim_generic_pad_attr.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_generic_pad_attr.sv
+      - rtl/prim_pad_attr.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
index 9e7ffc6ba1d4dd..764cd45f89ce3c 100644
--- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core
+++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_generic_pad_wrapper.sv
+      - rtl/prim_pad_wrapper.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core
index 52b98b589910dd..661a96627b5168 100644
--- a/hw/ip/prim_generic/prim_generic_ram_1p.core
+++ b/hw/ip/prim_generic/prim_generic_ram_1p.core
@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:ram_1p_pkg
       - lowrisc:prim:util_memload
     files:
-      - rtl/prim_generic_ram_1p.sv
+      - rtl/prim_ram_1p.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_ram_1r1w.core b/hw/ip/prim_generic/prim_generic_ram_1r1w.core
index 302a516a2d5666..efcbc802748bd7 100644
--- a/hw/ip/prim_generic/prim_generic_ram_1r1w.core
+++ b/hw/ip/prim_generic/prim_generic_ram_1r1w.core
@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:ram_2p_pkg
       - lowrisc:prim:util_memload
     files:
-      - rtl/prim_generic_ram_1r1w.sv
+      - rtl/prim_ram_1r1w.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core
index 7da402948ca41a..b246ce1164f306 100644
--- a/hw/ip/prim_generic/prim_generic_ram_2p.core
+++ b/hw/ip/prim_generic/prim_generic_ram_2p.core
@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:ram_2p_pkg
       - lowrisc:prim:util_memload
     files:
-      - rtl/prim_generic_ram_2p.sv
+      - rtl/prim_ram_2p.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_rom.core b/hw/ip/prim_generic/prim_generic_rom.core
index 32d3cb04e240f2..41d76d4fb95e4b 100644
--- a/hw/ip/prim_generic/prim_generic_rom.core
+++ b/hw/ip/prim_generic/prim_generic_rom.core
@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:rom_pkg
       - lowrisc:prim:util_memload
     files:
-      - rtl/prim_generic_rom.sv
+      - rtl/prim_rom.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core
index 59d18043ab0f88..f77bdeee108382 100644
--- a/hw/ip/prim_generic/prim_generic_usb_diff_rx.core
+++ b/hw/ip/prim_generic/prim_generic_usb_diff_rx.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_usb_diff_rx.sv
+      - rtl/prim_usb_diff_rx.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_xnor2.core b/hw/ip/prim_generic/prim_generic_xnor2.core
index c8e86b40174012..137af0183886b9 100644
--- a/hw/ip/prim_generic/prim_generic_xnor2.core
+++ b/hw/ip/prim_generic/prim_generic_xnor2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_xnor2.sv
+      - rtl/prim_xnor2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/prim_generic_xor2.core b/hw/ip/prim_generic/prim_generic_xor2.core
index 6d945cef6be270..b77448326d5a91 100644
--- a/hw/ip/prim_generic/prim_generic_xor2.core
+++ b/hw/ip/prim_generic/prim_generic_xor2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_generic_xor2.sv
+      - rtl/prim_xor2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_generic/rtl/prim_generic_and2.sv b/hw/ip/prim_generic/rtl/prim_and2.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_and2.sv
rename to hw/ip/prim_generic/rtl/prim_and2.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_buf.sv b/hw/ip/prim_generic/rtl/prim_buf.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_buf.sv
rename to hw/ip/prim_generic/rtl/prim_buf.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv b/hw/ip/prim_generic/rtl/prim_clock_buf.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv
rename to hw/ip/prim_generic/rtl/prim_clock_buf.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_div.sv b/hw/ip/prim_generic/rtl/prim_clock_div.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_clock_div.sv
rename to hw/ip/prim_generic/rtl/prim_clock_div.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv b/hw/ip/prim_generic/rtl/prim_clock_gating.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv
rename to hw/ip/prim_generic/rtl/prim_clock_gating.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv b/hw/ip/prim_generic/rtl/prim_clock_inv.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_clock_inv.sv
rename to hw/ip/prim_generic/rtl/prim_clock_inv.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv b/hw/ip/prim_generic/rtl/prim_clock_mux2.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
rename to hw/ip/prim_generic/rtl/prim_clock_mux2.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_flash.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_flash.sv
rename to hw/ip/prim_generic/rtl/prim_flash.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop.sv b/hw/ip/prim_generic/rtl/prim_flop.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_flop.sv
rename to hw/ip/prim_generic/rtl/prim_flop.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv b/hw/ip/prim_generic/rtl/prim_flop_2sync.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv
rename to hw/ip/prim_generic/rtl/prim_flop_2sync.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv b/hw/ip/prim_generic/rtl/prim_flop_en.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_flop_en.sv
rename to hw/ip/prim_generic/rtl/prim_flop_en.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_otp.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_otp.sv
rename to hw/ip/prim_generic/rtl/prim_otp.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/hw/ip/prim_generic/rtl/prim_pad_attr.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv
rename to hw/ip/prim_generic/rtl/prim_pad_attr.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/hw/ip/prim_generic/rtl/prim_pad_wrapper.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
rename to hw/ip/prim_generic/rtl/prim_pad_wrapper.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_ram_1p.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv
rename to hw/ip/prim_generic/rtl/prim_ram_1p.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/hw/ip/prim_generic/rtl/prim_ram_1r1w.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv
rename to hw/ip/prim_generic/rtl/prim_ram_1r1w.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_ram_2p.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv
rename to hw/ip/prim_generic/rtl/prim_ram_2p.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_rom.sv b/hw/ip/prim_generic/rtl/prim_rom.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_rom.sv
rename to hw/ip/prim_generic/rtl/prim_rom.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv b/hw/ip/prim_generic/rtl/prim_usb_diff_rx.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv
rename to hw/ip/prim_generic/rtl/prim_usb_diff_rx.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv b/hw/ip/prim_generic/rtl/prim_xnor2.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_xnor2.sv
rename to hw/ip/prim_generic/rtl/prim_xnor2.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_xor2.sv b/hw/ip/prim_generic/rtl/prim_xor2.sv
similarity index 100%
rename from hw/ip/prim_generic/rtl/prim_generic_xor2.sv
rename to hw/ip/prim_generic/rtl/prim_xor2.sv
diff --git a/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver b/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
index 198eeeace1f7f3..05764f141f7966 100644
--- a/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
+++ b/hw/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
@@ -5,8 +5,8 @@
 # waiver file for prim_xilinx_pad_wrapper
 # note that this code is NOT synthesizable and meant for sim only
 waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} \
-      -location {prim_xilinx_pad_wrapper.sv} \
+      -location {prim_pad_wrapper.sv} \
       -comment "This is a bidirectional pad inout."
 waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i\[.:2\]' is not read from} \
-      -location {prim_xilinx_pad_wrapper.sv} \
+      -location {prim_pad_wrapper.sv} \
       -comment "Some IO attributes may not be implemented."
diff --git a/hw/ip/prim_xilinx/prim_xilinx_and2.core b/hw/ip/prim_xilinx/prim_xilinx_and2.core
index 5db713bd5b3ddb..a88998653ab887 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_and2.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_and2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_and2.sv
+      - rtl/prim_and2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_buf.core b/hw/ip/prim_xilinx/prim_xilinx_buf.core
index d5cd793214d946..a7402d416ea741 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_buf.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_buf.sv
+      - rtl/prim_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core
index b458d4db454f3a..c315943b882394 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_clock_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_clock_buf.sv
+      - rtl/prim_clock_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core
index e80bd4a44114a4..5345ab9fabe611 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_clock_gating.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_clock_gating.sv
+      - rtl/prim_clock_gating.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core
index e08e8301d829e3..a1e8463caab8ed 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_clock_mux2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_clock_mux2.sv
+      - rtl/prim_clock_mux2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop.core b/hw/ip/prim_xilinx/prim_xilinx_flop.core
index 427449775d7e25..2cd60711776b24 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_flop.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_flop.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_flop.sv
+      - rtl/prim_flop.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core
index 0edee3a33f08ab..cc3176d0ee14d0 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_flop_en.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_flop_en.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_flop_en.sv
+      - rtl/prim_flop_en.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core
index 866ef847ac2c8a..ef179b09b09a4f 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_xilinx_pad_attr.sv
+      - rtl/prim_pad_attr.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
index cba9144762ec88..42e2495071a434 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_xilinx_pad_wrapper.sv
+      - rtl/prim_pad_wrapper.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/prim_xilinx_xor2.core b/hw/ip/prim_xilinx/prim_xilinx_xor2.core
index e46943e84115ad..09b321f9d585f5 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_xor2.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_xor2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_xor2.sv
+      - rtl/prim_xor2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv b/hw/ip/prim_xilinx/rtl/prim_and2.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_and2.sv
rename to hw/ip/prim_xilinx/rtl/prim_and2.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv b/hw/ip/prim_xilinx/rtl/prim_buf.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv
rename to hw/ip/prim_xilinx/rtl/prim_buf.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv b/hw/ip/prim_xilinx/rtl/prim_clock_buf.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv
rename to hw/ip/prim_xilinx/rtl/prim_clock_buf.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv b/hw/ip/prim_xilinx/rtl/prim_clock_gating.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv
rename to hw/ip/prim_xilinx/rtl/prim_clock_gating.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/hw/ip/prim_xilinx/rtl/prim_clock_mux2.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv
rename to hw/ip/prim_xilinx/rtl/prim_clock_mux2.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_flop.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
rename to hw/ip/prim_xilinx/rtl/prim_flop.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv b/hw/ip/prim_xilinx/rtl/prim_flop_en.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv
rename to hw/ip/prim_xilinx/rtl/prim_flop_en.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/hw/ip/prim_xilinx/rtl/prim_pad_attr.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
rename to hw/ip/prim_xilinx/rtl/prim_pad_attr.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/hw/ip/prim_xilinx/rtl/prim_pad_wrapper.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
rename to hw/ip/prim_xilinx/rtl/prim_pad_wrapper.sv
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv b/hw/ip/prim_xilinx/rtl/prim_xor2.sv
similarity index 100%
rename from hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv
rename to hw/ip/prim_xilinx/rtl/prim_xor2.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver
index 198eeeace1f7f3..05764f141f7966 100644
--- a/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver
+++ b/hw/ip/prim_xilinx_ultrascale/lint/prim_xilinx_ultrascale_pad_wrapper.waiver
@@ -5,8 +5,8 @@
 # waiver file for prim_xilinx_pad_wrapper
 # note that this code is NOT synthesizable and meant for sim only
 waive -rules TRI_DRIVER -regexp {'inout_io' is driven by a tristate driver} \
-      -location {prim_xilinx_pad_wrapper.sv} \
+      -location {prim_pad_wrapper.sv} \
       -comment "This is a bidirectional pad inout."
 waive -rules INPUT_NOT_READ -regexp {Input port 'attr\_i\[.:2\]' is not read from} \
-      -location {prim_xilinx_pad_wrapper.sv} \
+      -location {prim_pad_wrapper.sv} \
       -comment "Some IO attributes may not be implemented."
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core
index ee2214956f8f7a..8731e3a4e1c69f 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_and2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_and2.sv
+      - rtl/prim_and2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core
index 616e78504f6f89..a66b1a1972846c 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_buf.sv
+      - rtl/prim_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core
index f182ea3d71a180..18eb366e6eac8f 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_buf.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_clock_buf.sv
+      - rtl/prim_clock_buf.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core
index af7ee41bb1deec..54a47d364e670f 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_div.core
@@ -16,7 +16,7 @@ filesets:
       - lowrisc:prim:clock_inv
       - lowrisc:prim:clock_buf
     files:
-      - rtl/prim_xilinx_ultrascale_clock_div.sv
+      - rtl/prim_clock_div.sv
     file_type: systemVerilogSource
 
   files_ascentlint_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core
index 26df5f421777c0..31090b7ba36e65 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_gating.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_clock_gating.sv
+      - rtl/prim_clock_gating.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core
index af0561157981f6..416e194c5ae8c8 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_inv.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_clock_inv.sv
+      - rtl/prim_clock_inv.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core
index 642464ca36a618..d5e4ae6ed8007a 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_clock_mux2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_clock_mux2.sv
+      - rtl/prim_clock_mux2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core
index 2406237e2e7a30..92dc918f006128 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_flop.sv
+      - rtl/prim_flop.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core
index 9b0f752c6c0302..f6d66a074cf465 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_flop_en.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_flop_en.sv
+      - rtl/prim_flop_en.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core
index 6c99f0177a674d..eed92ffcc27430 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_attr.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_xilinx_ultrascale_pad_attr.sv
+      - rtl/prim_pad_attr.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core
index 623620aeb1a776..a9e7ecaceff00e 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_pad_wrapper.core
@@ -14,7 +14,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:pad_wrapper_pkg
     files:
-      - rtl/prim_xilinx_ultrascale_pad_wrapper.sv
+      - rtl/prim_pad_wrapper.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core
index 6318ace2a58676..4ebe867d641646 100644
--- a/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core
+++ b/hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_xor2.core
@@ -11,7 +11,7 @@ virtual:
 filesets:
   files_rtl:
     files:
-      - rtl/prim_xilinx_ultrascale_xor2.sv
+      - rtl/prim_xor2.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_and2.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_and2.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_and2.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_buf.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_buf.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_buf.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_buf.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_buf.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_div.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_div.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_gating.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_gating.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_gating.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_inv.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_inv.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_inv.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_mux2.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_mux2.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_clock_mux2.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_flop.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_flop.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_flop_en.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop_en.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_flop_en.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_attr.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_attr.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_attr.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_wrapper.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_pad_wrapper.sv
diff --git a/hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv b/hw/ip/prim_xilinx_ultrascale/rtl/prim_xor2.sv
similarity index 100%
rename from hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv
rename to hw/ip/prim_xilinx_ultrascale/rtl/prim_xor2.sv