From 3f02a04a652e9105cdefde4a649d818a73290d73 Mon Sep 17 00:00:00 2001 From: Martin Velay Date: Fri, 7 Feb 2025 07:45:22 +0000 Subject: [PATCH] [hmac,dv] Exclude TLUL adapter 'read' assertions - Exclude the assertions related to the read part as this particular FIFO instance is WO, to avoid to have uncovered assertions. Signed-off-by: Martin Velay --- hw/ip/hmac/dv/cov/hmac_cov_excl.el | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/ip/hmac/dv/cov/hmac_cov_excl.el b/hw/ip/hmac/dv/cov/hmac_cov_excl.el index e4f09b1f70408..a9139f7e55856 100644 --- a/hw/ip/hmac/dv/cov/hmac_cov_excl.el +++ b/hw/ip/hmac/dv/cov/hmac_cov_excl.el @@ -23,3 +23,17 @@ Transition StPad00->StFifoReceive "3->1" Fsm st_q "1171249183" ANNOTATION: "[INVALID] Intend to remove transition" Transition StLenLo->StFifoReceive "5->1" +CHECKSUM: "1785966602" +INSTANCE: tb.dut.u_tlul_adapter.u_rspfifo +ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO" +Assert DataKnown_A "assertion" +CHECKSUM: "1785966602" +INSTANCE: tb.dut.u_tlul_adapter.u_sramreqfifo +ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO" +Assert DataKnown_A "assertion" +CHECKSUM: "3919502532" +INSTANCE: tb.dut.u_tlul_adapter +ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO" +Assert rvalidHighReqFifoEmpty "assertion" +ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO" +Assert rvalidHighWhenRspFifoFull "assertion"