From a8416cbf30be6ad090a605c5043165b234a1d6ed Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Wed, 27 Nov 2024 15:28:06 +0100 Subject: [PATCH] [rtl] Fix counter reset value on FPGA If the counter width is >= 49, we do not use a DSP on the FPGA. Then, we should use an asynchronous reset to initialize the counter. This bug was detected when enabling the lockstep for the CW340. A lockstep mismatch happend as the mcycle counters of the main and shadow core did not match due to this bug. Signed-off-by: Pascal Nasahl --- rtl/ibex_counter.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/rtl/ibex_counter.sv b/rtl/ibex_counter.sv index c78e510ee4..a24870d434 100644 --- a/rtl/ibex_counter.sv +++ b/rtl/ibex_counter.sv @@ -55,8 +55,12 @@ module ibex_counter #( localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; - // DSP output register requires synchronous reset. - `define COUNTER_FLOP_RST posedge clk_i + if (CounterWidth < 49) begin : g_sync_reset + // DSP output register requires synchronous reset. + `define COUNTER_FLOP_RST posedge clk_i + end else begin : g_async_reset + `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni + end `else logic [CounterWidth-1:0] counter_q;