Tang Nano 4K and 20K boards broken on vendor tools

[pepijndevos]

On the 20K I needed to add self.toolchain.options["use_mode_as_gpio"] = 1 and then stuff seemed to work, though I don't have the hardware currently so I'm hesitant to submit a PR until my AliExpress order arrives.

4K seems bitrotted? First I got errors that kB isn't defined. There is a capital K definition but I'm not sure if that would mix bits and bytes. But when running --with-hyperram there are further errors using V1.9.8:

*** GOWIN Tcl Command Line Console  *** 
current device: GW1NSR-4C  GW1NSR-LV4CQN48PC6/I5
add new file: "sipeed_tang_nano_4k.cst"
add new file: "sipeed_tang_nano_4k.sdc"
add new file: "/home/pepijn/code/apicula/env/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/picorv32.v"
add new file: "/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/home/pepijn/code/apicula/env/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/picorv32.v'
Analyzing Verilog file '/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v'
WARN  (EX3373) : Port 'IO_hpram_rwds' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
WARN  (EX3373) : Port 'O_hpram_ck' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
WARN  (EX3373) : Port 'O_hpram_ck_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
WARN  (EX3373) : Port 'O_hpram_cs_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
WARN  (EX3373) : Port 'O_hpram_reset_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3928) : Module 'sipeed_tang_nano_4k' is ignored due to previous errors("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":4227)
Verilog file '/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v' ignored due to errors

So that requires further investigation... the problem seems to be that the IDE is very particular about if its magic pin names are single bit vectors or single bits.

[Peter-van-Tol]

Yesterday I've recieved a Tang Nano 20K and it compiled directly with the toolchain apicula. However, I did only use the pins as GPIO and do not use any RAM or other pheriphals as it is intended as a CNC controller.

If you have certain bit-files, I can test for you.

[pepijndevos]

I have the boards by now, so what is needed is fixing the vendor integration.

[Peter-van-Tol]

Please post your progress on that subject.

I've managed to compile the firmware using occ-cad-suite. However, I cannot load the firmware with openFPGALoader. I keep getting errors. I changed to the Gowin Loader and verified I can communicate with the FPGA, as I can erase the SRAM from that program. Flashing my firmware to the FPGA did not work; the .fs file has appearantly a wrong ID and the Gowin Loader refuses to upload the image.

I'm going to redo the program in Gowin EDA to check what the differences are in the header of the .fs file.

[pasquinadeus]

Hi, complete noob to FPGAs in general, but I managed to track down this issue to this commit (I'm also not able to add HyperRam to the 4k):

enjoy-digital/litex@9c37324

Hoping that perhaps Gowin might have changed something in the toolset in the 4 years since, I simply removed the call to the hack. It now synthesises correctly, but the bootloader is stuck on the hyperram initialization step:

HyperRAM init...
HyperRAM Clk Ratio 4:1
HyperRAM Fixed Latency: 3 CK (X1)

Perhaps someone more versed in SoC/verilog/FPGAs can take a look?

Hope this helps in any way!

[Peter-van-Tol]

Hope that this helps on integrating the tools.

I have encountered two problems:

1. The .fs-file created by LiteX, using the apicula toolchain cannot be loaded by either openFPGALoader, nor the Gowin programmer.
2. A program created with Gowin EDA can successfully be uploaded with the Gowin Programmer, but fails with the openFPGALoader.

So there are two problems.

1. cannot upload with OpenFPGALoader
This issue I will forward to Sipeed, because according to their website using OpenFPGALoader is the recommended way to upload the bitstream on Linux systems.

2. the apicula does not produce a valid bitstream for the Tang Nano 20 k
The .fs-file is missing a header to be used with the Gowin programmer. If I add the information below to the file, it is accepted by the programmer and my blink example works!

//File Title: Bitstream file
//Device: GW2AR-18
//Device Version: C
//Part Number: GW2AR-LV18QN88C8/I7
//Device-package: GW2AR-18C-QFN88
//BackgroundProgramming: OFF
//LoadingRate: 2.500MHz
//CRCCheck: ON
//Compress: OFF
//Encryption: OFF
//SecurityBit: ON
//SecureMode: OFF
//JTAGAsRegularIO: OFF
//MultiBootSPIAddr: 0x00000000

Conclusion
If only the openFPGALoader would work, then we have a truly open source toolchain for this board.

[trabucayre]

@Peter-van-Tol Could you adds more details for "but fails with the openFPGALoader."?
Is it a fail during load/flash sequence or is the FPGA is stalled after this step?

Adding the header as work around looks strange: all header's informations are for user, but are also present as a bit, or bits sequence, in the remaining part of the bitstream.

Thanks

[Peter-van-Tol]

@trabucayre : Adding the headers was really the only way to get it working. Maybe not all headers are required, so maybe the amount can be reduced by trying out which ones can be omitted. Is there a definition of the .fs-file available, which describes the bits set?

Relating to the fails with the openFPGALoader, I tried three scenario's:

1. There is an existing sketch in the flash.
   In this case an error FLASH lock FAIL is given. You can find the complete log here: log.txt
2. The flash memory is erased using the Gowin Programmer, trying to write the SRAM:
   According to the output of openFPGALoader the flashing was succesfull (no indication of any error), however the LED doesn't start blinking as it does using the Gowin Programmer. It seems (assuming here), the FPGA is either not programmed or needs to be reset to start functioning. Sending the reset command with the openFPGALoader does not resolve this.
3. The flash memory is erased using the Gowin Programmer, trying to write the SRAM:
   This does not work, an error is given that the flash memory could not be prepared. Tried running openFPGALoader with both the -f command and the --external-flash, both give the same error.

[trabucayre]

Strange: I have tried today to build this gateware with both gowin and apicula:

• apicula is up to date (pipto install apycula but nextpnr and yosys are built with HEAD)
• openFPGALoaderup to date too
• with apicula I need to adds --cpu-type serv to have a success (this is not required with gowin tools).
• with apicula openFPGALoader works as expected to load bitstream (write not tested): ledChaser is working but nothing via UART
• with gowin tools same results for openFPGALoader with serv and vexriscv and UART is also working.

Could you provides your OS (windows/mac/linux) and openFPGALoader version please?
log file shows some weird errors in status register.

Thanks

[Peter-van-Tol]

The OS is Linux. The version of openFPGALoader is version v0.12.1, which is part of oss-CAD-suite. So I did not install or build it separately.

The toolchain with apicula does work, because the .fs-file does work when programmed with Gowin Programmer.