From f7aadbd2d7c782cdc4f9df62c6ae3eceb5bbcbbb Mon Sep 17 00:00:00 2001
From: Gautham Ganapathy <gauthamg@gmail.com>
Date: Wed, 25 Oct 2023 00:53:11 +0100
Subject: [PATCH 1/2] Skip non-compute tiles when in indices of asm sources

---
 examples/segment00150/segment00150.asm | 22 ++++++++++++++--------
 examples/segment20176/segment20176.asm | 23 ++++++++++++++++++++---
 run_tests.sh                           |  4 ++--
 src/TIS100/Sim/CPU.hs                  | 24 ++++++++++++++++--------
 4 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/examples/segment00150/segment00150.asm b/examples/segment00150/segment00150.asm
index 51aa2ad..97f76a3 100644
--- a/examples/segment00150/segment00150.asm
+++ b/examples/segment00150/segment00150.asm
@@ -1,17 +1,23 @@
 @0
 MOV UP, DOWN
+
+@1
+MOV RIGHT, DOWN
+
+@2
+MOV UP, LEFT
+
+@3
+MOV UP, DOWN
+
 @4
 MOV UP, DOWN
-@8
+
+@5
 MOV UP, DOWN
 
-@3
-MOV UP, LEFT
-@2
-MOV RIGHT, DOWN
 @6
-MOV UP, DOWN
-@10
 MOV UP, RIGHT
-@11
+
+@7
 MOV LEFT, DOWN
\ No newline at end of file
diff --git a/examples/segment20176/segment20176.asm b/examples/segment20176/segment20176.asm
index 910618b..3712d23 100644
--- a/examples/segment20176/segment20176.asm
+++ b/examples/segment20176/segment20176.asm
@@ -1,3 +1,6 @@
+@0
+
+
 @1
 MOV UP, ACC
 SUB RIGHT
@@ -6,16 +9,30 @@ MOV ACC, DOWN
 @2
 MOV UP, LEFT
 
+@3
+
+
+@4
+
+
 @5
 MOV UP, ACC
 MOV ACC, DOWN
 MOV ACC, DOWN
 
-@9
+@6
+
+
+@7
+
+
+@8
 MOV UP, RIGHT
 MOV UP, DOWN
 
-@10
+@9
 MOV LEFT, ACC
 NEG
-MOV ACC, DOWN
\ No newline at end of file
+MOV ACC, DOWN
+
+@10
diff --git a/run_tests.sh b/run_tests.sh
index 5a6bf5a..9f4b3af 100755
--- a/run_tests.sh
+++ b/run_tests.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
 
 ./build.sh
-# stack run tissim -- examples/segment00150/segment00150.asm -c examples/segment00150/segment00150.cfg 2>&1 | tee test.log
-stack run tissim -- examples/segment20176/segment20176.asm -c examples/segment20176/segment20176.cfg 2>&1 | tee test.log
+stack run tissim -- examples/segment00150/segment00150.asm -c examples/segment00150/segment00150.cfg 2>&1 | tee test.log
+# stack run tissim -- examples/segment20176/segment20176.asm -c examples/segment20176/segment20176.cfg 2>&1 | tee test.log
diff --git a/src/TIS100/Sim/CPU.hs b/src/TIS100/Sim/CPU.hs
index 1584d8d..942313a 100644
--- a/src/TIS100/Sim/CPU.hs
+++ b/src/TIS100/Sim/CPU.hs
@@ -1,6 +1,5 @@
 module TIS100.Sim.CPU where
 
-import Control.Monad (zipWithM)
 import Data.IntMap qualified as IM
 import Data.Map qualified as M
 import Data.Vector qualified as V
@@ -38,15 +37,24 @@ data CPUState = CPUState
 createInitialCPUState :: C.Config -> AP.AsmSource -> TISErrorOr CPUState
 createInitialCPUState cfg asm =
   let tileTypes = concat $ C.tiles cfg
-   in (CPUState (CPUConfig (C.rows cfg) (C.cols cfg)) . V.fromList <$> zipWithM createTile [0 ..] tileTypes)
+   in (CPUState (CPUConfig (C.rows cfg) (C.cols cfg)) . V.fromList <$> createTiles 0 0 tileTypes)
  where
-  createTile :: Int -> C.TileType -> TISErrorOr PositionedTile
-  createTile i tileType =
-    let pos = i `divMod` C.cols cfg
+  createTiles :: Int -> Int -> [C.TileType] -> TISErrorOr [PositionedTile]
+  createTiles _ _ [] = Right []
+  createTiles asmIdx tileIdx (t : ts) = do
+    tile' <- createTile asmIdx tileIdx t
+    tiles' <- case t of
+      C.Conpute -> createTiles (asmIdx + 1) (tileIdx + 1) ts
+      _ -> createTiles asmIdx (tileIdx + 1) ts
+    return $ tile' : tiles'
+
+  createTile :: Int -> Int -> C.TileType -> TISErrorOr PositionedTile
+  createTile asmIdx tileIdx tileType =
+    let pos = tileIdx `divMod` C.cols cfg
      in case tileType of
-          C.Conpute -> PositionedTile pos i . ConnectedTile . T21.createTileState <$> getTileAsm i
-          C.Stack -> Right $ PositionedTile pos i $ ConnectedTile $ T30.T30 []
-          C.Disabled -> Right $ PositionedTile pos i $ ConnectedTile $ Inactive.InactiveTile
+          C.Conpute -> PositionedTile pos tileIdx . ConnectedTile . T21.createTileState <$> getTileAsm asmIdx
+          C.Stack -> Right $ PositionedTile pos tileIdx $ ConnectedTile $ T30.T30 []
+          C.Disabled -> Right $ PositionedTile pos tileIdx $ ConnectedTile $ Inactive.InactiveTile
 
   getTileAsm :: Int -> TISErrorOr T21.TileProgram
   getTileAsm i = case IM.lookup i asm of

From 2bba0b10f33fbef46ebcd82d774af9feb956b8a1 Mon Sep 17 00:00:00 2001
From: Gautham Ganapathy <gauthamg@gmail.com>
Date: Wed, 25 Oct 2023 01:15:53 +0100
Subject: [PATCH 2/2] Fixes

---
 build.sh                |  2 +-
 src/TIS100/Tiles/T21.hs | 13 ++++++++-----
 tissim/Main.hs          |  2 ++
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/build.sh b/build.sh
index c363698..0b52fd6 100755
--- a/build.sh
+++ b/build.sh
@@ -1,3 +1,3 @@
 #!/bin/bash
 
-stack build --pedantic 2>&1 | tee build.log
+stack build 2>&1 | tee build.log
diff --git a/src/TIS100/Tiles/T21.hs b/src/TIS100/Tiles/T21.hs
index 291a890..5de97f2 100644
--- a/src/TIS100/Tiles/T21.hs
+++ b/src/TIS100/Tiles/T21.hs
@@ -150,11 +150,14 @@ instance IsConnectedTile T21 where
 
   writeValueTo = setPortVal False -- External call
 
-  step t = case (runState . tileState) t of
-    Ready -> stepReady
-    WaitingOnRead _ Nothing -> t
-    WaitingOnRead _ (Just _) -> stepReady
-    WaitingOnWrite _ _ -> t
+  step t =
+    if null (tileProgram t)
+      then t
+      else case (runState . tileState) t of
+        Ready -> stepReady
+        WaitingOnRead _ Nothing -> t
+        WaitingOnRead _ (Just _) -> stepReady
+        WaitingOnWrite _ _ -> t
    where
     stepReady :: T21
     stepReady = stepReady'
diff --git a/tissim/Main.hs b/tissim/Main.hs
index 939645b..f91e78d 100644
--- a/tissim/Main.hs
+++ b/tissim/Main.hs
@@ -17,6 +17,8 @@ main = do
   print asm
 
   let initialCPUState = CPU.createInitialCPUState cfg asm
+  print initialCPUState
+
   finalSimState <- case initialCPUState of
     Left err -> error $ show err
     Right cpuState -> Run.run $ Run.SimState cpuState (ParserCfg.inputs cfg) (ParserCfg.outputs cfg)