diff --git a/nvme-print.c b/nvme-print.c
index 0c00b80c60..b1134c3089 100644
--- a/nvme-print.c
+++ b/nvme-print.c
@@ -369,6 +369,23 @@ const char *nvme_register_unit_to_string(__u8 unit)
 	return "Reserved";
 }
 
+bool nvme_is_fabrics_reg(int offset)
+{
+	switch (offset) {
+	case NVME_REG_CAP:
+	case NVME_REG_VS:
+	case NVME_REG_CC:
+	case NVME_REG_CSTS:
+	case NVME_REG_NSSR:
+	case NVME_REG_CRTO:
+		return true;
+	default:
+		break;
+	}
+
+	return false;
+}
+
 bool nvme_registers_cmbloc_support(__u32 cmbsz)
 {
 	return !!cmbsz;
@@ -378,6 +395,25 @@ bool nvme_registers_pmrctl_ready(__u32 pmrctl)
 {
 	return NVME_PMRCTL_EN(pmrctl);
 }
+
+void nvme_show_ctrl_register(void *bar, bool fabrics, int offset, enum nvme_print_flags flags)
+{
+	uint64_t value;
+
+	if (fabrics && !nvme_is_fabrics_reg(offset)) {
+		printf("register: %#04x (%s) not fabrics\n", offset,
+		       nvme_register_to_string(offset));
+		return;
+	}
+
+	if (nvme_is_64bit_reg(offset))
+		value = mmio_read64(bar + offset);
+	else
+		value = mmio_read32(bar + offset);
+
+	nvme_print(ctrl_register, flags, offset, value);
+}
+
 void nvme_show_ctrl_registers(void *bar, bool fabrics, enum nvme_print_flags flags)
 {
 	nvme_print(ctrl_registers, flags, bar, fabrics);
@@ -777,20 +813,67 @@ const char *nvme_feature_to_string(enum nvme_features_id feature)
 const char *nvme_register_to_string(int reg)
 {
 	switch (reg) {
-	case NVME_REG_CAP:	return "Controller Capabilities";
-	case NVME_REG_VS:	return "Version";
-	case NVME_REG_INTMS:	return "Interrupt Vector Mask Set";
-	case NVME_REG_INTMC:	return "Interrupt Vector Mask Clear";
-	case NVME_REG_CC:	return "Controller Configuration";
-	case NVME_REG_CSTS:	return "Controller Status";
-	case NVME_REG_NSSR:	return "NVM Subsystem Reset";
-	case NVME_REG_AQA:	return "Admin Queue Attributes";
-	case NVME_REG_ASQ:	return "Admin Submission Queue Base Address";
-	case NVME_REG_ACQ:	return "Admin Completion Queue Base Address";
-	case NVME_REG_CMBLOC:	return "Controller Memory Buffer Location";
-	case NVME_REG_CMBSZ:	return "Controller Memory Buffer Size";
-	default:		return "Unknown";
+	case NVME_REG_CAP:
+		return "Controller Capabilities";
+	case NVME_REG_VS:
+		return "Version";
+	case NVME_REG_INTMS:
+		return "Interrupt Vector Mask Set";
+	case NVME_REG_INTMC:
+		return "Interrupt Vector Mask Clear";
+	case NVME_REG_CC:
+		return "Controller Configuration";
+	case NVME_REG_CSTS:
+		return "Controller Status";
+	case NVME_REG_NSSR:
+		return "NVM Subsystem Reset";
+	case NVME_REG_AQA:
+		return "Admin Queue Attributes";
+	case NVME_REG_ASQ:
+		return "Admin Submission Queue Base Address";
+	case NVME_REG_ACQ:
+		return "Admin Completion Queue Base Address";
+	case NVME_REG_CMBLOC:
+		return "Controller Memory Buffer Location";
+	case NVME_REG_CMBSZ:
+		return "Controller Memory Buffer Size";
+	case NVME_REG_BPINFO:
+		return "Boot Partition Information";
+	case NVME_REG_BPRSEL:
+		return "Boot Partition Read Select";
+	case NVME_REG_BPMBL:
+		return "Boot Partition Memory Buffer Location";
+	case NVME_REG_CMBMSC:
+		return "Controller Memory Buffer Memory Space Control";
+	case NVME_REG_CMBSTS:
+		return "Controller Memory Buffer Status";
+	case NVME_REG_CMBEBS:
+		return "Controller Memory Buffer Elasticity Buffer Size";
+	case NVME_REG_CMBSWTP:
+		return "Controller Memory Buffer Sustained Write Throughput";
+	case NVME_REG_NSSD:
+		return "NVM Subsystem Shutdown";
+	case NVME_REG_CRTO:
+		return "Controller Ready Timeouts";
+	case NVME_REG_PMRCAP:
+		return "Persistent Memory Region Capabilities";
+	case NVME_REG_PMRCTL:
+		return "Persistent Memory Region Control";
+	case NVME_REG_PMRSTS:
+		return "Persistent Memory Region Status";
+	case NVME_REG_PMREBS:
+		return "Persistent Memory Region Elasticity Buffer Size";
+	case NVME_REG_PMRSWTP:
+		return "Persistent Memory Region Sustained Write Throughput";
+	case NVME_REG_PMRMSCL:
+		return "Persistent Memory Region Memory Space Control Lower";
+	case NVME_REG_PMRMSCU:
+		return "Persistent Memory Region Memory Space Control Upper";
+	default:
+		break;
 	}
+
+	return "Unknown";
 }
 
 const char *nvme_select_to_string(int sel)
@@ -980,6 +1063,72 @@ const char *nvme_pel_rci_rcpit_to_string(enum nvme_pel_rci_rcpit rcpit)
 	return "Reserved";
 }
 
+const char *nvme_register_symbol_to_string(int offset)
+{
+	switch (offset) {
+	case NVME_REG_CAP:
+		return "cap";
+	case NVME_REG_VS:
+		return "version";
+	case NVME_REG_INTMS:
+		return "intms";
+	case NVME_REG_INTMC:
+		return "intmc";
+	case NVME_REG_CC:
+		return "cc";
+	case NVME_REG_CSTS:
+		return "csts";
+	case NVME_REG_NSSR:
+		return "nssr";
+	case NVME_REG_AQA:
+		return "aqa";
+	case NVME_REG_ASQ:
+		return "asq";
+	case NVME_REG_ACQ:
+		return "acq";
+	case NVME_REG_CMBLOC:
+		return "cmbloc";
+	case NVME_REG_CMBSZ:
+		return "cmbsz";
+	case NVME_REG_BPINFO:
+		return "bpinfo";
+	case NVME_REG_BPRSEL:
+		return "bprsel";
+	case NVME_REG_BPMBL:
+		return "bpmbl";
+	case NVME_REG_CMBMSC:
+		return "cmbmsc";
+	case NVME_REG_CMBSTS:
+		return "cmbsts";
+	case NVME_REG_CMBEBS:
+		return "cmbebs";
+	case NVME_REG_CMBSWTP:
+		return "cmbswtp";
+	case NVME_REG_NSSD:
+		return "nssd";
+	case NVME_REG_CRTO:
+		return "crto";
+	case NVME_REG_PMRCAP:
+		return "pmrcap";
+	case NVME_REG_PMRCTL:
+		return "pmrctl";
+	case NVME_REG_PMRSTS:
+		return "pmrsts";
+	case NVME_REG_PMREBS:
+		return "pmrebs";
+	case NVME_REG_PMRSWTP:
+		return "pmrswtp";
+	case NVME_REG_PMRMSCL:
+		return "pmrmscl";
+	case NVME_REG_PMRMSCU:
+		return "pmrmscu";
+	default:
+		break;
+	}
+
+	return "unknown";
+}
+
 void nvme_feature_show(enum nvme_features_id fid, int sel, unsigned int result)
 {
 	nvme_print(show_feature, NORMAL, fid, sel, result);
diff --git a/nvme-print.h b/nvme-print.h
index c0be86c4e8..cf984e3548 100644
--- a/nvme-print.h
+++ b/nvme-print.h
@@ -26,6 +26,7 @@ struct print_ops {
 	void (*phy_rx_eom_log)(struct nvme_phy_rx_eom_log *log, __u16 controller);
 	void (*ctrl_list)(struct nvme_ctrl_list *ctrl_list);
 	void (*ctrl_registers)(void *bar, bool fabrics);
+	void (*ctrl_register)(int offset, uint64_t value);
 	void (*directive)(__u8 type, __u8 oper, __u16 spec, __u32 nsid, __u32 result, void *buf, __u32 len);
 	void (*discovery_log)(struct nvmf_discovery_log *log, int numrec);
 	void (*effects_log_list)(struct list_head *list);
@@ -205,6 +206,7 @@ void nvme_show_media_unit_stat_log(struct nvme_media_unit_stat_log *mus,
 void nvme_show_supported_cap_config_log(struct nvme_supported_cap_config_list_log *caplog,
 				enum nvme_print_flags flags);
 void nvme_show_ctrl_registers(void *bar, bool fabrics, enum nvme_print_flags flags);
+void nvme_show_ctrl_register(void *bar, bool fabrics, int offset, enum nvme_print_flags flags);
 void nvme_show_single_property(int offset, uint64_t prop, enum nvme_print_flags flags);
 void nvme_show_id_ns_descs(void *data, unsigned nsid, enum nvme_print_flags flags);
 void nvme_show_lba_status(struct nvme_lba_status *list, unsigned long len,
@@ -294,6 +296,7 @@ const char *nvme_register_pmr_hsts_to_string(__u8 hsts);
 const char *nvme_register_unit_to_string(__u8 unit);
 const char *nvme_register_szu_to_string(__u8 szu);
 const char *nvme_register_to_string(int reg);
+const char *nvme_register_symbol_to_string(int offset);
 const char *nvme_resv_notif_to_string(__u8 type);
 const char *nvme_select_to_string(int sel);
 const char *nvme_sstat_status_to_string(__u16 status);
@@ -311,6 +314,7 @@ void nvme_show_perror(const char *msg);
 void nvme_show_error_status(int status, const char *msg, ...);
 void nvme_show_init(void);
 void nvme_show_finish(void);
+bool nvme_is_fabrics_reg(int offset);
 bool nvme_registers_cmbloc_support(__u32 cmbsz);
 bool nvme_registers_pmrctl_ready(__u32 pmrctl);
 #endif /* NVME_PRINT_H */